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|
- extern const UQItype __clz_tab[256] attribute_hidden;
- do { \
- UDItype __m0 = (m0), __m1 = (m1); \
- (ph) = __builtin_alpha_umulh (__m0, __m1); \
- (pl) = __m0 * __m1; \
- } while (0)
- do { UDItype __r; \
- (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
- (r) = __r; \
- } while (0)
- extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
- do { \
- UDItype __xr = (X), __t, __a; \
- __t = __builtin_alpha_cmpbge (0, __xr); \
- __a = __clz_tab[__t ^ 0xff] - 1; \
- __t = __builtin_alpha_extbl (__xr, __a); \
- (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
- } while (0)
- do { \
- UDItype __xr = (X), __t, __a; \
- __t = __builtin_alpha_cmpbge (0, __xr); \
- __t = ~__t & -~__t; \
- __a = ((__t & 0xCC) != 0) * 2; \
- __a += ((__t & 0xF0) != 0) * 4; \
- __a += ((__t & 0xAA) != 0); \
- __t = __builtin_alpha_extbl (__xr, __a); \
- __a <<= 3; \
- __t &= -__t; \
- __a += ((__t & 0xCC) != 0) * 2; \
- __a += ((__t & 0xF0) != 0) * 4; \
- __a += ((__t & 0xAA) != 0); \
- (COUNT) = __a; \
- } while (0)
- __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "rIJ" ((USItype) (bh)), \
- "%r" ((USItype) (al)), \
- "rIJ" ((USItype) (bl)))
- __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "rIJ" ((USItype) (bh)), \
- "r" ((USItype) (al)), \
- "rIJ" ((USItype) (bl)))
- do \
- { \
- SItype c_; \
- \
- __asm__ ("norm.f\t%0,%1\n\tmov.mi\t%0,-1" : "=r" (c_) : "r" (x) : "cc");\
- (count) = c_ + 1; \
- } \
- while (0)
- && W_TYPE_SIZE == 32
- __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%r" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "%r" ((USItype) (al)), \
- "rI" ((USItype) (bl)) __CLOBBER_CC)
- __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "r" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "r" ((USItype) (al)), \
- "rI" ((USItype) (bl)) __CLOBBER_CC)
- || defined(__ARM_ARCH_3__)
- do { \
- register USItype __t0, __t1, __t2; \
- __asm__ ("%@ Inlined umul_ppmm\n" \
- " mov %2, %5, lsr #16\n" \
- " mov %0, %6, lsr #16\n" \
- " bic %3, %5, %2, lsl #16\n" \
- " bic %4, %6, %0, lsl #16\n" \
- " mul %1, %3, %4\n" \
- " mul %4, %2, %4\n" \
- " mul %3, %0, %3\n" \
- " mul %0, %2, %0\n" \
- " adds %3, %4, %3\n" \
- " addcs %0, %0, #65536\n" \
- " adds %1, %1, %3, lsl #16\n" \
- " adc %0, %0, %3, lsr #16" \
- : "=&r" ((USItype) (xh)), \
- "=r" ((USItype) (xl)), \
- "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
- : "r" ((USItype) (a)), \
- "r" ((USItype) (b)) __CLOBBER_CC ); \
- } while (0)
- do { \
- \
- register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
- (xl) = (USItype)__t0; \
- (xh) = (USItype)(__t0 >> 32); \
- } while (0)
- extern UDItype __umulsidi3 (USItype, USItype);
- do { \
- UDItype __x = __umulsidi3 (u, v); \
- (w0) = (USItype) (__x); \
- (w1) = (USItype) (__x >> 32); \
- } while (0)
- __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%rM" ((USItype) (ah)), \
- "rM" ((USItype) (bh)), \
- "%rM" ((USItype) (al)), \
- "rM" ((USItype) (bl)))
- __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "rM" ((USItype) (ah)), \
- "rM" ((USItype) (bh)), \
- "rM" ((USItype) (al)), \
- "rM" ((USItype) (bl)))
- do { \
- union \
- { \
- UDItype __f; \
- struct {USItype __w1, __w0;} __w1w0; \
- } __t; \
- __asm__ ("xmpyu %1,%2,%0" \
- : "=x" (__t.__f) \
- : "x" ((USItype) (u)), \
- "x" ((USItype) (v))); \
- (w1) = __t.__w1w0.__w1; \
- (w0) = __t.__w1w0.__w0; \
- } while (0)
- do { \
- USItype __tmp; \
- __asm__ ( \
- "ldi 1,%0\n" \
- " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
- " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
- " ldo 16(%0),%0 ; Yes. Perform add.\n" \
- " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
- " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
- " ldo 8(%0),%0 ; Yes. Perform add.\n" \
- " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
- " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
- " ldo 4(%0),%0 ; Yes. Perform add.\n" \
- " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
- " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
- " ldo 2(%0),%0 ; Yes. Perform add.\n" \
- " extru %1,30,1,%1 ; Extract bit 1.\n" \
- " sub %0,%1,%0 ; Subtract it.\n" \
- : "=r" (count), "=r" (__tmp) : "1" (x)); \
- } while (0)
- do { \
- union {DItype __ll; \
- struct {USItype __h, __l;} __i; \
- } __x; \
- __asm__ ("lr %N0,%1\n\tmr %0,%2" \
- : "=&r" (__x.__ll) \
- : "r" (m0), "r" (m1)); \
- (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
- } while (0)
- do { \
- union {DItype __ll; \
- struct {USItype __h, __l;} __i; \
- } __x; \
- __x.__i.__h = n1; __x.__i.__l = n0; \
- __asm__ ("dr %0,%2" \
- : "=r" (__x.__ll) \
- : "0" (__x.__ll), "r" (d)); \
- (q) = __x.__i.__l; (r) = __x.__i.__h; \
- } while (0)
- do { \
- register SItype __r0 __asm__ ("0"); \
- register SItype __r1 __asm__ ("1") = (m0); \
- \
- __asm__ ("mr\t%%r0,%3" \
- : "=r" (__r0), "=r" (__r1) \
- : "r" (__r1), "r" (m1)); \
- (xh) = __r0; (xl) = __r1; \
- } while (0)
- do { \
- register SItype __r0 __asm__ ("0") = (n1); \
- register SItype __r1 __asm__ ("1") = (n0); \
- \
- __asm__ ("dr\t%%r0,%4" \
- : "=r" (__r0), "=r" (__r1) \
- : "r" (__r0), "r" (__r1), "r" (d)); \
- (q) = __r1; (r) = __r0; \
- } while (0)
- __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- __asm__ ("mul{l} %3" \
- : "=a" ((USItype) (w0)), \
- "=d" ((USItype) (w1)) \
- : "%0" ((USItype) (u)), \
- "rm" ((USItype) (v)))
- __asm__ ("div{l} %4" \
- : "=a" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
- : "0" ((USItype) (n0)), \
- "1" ((USItype) (n1)), \
- "rm" ((USItype) (dv)))
- __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "%0" ((UDItype) (ah)), \
- "rme" ((UDItype) (bh)), \
- "%1" ((UDItype) (al)), \
- "rme" ((UDItype) (bl)))
- __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
- : "0" ((UDItype) (ah)), \
- "rme" ((UDItype) (bh)), \
- "1" ((UDItype) (al)), \
- "rme" ((UDItype) (bl)))
- __asm__ ("mul{q} %3" \
- : "=a" ((UDItype) (w0)), \
- "=d" ((UDItype) (w1)) \
- : "%0" ((UDItype) (u)), \
- "rm" ((UDItype) (v)))
- __asm__ ("div{q} %4" \
- : "=a" ((UDItype) (q)), \
- "=d" ((UDItype) (r)) \
- : "0" ((UDItype) (n0)), \
- "1" ((UDItype) (n1)), \
- "rm" ((UDItype) (dv)))
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __asm__ ("emul %2,%1,%0" \
- : "=d" (__xx.__ll) \
- : "%dI" ((USItype) (u)), \
- "dI" ((USItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
- ({UDItype __w; \
- __asm__ ("emul %2,%1,%0" \
- : "=d" (__w) \
- : "%dI" ((USItype) (u)), \
- "dI" ((USItype) (v))); \
- __w; })
- do { \
- UWtype __x; \
- __x = (al) - (bl); \
- if ((al) < (bl)) \
- (sh) = (ah) - (bh) - 1; \
- else \
- (sh) = (ah) - (bh); \
- (sl) = __x; \
- } while (0)
- __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
- : "=&f" (ph), "=f" (pl) \
- : "f" (m0), "f" (m1))
- do { \
- UWtype _x = (x), _y, _a, _c; \
- __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
- __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
- _c = (_a - 1) << 3; \
- _x >>= _c; \
- if (_x >= 1 << 4) \
- _x >>= 4, _c += 4; \
- if (_x >= 1 << 2) \
- _x >>= 2, _c += 2; \
- _c += _x >> 1; \
- (count) = W_TYPE_SIZE - 1 - _c; \
- } while (0)
- do { \
- UWtype __ctz_x = (x); \
- __asm__ ("popcnt %0 = %1" \
- : "=r" (count) \
- : "r" ((__ctz_x-1) & ~__ctz_x)); \
- } while (0)
- \
- __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "r" ((USItype) (bl)) \
- : "cbit")
- \
- __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "r" ((USItype) (bl)) \
- : "cbit")
- __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
- : "=d" ((USItype) (sh)), \
- "=&d" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "d" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
- : "=d" ((USItype) (sh)), \
- "=&d" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "d" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- __asm__ ("mulu%.l %3,%1:%0" \
- : "=d" ((USItype) (w0)), \
- "=d" ((USItype) (w1)) \
- : "%0" ((USItype) (u)), \
- "dmi" ((USItype) (v)))
- __asm__ ("divu%.l %4,%1:%0" \
- : "=d" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
- : "0" ((USItype) (n0)), \
- "1" ((USItype) (n1)), \
- "dmi" ((USItype) (d)))
- __asm__ ("divs%.l %4,%1:%0" \
- : "=d" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
- : "0" ((USItype) (n0)), \
- "1" ((USItype) (n1)), \
- "dmi" ((USItype) (d)))
- __asm__ ("| Inlined umul_ppmm\n" \
- " move%.l %2,%/d0\n" \
- " move%.l %3,%/d1\n" \
- " move%.l %/d0,%/d2\n" \
- " swap %/d0\n" \
- " move%.l %/d1,%/d3\n" \
- " swap %/d1\n" \
- " move%.w %/d2,%/d4\n" \
- " mulu %/d3,%/d4\n" \
- " mulu %/d1,%/d2\n" \
- " mulu %/d0,%/d3\n" \
- " mulu %/d0,%/d1\n" \
- " move%.l %/d4,%/d0\n" \
- " clr%.w %/d0\n" \
- " swap %/d0\n" \
- " add%.l %/d0,%/d2\n" \
- " add%.l %/d3,%/d2\n" \
- " jcc 1f\n" \
- " add%.l %#65536,%/d1\n" \
- "1: swap %/d2\n" \
- " moveq %#0,%/d0\n" \
- " move%.w %/d2,%/d0\n" \
- " move%.w %/d4,%/d2\n" \
- " move%.l %/d2,%1\n" \
- " add%.l %/d1,%/d0\n" \
- " move%.l %/d0,%0" \
- : "=g" ((USItype) (xh)), \
- "=g" ((USItype) (xl)) \
- : "g" ((USItype) (a)), \
- "g" ((USItype) (b)) \
- : "d0", "d1", "d2", "d3", "d4")
- __asm__ ("| Inlined umul_ppmm\n" \
- " move%.l %2,%/d0\n" \
- " move%.l %3,%/d1\n" \
- " move%.l %/d0,%/d2\n" \
- " swap %/d0\n" \
- " move%.l %/d1,%/d3\n" \
- " swap %/d1\n" \
- " move%.w %/d2,%/d4\n" \
- " mulu %/d3,%/d4\n" \
- " mulu %/d1,%/d2\n" \
- " mulu %/d0,%/d3\n" \
- " mulu %/d0,%/d1\n" \
- " move%.l %/d4,%/d0\n" \
- " eor%.w %/d0,%/d0\n" \
- " swap %/d0\n" \
- " add%.l %/d0,%/d2\n" \
- " add%.l %/d3,%/d2\n" \
- " jcc 1f\n" \
- " add%.l %#65536,%/d1\n" \
- "1: swap %/d2\n" \
- " moveq %#0,%/d0\n" \
- " move%.w %/d2,%/d0\n" \
- " move%.w %/d4,%/d2\n" \
- " move%.l %/d2,%1\n" \
- " add%.l %/d1,%/d0\n" \
- " move%.l %/d0,%0" \
- : "=g" ((USItype) (xh)), \
- "=g" ((USItype) (xl)) \
- : "g" ((USItype) (a)), \
- "g" ((USItype) (b)) \
- : "d0", "d1", "d2", "d3", "d4")
- __asm__ ("bfffo %1{%b2:%b2},%0" \
- : "=d" ((USItype) (count)) \
- : "od" ((USItype) (x)), "n" (0))
- __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%rJ" ((USItype) (ah)), \
- "rJ" ((USItype) (bh)), \
- "%rJ" ((USItype) (al)), \
- "rJ" ((USItype) (bl)))
- __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "rJ" ((USItype) (ah)), \
- "rJ" ((USItype) (bh)), \
- "rJ" ((USItype) (al)), \
- "rJ" ((USItype) (bl)))
- do { \
- USItype __cbtmp; \
- __asm__ ("ff1 %0,%1" \
- : "=r" (__cbtmp) \
- : "r" ((USItype) (x))); \
- (count) = __cbtmp ^ 31; \
- } while (0)
- do { \
- union {UDItype __ll; \
- struct {USItype __h, __l;} __i; \
- } __xx; \
- __asm__ ("mulu.d %0,%1,%2" \
- : "=r" (__xx.__ll) \
- : "r" ((USItype) (u)), \
- "r" ((USItype) (v))); \
- (wh) = __xx.__i.__h; \
- (wl) = __xx.__i.__l; \
- } while (0)
- ({union {UDItype __ll; \
- struct {USItype __h, __l;} __i; \
- } __xx; \
- USItype __q; \
- __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
- __asm__ ("divu.d %0,%1,%2" \
- : "=r" (__q) \
- : "r" (__xx.__ll), \
- "r" ((USItype) (d))); \
- (r) = (n0) - __q * (d); (q) = __q; })
- asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
- asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
- asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
- asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
- do { \
- DWunion __s, __a, __b; \
- __a.s.low = (al); __a.s.high = (ah); \
- __b.s.low = (bl); __b.s.high = (bh); \
- __s.ll = __a.ll + __b.ll; \
- (sl) = __s.s.low; (sh) = __s.s.high; \
- } while (0)
- do { \
- DWunion __s, __a, __b; \
- __a.s.low = (al); __a.s.high = (ah); \
- __b.s.low = (bl); __b.s.high = (bh); \
- __s.ll = __a.ll - __b.ll; \
- (sl) = __s.s.low; (sh) = __s.s.high; \
- } while (0)
- asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
- asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
- do { \
- UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
- (w1) = (USItype) (__x >> 32); \
- (w0) = (USItype) (__x); \
- } while (0)
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __asm__ ("meid %2,%0" \
- : "=g" (__xx.__ll) \
- : "%0" ((USItype) (u)), \
- "g" ((USItype) (v))); \
- (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
- ({UDItype __w; \
- __asm__ ("meid %2,%0" \
- : "=g" (__w) \
- : "%0" ((USItype) (u)), \
- "g" ((USItype) (v))); \
- __w; })
- ({union {UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
- __asm__ ("deid %2,%0" \
- : "=g" (__xx.__ll) \
- : "0" (__xx.__ll), \
- "g" ((USItype) (d))); \
- (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
- do { \
- __asm__ ("ffsd %2,%0" \
- : "=r" ((USItype) (count)) \
- : "0" ((USItype) 0), \
- "r" ((USItype) (x))); \
- } while (0)
- || defined (__powerpc__) \
- || defined (__POWERPC__) \
- || defined (__ppc__) \
- || (defined (PPC) && ! defined (CPU_FAMILY)) \
- || (defined (PPC) && defined (CPU_FAMILY) \
- && CPU_FAMILY == PPC) \
- ) && W_TYPE_SIZE == 32
- do { \
- if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
- __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
- else \
- __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
- : "=r" (sh), "=&r" (sl) \
- : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
- } while (0)
- do { \
- if (__builtin_constant_p (ah) && (ah) == 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
- else \
- __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
- : "=r" (sh), "=&r" (sl) \
- : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
- } while (0)
- __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
- || defined (__ppc__) \
- || (defined (PPC) && ! defined (CPU_FAMILY)) \
- || (defined (PPC) && defined (CPU_FAMILY) \
- && CPU_FAMILY == PPC)
- do { \
- USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
- (pl) = __m0 * __m1; \
- } while (0)
- do { \
- SItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
- (pl) = __m0 * __m1; \
- } while (0)
- do { \
- if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
- __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
- else \
- __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
- : "=r" (sh), "=&r" (sl) \
- : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
- } while (0)
- do { \
- if (__builtin_constant_p (ah) && (ah) == 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
- else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
- __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
- : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
- else \
- __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
- : "=r" (sh), "=&r" (sl) \
- : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
- } while (0)
- __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
- do { \
- UDItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
- (pl) = __m0 * __m1; \
- } while (0)
- do { \
- DItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
- (pl) = __m0 * __m1; \
- } while (0)
- __asm__ ("a %1,%5\n\tae %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "r" ((USItype) (bl)))
- __asm__ ("s %1,%5\n\tse %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "r" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "r" ((USItype) (bl)))
- do { \
- USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ( \
- "s r2,r2\n" \
- " mts r10,%2\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " m r2,%3\n" \
- " cas %0,r2,r0\n" \
- " mfs r10,%1" \
- : "=r" ((USItype) (ph)), \
- "=r" ((USItype) (pl)) \
- : "%r" (__m0), \
- "r" (__m1) \
- : "r2"); \
- (ph) += ((((SItype) __m0 >> 31) & __m1) \
- + (((SItype) __m1 >> 31) & __m0)); \
- } while (0)
- do { \
- if ((x) >= 0x10000) \
- __asm__ ("clz %0,%1" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x) >> 16)); \
- else \
- { \
- __asm__ ("clz %0,%1" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x))); \
- (count) += 16; \
- } \
- } while (0)
- __asm__ ( \
- "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
- : "=r<" ((USItype)(w1)), \
- "=r<" ((USItype)(w0)) \
- : "r" ((USItype)(u)), \
- "r" ((USItype)(v)) \
- : "macl", "mach")
- do { \
- extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
- __attribute__ ((visibility ("hidden"))); \
- \
- __asm__ ( \
- "mov%M4 %4,r5\n" \
- " swap.w %3,r4\n" \
- " swap.w r5,r6\n" \
- " mov.l @%5,r2\n" \
- " jsr @r2\n" \
- " shll16 r6\n" \
- " swap.w r4,r4\n" \
- " mov.l @%5,r2\n" \
- " jsr @r2\n" \
- " swap.w r1,%0\n" \
- " or r1,%0" \
- : "=r" (q), "=&z" (r) \
- : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
- : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
- } while (0)
- do { \
- extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
- __attribute__ ((visibility ("hidden"))); \
- \
- __asm__ ( \
- "mov%M4 %4,r5\n" \
- " swap.w %3,r4\n" \
- " swap.w r5,r6\n" \
- " jsr @%5\n" \
- " shll16 r6\n" \
- " swap.w r4,r4\n" \
- " jsr @%5\n" \
- " swap.w r1,%0\n" \
- " or r1,%0" \
- : "=r" (q), "=&z" (r) \
- : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
- : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
- } while (0)
- __asm__ ("clrt;subc %5,%1; subc %4,%0" \
- : "=r" (sh), "=r" (sl) \
- : "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
- do \
- { \
- UDItype x_ = (USItype)(x); \
- SItype c_; \
- \
- __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
- (count) = c_ - 31; \
- } \
- while (0)
- && W_TYPE_SIZE == 32
- __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "%rJ" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "%rJ" ((USItype) (al)), \
- "rI" ((USItype) (bl)) \
- __CLOBBER_CC)
- __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
- : "rJ" ((USItype) (ah)), \
- "rI" ((USItype) (bh)), \
- "rJ" ((USItype) (al)), \
- "rI" ((USItype) (bl)) \
- __CLOBBER_CC)
- do { \
- register USItype __g1 asm ("g1"); \
- __asm__ ("umul\t%2,%3,%1\n\t" \
- "srlx\t%1, 32, %0" \
- : "=r" ((USItype) (w1)), \
- "=r" (__g1) \
- : "r" ((USItype) (u)), \
- "r" ((USItype) (v))); \
- (w0) = __g1; \
- } while (0)
- __asm__ ("mov\t%2,%%y\n\t" \
- "udiv\t%3,%4,%0\n\t" \
- "umul\t%0,%4,%1\n\t" \
- "sub\t%3,%1,%1" \
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
- : "r" ((USItype) (__n1)), \
- "r" ((USItype) (__n0)), \
- "r" ((USItype) (__d)))
- __asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
- : "r" ((USItype) (u)), \
- "r" ((USItype) (v)))
- __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
- : "r" ((USItype) (__n1)), \
- "r" ((USItype) (__n0)), \
- "r" ((USItype) (__d)))
- __asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
- : "r" ((USItype) (u)), \
- "r" ((USItype) (v)))
- __asm__ ("! Inlined udiv_qrnnd\n" \
- " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
- " tst %%g0\n" \
- " divscc %3,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%%g1\n" \
- " divscc %%g1,%4,%0\n" \
- " rd %%y,%1\n" \
- " bl,a 1f\n" \
- " add %1,%4,%1\n" \
- "1: ! End of inline udiv_qrnnd" \
- : "=r" ((USItype) (q)), \
- "=r" ((USItype) (r)) \
- : "r" ((USItype) (n1)), \
- "r" ((USItype) (n0)), \
- "rI" ((USItype) (d)) \
- : "g1" __AND_CLOBBER_CC)
- do { \
- __asm__ ("scan %1,1,%0" \
- : "=r" ((USItype) (count)) \
- : "r" ((USItype) (x))); \
- } while (0)
- __asm__ ("! Inlined umul_ppmm\n" \
- " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
- " sra %3,31,%%o5 ! Don't move this insn\n" \
- " and %2,%%o5,%%o5 ! Don't move this insn\n" \
- " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,%3,%%g1\n" \
- " mulscc %%g1,0,%%g1\n" \
- " add %%g1,%%o5,%0\n" \
- " rd %%y,%1" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
- : "%rI" ((USItype) (u)), \
- "r" ((USItype) (v)) \
- : "g1", "o5" __AND_CLOBBER_CC)
- __asm__ ("! Inlined udiv_qrnnd\n" \
- " mov 32,%%g1\n" \
- " subcc %1,%2,%%g0\n" \
- "1: bcs 5f\n" \
- " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
- " sub %1,%2,%1 ! this kills msb of n\n" \
- " addx %1,%1,%1 ! so this can't give carry\n" \
- " subcc %%g1,1,%%g1\n" \
- "2: bne 1b\n" \
- " subcc %1,%2,%%g0\n" \
- " bcs 3f\n" \
- " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
- " b 3f\n" \
- " sub %1,%2,%1 ! this kills msb of n\n" \
- "4: sub %1,%2,%1\n" \
- "5: addxcc %1,%1,%1\n" \
- " bcc 2b\n" \
- " subcc %%g1,1,%%g1\n" \
- "! Got carry from n. Subtract next step to cancel this carry.\n" \
- " bne 4b\n" \
- " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
- " sub %1,%2,%1\n" \
- "3: xnor %0,0,%0\n" \
- " ! End of inline udiv_qrnnd" \
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
- : "r" ((USItype) (__d)), \
- "1" ((USItype) (__n1)), \
- "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
- && W_TYPE_SIZE == 64
- do { \
- UDItype __carry = 0; \
- __asm__ ("addcc\t%r5,%6,%1\n\t" \
- "add\t%r3,%4,%0\n\t" \
- "movcs\t%%xcc, 1, %2\n\t" \
- "add\t%0, %2, %0" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)), \
- "+r" (__carry) \
- : "%rJ" ((UDItype)(ah)), \
- "rI" ((UDItype)(bh)), \
- "%rJ" ((UDItype)(al)), \
- "rI" ((UDItype)(bl)) \
- __CLOBBER_CC); \
- } while (0)
- do { \
- UDItype __carry = 0; \
- __asm__ ("subcc\t%r5,%6,%1\n\t" \
- "sub\t%r3,%4,%0\n\t" \
- "movcs\t%%xcc, 1, %2\n\t" \
- "sub\t%0, %2, %0" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)), \
- "+r" (__carry) \
- : "%rJ" ((UDItype)(ah)), \
- "rI" ((UDItype)(bh)), \
- "%rJ" ((UDItype)(al)), \
- "rI" ((UDItype)(bl)) \
- __CLOBBER_CC); \
- } while (0)
- do { \
- UDItype tmp1, tmp2, tmp3, tmp4; \
- __asm__ __volatile__ ( \
- "srl %7,0,%3\n\t" \
- "mulx %3,%6,%1\n\t" \
- "srlx %6,32,%2\n\t" \
- "mulx %2,%3,%4\n\t" \
- "sllx %4,32,%5\n\t" \
- "srl %6,0,%3\n\t" \
- "sub %1,%5,%5\n\t" \
- "srlx %5,32,%5\n\t" \
- "addcc %4,%5,%4\n\t" \
- "srlx %7,32,%5\n\t" \
- "mulx %3,%5,%3\n\t" \
- "mulx %2,%5,%5\n\t" \
- "sethi %%hi(0x80000000),%2\n\t" \
- "addcc %4,%3,%4\n\t" \
- "srlx %4,32,%4\n\t" \
- "add %2,%2,%2\n\t" \
- "movcc %%xcc,%%g0,%2\n\t" \
- "addcc %5,%4,%5\n\t" \
- "sllx %3,32,%3\n\t" \
- "add %1,%3,%1\n\t" \
- "add %5,%2,%0" \
- : "=r" ((UDItype)(wh)), \
- "=&r" ((UDItype)(wl)), \
- "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
- : "r" ((UDItype)(u)), \
- "r" ((UDItype)(v)) \
- __CLOBBER_CC); \
- } while (0)
- __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
- : "%0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "%1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
- : "0" ((USItype) (ah)), \
- "g" ((USItype) (bh)), \
- "1" ((USItype) (al)), \
- "g" ((USItype) (bl)))
- do { \
- union { \
- UDItype __ll; \
- struct {USItype __l, __h;} __i; \
- } __xx; \
- USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("emul %1,%2,$0,%0" \
- : "=r" (__xx.__ll) \
- : "g" (__m0), \
- "g" (__m1)); \
- (xh) = __xx.__i.__h; \
- (xl) = __xx.__i.__l; \
- (xh) += ((((SItype) __m0 >> 31) & __m1) \
- + (((SItype) __m1 >> 31) & __m0)); \
- } while (0)
- do { \
- union {DItype __ll; \
- struct {SItype __l, __h;} __i; \
- } __xx; \
- __xx.__i.__h = n1; __xx.__i.__l = n0; \
- __asm__ ("ediv %3,%2,%0,%1" \
- : "=g" (q), "=g" (r) \
- : "g" (__xx.__ll), "g" (d)); \
- } while (0)
- do \
- { \
- UDItype __ll; \
- __asm__ ("addu .l1 %1, %2, %0" \
- : "=a" (__ll) : "a" (al), "a" (bl)); \
- (sl) = (USItype)__ll; \
- (sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
- } \
- while (0)
- do { \
- UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
- (w1) = (USItype) (__x >> 32); \
- (w0) = (USItype) (__x); \
- } while (0)
- do { \
- DWunion __w; \
- __w.ll = __builtin_umulsidi3 (u, v); \
- w1 = __w.s.high; \
- w0 = __w.s.low; \
- } while (0)
- extern UHItype __stormy16_count_leading_zeros (UHItype);
- do \
- { \
- UHItype size; \
- \
- \
- for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
- { \
- UHItype c; \
- \
- c = __clzhi2 ((x) >> (size - 16)); \
- (count) += c; \
- if (c != 16) \
- break; \
- } \
- } \
- while (0)
- __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), \
- "=&r" ((unsigned int)(sl)) \
- : "%0" ((unsigned int)(ah)), \
- "r" ((unsigned int)(bh)), \
- "%1" ((unsigned int)(al)), \
- "rQR" ((unsigned int)(bl)))
- __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), \
- "=&r" ((unsigned int)(sl)) \
- : "0" ((unsigned int)(ah)), \
- "r" ((unsigned int)(bh)), \
- "1" ((unsigned int)(al)), \
- "rQR" ((unsigned int)(bl)))
- do { \
- union {long int __ll; \
- struct {unsigned int __h, __l;} __i; \
- } __xx; \
- unsigned int __m0 = (m0), __m1 = (m1); \
- __asm__ ("mult %S0,%H3" \
- : "=r" (__xx.__i.__h), \
- "=r" (__xx.__i.__l) \
- : "%1" (__m0), \
- "rQR" (__m1)); \
- (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
- (xh) += ((((signed int) __m0 >> 15) & __m1) \
- + (((signed int) __m1 >> 15) & __m0)); \
- } while (0)
- do { \
- UWtype __x; \
- __x = (al) + (bl); \
- (sh) = (ah) + (bh) + (__x < (al)); \
- (sl) = __x; \
- } while (0)
- do { \
- UWtype __x; \
- __x = (al) - (bl); \
- (sh) = (ah) - (bh) - (__x > (al)); \
- (sl) = __x; \
- } while (0)
- do { \
- UWtype __w1; \
- UWtype __xm0 = (u), __xm1 = (v); \
- smul_ppmm (__w1, w0, __xm0, __xm1); \
- (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
- + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
- } while (0)
- do { \
- UWtype __x0, __x1, __x2, __x3; \
- UHWtype __ul, __vl, __uh, __vh; \
- \
- __ul = __ll_lowpart (u); \
- __uh = __ll_highpart (u); \
- __vl = __ll_lowpart (v); \
- __vh = __ll_highpart (v); \
- \
- __x0 = (UWtype) __ul * __vl; \
- __x1 = (UWtype) __ul * __vh; \
- __x2 = (UWtype) __uh * __vl; \
- __x3 = (UWtype) __uh * __vh; \
- \
- __x1 += __ll_highpart (__x0); \
- __x1 += __x2; \
- if (__x1 < __x2) \
- __x3 += __ll_B; \
- \
- (w1) = __x3 + __ll_highpart (__x1); \
- (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
- } while (0)
- ({DWunion __w; \
- umul_ppmm (__w.s.high, __w.s.low, u, v); \
- __w.ll; })
- do { \
- UWtype __d1, __d0, __q1, __q0; \
- UWtype __r1, __r0, __m; \
- __d1 = __ll_highpart (d); \
- __d0 = __ll_lowpart (d); \
- \
- __r1 = (n1) % __d1; \
- __q1 = (n1) / __d1; \
- __m = (UWtype) __q1 * __d0; \
- __r1 = __r1 * __ll_B | __ll_highpart (n0); \
- if (__r1 < __m) \
- { \
- __q1--, __r1 += (d); \
- if (__r1 >= (d)) \
- if (__r1 < __m) \
- __q1--, __r1 += (d); \
- } \
- __r1 -= __m; \
- \
- __r0 = __r1 % __d1; \
- __q0 = __r1 / __d1; \
- __m = (UWtype) __q0 * __d0; \
- __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
- if (__r0 < __m) \
- { \
- __q0--, __r0 += (d); \
- if (__r0 >= (d)) \
- if (__r0 < __m) \
- __q0--, __r0 += (d); \
- } \
- __r0 -= __m; \
- \
- (q) = (UWtype) __q1 * __ll_B | __q0; \
- (r) = __r0; \
- } while (0)
- do { \
- extern UWtype __udiv_w_sdiv (UWtype *, UWtype, UWtype, UWtype); \
- UWtype __r; \
- (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
- (r) = __r; \
- } while (0)
- do { \
- UWtype __xr = (x); \
- UWtype __a; \
- \
- if (W_TYPE_SIZE <= 32) \
- { \
- __a = __xr < ((UWtype)1<<2*__BITS4) \
- ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
- : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
- } \
- else \
- { \
- for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
- if (((__xr >> __a) & 0xff) != 0) \
- break; \
- } \
- \
- (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
- } while (0)
- do { \
- UWtype __ctz_x = (x); \
- UWtype __ctz_c; \
- count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
- (count) = W_TYPE_SIZE - 1 - __ctz_c; \
- } while (0)
|