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ml605.dts 13 KB

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  1. /dts-v1/;
  2. / {
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. compatible = "xlnx,microblaze";
  6. model = "petalogix-ml605";
  7. ddr3_sdram: memory@50000000 {
  8. device_type = "memory";
  9. reg = < 0x50000000 0x4000000 >;
  10. } ;
  11. aliases {
  12. ethernet0 = &ethernet;
  13. serial0 = &rs232_uart_1;
  14. } ;
  15. chosen {
  16. bootargs = "console=ttyS0,115200";
  17. linux,stdout-path = "/axi@1/serial@83e00000";
  18. } ;
  19. cpus {
  20. #address-cells = <1>;
  21. #cpus = <0x1>;
  22. #size-cells = <0>;
  23. microblaze_0: cpu@0 {
  24. clock-frequency = <100000000>;
  25. compatible = "xlnx,microblaze-8.40.a";
  26. d-cache-baseaddr = <0x50000000>;
  27. d-cache-highaddr = <0x53ffffff>;
  28. d-cache-line-size = <0x10>;
  29. d-cache-size = <0x8000>;
  30. device_type = "cpu";
  31. i-cache-baseaddr = <0x50000000>;
  32. i-cache-highaddr = <0x53ffffff>;
  33. i-cache-line-size = <0x10>;
  34. i-cache-size = <0x8000>;
  35. model = "microblaze,8.40.a";
  36. reg = <0>;
  37. timebase-frequency = <100000000>;
  38. xlnx,addr-tag-bits = <0xb>;
  39. xlnx,allow-dcache-wr = <0x1>;
  40. xlnx,allow-icache-wr = <0x1>;
  41. xlnx,area-optimized = <0x0>;
  42. xlnx,avoid-primitives = <0x0>;
  43. xlnx,branch-target-cache-size = <0x0>;
  44. xlnx,cache-byte-size = <0x8000>;
  45. xlnx,d-axi = <0x1>;
  46. xlnx,d-lmb = <0x1>;
  47. xlnx,d-plb = <0x0>;
  48. xlnx,data-size = <0x20>;
  49. xlnx,dcache-addr-tag = <0xb>;
  50. xlnx,dcache-always-used = <0x1>;
  51. xlnx,dcache-byte-size = <0x8000>;
  52. xlnx,dcache-data-width = <0x0>;
  53. xlnx,dcache-force-tag-lutram = <0x0>;
  54. xlnx,dcache-interface = <0x0>;
  55. xlnx,dcache-line-len = <0x4>;
  56. xlnx,dcache-use-fsl = <0x0>;
  57. xlnx,dcache-use-writeback = <0x0>;
  58. xlnx,dcache-victims = <0x0>;
  59. xlnx,debug-enabled = <0x0>;
  60. xlnx,div-zero-exception = <0x1>;
  61. xlnx,dynamic-bus-sizing = <0x1>;
  62. xlnx,ecc-use-ce-exception = <0x0>;
  63. xlnx,edge-is-positive = <0x1>;
  64. xlnx,endianness = <0x1>;
  65. xlnx,family = "virtex6";
  66. xlnx,fault-tolerant = <0x0>;
  67. xlnx,fpu-exception = <0x1>;
  68. xlnx,freq = <0x5f5e100>;
  69. xlnx,fsl-data-size = <0x20>;
  70. xlnx,fsl-exception = <0x0>;
  71. xlnx,fsl-links = <0x0>;
  72. xlnx,i-axi = <0x1>;
  73. xlnx,i-lmb = <0x1>;
  74. xlnx,i-plb = <0x0>;
  75. xlnx,icache-always-used = <0x1>;
  76. xlnx,icache-data-width = <0x0>;
  77. xlnx,icache-force-tag-lutram = <0x0>;
  78. xlnx,icache-interface = <0x0>;
  79. xlnx,icache-line-len = <0x4>;
  80. xlnx,icache-streams = <0x0>;
  81. xlnx,icache-use-fsl = <0x0>;
  82. xlnx,icache-victims = <0x0>;
  83. xlnx,ill-opcode-exception = <0x1>;
  84. xlnx,instance = "microblaze_0";
  85. xlnx,interconnect = <0x2>;
  86. xlnx,interrupt-is-edge = <0x0>;
  87. xlnx,lockstep-slave = <0x0>;
  88. xlnx,mmu-dtlb-size = <0x2>;
  89. xlnx,mmu-itlb-size = <0x4>;
  90. xlnx,mmu-privileged-instr = <0x0>;
  91. xlnx,mmu-tlb-access = <0x3>;
  92. xlnx,mmu-zones = <0x2>;
  93. xlnx,number-of-pc-brk = <0x1>;
  94. xlnx,number-of-rd-addr-brk = <0x0>;
  95. xlnx,number-of-wr-addr-brk = <0x0>;
  96. xlnx,opcode-0x0-illegal = <0x0>;
  97. xlnx,optimization = <0x0>;
  98. xlnx,pc-width = <0x20>;
  99. xlnx,pvr = <0x2>;
  100. xlnx,pvr-user1 = <0x0>;
  101. xlnx,pvr-user2 = <0x0>;
  102. xlnx,reset-msr = <0x0>;
  103. xlnx,sco = <0x0>;
  104. xlnx,stream-interconnect = <0x0>;
  105. xlnx,unaligned-exceptions = <0x0>;
  106. xlnx,use-barrel = <0x1>;
  107. xlnx,use-branch-target-cache = <0x0>;
  108. xlnx,use-dcache = <0x1>;
  109. xlnx,use-div = <0x1>;
  110. xlnx,use-ext-brk = <0x1>;
  111. xlnx,use-ext-nm-brk = <0x1>;
  112. xlnx,use-extended-fsl-instr = <0x0>;
  113. xlnx,use-fpu = <0x1>;
  114. xlnx,use-hw-mul = <0x2>;
  115. xlnx,use-icache = <0x1>;
  116. xlnx,use-interrupt = <0x1>;
  117. xlnx,use-mmu = <0x3>;
  118. xlnx,use-msr-instr = <0x1>;
  119. xlnx,use-pcmp-instr = <0x1>;
  120. xlnx,use-reorder-instr = <0x1>;
  121. xlnx,use-stack-protection = <0x0>;
  122. } ;
  123. } ;
  124. axi4_0: axi@0 {
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
  128. ranges ;
  129. } ;
  130. axi4lite_0: axi@1 {
  131. #address-cells = <1>;
  132. #size-cells = <1>;
  133. compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
  134. ranges ;
  135. ethernet: axi-ethernet@82780000 {
  136. axistream-connected = <&ethernet_dma>;
  137. axistream-control-connected = <&ethernet_dma>;
  138. clock-frequency = <100000000>;
  139. compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
  140. device_type = "network";
  141. interrupt-parent = <&microblaze_0_intc>;
  142. interrupts = < 3 2 >;
  143. local-mac-address = [ 00 0a 35 00 81 91 ];
  144. phy-handle = <&phy0>;
  145. reg = < 0x82780000 0x40000 >;
  146. xlnx,avb = <0x0>;
  147. xlnx,halfdup = <0x0>;
  148. xlnx,include-io = <0x1>;
  149. xlnx,mcast-extend = <0x0>;
  150. xlnx,phy-type = <0x1>;
  151. xlnx,phyaddr = "0B00001";
  152. xlnx,rxcsum = <0x0>;
  153. xlnx,rxmem = <0x1000>;
  154. xlnx,rxvlan-strp = <0x0>;
  155. xlnx,rxvlan-tag = <0x0>;
  156. xlnx,rxvlan-tran = <0x0>;
  157. xlnx,stats = <0x0>;
  158. xlnx,txcsum = <0x0>;
  159. xlnx,txmem = <0x1000>;
  160. xlnx,txvlan-strp = <0x0>;
  161. xlnx,txvlan-tag = <0x0>;
  162. xlnx,txvlan-tran = <0x0>;
  163. xlnx,type = <0x2>;
  164. mdio {
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. phy0: phy@7 {
  168. compatible = "marvell,88e1111";
  169. device_type = "ethernet-phy";
  170. reg = <7>;
  171. } ;
  172. } ;
  173. } ;
  174. ethernet_dma: axi-dma@84600000 {
  175. axistream-connected = <&ethernet>;
  176. axistream-control-connected = <&ethernet>;
  177. compatible = "xlnx,axi-dma-4.00.a", "xlnx,axi-dma-1.00.a";
  178. interrupt-parent = <&microblaze_0_intc>;
  179. interrupts = < 1 2 0 2 >;
  180. reg = < 0x84600000 0x10000 >;
  181. xlnx,dlytmr-resolution = <0x4e2>;
  182. xlnx,family = "virtex6";
  183. xlnx,include-mm2s = <0x1>;
  184. xlnx,include-mm2s-dre = <0x1>;
  185. xlnx,include-s2mm = <0x1>;
  186. xlnx,include-s2mm-dre = <0x1>;
  187. xlnx,include-sg = <0x1>;
  188. xlnx,mm2s-burst-size = <0x10>;
  189. xlnx,prmry-is-aclk-async = <0x0>;
  190. xlnx,s2mm-burst-size = <0x10>;
  191. xlnx,sg-include-desc-queue = <0x1>;
  192. xlnx,sg-include-stscntrl-strm = <0x1>;
  193. xlnx,sg-length-width = <0x10>;
  194. xlnx,sg-use-stsapp-length = <0x1>;
  195. } ;
  196. rs232_uart_1: serial@83e00000 {
  197. clock-frequency = <100000000>;
  198. compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
  199. current-speed = <115200>;
  200. device_type = "serial";
  201. interrupt-parent = <&microblaze_0_intc>;
  202. interrupts = < 5 2 >;
  203. reg = < 0x83e00000 0x10000 >;
  204. reg-offset = <0x1000>;
  205. reg-shift = <2>;
  206. xlnx,external-xin-clk-hz = <0x17d7840>;
  207. xlnx,family = "virtex6";
  208. xlnx,has-external-rclk = <0x0>;
  209. xlnx,has-external-xin = <0x0>;
  210. xlnx,instance = "RS232_Uart_1";
  211. xlnx,is-a-16550 = <0x1>;
  212. xlnx,use-modem-ports = <0x0>;
  213. xlnx,use-user-ports = <0x0>;
  214. } ;
  215. pflash: flash@86000000 {
  216. #address-cells = <1>;
  217. #size-cells = <1>;
  218. compatible = "xlnx,axi-emc-1.03.a", "cfi-flash";
  219. bank-width = <2>;
  220. reg = < 0x86000000 0x02000000 >;
  221. xlnx,axi-clk-period-ps = <0x2710>;
  222. xlnx,family = "virtex6";
  223. xlnx,include-datawidth-matching-0 = <0x1>;
  224. xlnx,include-datawidth-matching-1 = <0x0>;
  225. xlnx,include-datawidth-matching-2 = <0x0>;
  226. xlnx,include-datawidth-matching-3 = <0x0>;
  227. xlnx,include-negedge-ioregs = <0x0>;
  228. xlnx,instance = "Linear_Flash";
  229. xlnx,lflash-period-ps = <0x4e20>;
  230. xlnx,linear-flash-sync-burst = <0x0>;
  231. xlnx,max-mem-width = <0x10>;
  232. xlnx,mem0-type = <0x2>;
  233. xlnx,mem0-width = <0x10>;
  234. xlnx,mem1-type = <0x0>;
  235. xlnx,mem1-width = <0x20>;
  236. xlnx,mem2-type = <0x0>;
  237. xlnx,mem2-width = <0x20>;
  238. xlnx,mem3-type = <0x0>;
  239. xlnx,mem3-width = <0x20>;
  240. xlnx,num-banks-mem = <0x1>;
  241. xlnx,parity-type-mem-0 = <0x0>;
  242. xlnx,parity-type-mem-1 = <0x0>;
  243. xlnx,parity-type-mem-2 = <0x0>;
  244. xlnx,parity-type-mem-3 = <0x0>;
  245. xlnx,s-axi-en-reg = <0x0>;
  246. xlnx,s-axi-mem-addr-width = <0x20>;
  247. xlnx,s-axi-mem-data-width = <0x20>;
  248. xlnx,s-axi-mem-id-width = <0x1>;
  249. xlnx,s-axi-mem-protocol = "AXI4LITE";
  250. xlnx,s-axi-reg-addr-width = <0x5>;
  251. xlnx,s-axi-reg-data-width = <0x20>;
  252. xlnx,s-axi-reg-protocol = "axi4";
  253. xlnx,synch-pipedelay-0 = <0x2>;
  254. xlnx,synch-pipedelay-1 = <0x2>;
  255. xlnx,synch-pipedelay-2 = <0x2>;
  256. xlnx,synch-pipedelay-3 = <0x2>;
  257. xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
  258. xlnx,tavdv-ps-mem-1 = <0x3a98>;
  259. xlnx,tavdv-ps-mem-2 = <0x3a98>;
  260. xlnx,tavdv-ps-mem-3 = <0x3a98>;
  261. xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
  262. xlnx,tcedv-ps-mem-1 = <0x3a98>;
  263. xlnx,tcedv-ps-mem-2 = <0x3a98>;
  264. xlnx,tcedv-ps-mem-3 = <0x3a98>;
  265. xlnx,thzce-ps-mem-0 = <0x88b8>;
  266. xlnx,thzce-ps-mem-1 = <0x1b58>;
  267. xlnx,thzce-ps-mem-2 = <0x1b58>;
  268. xlnx,thzce-ps-mem-3 = <0x1b58>;
  269. xlnx,thzoe-ps-mem-0 = <0x1b58>;
  270. xlnx,thzoe-ps-mem-1 = <0x1b58>;
  271. xlnx,thzoe-ps-mem-2 = <0x1b58>;
  272. xlnx,thzoe-ps-mem-3 = <0x1b58>;
  273. xlnx,tlzwe-ps-mem-0 = <0x88b8>;
  274. xlnx,tlzwe-ps-mem-1 = <0x0>;
  275. xlnx,tlzwe-ps-mem-2 = <0x0>;
  276. xlnx,tlzwe-ps-mem-3 = <0x0>;
  277. xlnx,tpacc-ps-flash-0 = <0x61a8>;
  278. xlnx,tpacc-ps-flash-1 = <0x61a8>;
  279. xlnx,tpacc-ps-flash-2 = <0x61a8>;
  280. xlnx,tpacc-ps-flash-3 = <0x61a8>;
  281. xlnx,twc-ps-mem-0 = <0x11170>;
  282. xlnx,twc-ps-mem-1 = <0x3a98>;
  283. xlnx,twc-ps-mem-2 = <0x3a98>;
  284. xlnx,twc-ps-mem-3 = <0x3a98>;
  285. xlnx,twp-ps-mem-0 = <0x11170>;
  286. xlnx,twp-ps-mem-1 = <0x2ee0>;
  287. xlnx,twp-ps-mem-2 = <0x2ee0>;
  288. xlnx,twp-ps-mem-3 = <0x2ee0>;
  289. xlnx,twph-ps-mem-0 = <0x2ee0>;
  290. xlnx,twph-ps-mem-1 = <0x2ee0>;
  291. xlnx,twph-ps-mem-2 = <0x2ee0>;
  292. xlnx,twph-ps-mem-3 = <0x2ee0>;
  293. xlnx,wr-rec-time-mem-0 = <0x186a0>;
  294. xlnx,wr-rec-time-mem-1 = <0x186a0>;
  295. xlnx,wr-rec-time-mem-2 = <0x186a0>;
  296. xlnx,wr-rec-time-mem-3 = <0x186a0>;
  297. partition@0x00000000 {
  298. label = "rootfs";
  299. reg = <0x00000000 0x02000000>;
  300. };
  301. } ;
  302. microblaze_0_intc: interrupt-controller@81800000 {
  303. #interrupt-cells = <0x2>;
  304. compatible = "xlnx,axi-intc-1.02.a", "xlnx,xps-intc-1.00.a";
  305. interrupt-controller ;
  306. reg = < 0x81800000 0x10000 >;
  307. xlnx,kind-of-intr = <0x0>;
  308. xlnx,num-intr-inputs = <0x7>;
  309. } ;
  310. system_timer: system-timer@83c00000 {
  311. clock-frequency = <100000000>;
  312. compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
  313. interrupt-parent = <&microblaze_0_intc>;
  314. interrupts = < 2 2 >;
  315. reg = < 0x83c00000 0x10000 >;
  316. xlnx,count-width = <0x20>;
  317. xlnx,family = "virtex6";
  318. xlnx,gen0-assert = <0x1>;
  319. xlnx,gen1-assert = <0x1>;
  320. xlnx,instance = "system_timer";
  321. xlnx,one-timer-only = <0x0>;
  322. xlnx,trig0-assert = <0x1>;
  323. xlnx,trig1-assert = <0x1>;
  324. } ;
  325. axi_pcie_0: axi-pcie@80000000 {
  326. #address-cells = <2>;
  327. #size-cells = <2>;
  328. compatible = "xlnx,axi-pcie-1.05.a";
  329. interrupt-parent = <&microblaze_0_intc>;
  330. interrupts = < 6 2 >;
  331. ranges = < 0x00000002 0x00000000 0x40000000 0x70000000 0x00000000 0x00000000 0x10000000 >;
  332. reg = < 0x80000000 0x1000000 >;
  333. xlnx,axi-aclk-freq-hz = <0x7735940>;
  334. xlnx,axibar-0 = <0x70000000>;
  335. xlnx,axibar-1 = <0xffffffff>;
  336. xlnx,axibar-2 = <0xffffffff>;
  337. xlnx,axibar-3 = <0xffffffff>;
  338. xlnx,axibar-4 = <0xffffffff>;
  339. xlnx,axibar-5 = <0xffffffff>;
  340. xlnx,axibar-as-0 = <0x0>;
  341. xlnx,axibar-as-1 = <0x0>;
  342. xlnx,axibar-as-2 = <0x0>;
  343. xlnx,axibar-as-3 = <0x0>;
  344. xlnx,axibar-as-4 = <0x0>;
  345. xlnx,axibar-as-5 = <0x0>;
  346. xlnx,axibar-highaddr-0 = <0x7fffffff>;
  347. xlnx,axibar-highaddr-1 = <0x0>;
  348. xlnx,axibar-highaddr-2 = <0x0>;
  349. xlnx,axibar-highaddr-3 = <0x0>;
  350. xlnx,axibar-highaddr-4 = <0x0>;
  351. xlnx,axibar-highaddr-5 = <0x0>;
  352. xlnx,axibar-num = <0x1>;
  353. xlnx,axibar2pciebar-0 = <0x40000000>;
  354. xlnx,axibar2pciebar-1 = <0x0>;
  355. xlnx,axibar2pciebar-2 = <0x0>;
  356. xlnx,axibar2pciebar-3 = <0x0>;
  357. xlnx,axibar2pciebar-4 = <0x0>;
  358. xlnx,axibar2pciebar-5 = <0x0>;
  359. xlnx,class-code = <0x60400>;
  360. xlnx,comp-timeout = <0x1>;
  361. xlnx,device-id = <0x705>;
  362. xlnx,family = "virtex6";
  363. xlnx,include-baroffset-reg = <0x0>;
  364. xlnx,include-rc = <0x1>;
  365. xlnx,instance = "axi_pcie_0";
  366. xlnx,interrupt-pin = <0x0>;
  367. xlnx,max-link-speed = <0x0>;
  368. xlnx,no-of-lanes = <0x1>;
  369. xlnx,num-msi-req = <0x0>;
  370. xlnx,pcie-cap-slot-implemented = <0x0>;
  371. xlnx,pcie-use-mode = "1.0";
  372. xlnx,pciebar-as = <0x0>;
  373. xlnx,pciebar-len-0 = <0x1c>;
  374. xlnx,pciebar-len-1 = <0xd>;
  375. xlnx,pciebar-len-2 = <0xd>;
  376. xlnx,pciebar-num = <0x1>;
  377. xlnx,pciebar2axibar-0 = <0xc0000000>;
  378. xlnx,pciebar2axibar-0-sec = <0x0>;
  379. xlnx,pciebar2axibar-1 = <0xffffffff>;
  380. xlnx,pciebar2axibar-1-sec = <0x0>;
  381. xlnx,pciebar2axibar-2 = <0xffffffff>;
  382. xlnx,pciebar2axibar-2-sec = <0x0>;
  383. xlnx,ref-clk-freq = <0x0>;
  384. xlnx,ref-clk-freq-hz = <0x5f5e100>;
  385. xlnx,rev-id = <0x0>;
  386. xlnx,s-axi-ctl-aclk-freq-hz = <0x7735940>;
  387. xlnx,s-axi-ctl-protocol = "AXI4LITE";
  388. xlnx,s-axi-id-width = <0x1>;
  389. xlnx,s-axi-support-threads = <0x1>;
  390. xlnx,s-axi-supports-narrow-burst = <0x0>;
  391. xlnx,s-axi-supports-read = <0x1>;
  392. xlnx,s-axi-supports-write = <0x1>;
  393. xlnx,subsystem-id = <0x0>;
  394. xlnx,subsystem-vendor-id = <0x0>;
  395. xlnx,vendor-id = <0x10ee>;
  396. } ;
  397. } ;
  398. } ;