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j2-core.patch 56 KB

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  1. diff -Nur linux-4.1.13.orig/arch/sh/Kconfig linux-4.1.13/arch/sh/Kconfig
  2. --- linux-4.1.13.orig/arch/sh/Kconfig 2015-11-09 23:34:10.000000000 +0100
  3. +++ linux-4.1.13/arch/sh/Kconfig 2015-12-05 00:16:48.000000000 +0100
  4. @@ -66,7 +66,7 @@
  5. select HAVE_MIXED_BREAKPOINTS_REGS
  6. select PERF_EVENTS
  7. select ARCH_HIBERNATION_POSSIBLE if MMU
  8. - select SPARSE_IRQ
  9. + select SPARSE_IRQ if !CPU_SUBTYPE_0PF
  10. select HAVE_CC_STACKPROTECTOR
  11. config SUPERH64
  12. @@ -108,6 +108,9 @@
  13. config ARCH_HIBERNATION_POSSIBLE
  14. def_bool n
  15. +config ARCH_USES_GETTIMEOFFSET
  16. + def_bool n
  17. +
  18. config SYS_SUPPORTS_APM_EMULATION
  19. bool
  20. select ARCH_SUSPEND_POSSIBLE
  21. @@ -184,6 +187,11 @@
  22. select CPU_SH2
  23. select UNCACHED_MAPPING
  24. +config CPU_SH2J
  25. + bool
  26. + select CPU_SH2
  27. + select ARCH_USES_GETTIMEOFFSET
  28. +
  29. config CPU_SH3
  30. bool
  31. select CPU_HAS_INTEVT
  32. @@ -303,6 +311,12 @@
  33. help
  34. Select MX-G if running on an R8A03022BG part.
  35. +# SH-2J Processor Support
  36. +
  37. +config CPU_SUBTYPE_0PF
  38. + bool "Support 0PF J2 SoftCore"
  39. + select CPU_SH2J
  40. +
  41. # SH-3 Processor Support
  42. config CPU_SUBTYPE_SH7705
  43. @@ -753,6 +767,7 @@
  44. SH_7751_SOLUTION_ENGINE
  45. default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
  46. default "0x00002000" if PAGE_SIZE_8KB
  47. + default "0x0003F000" if CPU_SUBTYPE_0PF
  48. default "0x00001000"
  49. help
  50. This sets the default offset of zero page.
  51. diff -Nur linux-4.1.13.orig/arch/sh/Makefile linux-4.1.13/arch/sh/Makefile
  52. --- linux-4.1.13.orig/arch/sh/Makefile 2015-11-09 23:34:10.000000000 +0100
  53. +++ linux-4.1.13/arch/sh/Makefile 2015-12-05 00:16:48.000000000 +0100
  54. @@ -4,6 +4,7 @@
  55. # Copyright (C) 1999 Kaz Kojima
  56. # Copyright (C) 2002 - 2008 Paul Mundt
  57. # Copyright (C) 2002 M. R. Brown
  58. +# Copyright (C) 2012 SEI, Inc. (sh2j)
  59. #
  60. # This file is subject to the terms and conditions of the GNU General Public
  61. # License. See the file "COPYING" in the main directory of this archive
  62. @@ -19,6 +20,7 @@
  63. isa-$(CONFIG_SH_DSP) := sh
  64. isa-$(CONFIG_CPU_SH2) := sh2
  65. isa-$(CONFIG_CPU_SH2A) := sh2a
  66. +isa-$(CONFIG_CPU_SH2J) := sh2j
  67. isa-$(CONFIG_CPU_SH3) := sh3
  68. isa-$(CONFIG_CPU_SH4) := sh4
  69. isa-$(CONFIG_CPU_SH4A) := sh4a
  70. @@ -31,6 +33,8 @@
  71. endif
  72. cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
  73. +cflags-$(CONFIG_CPU_SH2J) := $(call cc-option,-m2,) \
  74. + $(call cc-option,-melf,)
  75. cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \
  76. $(call cc-option,-m2a-nofpu,) \
  77. $(call cc-option,-m4-nofpu,)
  78. @@ -91,6 +95,7 @@
  79. defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE) := uImage
  80. defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
  81. defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
  82. +defaultimage-$(CONFIG_SH_0PF) := vmlinux
  83. # Set some sensible Kbuild defaults
  84. KBUILD_IMAGE := $(defaultimage-y)
  85. @@ -173,6 +178,7 @@
  86. # As an example, in order of preference, SH-2A > SH-2 > common definitions.
  87. #
  88. cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a
  89. +cpuincdir-$(CONFIG_CPU_SH2J) += cpu-sh2j
  90. cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
  91. cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
  92. cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
  93. diff -Nur linux-4.1.13.orig/arch/sh/boards/Kconfig linux-4.1.13/arch/sh/boards/Kconfig
  94. --- linux-4.1.13.orig/arch/sh/boards/Kconfig 2015-11-09 23:34:10.000000000 +0100
  95. +++ linux-4.1.13/arch/sh/boards/Kconfig 2015-12-05 00:16:48.000000000 +0100
  96. @@ -90,6 +90,13 @@
  97. Select 7343 SolutionEngine if configuring for a Hitachi
  98. SH7343 (SH-Mobile 3AS) evaluation board.
  99. +config 0PF_FPGA
  100. + bool "0PF FPGA"
  101. + depends on CPU_SUBTYPE_0PF
  102. + help
  103. + Select 0PF_FPGA if you are configuring for an FPGA with
  104. + the SH2j-workalike SoftCore from http://0pf.org
  105. +
  106. config SH_HP6XX
  107. bool "HP6XX"
  108. select SYS_SUPPORTS_APM_EMULATION
  109. diff -Nur linux-4.1.13.orig/arch/sh/boards/Makefile linux-4.1.13/arch/sh/boards/Makefile
  110. --- linux-4.1.13.orig/arch/sh/boards/Makefile 2015-11-09 23:34:10.000000000 +0100
  111. +++ linux-4.1.13/arch/sh/boards/Makefile 2015-12-05 00:16:48.000000000 +0100
  112. @@ -15,3 +15,4 @@
  113. obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o
  114. obj-$(CONFIG_SH_APSH4A3A) += board-apsh4a3a.o
  115. obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o
  116. +obj-$(CONFIG_0PF_FPGA) += board-0pf.o
  117. diff -Nur linux-4.1.13.orig/arch/sh/boards/board-0pf.c linux-4.1.13/arch/sh/boards/board-0pf.c
  118. --- linux-4.1.13.orig/arch/sh/boards/board-0pf.c 1970-01-01 01:00:00.000000000 +0100
  119. +++ linux-4.1.13/arch/sh/boards/board-0pf.c 2015-12-05 00:16:48.000000000 +0100
  120. @@ -0,0 +1,270 @@
  121. +/*
  122. + * board-0pf.c
  123. + *
  124. + * Copyright (C) 2006 Yoshinori Sato
  125. + * Copyright (C) 2009 D. Jeff Dionne
  126. + *
  127. + * 0PF j-series CPU on FPGA
  128. + */
  129. +#include <linux/platform_device.h>
  130. +#include <linux/sched.h>
  131. +#include <linux/kernel.h>
  132. +#include <linux/param.h>
  133. +#include <linux/interrupt.h>
  134. +#include <linux/profile.h>
  135. +#include <linux/init.h>
  136. +#include <linux/irq.h>
  137. +#include <linux/device.h>
  138. +#include <linux/module.h>
  139. +#include <asm/io.h>
  140. +#include <asm/irq.h>
  141. +#include <asm/rtc.h>
  142. +#include <asm/machvec.h>
  143. +#include <asm/board-0pf.h>
  144. +
  145. +int shj_irq_demux(int irq)
  146. +{
  147. + return irq; /* punt.. */
  148. +}
  149. +
  150. +static void shj_ack_noop(struct irq_data *data)
  151. +{
  152. + asm("nop;nop");
  153. + /* Dummy function. */
  154. +}
  155. +
  156. +static inline void shj_enable_irq(struct irq_data *data)
  157. +{
  158. + unsigned int irq = data->irq;
  159. + volatile unsigned int vui;
  160. +
  161. +// printk("%s: IRQ %d (0x%x)\n", __func__, irq, irq);
  162. +
  163. + switch (irq) {
  164. + case PIT_IRQ:
  165. + //AQ_PIO = 0x0BB;
  166. + /* enable, lvl 2, vector 64 */
  167. + AQ_SYS = (1 << 26) | /* enable PIT */
  168. + (0x02 << 20) | /* interrupt level 2 */
  169. + (PIT_IRQ << 12) | /* vector 64 */
  170. + 1; /* turn off interval timer */
  171. + break;
  172. +
  173. + case Irq_UART0:
  174. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  175. + vui &= ~ID2Pri(EIrqID_UART0, 0xf); /* clear old setting */
  176. + vui |= ID2Pri(EIrqID_UART0, 0x7); /* set interrupt level */
  177. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  178. + break;
  179. +
  180. + case Irq_UART1:
  181. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  182. + vui &= ~ID2Pri(EIrqID_UART1, 0xf); /* clear old setting */
  183. + vui |= ID2Pri(EIrqID_UART1, 0x7); /* set interrupt level */
  184. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  185. + break;
  186. +
  187. + case Irq_GPS:
  188. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  189. + vui &= ~ID2Pri(EIrqID_GPS, 0xf); /* clear old setting */
  190. + vui |= ID2Pri(EIrqID_GPS, 0x7); /* set interrupt level */
  191. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  192. + break;
  193. +
  194. + case Irq_I2C:
  195. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  196. + vui &= ~ID2Pri(EIrqID_I2C, 0xf); /* clear old setting */
  197. + vui |= ID2Pri(EIrqID_I2C, 0x7); /* set interrupt level */
  198. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  199. + break;
  200. +
  201. + case Irq_EMAC:
  202. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  203. + vui &= ~ID2Pri(EIrqID_EMAC, 0xf); /* clear old setting */
  204. + vui |= ID2Pri(EIrqID_EMAC, 0x8); /* set interrupt level */
  205. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  206. + printk("EMAC prio is: %x\n", vui);
  207. + break;
  208. +
  209. + case Irq_GPIO:
  210. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  211. + vui &= ~ID2Pri(EIrqID_GPIO, 0xf); /* clear old setting */
  212. + vui |= ID2Pri(EIrqID_GPIO, 0x7); /* set interrupt level */
  213. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  214. + break;
  215. +
  216. + case Irq_1PPS: // prio is higher for 1PPS porposes
  217. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  218. + vui &= ~ID2Pri(EIrqID_1PPS, 0xf); /* clear old setting */
  219. + vui |= ID2Pri(EIrqID_1PPS, 0x9); /* set interrupt level */
  220. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  221. + printk("1PPS prio is: %x\n", vui);
  222. + break;
  223. +
  224. + default:
  225. + break;
  226. +
  227. + }
  228. +}
  229. +
  230. +static inline void shj_disable_irq(struct irq_data *data)
  231. +{
  232. + volatile unsigned int vui;
  233. + unsigned int irq = data->irq;
  234. +
  235. + printk("%s: IRQ %d\n", __func__, irq);
  236. +
  237. + switch (irq) {
  238. + case PIT_IRQ:
  239. + /* enable, lvl 2, vector 64 */
  240. + AQ_SYS = (0 << 26) | /* disable PIT */
  241. + (0x02 << 20) | /* interrupt level 2 */
  242. + (PIT_IRQ << 12) | /* vector 64 */
  243. + 1; /* turn off interval timer */
  244. + break;
  245. +
  246. + case Irq_UART0:
  247. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  248. + vui &= ~ID2Pri(EIrqID_UART0, 0xf); /* clear setting */
  249. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  250. + break;
  251. +
  252. + case Irq_UART1:
  253. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  254. + vui &= ~ID2Pri(EIrqID_UART1, 0xf); /* clear setting */
  255. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  256. + break;
  257. +
  258. + case Irq_GPS:
  259. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  260. + vui &= ~ID2Pri(EIrqID_GPS, 0xf); /* clear setting */
  261. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  262. + break;
  263. +
  264. + case Irq_I2C:
  265. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  266. + vui &= ~ID2Pri(EIrqID_I2C, 0xf); /* clear setting */
  267. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  268. + break;
  269. +
  270. + case Irq_EMAC:
  271. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  272. + vui &= ~ID2Pri(EIrqID_EMAC, 0xf); /* clear setting */
  273. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  274. + break;
  275. +
  276. + case Irq_GPIO:
  277. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  278. + vui &= ~ID2Pri(EIrqID_GPIO, 0xf); /* clear setting */
  279. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  280. + break;
  281. +
  282. + case Irq_1PPS:
  283. + vui = *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri);
  284. + vui &= ~ID2Pri(EIrqID_1PPS, 0xf); /* clear setting */
  285. + *(volatile unsigned int *)(sys_SYS_BASE + Sys_IntPri) = vui;
  286. + break;
  287. +
  288. + default:
  289. + break;
  290. + }
  291. +}
  292. +
  293. +static struct irq_chip shj_irq_chip = {
  294. + .name = "0PF_INTC",
  295. + .irq_enable = shj_enable_irq,
  296. + .irq_disable = shj_disable_irq,
  297. + .irq_ack = shj_ack_noop,
  298. +};
  299. +
  300. +static void __init shj_irq_init(void)
  301. +{
  302. + int c;
  303. +
  304. + printk(KERN_INFO "0PF FPGA interrupt controller...\n");
  305. +
  306. + for (c = 0; c < NR_IRQS; c++) {
  307. + //irq_desc[c].action = NULL;
  308. + //irq_desc[c].depth = 1;
  309. + irq_set_chip_and_handler_name(c, &shj_irq_chip,
  310. + handle_simple_irq, "simple");
  311. + }
  312. +}
  313. +
  314. +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
  315. +// Commit 7b1f62076 switched this to a pointer
  316. +/*
  317. + * Should return nanoseconds since last timer tick
  318. + */
  319. +u32 shj_gettimeoffset(void)
  320. +{
  321. + u32 clocks_counter = readl(SHJ_PIT_PCNTR);
  322. +
  323. + return clocks_counter * readl(SHJ_NSEC_PER_CLOCK);
  324. +}
  325. +
  326. +static void __init shj_board_setup(char **cmdline)
  327. +{
  328. + arch_gettimeoffset = shj_gettimeoffset;
  329. +}
  330. +#else
  331. +#define shj_gettimeoffset 0
  332. +#endif
  333. +
  334. +static struct sh_machine_vector mv_se __initmv = {
  335. + .mv_name = "0PF_FPGA",
  336. + //.mv_nr_irqs = 256,
  337. + .mv_irq_demux = shj_irq_demux,
  338. + .mv_init_irq = shj_irq_init,
  339. + .mv_setup = shj_board_setup,
  340. +};
  341. +
  342. +static irqreturn_t timer_interrupt(int irq, void *dev_id)
  343. +{
  344. + // AQ_PIO = 0x011; // GREEN
  345. +
  346. + if (current->pid)
  347. + profile_tick(CPU_PROFILING);
  348. +
  349. + xtime_update(1);
  350. + update_process_times(user_mode(get_irq_regs()));
  351. +
  352. + return IRQ_HANDLED;
  353. +}
  354. +
  355. +static void __init start_pit(void)
  356. +{
  357. + if (request_irq
  358. + (PIT_IRQ, timer_interrupt, IRQF_TIMER, "pit", NULL))
  359. + printk("irq_desc[%p] : fail to register\n", &irq_desc[PIT_IRQ]);
  360. +
  361. + irq_set_chip_and_handler_name(PIT_IRQ, &shj_irq_chip, handle_edge_irq,
  362. + "pit");
  363. +}
  364. +
  365. +static int __init shj_initialise(void)
  366. +{
  367. + struct irq_data *data;
  368. +
  369. + pr_info("0PF Machine setup...\n");
  370. +
  371. + start_pit();
  372. +
  373. + data = irq_get_irq_data(Irq_UART0);
  374. + shj_enable_irq(data);
  375. +
  376. + data = irq_get_irq_data(Irq_UART1);
  377. + shj_enable_irq(data);
  378. +
  379. + data = irq_get_irq_data(Irq_EMAC);
  380. + shj_enable_irq(data);
  381. +
  382. + data = irq_get_irq_data(PIT_IRQ);
  383. + shj_enable_irq(data);
  384. +
  385. + pr_info("0PF Machine setup done.\n");
  386. +
  387. + return 0;
  388. +}
  389. +
  390. +arch_initcall(shj_initialise);
  391. diff -Nur linux-4.1.13.orig/arch/sh/configs/0pf_defconfig linux-4.1.13/arch/sh/configs/0pf_defconfig
  392. --- linux-4.1.13.orig/arch/sh/configs/0pf_defconfig 1970-01-01 01:00:00.000000000 +0100
  393. +++ linux-4.1.13/arch/sh/configs/0pf_defconfig 2015-12-05 00:16:48.000000000 +0100
  394. @@ -0,0 +1,945 @@
  395. +#
  396. +# Automatically generated file; DO NOT EDIT.
  397. +# Linux/sh 4.1.0-rc6 Kernel Configuration
  398. +#
  399. +CONFIG_SUPERH=y
  400. +CONFIG_SUPERH32=y
  401. +# CONFIG_SUPERH64 is not set
  402. +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
  403. +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  404. +CONFIG_GENERIC_BUG=y
  405. +CONFIG_GENERIC_HWEIGHT=y
  406. +# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
  407. +# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
  408. +CONFIG_ARCH_USES_GETTIMEOFFSET=y
  409. +CONFIG_STACKTRACE_SUPPORT=y
  410. +CONFIG_LOCKDEP_SUPPORT=y
  411. +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
  412. +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
  413. +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
  414. +CONFIG_NO_IOPORT_MAP=y
  415. +CONFIG_DMA_NONCOHERENT=y
  416. +CONFIG_NEED_DMA_MAP_STATE=y
  417. +CONFIG_NEED_SG_DMA_LENGTH=y
  418. +CONFIG_PGTABLE_LEVELS=2
  419. +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  420. +CONFIG_IRQ_WORK=y
  421. +
  422. +#
  423. +# General setup
  424. +#
  425. +CONFIG_BROKEN_ON_SMP=y
  426. +CONFIG_INIT_ENV_ARG_LIMIT=32
  427. +CONFIG_CROSS_COMPILE=""
  428. +# CONFIG_COMPILE_TEST is not set
  429. +CONFIG_LOCALVERSION=""
  430. +# CONFIG_LOCALVERSION_AUTO is not set
  431. +CONFIG_HAVE_KERNEL_GZIP=y
  432. +CONFIG_HAVE_KERNEL_BZIP2=y
  433. +CONFIG_HAVE_KERNEL_LZMA=y
  434. +CONFIG_HAVE_KERNEL_XZ=y
  435. +CONFIG_HAVE_KERNEL_LZO=y
  436. +CONFIG_KERNEL_GZIP=y
  437. +# CONFIG_KERNEL_BZIP2 is not set
  438. +# CONFIG_KERNEL_LZMA is not set
  439. +# CONFIG_KERNEL_XZ is not set
  440. +# CONFIG_KERNEL_LZO is not set
  441. +CONFIG_DEFAULT_HOSTNAME="(none)"
  442. +# CONFIG_SYSVIPC is not set
  443. +# CONFIG_FHANDLE is not set
  444. +# CONFIG_USELIB is not set
  445. +CONFIG_HAVE_ARCH_AUDITSYSCALL=y
  446. +
  447. +#
  448. +# IRQ subsystem
  449. +#
  450. +CONFIG_MAY_HAVE_SPARSE_IRQ=y
  451. +CONFIG_GENERIC_IRQ_SHOW=y
  452. +CONFIG_IRQ_DOMAIN=y
  453. +CONFIG_IRQ_FORCED_THREADING=y
  454. +# CONFIG_SPARSE_IRQ is not set
  455. +CONFIG_GENERIC_CLOCKEVENTS=y
  456. +
  457. +#
  458. +# Timers subsystem
  459. +#
  460. +CONFIG_HZ_PERIODIC=y
  461. +
  462. +#
  463. +# CPU/Task time and stats accounting
  464. +#
  465. +CONFIG_TICK_CPU_ACCOUNTING=y
  466. +# CONFIG_BSD_PROCESS_ACCT is not set
  467. +
  468. +#
  469. +# RCU Subsystem
  470. +#
  471. +CONFIG_TINY_RCU=y
  472. +CONFIG_SRCU=y
  473. +# CONFIG_TASKS_RCU is not set
  474. +# CONFIG_RCU_STALL_COMMON is not set
  475. +# CONFIG_TREE_RCU_TRACE is not set
  476. +CONFIG_RCU_KTHREAD_PRIO=0
  477. +# CONFIG_RCU_EXPEDITE_BOOT is not set
  478. +# CONFIG_BUILD_BIN2C is not set
  479. +# CONFIG_IKCONFIG is not set
  480. +CONFIG_LOG_BUF_SHIFT=17
  481. +# CONFIG_CGROUPS is not set
  482. +# CONFIG_CHECKPOINT_RESTORE is not set
  483. +CONFIG_NAMESPACES=y
  484. +# CONFIG_UTS_NS is not set
  485. +# CONFIG_USER_NS is not set
  486. +# CONFIG_PID_NS is not set
  487. +# CONFIG_SCHED_AUTOGROUP is not set
  488. +# CONFIG_SYSFS_DEPRECATED is not set
  489. +# CONFIG_RELAY is not set
  490. +CONFIG_BLK_DEV_INITRD=y
  491. +CONFIG_INITRAMFS_SOURCE="initrd/root-dev initrd/root-files"
  492. +CONFIG_INITRAMFS_ROOT_UID=0
  493. +CONFIG_INITRAMFS_ROOT_GID=0
  494. +# CONFIG_RD_GZIP is not set
  495. +# CONFIG_RD_BZIP2 is not set
  496. +# CONFIG_RD_LZMA is not set
  497. +# CONFIG_RD_XZ is not set
  498. +# CONFIG_RD_LZO is not set
  499. +# CONFIG_RD_LZ4 is not set
  500. +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
  501. +CONFIG_SYSCTL=y
  502. +CONFIG_ANON_INODES=y
  503. +CONFIG_HAVE_UID16=y
  504. +# CONFIG_EXPERT is not set
  505. +CONFIG_UID16=y
  506. +CONFIG_MULTIUSER=y
  507. +CONFIG_SGETMASK_SYSCALL=y
  508. +CONFIG_SYSFS_SYSCALL=y
  509. +# CONFIG_SYSCTL_SYSCALL is not set
  510. +CONFIG_KALLSYMS=y
  511. +CONFIG_PRINTK=y
  512. +CONFIG_BUG=y
  513. +CONFIG_ELF_CORE=y
  514. +CONFIG_BASE_FULL=y
  515. +CONFIG_FUTEX=y
  516. +CONFIG_EPOLL=y
  517. +CONFIG_SIGNALFD=y
  518. +CONFIG_TIMERFD=y
  519. +CONFIG_EVENTFD=y
  520. +# CONFIG_BPF_SYSCALL is not set
  521. +CONFIG_AIO=y
  522. +CONFIG_ADVISE_SYSCALLS=y
  523. +# CONFIG_EMBEDDED is not set
  524. +CONFIG_HAVE_PERF_EVENTS=y
  525. +CONFIG_PERF_USE_VMALLOC=y
  526. +
  527. +#
  528. +# Kernel Performance Events And Counters
  529. +#
  530. +CONFIG_PERF_EVENTS=y
  531. +CONFIG_VM_EVENT_COUNTERS=y
  532. +CONFIG_SLUB_DEBUG=y
  533. +# CONFIG_COMPAT_BRK is not set
  534. +# CONFIG_SLAB is not set
  535. +CONFIG_SLUB=y
  536. +# CONFIG_PROFILING is not set
  537. +CONFIG_HAVE_OPROFILE=y
  538. +# CONFIG_UPROBES is not set
  539. +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
  540. +CONFIG_HAVE_KPROBES=y
  541. +CONFIG_HAVE_KRETPROBES=y
  542. +CONFIG_HAVE_ARCH_TRACEHOOK=y
  543. +CONFIG_HAVE_DMA_ATTRS=y
  544. +CONFIG_GENERIC_SMP_IDLE_THREAD=y
  545. +CONFIG_GENERIC_IDLE_POLL_SETUP=y
  546. +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
  547. +CONFIG_HAVE_CLK=y
  548. +CONFIG_HAVE_DMA_API_DEBUG=y
  549. +CONFIG_HAVE_HW_BREAKPOINT=y
  550. +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
  551. +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
  552. +CONFIG_HAVE_CC_STACKPROTECTOR=y
  553. +# CONFIG_CC_STACKPROTECTOR is not set
  554. +CONFIG_CC_STACKPROTECTOR_NONE=y
  555. +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
  556. +# CONFIG_CC_STACKPROTECTOR_STRONG is not set
  557. +CONFIG_MODULES_USE_ELF_RELA=y
  558. +CONFIG_OLD_SIGSUSPEND=y
  559. +CONFIG_OLD_SIGACTION=y
  560. +
  561. +#
  562. +# GCOV-based kernel profiling
  563. +#
  564. +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
  565. +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
  566. +CONFIG_SLABINFO=y
  567. +CONFIG_RT_MUTEXES=y
  568. +CONFIG_BASE_SMALL=0
  569. +# CONFIG_MODULES is not set
  570. +CONFIG_BLOCK=y
  571. +# CONFIG_LBDAF is not set
  572. +# CONFIG_BLK_DEV_BSG is not set
  573. +# CONFIG_BLK_DEV_BSGLIB is not set
  574. +# CONFIG_BLK_DEV_INTEGRITY is not set
  575. +# CONFIG_BLK_CMDLINE_PARSER is not set
  576. +
  577. +#
  578. +# Partition Types
  579. +#
  580. +# CONFIG_PARTITION_ADVANCED is not set
  581. +CONFIG_MSDOS_PARTITION=y
  582. +CONFIG_EFI_PARTITION=y
  583. +
  584. +#
  585. +# IO Schedulers
  586. +#
  587. +CONFIG_IOSCHED_NOOP=y
  588. +# CONFIG_IOSCHED_DEADLINE is not set
  589. +# CONFIG_IOSCHED_CFQ is not set
  590. +CONFIG_DEFAULT_NOOP=y
  591. +CONFIG_DEFAULT_IOSCHED="noop"
  592. +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
  593. +CONFIG_INLINE_READ_UNLOCK=y
  594. +CONFIG_INLINE_READ_UNLOCK_IRQ=y
  595. +CONFIG_INLINE_WRITE_UNLOCK=y
  596. +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
  597. +# CONFIG_FREEZER is not set
  598. +
  599. +#
  600. +# System type
  601. +#
  602. +CONFIG_CPU_SH2=y
  603. +CONFIG_CPU_SH2J=y
  604. +# CONFIG_CPU_SUBTYPE_SH7619 is not set
  605. +# CONFIG_CPU_SUBTYPE_SH7201 is not set
  606. +# CONFIG_CPU_SUBTYPE_SH7203 is not set
  607. +# CONFIG_CPU_SUBTYPE_SH7206 is not set
  608. +# CONFIG_CPU_SUBTYPE_SH7263 is not set
  609. +# CONFIG_CPU_SUBTYPE_SH7264 is not set
  610. +# CONFIG_CPU_SUBTYPE_SH7269 is not set
  611. +# CONFIG_CPU_SUBTYPE_MXG is not set
  612. +CONFIG_CPU_SUBTYPE_0PF=y
  613. +# CONFIG_CPU_SUBTYPE_SH7705 is not set
  614. +# CONFIG_CPU_SUBTYPE_SH7706 is not set
  615. +# CONFIG_CPU_SUBTYPE_SH7707 is not set
  616. +# CONFIG_CPU_SUBTYPE_SH7708 is not set
  617. +# CONFIG_CPU_SUBTYPE_SH7709 is not set
  618. +# CONFIG_CPU_SUBTYPE_SH7710 is not set
  619. +# CONFIG_CPU_SUBTYPE_SH7712 is not set
  620. +# CONFIG_CPU_SUBTYPE_SH7720 is not set
  621. +# CONFIG_CPU_SUBTYPE_SH7721 is not set
  622. +# CONFIG_CPU_SUBTYPE_SH7750 is not set
  623. +# CONFIG_CPU_SUBTYPE_SH7091 is not set
  624. +# CONFIG_CPU_SUBTYPE_SH7750R is not set
  625. +# CONFIG_CPU_SUBTYPE_SH7750S is not set
  626. +# CONFIG_CPU_SUBTYPE_SH7751 is not set
  627. +# CONFIG_CPU_SUBTYPE_SH7751R is not set
  628. +# CONFIG_CPU_SUBTYPE_SH7760 is not set
  629. +# CONFIG_CPU_SUBTYPE_SH4_202 is not set
  630. +# CONFIG_CPU_SUBTYPE_SH7723 is not set
  631. +# CONFIG_CPU_SUBTYPE_SH7724 is not set
  632. +# CONFIG_CPU_SUBTYPE_SH7734 is not set
  633. +# CONFIG_CPU_SUBTYPE_SH7757 is not set
  634. +# CONFIG_CPU_SUBTYPE_SH7763 is not set
  635. +# CONFIG_CPU_SUBTYPE_SH7770 is not set
  636. +# CONFIG_CPU_SUBTYPE_SH7780 is not set
  637. +# CONFIG_CPU_SUBTYPE_SH7785 is not set
  638. +# CONFIG_CPU_SUBTYPE_SH7786 is not set
  639. +# CONFIG_CPU_SUBTYPE_SHX3 is not set
  640. +# CONFIG_CPU_SUBTYPE_SH7343 is not set
  641. +# CONFIG_CPU_SUBTYPE_SH7722 is not set
  642. +# CONFIG_CPU_SUBTYPE_SH7366 is not set
  643. +
  644. +#
  645. +# Memory management options
  646. +#
  647. +CONFIG_QUICKLIST=y
  648. +CONFIG_PAGE_OFFSET=0x00000000
  649. +CONFIG_FORCE_MAX_ZONEORDER=14
  650. +CONFIG_MEMORY_START=0x10000000
  651. +CONFIG_MEMORY_SIZE=0x8000000
  652. +# CONFIG_29BIT is not set
  653. +CONFIG_32BIT=y
  654. +CONFIG_ARCH_FLATMEM_ENABLE=y
  655. +CONFIG_ARCH_SPARSEMEM_ENABLE=y
  656. +CONFIG_ARCH_SPARSEMEM_DEFAULT=y
  657. +CONFIG_ARCH_SELECT_MEMORY_MODEL=y
  658. +CONFIG_PAGE_SIZE_4KB=y
  659. +# CONFIG_PAGE_SIZE_8KB is not set
  660. +# CONFIG_PAGE_SIZE_16KB is not set
  661. +# CONFIG_PAGE_SIZE_64KB is not set
  662. +CONFIG_SELECT_MEMORY_MODEL=y
  663. +CONFIG_FLATMEM_MANUAL=y
  664. +# CONFIG_SPARSEMEM_MANUAL is not set
  665. +CONFIG_FLATMEM=y
  666. +CONFIG_FLAT_NODE_MEM_MAP=y
  667. +CONFIG_SPARSEMEM_STATIC=y
  668. +CONFIG_HAVE_MEMBLOCK=y
  669. +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
  670. +CONFIG_ARCH_DISCARD_MEMBLOCK=y
  671. +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
  672. +CONFIG_PAGEFLAGS_EXTENDED=y
  673. +CONFIG_SPLIT_PTLOCK_CPUS=999999
  674. +# CONFIG_PHYS_ADDR_T_64BIT is not set
  675. +CONFIG_ZONE_DMA_FLAG=0
  676. +CONFIG_NR_QUICK=1
  677. +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1
  678. +CONFIG_NEED_PER_CPU_KM=y
  679. +# CONFIG_CLEANCACHE is not set
  680. +# CONFIG_ZPOOL is not set
  681. +# CONFIG_ZBUD is not set
  682. +
  683. +#
  684. +# Cache configuration
  685. +#
  686. +# CONFIG_CACHE_WRITEBACK is not set
  687. +# CONFIG_CACHE_WRITETHROUGH is not set
  688. +CONFIG_CACHE_OFF=y
  689. +
  690. +#
  691. +# Processor features
  692. +#
  693. +# CONFIG_CPU_LITTLE_ENDIAN is not set
  694. +CONFIG_CPU_BIG_ENDIAN=y
  695. +# CONFIG_SH_FPU_EMU is not set
  696. +
  697. +#
  698. +# Board support
  699. +#
  700. +CONFIG_0PF_FPGA=y
  701. +
  702. +#
  703. +# Timer and clock configuration
  704. +#
  705. +CONFIG_SH_PCLK_FREQ=32000000
  706. +CONFIG_SH_CLK_CPG=y
  707. +CONFIG_SH_CLK_CPG_LEGACY=y
  708. +
  709. +#
  710. +# CPU Frequency scaling
  711. +#
  712. +
  713. +#
  714. +# CPU Frequency scaling
  715. +#
  716. +# CONFIG_CPU_FREQ is not set
  717. +
  718. +#
  719. +# DMA support
  720. +#
  721. +
  722. +#
  723. +# Companion Chips
  724. +#
  725. +
  726. +#
  727. +# Additional SuperH Device Drivers
  728. +#
  729. +# CONFIG_HEARTBEAT is not set
  730. +# CONFIG_PUSH_SWITCH is not set
  731. +
  732. +#
  733. +# Kernel features
  734. +#
  735. +CONFIG_HZ_100=y
  736. +# CONFIG_HZ_250 is not set
  737. +# CONFIG_HZ_300 is not set
  738. +# CONFIG_HZ_1000 is not set
  739. +CONFIG_HZ=100
  740. +# CONFIG_SCHED_HRTICK is not set
  741. +# CONFIG_CRASH_DUMP is not set
  742. +CONFIG_PHYSICAL_START=0x10000000
  743. +# CONFIG_SECCOMP is not set
  744. +CONFIG_PREEMPT_NONE=y
  745. +# CONFIG_PREEMPT_VOLUNTARY is not set
  746. +# CONFIG_PREEMPT is not set
  747. +CONFIG_GUSA=y
  748. +
  749. +#
  750. +# SuperH / SH-Mobile Driver Options
  751. +#
  752. +CONFIG_SH_INTC=y
  753. +
  754. +#
  755. +# Interrupt controller options
  756. +#
  757. +
  758. +#
  759. +# Boot options
  760. +#
  761. +CONFIG_ZERO_PAGE_OFFSET=0x0003F000
  762. +CONFIG_BOOT_LINK_OFFSET=0x00800000
  763. +CONFIG_ENTRY_OFFSET=0x00001000
  764. +# CONFIG_CMDLINE_OVERWRITE is not set
  765. +CONFIG_CMDLINE_EXTEND=y
  766. +CONFIG_CMDLINE="console=ttyUL0"
  767. +
  768. +#
  769. +# Bus options
  770. +#
  771. +# CONFIG_PCCARD is not set
  772. +
  773. +#
  774. +# Executable file formats
  775. +#
  776. +CONFIG_BINFMT_ELF_FDPIC=y
  777. +CONFIG_BINFMT_SCRIPT=y
  778. +CONFIG_BINFMT_FLAT=y
  779. +# CONFIG_BINFMT_ZFLAT is not set
  780. +# CONFIG_BINFMT_SHARED_FLAT is not set
  781. +# CONFIG_HAVE_AOUT is not set
  782. +# CONFIG_BINFMT_MISC is not set
  783. +CONFIG_COREDUMP=y
  784. +
  785. +#
  786. +# Power management options (EXPERIMENTAL)
  787. +#
  788. +# CONFIG_PM is not set
  789. +
  790. +#
  791. +# CPU Idle
  792. +#
  793. +# CONFIG_CPU_IDLE is not set
  794. +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
  795. +# CONFIG_NET is not set
  796. +
  797. +#
  798. +# Device Drivers
  799. +#
  800. +
  801. +#
  802. +# Generic Driver Options
  803. +#
  804. +# CONFIG_UEVENT_HELPER is not set
  805. +CONFIG_DEVTMPFS=y
  806. +CONFIG_DEVTMPFS_MOUNT=y
  807. +# CONFIG_STANDALONE is not set
  808. +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
  809. +CONFIG_FW_LOADER=y
  810. +# CONFIG_FIRMWARE_IN_KERNEL is not set
  811. +CONFIG_EXTRA_FIRMWARE=""
  812. +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
  813. +CONFIG_ALLOW_DEV_COREDUMP=y
  814. +# CONFIG_SYS_HYPERVISOR is not set
  815. +# CONFIG_GENERIC_CPU_DEVICES is not set
  816. +# CONFIG_DMA_SHARED_BUFFER is not set
  817. +
  818. +#
  819. +# Bus devices
  820. +#
  821. +# CONFIG_MTD is not set
  822. +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
  823. +# CONFIG_PARPORT is not set
  824. +# CONFIG_BLK_DEV is not set
  825. +
  826. +#
  827. +# Misc devices
  828. +#
  829. +# CONFIG_SENSORS_LIS3LV02D is not set
  830. +# CONFIG_DUMMY_IRQ is not set
  831. +# CONFIG_ENCLOSURE_SERVICES is not set
  832. +# CONFIG_SRAM is not set
  833. +# CONFIG_C2PORT is not set
  834. +
  835. +#
  836. +# EEPROM support
  837. +#
  838. +# CONFIG_EEPROM_93CX6 is not set
  839. +
  840. +#
  841. +# Texas Instruments shared transport line discipline
  842. +#
  843. +
  844. +#
  845. +# Altera FPGA firmware download module
  846. +#
  847. +
  848. +#
  849. +# Intel MIC Bus Driver
  850. +#
  851. +
  852. +#
  853. +# Intel MIC Host Driver
  854. +#
  855. +
  856. +#
  857. +# Intel MIC Card Driver
  858. +#
  859. +# CONFIG_ECHO is not set
  860. +# CONFIG_CXL_BASE is not set
  861. +
  862. +#
  863. +# SCSI device support
  864. +#
  865. +CONFIG_SCSI_MOD=y
  866. +# CONFIG_RAID_ATTRS is not set
  867. +# CONFIG_SCSI is not set
  868. +# CONFIG_SCSI_DMA is not set
  869. +CONFIG_HAVE_PATA_PLATFORM=y
  870. +# CONFIG_ATA is not set
  871. +# CONFIG_MD is not set
  872. +
  873. +#
  874. +# Input device support
  875. +#
  876. +CONFIG_INPUT=y
  877. +# CONFIG_INPUT_FF_MEMLESS is not set
  878. +# CONFIG_INPUT_POLLDEV is not set
  879. +# CONFIG_INPUT_SPARSEKMAP is not set
  880. +# CONFIG_INPUT_MATRIXKMAP is not set
  881. +
  882. +#
  883. +# Userland interfaces
  884. +#
  885. +# CONFIG_INPUT_MOUSEDEV is not set
  886. +# CONFIG_INPUT_JOYDEV is not set
  887. +# CONFIG_INPUT_EVDEV is not set
  888. +# CONFIG_INPUT_EVBUG is not set
  889. +
  890. +#
  891. +# Input Device Drivers
  892. +#
  893. +# CONFIG_INPUT_KEYBOARD is not set
  894. +# CONFIG_INPUT_MOUSE is not set
  895. +# CONFIG_INPUT_JOYSTICK is not set
  896. +# CONFIG_INPUT_TABLET is not set
  897. +# CONFIG_INPUT_TOUCHSCREEN is not set
  898. +# CONFIG_INPUT_MISC is not set
  899. +
  900. +#
  901. +# Hardware I/O ports
  902. +#
  903. +# CONFIG_SERIO is not set
  904. +# CONFIG_GAMEPORT is not set
  905. +
  906. +#
  907. +# Character devices
  908. +#
  909. +CONFIG_TTY=y
  910. +CONFIG_VT=y
  911. +CONFIG_CONSOLE_TRANSLATIONS=y
  912. +CONFIG_VT_CONSOLE=y
  913. +CONFIG_HW_CONSOLE=y
  914. +# CONFIG_VT_HW_CONSOLE_BINDING is not set
  915. +CONFIG_UNIX98_PTYS=y
  916. +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
  917. +# CONFIG_LEGACY_PTYS is not set
  918. +# CONFIG_SERIAL_NONSTANDARD is not set
  919. +# CONFIG_TRACE_SINK is not set
  920. +CONFIG_DEVMEM=y
  921. +# CONFIG_DEVKMEM is not set
  922. +
  923. +#
  924. +# Serial drivers
  925. +#
  926. +# CONFIG_SERIAL_8250 is not set
  927. +
  928. +#
  929. +# Non-8250 serial port support
  930. +#
  931. +CONFIG_SERIAL_UARTLITE=y
  932. +CONFIG_SERIAL_UARTLITE_CONSOLE=y
  933. +CONFIG_SERIAL_UARTLITE_0PF=y
  934. +# CONFIG_SERIAL_SH_SCI is not set
  935. +CONFIG_SERIAL_CORE=y
  936. +CONFIG_SERIAL_CORE_CONSOLE=y
  937. +# CONFIG_SERIAL_SCCNXP is not set
  938. +# CONFIG_SERIAL_ALTERA_JTAGUART is not set
  939. +# CONFIG_SERIAL_ALTERA_UART is not set
  940. +# CONFIG_SERIAL_ARC is not set
  941. +# CONFIG_SERIAL_FSL_LPUART is not set
  942. +# CONFIG_IPMI_HANDLER is not set
  943. +# CONFIG_HW_RANDOM is not set
  944. +# CONFIG_R3964 is not set
  945. +# CONFIG_RAW_DRIVER is not set
  946. +# CONFIG_TCG_TPM is not set
  947. +
  948. +#
  949. +# I2C support
  950. +#
  951. +# CONFIG_I2C is not set
  952. +# CONFIG_SPI is not set
  953. +# CONFIG_SPMI is not set
  954. +# CONFIG_HSI is not set
  955. +
  956. +#
  957. +# PPS support
  958. +#
  959. +# CONFIG_PPS is not set
  960. +
  961. +#
  962. +# PPS generators support
  963. +#
  964. +
  965. +#
  966. +# PTP clock support
  967. +#
  968. +
  969. +#
  970. +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
  971. +#
  972. +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
  973. +# CONFIG_W1 is not set
  974. +# CONFIG_POWER_SUPPLY is not set
  975. +# CONFIG_POWER_AVS is not set
  976. +# CONFIG_HWMON is not set
  977. +# CONFIG_THERMAL is not set
  978. +# CONFIG_WATCHDOG is not set
  979. +CONFIG_SSB_POSSIBLE=y
  980. +
  981. +#
  982. +# Sonics Silicon Backplane
  983. +#
  984. +# CONFIG_SSB is not set
  985. +CONFIG_BCMA_POSSIBLE=y
  986. +
  987. +#
  988. +# Broadcom specific AMBA
  989. +#
  990. +# CONFIG_BCMA is not set
  991. +
  992. +#
  993. +# Multifunction device drivers
  994. +#
  995. +# CONFIG_MFD_CORE is not set
  996. +# CONFIG_MFD_CROS_EC is not set
  997. +# CONFIG_HTC_PASIC3 is not set
  998. +# CONFIG_MFD_KEMPLD is not set
  999. +# CONFIG_MFD_MT6397 is not set
  1000. +# CONFIG_MFD_SM501 is not set
  1001. +# CONFIG_ABX500_CORE is not set
  1002. +# CONFIG_MFD_SYSCON is not set
  1003. +# CONFIG_MFD_TI_AM335X_TSCADC is not set
  1004. +# CONFIG_MFD_TMIO is not set
  1005. +# CONFIG_REGULATOR is not set
  1006. +# CONFIG_MEDIA_SUPPORT is not set
  1007. +
  1008. +#
  1009. +# Graphics support
  1010. +#
  1011. +
  1012. +#
  1013. +# Direct Rendering Manager
  1014. +#
  1015. +
  1016. +#
  1017. +# Frame buffer Devices
  1018. +#
  1019. +# CONFIG_FB is not set
  1020. +# CONFIG_FB_SH_MOBILE_MERAM is not set
  1021. +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
  1022. +# CONFIG_VGASTATE is not set
  1023. +
  1024. +#
  1025. +# Console display driver support
  1026. +#
  1027. +CONFIG_DUMMY_CONSOLE=y
  1028. +CONFIG_DUMMY_CONSOLE_COLUMNS=80
  1029. +CONFIG_DUMMY_CONSOLE_ROWS=25
  1030. +# CONFIG_SOUND is not set
  1031. +
  1032. +#
  1033. +# HID support
  1034. +#
  1035. +# CONFIG_HID is not set
  1036. +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
  1037. +# CONFIG_USB_SUPPORT is not set
  1038. +# CONFIG_UWB is not set
  1039. +# CONFIG_MMC is not set
  1040. +# CONFIG_MEMSTICK is not set
  1041. +# CONFIG_NEW_LEDS is not set
  1042. +# CONFIG_ACCESSIBILITY is not set
  1043. +CONFIG_RTC_LIB=y
  1044. +# CONFIG_RTC_CLASS is not set
  1045. +# CONFIG_DMADEVICES is not set
  1046. +# CONFIG_AUXDISPLAY is not set
  1047. +# CONFIG_VIRT_DRIVERS is not set
  1048. +
  1049. +#
  1050. +# Virtio drivers
  1051. +#
  1052. +# CONFIG_VIRTIO_MMIO is not set
  1053. +
  1054. +#
  1055. +# Microsoft Hyper-V guest support
  1056. +#
  1057. +# CONFIG_STAGING is not set
  1058. +CONFIG_CLKDEV_LOOKUP=y
  1059. +
  1060. +#
  1061. +# Hardware Spinlock drivers
  1062. +#
  1063. +
  1064. +#
  1065. +# Clock Source drivers
  1066. +#
  1067. +# CONFIG_ATMEL_PIT is not set
  1068. +# CONFIG_SH_TIMER_CMT is not set
  1069. +# CONFIG_SH_TIMER_MTU2 is not set
  1070. +# CONFIG_SH_TIMER_TMU is not set
  1071. +# CONFIG_EM_TIMER_STI is not set
  1072. +# CONFIG_MAILBOX is not set
  1073. +
  1074. +#
  1075. +# Remoteproc drivers
  1076. +#
  1077. +# CONFIG_STE_MODEM_RPROC is not set
  1078. +
  1079. +#
  1080. +# Rpmsg drivers
  1081. +#
  1082. +
  1083. +#
  1084. +# SOC (System On Chip) specific Drivers
  1085. +#
  1086. +# CONFIG_SOC_TI is not set
  1087. +# CONFIG_PM_DEVFREQ is not set
  1088. +# CONFIG_EXTCON is not set
  1089. +# CONFIG_MEMORY is not set
  1090. +# CONFIG_IIO is not set
  1091. +# CONFIG_PWM is not set
  1092. +# CONFIG_IPACK_BUS is not set
  1093. +# CONFIG_RESET_CONTROLLER is not set
  1094. +# CONFIG_FMC is not set
  1095. +
  1096. +#
  1097. +# PHY Subsystem
  1098. +#
  1099. +# CONFIG_GENERIC_PHY is not set
  1100. +# CONFIG_BCM_KONA_USB2_PHY is not set
  1101. +# CONFIG_POWERCAP is not set
  1102. +# CONFIG_MCB is not set
  1103. +
  1104. +#
  1105. +# Android
  1106. +#
  1107. +# CONFIG_ANDROID is not set
  1108. +
  1109. +#
  1110. +# File systems
  1111. +#
  1112. +# CONFIG_EXT2_FS is not set
  1113. +# CONFIG_EXT3_FS is not set
  1114. +# CONFIG_EXT4_FS is not set
  1115. +# CONFIG_REISERFS_FS is not set
  1116. +# CONFIG_JFS_FS is not set
  1117. +# CONFIG_BTRFS_FS is not set
  1118. +# CONFIG_NILFS2_FS is not set
  1119. +# CONFIG_F2FS_FS is not set
  1120. +# CONFIG_FS_POSIX_ACL is not set
  1121. +CONFIG_FILE_LOCKING=y
  1122. +# CONFIG_FSNOTIFY is not set
  1123. +# CONFIG_DNOTIFY is not set
  1124. +# CONFIG_INOTIFY_USER is not set
  1125. +# CONFIG_FANOTIFY is not set
  1126. +# CONFIG_QUOTA is not set
  1127. +# CONFIG_QUOTACTL is not set
  1128. +# CONFIG_AUTOFS4_FS is not set
  1129. +# CONFIG_FUSE_FS is not set
  1130. +# CONFIG_OVERLAY_FS is not set
  1131. +
  1132. +#
  1133. +# Caches
  1134. +#
  1135. +# CONFIG_FSCACHE is not set
  1136. +
  1137. +#
  1138. +# CD-ROM/DVD Filesystems
  1139. +#
  1140. +# CONFIG_ISO9660_FS is not set
  1141. +# CONFIG_UDF_FS is not set
  1142. +
  1143. +#
  1144. +# DOS/FAT/NT Filesystems
  1145. +#
  1146. +CONFIG_FAT_FS=y
  1147. +# CONFIG_MSDOS_FS is not set
  1148. +CONFIG_VFAT_FS=y
  1149. +CONFIG_FAT_DEFAULT_CODEPAGE=437
  1150. +CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
  1151. +# CONFIG_NTFS_FS is not set
  1152. +
  1153. +#
  1154. +# Pseudo filesystems
  1155. +#
  1156. +CONFIG_PROC_FS=y
  1157. +CONFIG_PROC_SYSCTL=y
  1158. +CONFIG_KERNFS=y
  1159. +CONFIG_SYSFS=y
  1160. +# CONFIG_HUGETLB_PAGE is not set
  1161. +# CONFIG_CONFIGFS_FS is not set
  1162. +# CONFIG_MISC_FILESYSTEMS is not set
  1163. +CONFIG_NLS=y
  1164. +CONFIG_NLS_DEFAULT="utf8"
  1165. +# CONFIG_NLS_CODEPAGE_437 is not set
  1166. +# CONFIG_NLS_CODEPAGE_737 is not set
  1167. +# CONFIG_NLS_CODEPAGE_775 is not set
  1168. +# CONFIG_NLS_CODEPAGE_850 is not set
  1169. +# CONFIG_NLS_CODEPAGE_852 is not set
  1170. +# CONFIG_NLS_CODEPAGE_855 is not set
  1171. +# CONFIG_NLS_CODEPAGE_857 is not set
  1172. +# CONFIG_NLS_CODEPAGE_860 is not set
  1173. +# CONFIG_NLS_CODEPAGE_861 is not set
  1174. +# CONFIG_NLS_CODEPAGE_862 is not set
  1175. +# CONFIG_NLS_CODEPAGE_863 is not set
  1176. +# CONFIG_NLS_CODEPAGE_864 is not set
  1177. +# CONFIG_NLS_CODEPAGE_865 is not set
  1178. +# CONFIG_NLS_CODEPAGE_866 is not set
  1179. +# CONFIG_NLS_CODEPAGE_869 is not set
  1180. +# CONFIG_NLS_CODEPAGE_936 is not set
  1181. +# CONFIG_NLS_CODEPAGE_950 is not set
  1182. +# CONFIG_NLS_CODEPAGE_932 is not set
  1183. +# CONFIG_NLS_CODEPAGE_949 is not set
  1184. +# CONFIG_NLS_CODEPAGE_874 is not set
  1185. +# CONFIG_NLS_ISO8859_8 is not set
  1186. +# CONFIG_NLS_CODEPAGE_1250 is not set
  1187. +# CONFIG_NLS_CODEPAGE_1251 is not set
  1188. +# CONFIG_NLS_ASCII is not set
  1189. +# CONFIG_NLS_ISO8859_1 is not set
  1190. +# CONFIG_NLS_ISO8859_2 is not set
  1191. +# CONFIG_NLS_ISO8859_3 is not set
  1192. +# CONFIG_NLS_ISO8859_4 is not set
  1193. +# CONFIG_NLS_ISO8859_5 is not set
  1194. +# CONFIG_NLS_ISO8859_6 is not set
  1195. +# CONFIG_NLS_ISO8859_7 is not set
  1196. +# CONFIG_NLS_ISO8859_9 is not set
  1197. +# CONFIG_NLS_ISO8859_13 is not set
  1198. +# CONFIG_NLS_ISO8859_14 is not set
  1199. +# CONFIG_NLS_ISO8859_15 is not set
  1200. +# CONFIG_NLS_KOI8_R is not set
  1201. +# CONFIG_NLS_KOI8_U is not set
  1202. +# CONFIG_NLS_MAC_ROMAN is not set
  1203. +# CONFIG_NLS_MAC_CELTIC is not set
  1204. +# CONFIG_NLS_MAC_CENTEURO is not set
  1205. +# CONFIG_NLS_MAC_CROATIAN is not set
  1206. +# CONFIG_NLS_MAC_CYRILLIC is not set
  1207. +# CONFIG_NLS_MAC_GAELIC is not set
  1208. +# CONFIG_NLS_MAC_GREEK is not set
  1209. +# CONFIG_NLS_MAC_ICELAND is not set
  1210. +# CONFIG_NLS_MAC_INUIT is not set
  1211. +# CONFIG_NLS_MAC_ROMANIAN is not set
  1212. +# CONFIG_NLS_MAC_TURKISH is not set
  1213. +CONFIG_NLS_UTF8=y
  1214. +
  1215. +#
  1216. +# Kernel hacking
  1217. +#
  1218. +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  1219. +
  1220. +#
  1221. +# printk and dmesg options
  1222. +#
  1223. +# CONFIG_PRINTK_TIME is not set
  1224. +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
  1225. +
  1226. +#
  1227. +# Compile-time checks and compiler options
  1228. +#
  1229. +# CONFIG_ENABLE_WARN_DEPRECATED is not set
  1230. +# CONFIG_ENABLE_MUST_CHECK is not set
  1231. +CONFIG_FRAME_WARN=1024
  1232. +# CONFIG_STRIP_ASM_SYMS is not set
  1233. +# CONFIG_UNUSED_SYMBOLS is not set
  1234. +# CONFIG_DEBUG_FS is not set
  1235. +# CONFIG_HEADERS_CHECK is not set
  1236. +# CONFIG_DEBUG_SECTION_MISMATCH is not set
  1237. +# CONFIG_MAGIC_SYSRQ is not set
  1238. +# CONFIG_DEBUG_KERNEL is not set
  1239. +
  1240. +#
  1241. +# Memory Debugging
  1242. +#
  1243. +# CONFIG_PAGE_EXTENSION is not set
  1244. +# CONFIG_SLUB_DEBUG_ON is not set
  1245. +# CONFIG_SLUB_STATS is not set
  1246. +CONFIG_HAVE_DEBUG_KMEMLEAK=y
  1247. +CONFIG_DEBUG_MEMORY_INIT=y
  1248. +
  1249. +#
  1250. +# Debug Lockups and Hangs
  1251. +#
  1252. +# CONFIG_PANIC_ON_OOPS is not set
  1253. +CONFIG_PANIC_ON_OOPS_VALUE=0
  1254. +CONFIG_PANIC_TIMEOUT=0
  1255. +# CONFIG_DEBUG_TIMEKEEPING is not set
  1256. +
  1257. +#
  1258. +# Lock Debugging (spinlocks, mutexes, etc...)
  1259. +#
  1260. +# CONFIG_STACKTRACE is not set
  1261. +CONFIG_HAVE_DEBUG_BUGVERBOSE=y
  1262. +CONFIG_DEBUG_BUGVERBOSE=y
  1263. +
  1264. +#
  1265. +# RCU Debugging
  1266. +#
  1267. +# CONFIG_PROVE_RCU is not set
  1268. +# CONFIG_SPARSE_RCU_POINTER is not set
  1269. +# CONFIG_TORTURE_TEST is not set
  1270. +CONFIG_HAVE_FUNCTION_TRACER=y
  1271. +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
  1272. +CONFIG_HAVE_DYNAMIC_FTRACE=y
  1273. +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
  1274. +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
  1275. +CONFIG_TRACING_SUPPORT=y
  1276. +# CONFIG_FTRACE is not set
  1277. +
  1278. +#
  1279. +# Runtime Testing
  1280. +#
  1281. +# CONFIG_ATOMIC64_SELFTEST is not set
  1282. +# CONFIG_TEST_HEXDUMP is not set
  1283. +# CONFIG_TEST_STRING_HELPERS is not set
  1284. +# CONFIG_TEST_KSTRTOX is not set
  1285. +# CONFIG_TEST_RHASHTABLE is not set
  1286. +# CONFIG_DMA_API_DEBUG is not set
  1287. +# CONFIG_TEST_FIRMWARE is not set
  1288. +# CONFIG_TEST_UDELAY is not set
  1289. +# CONFIG_MEMTEST is not set
  1290. +# CONFIG_SAMPLES is not set
  1291. +CONFIG_HAVE_ARCH_KGDB=y
  1292. +# CONFIG_SH_STANDARD_BIOS is not set
  1293. +# CONFIG_DWARF_UNWINDER is not set
  1294. +
  1295. +#
  1296. +# Security options
  1297. +#
  1298. +# CONFIG_KEYS is not set
  1299. +# CONFIG_SECURITY_DMESG_RESTRICT is not set
  1300. +# CONFIG_SECURITY is not set
  1301. +# CONFIG_SECURITYFS is not set
  1302. +CONFIG_DEFAULT_SECURITY_DAC=y
  1303. +CONFIG_DEFAULT_SECURITY=""
  1304. +# CONFIG_CRYPTO is not set
  1305. +# CONFIG_BINARY_PRINTF is not set
  1306. +
  1307. +#
  1308. +# Library routines
  1309. +#
  1310. +CONFIG_BITREVERSE=y
  1311. +# CONFIG_HAVE_ARCH_BITREVERSE is not set
  1312. +CONFIG_GENERIC_STRNCPY_FROM_USER=y
  1313. +CONFIG_GENERIC_STRNLEN_USER=y
  1314. +CONFIG_GENERIC_IO=y
  1315. +# CONFIG_CRC_CCITT is not set
  1316. +# CONFIG_CRC16 is not set
  1317. +# CONFIG_CRC_T10DIF is not set
  1318. +# CONFIG_CRC_ITU_T is not set
  1319. +CONFIG_CRC32=y
  1320. +# CONFIG_CRC32_SELFTEST is not set
  1321. +CONFIG_CRC32_SLICEBY8=y
  1322. +# CONFIG_CRC32_SLICEBY4 is not set
  1323. +# CONFIG_CRC32_SARWATE is not set
  1324. +# CONFIG_CRC32_BIT is not set
  1325. +# CONFIG_CRC7 is not set
  1326. +# CONFIG_LIBCRC32C is not set
  1327. +# CONFIG_CRC8 is not set
  1328. +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
  1329. +# CONFIG_RANDOM32_SELFTEST is not set
  1330. +# CONFIG_XZ_DEC is not set
  1331. +# CONFIG_XZ_DEC_BCJ is not set
  1332. +CONFIG_HAS_IOMEM=y
  1333. +CONFIG_HAS_DMA=y
  1334. +CONFIG_GENERIC_ATOMIC64=y
  1335. +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
  1336. +# CONFIG_AVERAGE is not set
  1337. +# CONFIG_CORDIC is not set
  1338. +# CONFIG_DDR is not set
  1339. +# CONFIG_ARCH_HAS_SG_CHAIN is not set
  1340. diff -Nur linux-4.1.13.orig/arch/sh/include/asm/board-0pf.h linux-4.1.13/arch/sh/include/asm/board-0pf.h
  1341. --- linux-4.1.13.orig/arch/sh/include/asm/board-0pf.h 1970-01-01 01:00:00.000000000 +0100
  1342. +++ linux-4.1.13/arch/sh/include/asm/board-0pf.h 2015-12-05 00:16:48.000000000 +0100
  1343. @@ -0,0 +1,247 @@
  1344. +#ifndef SGM_BOARD_H
  1345. +#define SGM_BOARD_H
  1346. +
  1347. +#define sys_IntTable (*(unsigned*)0x0)
  1348. +#define sys_IntVectors 256
  1349. +
  1350. +/* Some of interrupt is fixed vector */
  1351. +#define Irq_MRES 0x02 /* Manual reset */
  1352. +#define Irq_CPUERR 0x09
  1353. +#define Irq_DMAERR 0x0a
  1354. +#define Irq_NMI 0x0b
  1355. +#define Irq_PIT 0x10 /* 100 Hz PIT */
  1356. +#define Irq_EMAC 0x11 /* irqs(0) */
  1357. +#define Irq_UART0 0x12 /* irqs(1) */
  1358. +#define Irq_GPS 0x13 /* irqs(2) */
  1359. +#define Irq_Ext 0x14 /* irqs(3) use by CS42518*/
  1360. +#define Irq_1PPS 0x16 /* irqs(5) */
  1361. +#define Irq_UART1 0x17 /* irqs(6) */
  1362. +#define Irq_I2C 0x18 /* irqs(7) */
  1363. +#define Irq_TMR 0x19 /* a 12 bit countdown counter */
  1364. +#define Irq_GPIO 0x15
  1365. +
  1366. +/* External interrupt IDs */
  1367. +#define EIrqID_EMAC 0
  1368. +#define EIrqID_UART0 1
  1369. +#define EIrqID_GPS 2
  1370. +#define EIrqID_Ext 3
  1371. +#define EIrqID_GPIO 4
  1372. +#define EIrqID_1PPS 5
  1373. +#define EIrqID_UART1 6
  1374. +#define EIrqID_I2C 7
  1375. +
  1376. +/* External Interrupt ID convert to interrupt vector */
  1377. +#define ID2Vect(x) (0x11 + (x))
  1378. +
  1379. +/* Convert external interupt ID to priority value */
  1380. +#define ID2Pri(id, pri) ((pri) << ((id) <<2))
  1381. +
  1382. +/* Convert vector to interrupt entry address */
  1383. +#define Vect2Irq(x) ((x) << 2)
  1384. +
  1385. +#define PIT_IRQ Vect2Irq(Irq_PIT)
  1386. +#define EMAC_IRQ Vect2Irq(Irq_EMAC)
  1387. +#define UART0_IRQ Vect2Irq(Irq_UART0)
  1388. +#define GPS_IRQ Vect2Irq(Irq_GPS)
  1389. +#define EXT_IRQ Vect2Irq(Irq_Ext)
  1390. +#define UART1_IRQ Vect2Irq(Irq_UART1)
  1391. +#define I2C_IRQ Vect2Irq(Irq_I2C)
  1392. +#define TMR_IRQ Vect2Irq(Irq_TMR)
  1393. +
  1394. +
  1395. +/* End of interrupt definations */
  1396. +#define sys_RAM_BASE 0x10000000
  1397. +#define sys_PIO_BASE 0xabcd0000
  1398. +#define sys_SPI_BASE 0xabcd0040
  1399. +#define sys_I2C_BASE 0xabcd0080 // 0xabcd0020
  1400. +#define sys_UART0_BASE 0xabcd0100
  1401. +#define sys_SYS_BASE 0xabcd0200
  1402. +#define sys_UART1_BASE 0xabcd0300
  1403. +#define sys_GPS_BASE 0xabcd0400
  1404. +#define sys_D2A_BASE 0xabcd0500
  1405. +#define sys_EMAC_BASE 0xabce0000
  1406. +
  1407. +#define AQ_PIO (*(volatile unsigned int *)sys_PIO_BASE)
  1408. +#define AQ_I2C (*(volatile unsigned int *)sys_I2C_BASE)
  1409. +#define AQ_SPI (*(volatile unsigned int *)sys_SPI_BASE)
  1410. +#define AQ_UART0 (*(volatile unsigned int *)sys_UART0_BASE)
  1411. +#define AQ_SYS (*(volatile unsigned int *)sys_SYS_BASE)
  1412. +#define AQ_UART1 (*(volatile unsigned int *)sys_UART1_BASE)
  1413. +#define AQ_GPS (*(volatile unsigned int *)sys_GPS_BASE)
  1414. +#define AQ_D2A (*(volatile unsigned int *)sys_D2A_BASE)
  1415. +#define AQ_EMAC (*(volatile unsigned int *)sys_EMAC_BASE)
  1416. +
  1417. +
  1418. +struct st_uart16550
  1419. +{
  1420. + unsigned int RTX;
  1421. + unsigned int IER;
  1422. + unsigned int IIR;
  1423. + unsigned int LCR;
  1424. + unsigned int MCR;
  1425. + unsigned int LSR;
  1426. + unsigned int MSR;
  1427. + unsigned int SCR;
  1428. +};
  1429. +#define uLSRDR 0x01
  1430. +#define uLSROE 0x02
  1431. +#define uLSRPE 0x04
  1432. +#define uLSRFE 0x08
  1433. +#define uLSRBI 0x10
  1434. +#define uLSRTHRE 0x20
  1435. +#define uLSRTEMT 0x40
  1436. +#define uLSRRFE 0x80 /* Error in Revr FIFO */
  1437. +
  1438. +#if 0
  1439. +#define B115200 0x000a
  1440. +#define B38400 0x001e
  1441. +#define B19200 0x003c
  1442. +#define B9600 0x0078
  1443. +#define B4800 0x00f0
  1444. +#endif
  1445. +
  1446. +/* the following is belong to sys_SYS_BASE */
  1447. +#define Sys_IntCon 0x0
  1448. +/* When SIC_BRKON is set, BreadAddress will compare with Bus address to generate NMI interrupt */
  1449. +#define Sys_BRKADR 0x04
  1450. +/* Interrupt priority is 4 bits width, irqs(0) is [3,0], irqs(1) is [7,4] ... */
  1451. +#define Sys_IntPri 0x08
  1452. +/* End of offset define of sys_SYS_BASE */
  1453. +/* Refer to Aquarius datasheet Page 12, NMI is lvl16, and lvl0 will not be accept */
  1454. +/* Refer to define.v, IBit in SR [7:4] */
  1455. +#define SIC_ENMI ((unsigned int) 0x1<<31) /* Emulate NMI */
  1456. +#define SIC EIRQ ((unsigned int) 0x1<<30) /* Emulate IRQ */
  1457. +#define SIC_ECER ((unsigned int) 0x1<<29) /* Emulate CPU Address Error */
  1458. +#define SIC_EDER ((unsigned int) 0x1<<28) /* Emulate DMA Address Error */
  1459. +#define SIC_EMRS ((unsigned int) 0x1<<27) /* Emulate Manual Reset */
  1460. +#define SIC_EPIT ((unsigned int) 0x1<<26) /* Enable Periodical interval timer(PIT) */
  1461. +#define SIC_TMRON ((unsigned int) 0x1<<25) /* Enable timer */
  1462. +#define SIC_BRKON ((unsigned int) 0x1<<24) /* Break ON */
  1463. +#define SIC_ILVL ((unsigned int) 0xF<<20) /* interrupt level for PIT */
  1464. +#define SIC_IVEC ((unsigned int) 0xFF<<12) /* Interrupt Vector for PIT */
  1465. +#define SIC_TMR ((unsigned int)0xFFF) /* Interval Timer when 0x0, it request IRQ*/
  1466. +
  1467. +/* PIO registers offset */
  1468. +#define Poffset_IO 0x00
  1469. +#define Poffset_imask 0x04
  1470. +#define Poffset_redge 0x08
  1471. +#define Poffset_changes 0x0c
  1472. +
  1473. +/* Keys are connected to Parallel Input, Active low */
  1474. +#define Pio_KeyEnter 0x0001
  1475. +#define Pio_KeyESC 0x0002
  1476. +#define Pio_KeyNorth 0x0020
  1477. +#define Pio_KeyEast 0x0040
  1478. +#define Pio_KeySouth 0x0080
  1479. +#define Pio_KeyWest 0x0100
  1480. +
  1481. +/* SD_CD is active high of this bit */
  1482. +#define Pio_SD_CD 0x00200000
  1483. +
  1484. +#define Pio_1PPS 0x00800000
  1485. +
  1486. +/* IMPORTANT!!! Pio_LEDPwr is connected with with reset pins of USB, ETH-PHY
  1487. + * and GPS. DON'T CHANGE IT or use it for now!!!
  1488. + * TODO: VHDL needs to fix Power LED to other location with set and reset feature
  1489. + */
  1490. +#define Pio_LEDPwr 0x0010
  1491. +#define Pio_LEDErr 0x0020
  1492. +#define Pio_TP70 0x0040
  1493. +
  1494. +#if 0
  1495. + #define I2c_busy 0x8000
  1496. + #define I2c_next 0x4000
  1497. + #define I2c_ack 0x2000
  1498. + #define I2c_timeout 0x1000
  1499. + #define I2c_timer 0x0800
  1500. + #define I2c_mask 0xf800
  1501. +#else
  1502. + #define I2cO_ctrl 0x00
  1503. + #define I2cO_slen 0x04
  1504. + #define I2cO_word 0x0C
  1505. +
  1506. + /* for I2cO_ctrl */
  1507. + #define I2cC_busy 0x01
  1508. + #define I2cC_timeout 0x02
  1509. + #define I2cC_complete 0x04
  1510. + #define I2cC_reset 0x08
  1511. + #define I2cC_run 0x10
  1512. + #define I2cC_irqen 0x20
  1513. + #define I2cC_clk 0x40
  1514. + #define I2cC_dat 0x80
  1515. + #define I2cC_MaskDelay 0xff00
  1516. + #define I2c_delay(x) ((x)<< 8)
  1517. + #define I2cC_MaskAckTimeout 0xf0000
  1518. + #define I2c_timeout(x) ((x) << 16)
  1519. + /* for I2cO_slen */
  1520. + #define I2cS_MaskXlen 0x1f
  1521. + #define I2cS_MaxLen 16
  1522. + #define I2cS_MaskSpeed 0x30000
  1523. + #define I2cS_100k 0x0
  1524. + #define I2cS_400k 0x10000
  1525. + #define I2cS_1m 0x20000
  1526. + #define I2cS_3m4 0x30000
  1527. + #define I2cS_Maskwordcount 0xf80000
  1528. +#endif
  1529. +
  1530. +/***********************************************************/
  1531. +/************************************ EMAC **************/
  1532. +/***********************************************************/
  1533. +
  1534. +#define AQ_EMAC_BASE 0xABCE0000
  1535. +#define AQ_EMAC_CONTROL 0xABCE0000
  1536. +#define AQ_EMAC_STATUS 0xABCE0000
  1537. +
  1538. +/* Control bits */
  1539. +#define AQ_EMAC_ENABLE_RX 0x00000002
  1540. +#define AQ_EMAC_ENABLE_TX 0x00000004
  1541. +#define AQ_EMAC_READ 0x00000010
  1542. +#define AQ_EMAC_ENABLE_INT_RX 0x00000020
  1543. +#define AQ_EMAC_ENABLE_INT_TX 0x00000040
  1544. +
  1545. +/* Status bits */
  1546. +#define AQ_EMAC_TX_BUSY 0x00000004
  1547. +#define AQ_EMAC_COMPLETE 0x00000100
  1548. +#define AQ_EMAC_CRC 0x00000200
  1549. +
  1550. +#define AQ_EMAC_TX_LEN 0xABCE0004
  1551. +#define AQ_EMAC_MACL 0xABCE0008
  1552. +#define AQ_EMAC_MACH 0xABCE000C
  1553. +#define AQ_EMAC_RX_BUF 0xABCE1000
  1554. +#define AQ_EMAC_TX_BUF 0xABCE1800
  1555. +
  1556. +#define Emac_Rbuf 0x1000
  1557. +#define Emac_Xbuf 0x1800
  1558. +#define Emac_Ctrl 0x0000
  1559. +#define Emac_xlen 0x0004
  1560. +#define Emac_MACL 0x0008
  1561. +#define Emac_MACH 0x000c
  1562. +#define ECtrl_RecvEnable 0x2 /* Receive enable */
  1563. +#define ECtrl_Xmit 0x4 /* Read: Transmit busy(1); Write: Start transmit(1) */
  1564. +#define ECtrl_MACReset 0x8 /* Reset MAC address */
  1565. +#define ECtrl_Read 0x10 /* complete read from Receive FIFO */
  1566. +#define ECtrl_RIntEnable 0x20 /* Receive interrupt enable(1) */
  1567. +#define ECtrl_XIntEnable 0x40 /* Transmit interrupt enable(1) */
  1568. +#define ECtrl_PROM 0x80 /* Promiscuous Mode enable(1)/disable(0) */
  1569. +#define ECtrl_Complete 0x100 /* Receive packet waiting in FIFO */
  1570. +#define ECtrl_CRC 0x200 /* Receive packet has CRC error */
  1571. +#define ECtrl_getrxlen(x) ((x) >> 16) /* Length of received package, when ECtrl_Complete is set */
  1572. +
  1573. +#define Spi_Ctrl 0x0
  1574. +#define Spi_Data 0x4
  1575. +#define SpiCtrl_ACS 0x01 /* chipselect for applcation data */
  1576. +#define SpiCtrl_CCS 0x04 /* chipselect for FPGA configure */
  1577. +#define SpiCtrl_DCS 0x10 /* chipselect for D2A or extra SPI device */
  1578. +#define SpiCtrl_setDiv(x) ((x) << 27) /* Div contrl SPI_CK = 12.5/(div + 1), Min: 400KHz for now*/
  1579. +#define SpiCtrl_Xmit 0x02
  1580. +#define SpiCtrl_Busy 0x02
  1581. +#define SpiCtrl_Loop 0x08 /* When it assert, mosi will connect to miso */
  1582. +/* by default SPI run at 12.5 MHz,maxium speed for Spartan 3E, for SPI Flash
  1583. + * We need a DDS delay for different devices
  1584. + */
  1585. +
  1586. +#define SHJ_PIT_PMR 0xABCD0210
  1587. +#define SHJ_PIT_PCNTR 0xABCD0214
  1588. +#define SHJ_NSEC_PER_CLOCK 0xABCD0218
  1589. +
  1590. +#endif
  1591. diff -Nur linux-4.1.13.orig/arch/sh/include/asm/processor.h linux-4.1.13/arch/sh/include/asm/processor.h
  1592. --- linux-4.1.13.orig/arch/sh/include/asm/processor.h 2015-11-09 23:34:10.000000000 +0100
  1593. +++ linux-4.1.13/arch/sh/include/asm/processor.h 2015-12-05 00:16:49.000000000 +0100
  1594. @@ -15,7 +15,7 @@
  1595. */
  1596. enum cpu_type {
  1597. /* SH-2 types */
  1598. - CPU_SH7619,
  1599. + CPU_SH7619, CPU_0PF,
  1600. /* SH-2A types */
  1601. CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
  1602. diff -Nur linux-4.1.13.orig/arch/sh/include/cpu-sh2/cpu/cache.h linux-4.1.13/arch/sh/include/cpu-sh2/cpu/cache.h
  1603. --- linux-4.1.13.orig/arch/sh/include/cpu-sh2/cpu/cache.h 2015-11-09 23:34:10.000000000 +0100
  1604. +++ linux-4.1.13/arch/sh/include/cpu-sh2/cpu/cache.h 2015-12-05 00:16:49.000000000 +0100
  1605. @@ -38,6 +38,10 @@
  1606. #define CCR_CACHE_INVALIDATE CCR_CACHE_CF
  1607. #define CACHE_PHYSADDR_MASK 0x1ffffc00
  1608. +#elif defined(CONFIG_CPU_SUBTYPE_0PF)
  1609. +#define CCR 0xabcd00c0
  1610. +#define CCR_CACHE_ENABLE 0x80000000
  1611. +#define CCR_CACHE_RESET 0x101
  1612. #endif
  1613. #endif /* __ASM_CPU_SH2_CACHE_H */
  1614. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/init.c linux-4.1.13/arch/sh/kernel/cpu/init.c
  1615. --- linux-4.1.13.orig/arch/sh/kernel/cpu/init.c 2015-11-09 23:34:10.000000000 +0100
  1616. +++ linux-4.1.13/arch/sh/kernel/cpu/init.c 2015-12-05 00:16:49.000000000 +0100
  1617. @@ -106,7 +106,7 @@
  1618. /*
  1619. * Generic first-level cache init
  1620. */
  1621. -#ifdef CONFIG_SUPERH32
  1622. +#if defined(CONFIG_SUPERH32) && !defined(CONFIG_CPU_SUBTYPE_0PF)
  1623. static void cache_init(void)
  1624. {
  1625. unsigned long ccr, flags;
  1626. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/proc.c linux-4.1.13/arch/sh/kernel/cpu/proc.c
  1627. --- linux-4.1.13.orig/arch/sh/kernel/cpu/proc.c 2015-11-09 23:34:10.000000000 +0100
  1628. +++ linux-4.1.13/arch/sh/kernel/cpu/proc.c 2015-12-05 00:16:49.000000000 +0100
  1629. @@ -26,6 +26,7 @@
  1630. [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
  1631. [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
  1632. [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
  1633. + [CPU_0PF] = "SH2J-0PF",
  1634. [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
  1635. [CPU_SH_NONE] = "Unknown"
  1636. };
  1637. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/Makefile linux-4.1.13/arch/sh/kernel/cpu/sh2/Makefile
  1638. --- linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/Makefile 2015-11-09 23:34:10.000000000 +0100
  1639. +++ linux-4.1.13/arch/sh/kernel/cpu/sh2/Makefile 2015-12-05 00:16:49.000000000 +0100
  1640. @@ -5,3 +5,4 @@
  1641. obj-y := ex.o probe.o entry.o
  1642. obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o clock-sh7619.o
  1643. +obj-$(CONFIG_CPU_SUBTYPE_0PF) += setup-0pf.o clock-0pf.o
  1644. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/clock-0pf.c linux-4.1.13/arch/sh/kernel/cpu/sh2/clock-0pf.c
  1645. --- linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/clock-0pf.c 1970-01-01 01:00:00.000000000 +0100
  1646. +++ linux-4.1.13/arch/sh/kernel/cpu/sh2/clock-0pf.c 2015-12-05 00:16:48.000000000 +0100
  1647. @@ -0,0 +1,80 @@
  1648. +/*
  1649. + * arch/sh/kernel/cpu/sh2/clock-0pf.c
  1650. + *
  1651. + * 0PF FPGA support for the clock framework
  1652. + *
  1653. + * Copyright (C) 2012 SEI, Inc.
  1654. + *
  1655. + * Based on clock-sh4.c
  1656. + * Copyright (C) 2005 Paul Mundt
  1657. + * Copyright (C) 2009 D. Jeff Dionne
  1658. + *
  1659. + * This file is subject to the terms and conditions of the GNU General Public
  1660. + * License. See the file "COPYING" in the main directory of this archive
  1661. + * for more details.
  1662. + */
  1663. +#include <linux/init.h>
  1664. +#include <linux/kernel.h>
  1665. +#include <asm/clock.h>
  1666. +#include <linux/timex.h>
  1667. +#include <linux/profile.h>
  1668. +#include <linux/interrupt.h>
  1669. +#include <linux/irq.h>
  1670. +
  1671. +#include <asm/freq.h>
  1672. +#include <asm/io.h>
  1673. +
  1674. +static void master_clk_init(struct clk *clk)
  1675. +{
  1676. + clk->rate = CONFIG_SH_PCLK_FREQ; /* Fixed Rate */
  1677. +}
  1678. +
  1679. +static struct sh_clk_ops shj_master_clk_ops = {
  1680. + .init = master_clk_init,
  1681. +};
  1682. +
  1683. +static unsigned long module_clk_recalc(struct clk *clk)
  1684. +{
  1685. + return clk->parent->rate;
  1686. +}
  1687. +
  1688. +static struct sh_clk_ops shj_module_clk_ops = {
  1689. + .recalc = module_clk_recalc,
  1690. +};
  1691. +
  1692. +static unsigned long bus_clk_recalc(struct clk *clk)
  1693. +{
  1694. + return clk->parent->rate;
  1695. +}
  1696. +
  1697. +static struct sh_clk_ops shj_bus_clk_ops = {
  1698. + .recalc = bus_clk_recalc,
  1699. +};
  1700. +
  1701. +static struct sh_clk_ops shj_cpu_clk_ops = {
  1702. + .recalc = followparent_recalc,
  1703. +};
  1704. +
  1705. +static struct sh_clk_ops *shj_clk_ops[] = {
  1706. + &shj_master_clk_ops,
  1707. + &shj_module_clk_ops,
  1708. + &shj_bus_clk_ops,
  1709. + &shj_cpu_clk_ops,
  1710. +};
  1711. +
  1712. +void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
  1713. +{
  1714. + if (idx < ARRAY_SIZE(shj_clk_ops))
  1715. + *ops = shj_clk_ops[idx];
  1716. +}
  1717. +
  1718. +int __init arch_clk_init()
  1719. +{
  1720. + int ret;
  1721. +
  1722. + printk("%s(): 0PF Clock init...\n", __func__);
  1723. +
  1724. + ret = cpg_clk_init(); /* appease Over-engineered "clock infrastructure" */
  1725. +
  1726. + return ret;
  1727. +}
  1728. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/entry.S linux-4.1.13/arch/sh/kernel/cpu/sh2/entry.S
  1729. --- linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/entry.S 2015-11-09 23:34:10.000000000 +0100
  1730. +++ linux-4.1.13/arch/sh/kernel/cpu/sh2/entry.S 2015-12-05 00:16:49.000000000 +0100
  1731. @@ -3,6 +3,7 @@
  1732. *
  1733. * The SH-2 exception entry
  1734. *
  1735. + * Copyright (C) 2012 SEI,Inc.
  1736. * Copyright (C) 2005-2008 Yoshinori Sato
  1737. * Copyright (C) 2005 AXE,Inc.
  1738. *
  1739. @@ -147,7 +148,11 @@
  1740. mov #32,r8
  1741. cmp/hs r8,r9
  1742. bt trap_entry ! 64 > vec >= 32 is trap
  1743. -
  1744. +#if defined(CONFIG_CPU_SUBTYPE_0PF)
  1745. + mov #16,r8
  1746. + cmp/hs r8,r9
  1747. + bt interrupt_entry ! 32 > vec >= 16 is interrupt
  1748. +#endif
  1749. mov.l 4f,r8
  1750. mov r9,r4
  1751. shll2 r9
  1752. @@ -245,6 +250,19 @@
  1753. .align 2
  1754. 1: .long do_address_error
  1755. +#if defined(CONFIG_CPU_SUBTYPE_0PF)
  1756. +ENTRY(pc_address_error_trap_handler)
  1757. + mov r15,r4 ! regs
  1758. + mov #OFF_PC,r0
  1759. + mov.l @(r0,r15),r6 ! pc
  1760. + mov.l 1f,r0
  1761. + jmp @r0
  1762. + mov #0,r5 ! writeaccess is unknown
  1763. +
  1764. + .align 2
  1765. +1: .long do_pc_address_error
  1766. +#endif // CONFIG_CPU_SUBTYPE_0PF
  1767. +
  1768. restore_all:
  1769. stc sr,r0
  1770. or #0xf0,r0
  1771. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/probe.c linux-4.1.13/arch/sh/kernel/cpu/sh2/probe.c
  1772. --- linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/probe.c 2015-11-09 23:34:10.000000000 +0100
  1773. +++ linux-4.1.13/arch/sh/kernel/cpu/sh2/probe.c 2015-12-05 00:16:49.000000000 +0100
  1774. @@ -24,6 +24,12 @@
  1775. boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
  1776. boot_cpu_data.dcache.flags = 0;
  1777. #endif
  1778. +
  1779. +#if defined(CONFIG_CPU_SUBTYPE_0PF)
  1780. + boot_cpu_data.type = CPU_0PF;
  1781. + boot_cpu_data.dcache.flags = 0;
  1782. +#endif
  1783. +
  1784. /*
  1785. * SH-2 doesn't have separate caches
  1786. */
  1787. diff -Nur linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/setup-0pf.c linux-4.1.13/arch/sh/kernel/cpu/sh2/setup-0pf.c
  1788. --- linux-4.1.13.orig/arch/sh/kernel/cpu/sh2/setup-0pf.c 1970-01-01 01:00:00.000000000 +0100
  1789. +++ linux-4.1.13/arch/sh/kernel/cpu/sh2/setup-0pf.c 2015-12-05 00:16:48.000000000 +0100
  1790. @@ -0,0 +1,82 @@
  1791. +/*
  1792. + * 0PF-FPGA Setup
  1793. + *
  1794. + * Copyright (C) 2006 Yoshinori Sato
  1795. + * Copyright (C) 2009 Paul Mundt
  1796. + * Copyright (C) 2009 D. Jeff Dionne
  1797. + * Copyright (C) 2012 SEI, Inc.
  1798. + * by Oleksandr Zhadan
  1799. + *
  1800. + * This file is subject to the terms and conditions of the GNU General Public
  1801. + * License. See the file "COPYING" in the main directory of this archive
  1802. + * for more details.
  1803. + */
  1804. +#include <linux/platform_device.h>
  1805. +#include <linux/init.h>
  1806. +#include <linux/module.h>
  1807. +#include <linux/io.h>
  1808. +#include <linux/interrupt.h>
  1809. +#include <linux/irq.h>
  1810. +#include <linux/serial_8250.h>
  1811. +#include <asm/board-0pf.h>
  1812. +
  1813. +#if defined(CONFIG_SERIAL_UARTLITE_0PF)
  1814. +static struct resource shj_uartlite_resources[] = {
  1815. + [0] = DEFINE_RES_MEM(0xABCD0100, 16),
  1816. + [1] = DEFINE_RES_IRQ(0x12),
  1817. +
  1818. + [2] = DEFINE_RES_MEM(0xABCD0300, 16),
  1819. + [3] = DEFINE_RES_IRQ(0x17),
  1820. +
  1821. + [4] = DEFINE_RES_MEM(0xABCD0400, 16),
  1822. + [5] = DEFINE_RES_IRQ(0x13),
  1823. +};
  1824. +
  1825. +static struct platform_device shj_uartlite_device[] = {
  1826. + [0] = { .name = "uartlite", .id = 0 },
  1827. + [1] = { .name = "uartlite", .id = 1 },
  1828. + [2] = { .name = "uartlite", .id = 2 },
  1829. +};
  1830. +#endif
  1831. +
  1832. +/*****************************************************************************
  1833. + * 0PF FPGA platform devices
  1834. + ****************************************************************************/
  1835. +static struct platform_device *shj_devices[] __initdata = {
  1836. +#if defined(CONFIG_SERIAL_UARTLITE_0PF)
  1837. + shj_uartlite_device,
  1838. + shj_uartlite_device + 1,
  1839. + shj_uartlite_device + 2,
  1840. +#endif
  1841. +};
  1842. +
  1843. +static int __init shj_devices_setup(void)
  1844. +{
  1845. + int i;
  1846. + pr_info("%s(): registering device resources\n", __func__);
  1847. +
  1848. +#if defined(CONFIG_SERIAL_UARTLITE_0PF)
  1849. + for (i = 0; i < ARRAY_SIZE(shj_uartlite_device); i++) {
  1850. + printk("Register UARTLITE resources %d\n", i);
  1851. + if (platform_device_add_resources(
  1852. + shj_uartlite_device + i,
  1853. + shj_uartlite_resources + 2 * i,
  1854. + 2))
  1855. + pr_err("Failed to set uartlite %d IRQ and MEM\n", i);
  1856. +
  1857. + }
  1858. +#endif
  1859. + platform_add_devices(shj_devices, ARRAY_SIZE(shj_devices));
  1860. +
  1861. + return 0;
  1862. +}
  1863. +
  1864. +arch_initcall(shj_devices_setup);
  1865. +
  1866. +void __init native_machine_early_platform_add_devices(void)
  1867. +{
  1868. +}
  1869. +
  1870. +void __init plat_irq_setup(void)
  1871. +{
  1872. +}
  1873. diff -Nur linux-4.1.13.orig/arch/sh/kernel/irq.c linux-4.1.13/arch/sh/kernel/irq.c
  1874. --- linux-4.1.13.orig/arch/sh/kernel/irq.c 2015-11-09 23:34:10.000000000 +0100
  1875. +++ linux-4.1.13/arch/sh/kernel/irq.c 2015-12-05 00:16:49.000000000 +0100
  1876. @@ -20,6 +20,8 @@
  1877. #include <asm/thread_info.h>
  1878. #include <cpu/mmu_context.h>
  1879. +#include <asm/board-0pf.h>
  1880. +
  1881. atomic_t irq_err_count;
  1882. /*
  1883. @@ -175,11 +177,24 @@
  1884. );
  1885. }
  1886. #else
  1887. +#define noinline __attribute__((noinline))
  1888. +static noinline void handle_irq_UART0(unsigned int irq) { generic_handle_irq(irq); }
  1889. +static noinline void handle_irq_UART1(unsigned int irq) { generic_handle_irq(irq); }
  1890. +static noinline void handle_irq_GPS(unsigned int irq) { generic_handle_irq(irq); }
  1891. +static noinline void handle_irq_EMAC(unsigned int irq) { generic_handle_irq(irq); }
  1892. static inline void handle_one_irq(unsigned int irq)
  1893. {
  1894. - generic_handle_irq(irq);
  1895. + switch(irq) {
  1896. + case Irq_UART0: handle_irq_UART0(irq); break;
  1897. + case Irq_UART1: handle_irq_UART1(irq); break;
  1898. + case Irq_GPS: handle_irq_GPS(irq); break;
  1899. + case Irq_EMAC: handle_irq_EMAC(irq); break;
  1900. + default:
  1901. + generic_handle_irq(irq);
  1902. + break;
  1903. + }
  1904. }
  1905. -#endif
  1906. +#endif // CONFIG_IRQSTACKS
  1907. asmlinkage __irq_entry int do_IRQ(unsigned int irq, struct pt_regs *regs)
  1908. {
  1909. diff -Nur linux-4.1.13.orig/arch/sh/kernel/traps_32.c linux-4.1.13/arch/sh/kernel/traps_32.c
  1910. --- linux-4.1.13.orig/arch/sh/kernel/traps_32.c 2015-11-09 23:34:10.000000000 +0100
  1911. +++ linux-4.1.13/arch/sh/kernel/traps_32.c 2015-12-05 00:16:49.000000000 +0100
  1912. @@ -34,6 +34,7 @@
  1913. #ifdef CONFIG_CPU_SH2
  1914. # define TRAP_RESERVED_INST 4
  1915. # define TRAP_ILLEGAL_SLOT_INST 6
  1916. +# define TRAP_PC_ADDRESS_ERROR 8 // Aug 20, 2012 ulianov - SEI extension - PC governor
  1917. # define TRAP_ADDRESS_ERROR 9
  1918. # ifdef CONFIG_CPU_SH2A
  1919. # define TRAP_UBC 12
  1920. @@ -458,6 +459,14 @@
  1921. return ret;
  1922. }
  1923. +#if defined(CONFIG_CPU_SUBTYPE_0PF)
  1924. +asmlinkage void do_pc_address_error(struct pt_regs *regs,
  1925. + unsigned long writeaccess,
  1926. + unsigned long address)
  1927. +{
  1928. +}
  1929. +#endif // CONFIG_CPU_SUBTYPE_0PF
  1930. +
  1931. /*
  1932. * Handle various address error exceptions:
  1933. * - instruction address error:
  1934. @@ -779,6 +788,9 @@
  1935. #endif
  1936. #ifdef CONFIG_CPU_SH2
  1937. + #if defined(CONFIG_CPU_SUBTYPE_0PF)
  1938. + set_exception_table_vec(TRAP_PC_ADDRESS_ERROR, address_error_trap_handler);
  1939. + #endif
  1940. set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
  1941. #endif
  1942. #ifdef CONFIG_CPU_SH2A
  1943. diff -Nur linux-4.1.13.orig/arch/sh/mm/cache-sh2.c linux-4.1.13/arch/sh/mm/cache-sh2.c
  1944. --- linux-4.1.13.orig/arch/sh/mm/cache-sh2.c 2015-11-09 23:34:10.000000000 +0100
  1945. +++ linux-4.1.13/arch/sh/mm/cache-sh2.c 2015-12-05 00:16:49.000000000 +0100
  1946. @@ -3,6 +3,7 @@
  1947. *
  1948. * Copyright (C) 2002 Paul Mundt
  1949. * Copyright (C) 2008 Yoshinori Sato
  1950. + * Copyright (C) 2012 SEI, Inc.
  1951. *
  1952. * Released under the terms of the GNU GPL v2.0.
  1953. */
  1954. @@ -16,6 +17,30 @@
  1955. #include <asm/cacheflush.h>
  1956. #include <asm/io.h>
  1957. +#if defined(CONFIG_CPU_SUBTYPE_0PF)
  1958. +
  1959. +// Just flush the whole thing each time
  1960. +static void j2_flush_icache_range(void *fwoosh)
  1961. +{
  1962. + __raw_writel(CCR_CACHE_RESET, CCR);
  1963. +}
  1964. +
  1965. +// This should never happen, but...
  1966. +static void j2_flush_icache_page(void *fwoosh)
  1967. +{
  1968. + __raw_writel(CCR_CACHE_RESET, CCR);
  1969. +}
  1970. +
  1971. +void __init sh2_cache_init(void)
  1972. +{
  1973. + local_flush_icache_range = j2_flush_icache_range;
  1974. + local_flush_icache_page = j2_flush_icache_page;
  1975. + boot_cpu_data.dcache.n_aliases = 0;
  1976. +
  1977. + __raw_writel(CCR_CACHE_RESET, CCR);
  1978. +}
  1979. +
  1980. +#else
  1981. static void sh2__flush_wback_region(void *start, int size)
  1982. {
  1983. unsigned long v;
  1984. @@ -89,3 +114,4 @@
  1985. __flush_purge_region = sh2__flush_purge_region;
  1986. __flush_invalidate_region = sh2__flush_invalidate_region;
  1987. }
  1988. +#endif
  1989. diff -Nur linux-4.1.13.orig/arch/sh/mm/cache.c linux-4.1.13/arch/sh/mm/cache.c
  1990. --- linux-4.1.13.orig/arch/sh/mm/cache.c 2015-11-09 23:34:10.000000000 +0100
  1991. +++ linux-4.1.13/arch/sh/mm/cache.c 2015-12-05 00:16:49.000000000 +0100
  1992. @@ -258,14 +258,16 @@
  1993. boot_cpu_data.icache.entry_mask,
  1994. boot_cpu_data.icache.alias_mask,
  1995. boot_cpu_data.icache.n_aliases);
  1996. - printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
  1997. - boot_cpu_data.dcache.ways,
  1998. - boot_cpu_data.dcache.sets,
  1999. - boot_cpu_data.dcache.way_incr);
  2000. - printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
  2001. - boot_cpu_data.dcache.entry_mask,
  2002. - boot_cpu_data.dcache.alias_mask,
  2003. - boot_cpu_data.dcache.n_aliases);
  2004. + if (boot_cpu_data.dcache.n_aliases) {
  2005. + printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
  2006. + boot_cpu_data.dcache.ways,
  2007. + boot_cpu_data.dcache.sets,
  2008. + boot_cpu_data.dcache.way_incr);
  2009. + printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
  2010. + boot_cpu_data.dcache.entry_mask,
  2011. + boot_cpu_data.dcache.alias_mask,
  2012. + boot_cpu_data.dcache.n_aliases);
  2013. + }
  2014. /*
  2015. * Emit Secondary Cache parameters if the CPU has a probed L2.
  2016. diff -Nur linux-4.1.13.orig/drivers/tty/serial/Kconfig linux-4.1.13/drivers/tty/serial/Kconfig
  2017. --- linux-4.1.13.orig/drivers/tty/serial/Kconfig 2015-11-09 23:34:10.000000000 +0100
  2018. +++ linux-4.1.13/drivers/tty/serial/Kconfig 2015-12-05 00:16:49.000000000 +0100
  2019. @@ -594,7 +594,7 @@
  2020. config SERIAL_UARTLITE
  2021. tristate "Xilinx uartlite serial port support"
  2022. - depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE || ARCH_ZYNQ
  2023. + depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE || ARCH_ZYNQ || CPU_SUBTYPE_0PF
  2024. select SERIAL_CORE
  2025. help
  2026. Say Y here if you want to use the Xilinx uartlite serial controller.
  2027. @@ -611,6 +611,12 @@
  2028. console (the system console is the device which receives all kernel
  2029. messages and warnings and which allows logins in single user mode).
  2030. +config SERIAL_UARTLITE_0PF
  2031. + tristate "Support 0PF UARTLITEs"
  2032. + depends on SERIAL_UARTLITE = y && CPU_SUBTYPE_0PF
  2033. + help
  2034. + Say Y here to set up 0PF's UARTLITEs.
  2035. +
  2036. config SERIAL_SUNCORE
  2037. bool
  2038. depends on SPARC