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gcc.nds32 2.2 MB

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  1. diff -Nur gcc-4.9.4.orig/gcc/c/gccspec.c gcc-4.9.4/gcc/c/gccspec.c
  2. --- gcc-4.9.4.orig/gcc/c/gccspec.c 2014-01-02 23:23:26.000000000 +0100
  3. +++ gcc-4.9.4/gcc/c/gccspec.c 2016-08-08 20:37:45.494269627 +0200
  4. @@ -104,5 +104,12 @@
  5. return 0; /* Not used for C. */
  6. }
  7. +/* Called before parsing the spec to tell which language driver is used. */
  8. +int
  9. +lang_specific_is_c_plus_plus (void)
  10. +{
  11. + return 0;
  12. +}
  13. +
  14. /* Number of extra output files that lang_specific_pre_link may generate. */
  15. int lang_specific_extra_outfiles = 0; /* Not used for C. */
  16. diff -Nur gcc-4.9.4.orig/gcc/c-family/c.opt gcc-4.9.4/gcc/c-family/c.opt
  17. --- gcc-4.9.4.orig/gcc/c-family/c.opt 2014-04-03 15:41:55.000000000 +0200
  18. +++ gcc-4.9.4/gcc/c-family/c.opt 2016-08-08 20:37:45.494269627 +0200
  19. @@ -851,10 +851,6 @@
  20. fbuilding-libgcc
  21. C ObjC C++ ObjC++ Undocumented Var(flag_building_libgcc)
  22. -fbuiltin
  23. -C ObjC C++ ObjC++ Var(flag_no_builtin, 0)
  24. -Recognize built-in functions
  25. -
  26. fbuiltin-
  27. C ObjC C++ ObjC++ Joined
  28. diff -Nur gcc-4.9.4.orig/gcc/c-family/cppspec.c gcc-4.9.4/gcc/c-family/cppspec.c
  29. --- gcc-4.9.4.orig/gcc/c-family/cppspec.c 2014-01-02 23:23:26.000000000 +0100
  30. +++ gcc-4.9.4/gcc/c-family/cppspec.c 2016-08-08 20:37:45.494269627 +0200
  31. @@ -194,5 +194,12 @@
  32. return 0; /* Not used for cpp. */
  33. }
  34. +/* Called before parsing the spec to tell which language driver is used. */
  35. +int
  36. +lang_specific_is_c_plus_plus (void)
  37. +{
  38. + return 0;
  39. +}
  40. +
  41. /* Number of extra output files that lang_specific_pre_link may generate. */
  42. int lang_specific_extra_outfiles = 0; /* Not used for cpp. */
  43. diff -Nur gcc-4.9.4.orig/gcc/common/config/nds32/nds32-common.c gcc-4.9.4/gcc/common/config/nds32/nds32-common.c
  44. --- gcc-4.9.4.orig/gcc/common/config/nds32/nds32-common.c 2014-01-02 23:23:26.000000000 +0100
  45. +++ gcc-4.9.4/gcc/common/config/nds32/nds32-common.c 2016-08-08 20:37:45.494269627 +0200
  46. @@ -1,5 +1,5 @@
  47. /* Common hooks of Andes NDS32 cpu for GNU compiler
  48. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  49. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  50. Contributed by Andes Technology Corporation.
  51. This file is part of GCC.
  52. @@ -74,15 +74,57 @@
  53. /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
  54. static const struct default_options nds32_option_optimization_table[] =
  55. {
  56. - /* Enable -fomit-frame-pointer by default at -O1 or higher. */
  57. - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
  58. +#ifdef TARGET_DEFAULT_NO_MATH_ERRNO
  59. + /* Under some configuration, we would like to use -fno-math-errno by default
  60. + at all optimization levels for performance and code size consideration.
  61. + Please check gcc/config.gcc for more implementation details. */
  62. + { OPT_LEVELS_ALL, OPT_fmath_errno, NULL, 0 },
  63. +#endif
  64. +#ifndef TARGET_LINUX_ABI
  65. + /* Disable -fdelete-null-pointer-checks by default in ELF toolchain. */
  66. + { OPT_LEVELS_ALL, OPT_flag_delete_null_pointer_checks,
  67. + NULL, 0 },
  68. +#endif
  69. + /* Enable -fomit-frame-pointer by default at all optimization levels. */
  70. + { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 },
  71. + /* Enable -mrelax-hint by default at all optimization levels. */
  72. + { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 },
  73. + /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */
  74. + { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 },
  75. /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */
  76. - { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 },
  77. + { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 },
  78. + /* Enable -mload-store-opt by default at -Os. */
  79. + { OPT_LEVELS_SIZE, OPT_mload_store_opt, NULL, 1 },
  80. + /* Enable -mregrename by default at -O1 and above. */
  81. + { OPT_LEVELS_1_PLUS, OPT_mregrename, NULL, 1 },
  82. + /* Enable -mgcse by default at -O1 and above. */
  83. + { OPT_LEVELS_1_PLUS, OPT_mgcse, NULL, 1 },
  84. +#ifdef TARGET_OS_DEFAULT_IFC
  85. + /* Enable -mifc by default at -Os, but it is useless under V2/V3M ISA. */
  86. + { OPT_LEVELS_SIZE, OPT_mifc, NULL, 1 },
  87. +#endif
  88. +#ifdef TARGET_OS_DEFAULT_EX9
  89. + /* Enable -mex9 by default at -Os, but it is useless under V2/V3M ISA. */
  90. + { OPT_LEVELS_SIZE, OPT_mex9, NULL, 1 },
  91. +#endif
  92. - { OPT_LEVELS_NONE, 0, NULL, 0 }
  93. + { OPT_LEVELS_NONE, 0, NULL, 0 }
  94. };
  95. /* ------------------------------------------------------------------------ */
  96. +
  97. +/* Implement TARGET_EXCEPT_UNWIND_INFO. */
  98. +static enum unwind_info_type
  99. +nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED)
  100. +{
  101. + if (TARGET_LINUX_ABI)
  102. + return UI_DWARF2;
  103. +
  104. + return UI_SJLJ;
  105. +}
  106. +
  107. +/* ------------------------------------------------------------------------ */
  108. +
  109. /* Run-time Target Specification. */
  110. @@ -95,16 +137,22 @@
  111. Other MASK_XXX flags are set individually.
  112. By default we enable
  113. - TARGET_GP_DIRECT: Generate gp-imply instruction.
  114. - TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
  115. - TARGET_PERF_EXT : Generate performance extention instrcution.
  116. - TARGET_CMOV : Generate conditional move instruction. */
  117. + TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
  118. + TARGET_EXT_PERF : Generate performance extention instrcution.
  119. + TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
  120. + TARGET_EXT_STRING : Generate string extention instrcution.
  121. + TARGET_HW_ABS : Generate hardware abs instruction.
  122. + TARGET_CMOV : Generate conditional move instruction. */
  123. #undef TARGET_DEFAULT_TARGET_FLAGS
  124. #define TARGET_DEFAULT_TARGET_FLAGS \
  125. (TARGET_CPU_DEFAULT \
  126. - | MASK_GP_DIRECT \
  127. + | TARGET_DEFAULT_FPU_ISA \
  128. + | TARGET_DEFAULT_FPU_FMA \
  129. | MASK_16_BIT \
  130. - | MASK_PERF_EXT \
  131. + | MASK_EXT_PERF \
  132. + | MASK_EXT_PERF2 \
  133. + | MASK_EXT_STRING \
  134. + | MASK_HW_ABS \
  135. | MASK_CMOV)
  136. #undef TARGET_HANDLE_OPTION
  137. @@ -117,7 +165,7 @@
  138. /* Defining the Output Assembler Language. */
  139. #undef TARGET_EXCEPT_UNWIND_INFO
  140. -#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
  141. +#define TARGET_EXCEPT_UNWIND_INFO nds32_except_unwind_info
  142. /* ------------------------------------------------------------------------ */
  143. diff -Nur gcc-4.9.4.orig/gcc/common.opt gcc-4.9.4/gcc/common.opt
  144. --- gcc-4.9.4.orig/gcc/common.opt 2015-02-26 03:43:52.000000000 +0100
  145. +++ gcc-4.9.4/gcc/common.opt 2016-08-08 20:37:45.494269627 +0200
  146. @@ -898,6 +898,10 @@
  147. Common Report Var(flag_btr_bb_exclusive) Optimization
  148. Restrict target load migration not to re-use registers in any basic block
  149. +fbuiltin
  150. +Common Var(flag_no_builtin, 0)
  151. +Recognize built-in functions
  152. +
  153. fcall-saved-
  154. Common Joined RejectNegative Var(common_deferred_options) Defer
  155. -fcall-saved-<register> Mark <register> as being preserved across functions
  156. @@ -1160,7 +1164,7 @@
  157. Common
  158. ffat-lto-objects
  159. -Common Var(flag_fat_lto_objects)
  160. +Common Var(flag_fat_lto_objects) Init(1)
  161. Output lto objects containing both the intermediate language and binary output.
  162. ffinite-math-only
  163. @@ -2202,6 +2206,10 @@
  164. Common Report Var(flag_tree_sra) Optimization
  165. Perform scalar replacement of aggregates
  166. +ftree-switch-shortcut
  167. +Common Report Var(flag_tree_switch_shortcut) Init(0) Optimization
  168. +Do fancy switch statement shortcutting
  169. +
  170. ftree-ter
  171. Common Report Var(flag_tree_ter) Optimization
  172. Replace temporary expressions in the SSA->normal pass
  173. diff -Nur gcc-4.9.4.orig/gcc/config/arm/arm.h gcc-4.9.4/gcc/config/arm/arm.h
  174. --- gcc-4.9.4.orig/gcc/config/arm/arm.h 2016-03-29 15:32:37.000000000 +0200
  175. +++ gcc-4.9.4/gcc/config/arm/arm.h 2016-08-08 20:37:45.494269627 +0200
  176. @@ -1162,7 +1162,7 @@
  177. /* Tell IRA to use the order we define rather than messing it up with its
  178. own cost calculations. */
  179. -#define HONOR_REG_ALLOC_ORDER
  180. +#define HONOR_REG_ALLOC_ORDER 1
  181. /* Interrupt functions can only use registers that have already been
  182. saved by the prologue, even if they would normally be
  183. diff -Nur gcc-4.9.4.orig/gcc/config/i386/host-cygwin.c gcc-4.9.4/gcc/config/i386/host-cygwin.c
  184. --- gcc-4.9.4.orig/gcc/config/i386/host-cygwin.c 2014-01-02 23:23:26.000000000 +0100
  185. +++ gcc-4.9.4/gcc/config/i386/host-cygwin.c 2016-08-08 20:37:45.494269627 +0200
  186. @@ -62,7 +62,7 @@
  187. fatal_error ("can%'t extend PCH file: %m");
  188. }
  189. - base = mmap (NULL, sz, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
  190. + base = mmap ((void *) 0x60000000, sz, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
  191. if (base == MAP_FAILED)
  192. base = NULL;
  193. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/0001-Add-option-m16bit-mno-16bit-for-backward-compatibili.patch gcc-4.9.4/gcc/config/nds32/0001-Add-option-m16bit-mno-16bit-for-backward-compatibili.patch
  194. --- gcc-4.9.4.orig/gcc/config/nds32/0001-Add-option-m16bit-mno-16bit-for-backward-compatibili.patch 1970-01-01 01:00:00.000000000 +0100
  195. +++ gcc-4.9.4/gcc/config/nds32/0001-Add-option-m16bit-mno-16bit-for-backward-compatibili.patch 2016-08-08 20:37:45.494269627 +0200
  196. @@ -0,0 +1,26 @@
  197. +From c8f442699258adea1df44e6a11906b6e98dbb793 Mon Sep 17 00:00:00 2001
  198. +From: Kito Cheng <kito@andestech.com>
  199. +Date: Mon, 7 Dec 2015 17:50:51 +0800
  200. +Subject: [PATCH 1/2] Add option -m16bit/-mno-16bit for backward compatibility
  201. +
  202. +---
  203. + gcc/config/nds32/nds32.opt | 3 +++
  204. + 1 file changed, 3 insertions(+)
  205. +
  206. +diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt
  207. +index ed3ccb9..78119a3 100644
  208. +--- a/gcc/config/nds32/nds32.opt
  209. ++++ b/gcc/config/nds32/nds32.opt
  210. +@@ -129,6 +129,9 @@ m16-bit
  211. + Target Report Mask(16_BIT)
  212. + Generate 16-bit instructions.
  213. +
  214. ++m16bit
  215. ++Target Alias(m16-bit) Undocumented
  216. ++
  217. + mrelax-hint
  218. + Target Report Mask(RELAX_HINT)
  219. + Insert relax hint for linker to do relaxation.
  220. +--
  221. +2.4.3
  222. +
  223. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/0002-Use-default-crt-begin-end-.o-which-provide-by-gcc-in.patch gcc-4.9.4/gcc/config/nds32/0002-Use-default-crt-begin-end-.o-which-provide-by-gcc-in.patch
  224. --- gcc-4.9.4.orig/gcc/config/nds32/0002-Use-default-crt-begin-end-.o-which-provide-by-gcc-in.patch 1970-01-01 01:00:00.000000000 +0100
  225. +++ gcc-4.9.4/gcc/config/nds32/0002-Use-default-crt-begin-end-.o-which-provide-by-gcc-in.patch 2016-08-08 20:37:45.494269627 +0200
  226. @@ -0,0 +1,142 @@
  227. +From 8079ff97a5ea42ac56765bce2b4855d24dcc7b10 Mon Sep 17 00:00:00 2001
  228. +From: Kito Cheng <kito@andestech.com>
  229. +Date: Mon, 7 Dec 2015 10:25:03 +0800
  230. +Subject: [PATCH 2/2] Use default crt[begin|end]*.o which provide by gcc in
  231. + linux toolchain
  232. +
  233. +---
  234. + gcc/config/nds32/elf.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++
  235. + gcc/config/nds32/nds32.h | 46 ----------------------------------------------
  236. + libgcc/config.host | 5 ++---
  237. + 3 files changed, 48 insertions(+), 49 deletions(-)
  238. +
  239. +diff --git a/gcc/config/nds32/elf.h b/gcc/config/nds32/elf.h
  240. +index 808fd44..67e5b0e 100644
  241. +--- a/gcc/config/nds32/elf.h
  242. ++++ b/gcc/config/nds32/elf.h
  243. +@@ -34,3 +34,49 @@
  244. + NDS32_RELAX_SPEC \
  245. + NDS32_IFC_SPEC \
  246. + NDS32_EX9_SPEC
  247. ++
  248. ++#define LIB_SPEC \
  249. ++ " -lc -lgloss"
  250. ++
  251. ++#define LIBGCC_SPEC \
  252. ++ " -lgcc"
  253. ++
  254. ++/* The option -mno-ctor-dtor can disable constructor/destructor feature
  255. ++ by applying different crt stuff. In the convention, crt0.o is the
  256. ++ startup file without constructor/destructor;
  257. ++ crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
  258. ++ startup files with constructor/destructor.
  259. ++ Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
  260. ++ by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
  261. ++ currently provided by GCC for nds32 target.
  262. ++
  263. ++ For nds32 target so far:
  264. ++ If -mno-ctor-dtor, we are going to link
  265. ++ "crt0.o [user objects]".
  266. ++ If -mctor-dtor, we are going to link
  267. ++ "crt1.o crtbegin1.o [user objects] crtend1.o".
  268. ++
  269. ++ Note that the TARGET_DEFAULT_CTOR_DTOR would effect the
  270. ++ default behavior. Check gcc/config.gcc for more information. */
  271. ++#ifdef TARGET_DEFAULT_CTOR_DTOR
  272. ++ #define STARTFILE_SPEC \
  273. ++ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  274. ++ " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  275. ++ " %{mcrt-arg:crtarg.o%s}"
  276. ++ #define ENDFILE_SPEC \
  277. ++ " %{!mno-ctor-dtor:crtend1.o%s}"
  278. ++#else
  279. ++ #define STARTFILE_SPEC \
  280. ++ " %{mctor-dtor|coverage:crt1.o%s;:crt0.o%s}" \
  281. ++ " %{mctor-dtor|coverage:crtbegin1.o%s}" \
  282. ++ " %{mcrt-arg:crtarg.o%s}"
  283. ++ #define ENDFILE_SPEC \
  284. ++ " %{mctor-dtor|coverage:crtend1.o%s}"
  285. ++#endif
  286. ++
  287. ++#define STARTFILE_CXX_SPEC \
  288. ++ " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  289. ++ " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  290. ++ " %{mcrt-arg:crtarg.o%s}"
  291. ++#define ENDFILE_CXX_SPEC \
  292. ++ " %{!mno-ctor-dtor:crtend1.o%s}"
  293. +diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
  294. +index 954f54f..19978a0 100644
  295. +--- a/gcc/config/nds32/nds32.h
  296. ++++ b/gcc/config/nds32/nds32.h
  297. +@@ -984,52 +984,6 @@ enum nds32_builtins
  298. + " %{mext-zol:-mzol-ext}" \
  299. + " %{O|O1|O2|O3|Ofast:-O1;:-Os}"
  300. +
  301. +-#define LIB_SPEC \
  302. +- " -lc -lgloss"
  303. +-
  304. +-#define LIBGCC_SPEC \
  305. +- " -lgcc"
  306. +-
  307. +-/* The option -mno-ctor-dtor can disable constructor/destructor feature
  308. +- by applying different crt stuff. In the convention, crt0.o is the
  309. +- startup file without constructor/destructor;
  310. +- crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
  311. +- startup files with constructor/destructor.
  312. +- Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
  313. +- by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
  314. +- currently provided by GCC for nds32 target.
  315. +-
  316. +- For nds32 target so far:
  317. +- If -mno-ctor-dtor, we are going to link
  318. +- "crt0.o [user objects]".
  319. +- If -mctor-dtor, we are going to link
  320. +- "crt1.o crtbegin1.o [user objects] crtend1.o".
  321. +-
  322. +- Note that the TARGET_DEFAULT_CTOR_DTOR would effect the
  323. +- default behavior. Check gcc/config.gcc for more information. */
  324. +-#ifdef TARGET_DEFAULT_CTOR_DTOR
  325. +- #define STARTFILE_SPEC \
  326. +- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  327. +- " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  328. +- " %{mcrt-arg:crtarg.o%s}"
  329. +- #define ENDFILE_SPEC \
  330. +- " %{!mno-ctor-dtor:crtend1.o%s}"
  331. +-#else
  332. +- #define STARTFILE_SPEC \
  333. +- " %{mctor-dtor|coverage:crt1.o%s;:crt0.o%s}" \
  334. +- " %{mctor-dtor|coverage:crtbegin1.o%s}" \
  335. +- " %{mcrt-arg:crtarg.o%s}"
  336. +- #define ENDFILE_SPEC \
  337. +- " %{mctor-dtor|coverage:crtend1.o%s}"
  338. +-#endif
  339. +-
  340. +-#define STARTFILE_CXX_SPEC \
  341. +- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  342. +- " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  343. +- " %{mcrt-arg:crtarg.o%s}"
  344. +-#define ENDFILE_CXX_SPEC \
  345. +- " %{!mno-ctor-dtor:crtend1.o%s}"
  346. +-
  347. + /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
  348. + configure gcc with --target=nds32be-* setting.
  349. + Check gcc/config.gcc for more information. */
  350. +diff --git a/libgcc/config.host b/libgcc/config.host
  351. +index d980d8a..3710504 100644
  352. +--- a/libgcc/config.host
  353. ++++ b/libgcc/config.host
  354. +@@ -882,9 +882,8 @@ msp430*-*-elf)
  355. + nds32*-linux*)
  356. + # Basic makefile fragment and extra_parts for crt stuff.
  357. + # We also append c-isr library implementation.
  358. +- tmake_file="${tmake_file} nds32/t-nds32 t-slibgcc-libgcc"
  359. +- extra_parts="crtbegin1.o crtend1.o crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o "
  360. +- tmake_file="${tmake_file} nds32/t-nds32-glibc t-softfp-sfdf t-softfp"
  361. ++ tmake_file="${tmake_file} t-slibgcc-libgcc"
  362. ++ tmake_file="${tmake_file} nds32/t-nds32-glibc nds32/t-crtstuff t-softfp-sfdf t-softfp"
  363. + # Append library definition makefile fragment according to --with-nds32-lib=X setting.
  364. + case "${with_nds32_lib}" in
  365. + "" )
  366. +--
  367. +2.4.3
  368. +
  369. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/constants.md gcc-4.9.4/gcc/config/nds32/constants.md
  370. --- gcc-4.9.4.orig/gcc/config/nds32/constants.md 2014-01-02 23:23:26.000000000 +0100
  371. +++ gcc-4.9.4/gcc/config/nds32/constants.md 2016-08-08 20:37:45.494269627 +0200
  372. @@ -1,5 +1,5 @@
  373. ;; Constant defintions of Andes NDS32 cpu for GNU compiler
  374. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  375. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  376. ;; Contributed by Andes Technology Corporation.
  377. ;;
  378. ;; This file is part of GCC.
  379. @@ -23,24 +23,191 @@
  380. (define_constants
  381. [(R8_REGNUM 8)
  382. (TA_REGNUM 15)
  383. + (TP_REGNUM 25)
  384. (FP_REGNUM 28)
  385. (GP_REGNUM 29)
  386. (LP_REGNUM 30)
  387. (SP_REGNUM 31)
  388. + (LB_REGNUM 98)
  389. + (LE_REGNUM 99)
  390. + (LC_REGNUM 100)
  391. ])
  392. +;; The unpec operation index.
  393. +(define_c_enum "unspec_element" [
  394. + UNSPEC_COPYSIGN
  395. + UNSPEC_FCPYNSD
  396. + UNSPEC_FCPYNSS
  397. + UNSPEC_FCPYSD
  398. + UNSPEC_FCPYSS
  399. + UNSPEC_AVE
  400. + UNSPEC_BCLR
  401. + UNSPEC_BSET
  402. + UNSPEC_BTGL
  403. + UNSPEC_BTST
  404. + UNSPEC_CLIP
  405. + UNSPEC_CLIPS
  406. + UNSPEC_CLZ
  407. + UNSPEC_CLO
  408. + UNSPEC_ABS
  409. + UNSPEC_MAX
  410. + UNSPEC_MIN
  411. + UNSPEC_PBSAD
  412. + UNSPEC_PBSADA
  413. + UNSPEC_BSE
  414. + UNSPEC_BSE_2
  415. + UNSPEC_BSP
  416. + UNSPEC_BSP_2
  417. + UNSPEC_FFB
  418. + UNSPEC_FFMISM
  419. + UNSPEC_FLMISM
  420. + UNSPEC_KADDW
  421. + UNSPEC_KSUBW
  422. + UNSPEC_KADDH
  423. + UNSPEC_KSUBH
  424. + UNSPEC_KDMBB
  425. + UNSPEC_KDMBT
  426. + UNSPEC_KDMTB
  427. + UNSPEC_KDMTT
  428. + UNSPEC_KHMBB
  429. + UNSPEC_KHMBT
  430. + UNSPEC_KHMTB
  431. + UNSPEC_KHMTT
  432. + UNSPEC_KSLRAW
  433. + UNSPEC_KSLRAWU
  434. + UNSPEC_RDOV
  435. + UNSPEC_CLROV
  436. + UNSPEC_SVA
  437. + UNSPEC_SVS
  438. + UNSPEC_WSBH
  439. + UNSPEC_LWUP
  440. + UNSPEC_LBUP
  441. + UNSPEC_SWUP
  442. + UNSPEC_SBUP
  443. + UNSPEC_LMWZB
  444. + UNSPEC_SMWZB
  445. + UNSPEC_UALOAD_HW
  446. + UNSPEC_UALOAD_W
  447. + UNSPEC_UALOAD_DW
  448. + UNSPEC_UASTORE_HW
  449. + UNSPEC_UASTORE_W
  450. + UNSPEC_UASTORE_DW
  451. + UNSPEC_GOTINIT
  452. + UNSPEC_GOT
  453. + UNSPEC_GOTOFF
  454. + UNSPEC_PLT
  455. + UNSPEC_TLSGD
  456. + UNSPEC_TLSLD
  457. + UNSPEC_TLSIE
  458. + UNSPEC_TLSLE
  459. + UNSPEC_ROUND
  460. + UNSPEC_VEC_COMPARE
  461. + UNSPEC_KHM
  462. + UNSPEC_KHMX
  463. + UNSPEC_CLIP_OV
  464. + UNSPEC_CLIPS_OV
  465. + UNSPEC_BITREV
  466. + UNSPEC_KABS
  467. + UNSPEC_LOOP_END
  468. + UNSPEC_TLS_DESC
  469. + UNSPEC_TLS_IE
  470. +])
  471. +
  472. +
  473. ;; The unspec_volatile operation index.
  474. (define_c_enum "unspec_volatile_element" [
  475. - UNSPEC_VOLATILE_FUNC_RETURN
  476. + UNSPEC_VOLATILE_EH_RETURN
  477. UNSPEC_VOLATILE_ISYNC
  478. UNSPEC_VOLATILE_ISB
  479. + UNSPEC_VOLATILE_DSB
  480. + UNSPEC_VOLATILE_MSYNC
  481. + UNSPEC_VOLATILE_MSYNC_ALL
  482. + UNSPEC_VOLATILE_MSYNC_STORE
  483. UNSPEC_VOLATILE_MFSR
  484. UNSPEC_VOLATILE_MFUSR
  485. UNSPEC_VOLATILE_MTSR
  486. UNSPEC_VOLATILE_MTUSR
  487. UNSPEC_VOLATILE_SETGIE_EN
  488. UNSPEC_VOLATILE_SETGIE_DIS
  489. + UNSPEC_VOLATILE_FMFCSR
  490. + UNSPEC_VOLATILE_FMTCSR
  491. + UNSPEC_VOLATILE_FMFCFG
  492. + UNSPEC_VOLATILE_JR_ITOFF
  493. + UNSPEC_VOLATILE_JR_TOFF
  494. + UNSPEC_VOLATILE_JRAL_ITON
  495. + UNSPEC_VOLATILE_JRAL_TON
  496. + UNSPEC_VOLATILE_RET_ITOFF
  497. + UNSPEC_VOLATILE_RET_TOFF
  498. + UNSPEC_VOLATILE_STANDBY_NO_WAKE_GRANT
  499. + UNSPEC_VOLATILE_STANDBY_WAKE_GRANT
  500. + UNSPEC_VOLATILE_STANDBY_WAKE_DONE
  501. + UNSPEC_VOLATILE_TEQZ
  502. + UNSPEC_VOLATILE_TNEZ
  503. + UNSPEC_VOLATILE_TRAP
  504. + UNSPEC_VOLATILE_SETEND_BIG
  505. + UNSPEC_VOLATILE_SETEND_LITTLE
  506. + UNSPEC_VOLATILE_BREAK
  507. + UNSPEC_VOLATILE_SYSCALL
  508. + UNSPEC_VOLATILE_NOP
  509. + UNSPEC_VOLATILE_RES_DEP
  510. + UNSPEC_VOLATILE_DATA_DEP
  511. + UNSPEC_VOLATILE_GET_CURRENT_SP
  512. + UNSPEC_VOLATILE_SET_CURRENT_SP
  513. + UNSPEC_VOLATILE_LLW
  514. + UNSPEC_VOLATILE_SCW
  515. + UNSPEC_VOLATILE_CCTL_L1D_INVALALL
  516. + UNSPEC_VOLATILE_CCTL_L1D_WBALL_ALVL
  517. + UNSPEC_VOLATILE_CCTL_L1D_WBALL_ONE_LVL
  518. + UNSPEC_VOLATILE_CCTL_IDX_WRITE
  519. + UNSPEC_VOLATILE_CCTL_IDX_READ
  520. + UNSPEC_VOLATILE_CCTL_VA_WBINVAL_L1
  521. + UNSPEC_VOLATILE_CCTL_VA_WBINVAL_LA
  522. + UNSPEC_VOLATILE_CCTL_IDX_WBINVAL
  523. + UNSPEC_VOLATILE_CCTL_VA_LCK
  524. + UNSPEC_VOLATILE_DPREF_QW
  525. + UNSPEC_VOLATILE_DPREF_HW
  526. + UNSPEC_VOLATILE_DPREF_W
  527. + UNSPEC_VOLATILE_DPREF_DW
  528. + UNSPEC_VOLATILE_TLBOP_TRD
  529. + UNSPEC_VOLATILE_TLBOP_TWR
  530. + UNSPEC_VOLATILE_TLBOP_RWR
  531. + UNSPEC_VOLATILE_TLBOP_RWLK
  532. + UNSPEC_VOLATILE_TLBOP_UNLK
  533. + UNSPEC_VOLATILE_TLBOP_PB
  534. + UNSPEC_VOLATILE_TLBOP_INV
  535. + UNSPEC_VOLATILE_TLBOP_FLUA
  536. + UNSPEC_VOLATILE_ENABLE_INT
  537. + UNSPEC_VOLATILE_DISABLE_INT
  538. + UNSPEC_VOLATILE_SET_PENDING_SWINT
  539. + UNSPEC_VOLATILE_CLR_PENDING_SWINT
  540. + UNSPEC_VOLATILE_CLR_PENDING_HWINT
  541. + UNSPEC_VOLATILE_GET_ALL_PENDING_INT
  542. + UNSPEC_VOLATILE_GET_PENDING_INT
  543. + UNSPEC_VOLATILE_SET_INT_PRIORITY
  544. + UNSPEC_VOLATILE_GET_INT_PRIORITY
  545. + UNSPEC_VOLATILE_SET_TRIG_LEVEL
  546. + UNSPEC_VOLATILE_SET_TRIG_EDGE
  547. + UNSPEC_VOLATILE_GET_TRIG_TYPE
  548. + UNSPEC_VOLATILE_RELAX_GROUP
  549. + UNSPEC_VOLATILE_INNERMOST_LOOP_BEGIN
  550. + UNSPEC_VOLATILE_INNERMOST_LOOP_END
  551. + UNSPEC_VOLATILE_MAYBE_ALIGN
  552. + UNSPEC_VOLATILE_OMIT_FP_BEGIN
  553. + UNSPEC_VOLATILE_OMIT_FP_END
  554. + UNSPEC_VOLATILE_RETURN_ADDRESS
  555. + UNSPEC_VOLATILE_POP25_RETURN
  556. + UNSPEC_VOLATILE_UPDATE_GP
  557. + UNSPEC_VOLATILE_SIGNATURE_BEGIN
  558. + UNSPEC_VOLATILE_SIGNATURE_END
  559. + UNSPEC_VOLATILE_NO_HWLOOP
  560. + UNSPEC_VOLATILE_NO_IFC_BEGIN
  561. + UNSPEC_VOLATILE_NO_IFC_END
  562. + UNSPEC_VOLATILE_NO_EX9_BEGIN
  563. + UNSPEC_VOLATILE_NO_EX9_END
  564. + UNSPEC_VOLATILE_UNALIGNED_FEATURE
  565. + UNSPEC_VOLATILE_ENABLE_UNALIGNED
  566. + UNSPEC_VOLATILE_DISABLE_UNALIGNED
  567. ])
  568. ;; ------------------------------------------------------------------------
  569. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/constraints.md gcc-4.9.4/gcc/config/nds32/constraints.md
  570. --- gcc-4.9.4.orig/gcc/config/nds32/constraints.md 2014-01-02 23:23:26.000000000 +0100
  571. +++ gcc-4.9.4/gcc/config/nds32/constraints.md 2016-08-08 20:37:45.498269782 +0200
  572. @@ -1,5 +1,5 @@
  573. ;; Constraint definitions of Andes NDS32 cpu for GNU compiler
  574. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  575. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  576. ;; Contributed by Andes Technology Corporation.
  577. ;;
  578. ;; This file is part of GCC.
  579. @@ -25,9 +25,6 @@
  580. ;; Machine-dependent floating: G H
  581. -(define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
  582. - "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
  583. -
  584. (define_register_constraint "l" "LOW_REGS"
  585. "LOW register class $r0 ~ $r7")
  586. @@ -41,9 +38,59 @@
  587. (define_register_constraint "t" "R15_TA_REG"
  588. "Temporary Assist register $ta (i.e. $r15)")
  589. +(define_register_constraint "e" "R8_REG"
  590. + "Function Entry register $r8)")
  591. +
  592. (define_register_constraint "k" "STACK_REG"
  593. "Stack register $sp")
  594. +(define_register_constraint "v" "R5_REG"
  595. + "Register $r5")
  596. +
  597. +(define_register_constraint "x" "FRAME_POINTER_REG"
  598. + "Frame pointer register $fp")
  599. +
  600. +(define_register_constraint "f"
  601. + "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
  602. + "The Floating point registers $fs0 ~ $fs31")
  603. +
  604. +(define_register_constraint "A" "LOOP_REGS"
  605. + "Loop register class")
  606. +
  607. +(define_constraint "Iv00"
  608. + "Constant value 0"
  609. + (and (match_code "const_int")
  610. + (match_test "ival == 0")))
  611. +
  612. +(define_constraint "Iv01"
  613. + "Constant value 1"
  614. + (and (match_code "const_int")
  615. + (match_test "ival == 1")))
  616. +
  617. +(define_constraint "Iv02"
  618. + "Constant value 2"
  619. + (and (match_code "const_int")
  620. + (match_test "ival == 2")))
  621. +
  622. +(define_constraint "Iv04"
  623. + "Constant value 4"
  624. + (and (match_code "const_int")
  625. + (match_test "ival == 4")))
  626. +
  627. +(define_constraint "Iv08"
  628. + "Constant value 8"
  629. + (and (match_code "const_int")
  630. + (match_test "ival == 8")))
  631. +
  632. +(define_constraint "Iu01"
  633. + "Unsigned immediate 1-bit value"
  634. + (and (match_code "const_int")
  635. + (match_test "ival == 1 || ival == 0")))
  636. +
  637. +(define_constraint "Iu02"
  638. + "Unsigned immediate 2-bit value"
  639. + (and (match_code "const_int")
  640. + (match_test "ival < (1 << 2) && ival >= 0")))
  641. (define_constraint "Iu03"
  642. "Unsigned immediate 3-bit value"
  643. @@ -65,6 +112,11 @@
  644. (and (match_code "const_int")
  645. (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
  646. +(define_constraint "Cs05"
  647. + "Signed immediate 5-bit value"
  648. + (and (match_code "const_double")
  649. + (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))
  650. +
  651. (define_constraint "Iu05"
  652. "Unsigned immediate 5-bit value"
  653. (and (match_code "const_int")
  654. @@ -75,6 +127,11 @@
  655. (and (match_code "const_int")
  656. (match_test "IN_RANGE (ival, -31, 0)")))
  657. +(define_constraint "Iu06"
  658. + "Unsigned immediate 6-bit value"
  659. + (and (match_code "const_int")
  660. + (match_test "ival < (1 << 6) && ival >= 0")))
  661. +
  662. ;; Ip05 is special and dedicated for v3 movpi45 instruction.
  663. ;; movpi45 has imm5u field but the range is 16 ~ 47.
  664. (define_constraint "Ip05"
  665. @@ -84,10 +141,10 @@
  666. && ival >= (0 + 16)
  667. && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
  668. -(define_constraint "Iu06"
  669. +(define_constraint "IU06"
  670. "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
  671. (and (match_code "const_int")
  672. - (match_test "ival < (1 << 6)
  673. + (match_test "ival < (1 << 8)
  674. && ival >= 0
  675. && (ival % 4 == 0)
  676. && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
  677. @@ -103,6 +160,11 @@
  678. (match_test "ival < (1 << 9) && ival >= 0")))
  679. +(define_constraint "Is08"
  680. + "Signed immediate 8-bit value"
  681. + (and (match_code "const_int")
  682. + (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
  683. +
  684. (define_constraint "Is10"
  685. "Signed immediate 10-bit value"
  686. (and (match_code "const_int")
  687. @@ -113,6 +175,10 @@
  688. (and (match_code "const_int")
  689. (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
  690. +(define_constraint "Is14"
  691. + "Signed immediate 14-bit value"
  692. + (and (match_code "const_int")
  693. + (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
  694. (define_constraint "Is15"
  695. "Signed immediate 15-bit value"
  696. @@ -194,12 +260,21 @@
  697. (and (match_code "const_int")
  698. (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
  699. +(define_constraint "Cs20"
  700. + "Signed immediate 20-bit value"
  701. + (and (match_code "const_double")
  702. + (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))
  703. (define_constraint "Ihig"
  704. "The immediate value that can be simply set high 20-bit"
  705. (and (match_code "const_int")
  706. (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
  707. +(define_constraint "Chig"
  708. + "The immediate value that can be simply set high 20-bit"
  709. + (and (match_code "high")
  710. + (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
  711. +
  712. (define_constraint "Izeb"
  713. "The immediate value 0xff"
  714. (and (match_code "const_int")
  715. @@ -213,12 +288,12 @@
  716. (define_constraint "Ixls"
  717. "The immediate value 0x01"
  718. (and (match_code "const_int")
  719. - (match_test "TARGET_PERF_EXT && (ival == 0x1)")))
  720. + (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
  721. (define_constraint "Ix11"
  722. "The immediate value 0x7ff"
  723. (and (match_code "const_int")
  724. - (match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
  725. + (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
  726. (define_constraint "Ibms"
  727. "The immediate value with power of 2"
  728. @@ -232,23 +307,70 @@
  729. (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
  730. && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
  731. +(define_constraint "CVp5"
  732. + "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
  733. + (and (match_code "const_vector")
  734. + (match_test "nds32_valid_CVp5_p (op)")))
  735. +
  736. +(define_constraint "CVs5"
  737. + "Signed immediate 5-bit value"
  738. + (and (match_code "const_vector")
  739. + (match_test "nds32_valid_CVs5_p (op)")))
  740. +
  741. +(define_constraint "CVs2"
  742. + "Signed immediate 20-bit value"
  743. + (and (match_code "const_vector")
  744. + (match_test "nds32_valid_CVs2_p (op)")))
  745. +
  746. +(define_constraint "CVhi"
  747. + "The immediate value that can be simply set high 20-bit"
  748. + (and (match_code "const_vector")
  749. + (match_test "nds32_valid_CVhi_p (op)")))
  750. (define_memory_constraint "U33"
  751. "Memory constraint for 333 format"
  752. (and (match_code "mem")
  753. - (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
  754. + (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
  755. + || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
  756. + || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
  757. (define_memory_constraint "U45"
  758. "Memory constraint for 45 format"
  759. (and (match_code "mem")
  760. (match_test "(nds32_mem_format (op) == ADDRESS_REG)
  761. - && (GET_MODE (op) == SImode)")))
  762. + && ((GET_MODE (op) == SImode)
  763. + || (GET_MODE (op) == SFmode))")))
  764. +
  765. +(define_memory_constraint "Ufe"
  766. + "Memory constraint for fe format"
  767. + (and (match_code "mem")
  768. + (match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
  769. + && (GET_MODE (op) == SImode
  770. + || GET_MODE (op) == SFmode)")))
  771. (define_memory_constraint "U37"
  772. "Memory constraint for 37 format"
  773. (and (match_code "mem")
  774. (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
  775. || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
  776. - && (GET_MODE (op) == SImode)")))
  777. + && (GET_MODE (op) == SImode
  778. + || GET_MODE (op) == SFmode)")))
  779. +
  780. +(define_memory_constraint "Umw"
  781. + "Memory constraint for lwm/smw"
  782. + (and (match_code "mem")
  783. + (match_test "nds32_valid_smw_lwm_base_p (op)")))
  784. +
  785. +(define_memory_constraint "Da"
  786. + "Memory constraint for non-offset loads/stores"
  787. + (and (match_code "mem")
  788. + (match_test "REG_P (XEXP (op, 0))
  789. + || (GET_CODE (XEXP (op, 0)) == POST_INC)")))
  790. +
  791. +(define_memory_constraint "Q"
  792. + "Memory constraint for no symbol_ref and const"
  793. + (and (match_code "mem")
  794. + (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  795. + && nds32_float_mem_operand_p (op)")))
  796. ;; ------------------------------------------------------------------------
  797. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/elf.h gcc-4.9.4/gcc/config/nds32/elf.h
  798. --- gcc-4.9.4.orig/gcc/config/nds32/elf.h 1970-01-01 01:00:00.000000000 +0100
  799. +++ gcc-4.9.4/gcc/config/nds32/elf.h 2016-08-08 20:37:45.498269782 +0200
  800. @@ -0,0 +1,82 @@
  801. +/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
  802. + Copyright (C) 2012-2014 Free Software Foundation, Inc.
  803. + Contributed by Andes Technology Corporation.
  804. +
  805. + This file is part of GCC.
  806. +
  807. + GCC is free software; you can redistribute it and/or modify it
  808. + under the terms of the GNU General Public License as published
  809. + by the Free Software Foundation; either version 3, or (at your
  810. + option) any later version.
  811. +
  812. + GCC is distributed in the hope that it will be useful, but WITHOUT
  813. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  814. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  815. + License for more details.
  816. +
  817. + You should have received a copy of the GNU General Public License
  818. + along with GCC; see the file COPYING3. If not see
  819. + <http://www.gnu.org/licenses/>. */
  820. +
  821. +
  822. +/* ------------------------------------------------------------------------ */
  823. +
  824. +#define TARGET_LINUX_ABI 0
  825. +
  826. +/* In the configure stage we may use options --enable-default-relax,
  827. + --enable-Os-default-ifc and --enable-Os-default-ex9. They effect
  828. + the default spec of passing --relax, --mifc, and --mex9 to linker.
  829. + We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC
  830. + so that we can customize them conveniently. */
  831. +#define LINK_SPEC \
  832. + " %{G*}" \
  833. + " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
  834. + NDS32_RELAX_SPEC \
  835. + NDS32_IFC_SPEC \
  836. + NDS32_EX9_SPEC
  837. +
  838. +#define LIB_SPEC \
  839. + " -lc -lgloss"
  840. +
  841. +#define LIBGCC_SPEC \
  842. + " -lgcc"
  843. +
  844. +/* The option -mno-ctor-dtor can disable constructor/destructor feature
  845. + by applying different crt stuff. In the convention, crt0.o is the
  846. + startup file without constructor/destructor;
  847. + crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
  848. + startup files with constructor/destructor.
  849. + Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
  850. + by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
  851. + currently provided by GCC for nds32 target.
  852. +
  853. + For nds32 target so far:
  854. + If -mno-ctor-dtor, we are going to link
  855. + "crt0.o [user objects]".
  856. + If -mctor-dtor, we are going to link
  857. + "crt1.o crtbegin1.o [user objects] crtend1.o".
  858. +
  859. + Note that the TARGET_DEFAULT_CTOR_DTOR would effect the
  860. + default behavior. Check gcc/config.gcc for more information. */
  861. +#ifdef TARGET_DEFAULT_CTOR_DTOR
  862. + #define STARTFILE_SPEC \
  863. + " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  864. + " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  865. + " %{mcrt-arg:crtarg.o%s}"
  866. + #define ENDFILE_SPEC \
  867. + " %{!mno-ctor-dtor:crtend1.o%s}"
  868. +#else
  869. + #define STARTFILE_SPEC \
  870. + " %{mctor-dtor|coverage:crt1.o%s;:crt0.o%s}" \
  871. + " %{mctor-dtor|coverage:crtbegin1.o%s}" \
  872. + " %{mcrt-arg:crtarg.o%s}"
  873. + #define ENDFILE_SPEC \
  874. + " %{mctor-dtor|coverage:crtend1.o%s}"
  875. +#endif
  876. +
  877. +#define STARTFILE_CXX_SPEC \
  878. + " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  879. + " %{!mno-ctor-dtor:crtbegin1.o%s}" \
  880. + " %{mcrt-arg:crtarg.o%s}"
  881. +#define ENDFILE_CXX_SPEC \
  882. + " %{!mno-ctor-dtor:crtend1.o%s}"
  883. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/iterators.md gcc-4.9.4/gcc/config/nds32/iterators.md
  884. --- gcc-4.9.4.orig/gcc/config/nds32/iterators.md 2014-01-02 23:23:26.000000000 +0100
  885. +++ gcc-4.9.4/gcc/config/nds32/iterators.md 2016-08-08 20:37:45.498269782 +0200
  886. @@ -1,6 +1,6 @@
  887. ;; Code and mode itertator and attribute definitions
  888. ;; of Andes NDS32 cpu for GNU compiler
  889. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  890. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  891. ;; Contributed by Andes Technology Corporation.
  892. ;;
  893. ;; This file is part of GCC.
  894. @@ -26,30 +26,99 @@
  895. ;; A list of integer modes that are up to one word long.
  896. (define_mode_iterator QIHISI [QI HI SI])
  897. +;; A list of integer modes for one word and double word.
  898. +(define_mode_iterator SIDI [SI DI])
  899. +
  900. ;; A list of integer modes that are up to one half-word long.
  901. (define_mode_iterator QIHI [QI HI])
  902. ;; A list of the modes that are up to double-word long.
  903. (define_mode_iterator DIDF [DI DF])
  904. +;; A list of the modes that are up to one word long vector.
  905. +(define_mode_iterator VQIHI [V4QI V2HI])
  906. +
  907. +;; A list of the modes that are up to one word long vector and scalar.
  908. +(define_mode_iterator VSQIHI [V4QI V2HI QI HI])
  909. +
  910. +(define_mode_iterator VSQIHIDI [V4QI V2HI QI HI DI])
  911. +
  912. +(define_mode_iterator VQIHIDI [V4QI V2HI DI])
  913. +
  914. +;; A list of the modes that are up to one word long vector
  915. +;; and scalar for HImode.
  916. +(define_mode_iterator VSHI [V2HI HI])
  917. +
  918. +;; A list of the modes that are up to double-word long.
  919. +(define_mode_iterator ANYF [(SF "TARGET_FPU_SINGLE")
  920. + (DF "TARGET_FPU_DOUBLE")])
  921. ;;----------------------------------------------------------------------------
  922. ;; Mode attributes.
  923. ;;----------------------------------------------------------------------------
  924. -(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
  925. +(define_mode_attr size [(QI "b") (HI "h") (SI "w") (SF "s") (DF "d")])
  926. -(define_mode_attr byte [(QI "1") (HI "2") (SI "4")])
  927. +(define_mode_attr byte [(QI "1") (HI "2") (SI "4") (V4QI "4") (V2HI "4")])
  928. +(define_mode_attr bits [(V4QI "8") (QI "8") (V2HI "16") (HI "16") (DI "64")])
  929. +
  930. +(define_mode_attr VELT [(V4QI "QI") (V2HI "HI")])
  931. ;;----------------------------------------------------------------------------
  932. ;; Code iterators.
  933. ;;----------------------------------------------------------------------------
  934. +;; shifts
  935. +(define_code_iterator shift_rotate [ashift ashiftrt lshiftrt rotatert])
  936. +
  937. +(define_code_iterator shifts [ashift ashiftrt lshiftrt])
  938. +
  939. +(define_code_iterator shiftrt [ashiftrt lshiftrt])
  940. +
  941. +(define_code_iterator sat_plus [ss_plus us_plus])
  942. +
  943. +(define_code_iterator all_plus [plus ss_plus us_plus])
  944. +
  945. +(define_code_iterator sat_minus [ss_minus us_minus])
  946. +
  947. +(define_code_iterator all_minus [minus ss_minus us_minus])
  948. +
  949. +(define_code_iterator plus_minus [plus minus])
  950. +
  951. +(define_code_iterator extend [sign_extend zero_extend])
  952. +
  953. +(define_code_iterator sumax [smax umax])
  954. +
  955. +(define_code_iterator sumin [smin umin])
  956. +
  957. +(define_code_iterator sumin_max [smax umax smin umin])
  958. ;;----------------------------------------------------------------------------
  959. ;; Code attributes.
  960. ;;----------------------------------------------------------------------------
  961. +;; shifts
  962. +(define_code_attr shift
  963. + [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr") (rotatert "rotr")])
  964. +
  965. +(define_code_attr su
  966. + [(ashiftrt "") (lshiftrt "u") (sign_extend "s") (zero_extend "u")])
  967. +
  968. +(define_code_attr zs
  969. + [(sign_extend "s") (zero_extend "z")])
  970. +
  971. +(define_code_attr uk
  972. + [(plus "") (ss_plus "k") (us_plus "uk")
  973. + (minus "") (ss_minus "k") (us_minus "uk")])
  974. +
  975. +(define_code_attr opcode
  976. + [(plus "add") (minus "sub") (smax "smax") (umax "umax") (smin "smin") (umin "umin")])
  977. +
  978. +(define_code_attr add_rsub
  979. + [(plus "a") (minus "rs")])
  980. +
  981. +(define_code_attr add_sub
  982. + [(plus "a") (minus "s")])
  983. ;;----------------------------------------------------------------------------
  984. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/linux.h gcc-4.9.4/gcc/config/nds32/linux.h
  985. --- gcc-4.9.4.orig/gcc/config/nds32/linux.h 1970-01-01 01:00:00.000000000 +0100
  986. +++ gcc-4.9.4/gcc/config/nds32/linux.h 2016-08-08 20:37:45.498269782 +0200
  987. @@ -0,0 +1,70 @@
  988. +/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
  989. + Copyright (C) 2012-2014 Free Software Foundation, Inc.
  990. + Contributed by Andes Technology Corporation.
  991. +
  992. + This file is part of GCC.
  993. +
  994. + GCC is free software; you can redistribute it and/or modify it
  995. + under the terms of the GNU General Public License as published
  996. + by the Free Software Foundation; either version 3, or (at your
  997. + option) any later version.
  998. +
  999. + GCC is distributed in the hope that it will be useful, but WITHOUT
  1000. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  1001. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  1002. + License for more details.
  1003. +
  1004. + You should have received a copy of the GNU General Public License
  1005. + along with GCC; see the file COPYING3. If not see
  1006. + <http://www.gnu.org/licenses/>. */
  1007. +
  1008. +
  1009. +/* ------------------------------------------------------------------------ */
  1010. +
  1011. +#define TARGET_LINUX_ABI 1
  1012. +
  1013. +#undef SIZE_TYPE
  1014. +#define SIZE_TYPE "unsigned int"
  1015. +
  1016. +#undef PTRDIFF_TYPE
  1017. +#define PTRDIFF_TYPE "int"
  1018. +
  1019. +#define TARGET_OS_CPP_BUILTINS() \
  1020. + do \
  1021. + { \
  1022. + GNU_USER_TARGET_OS_CPP_BUILTINS(); \
  1023. + } \
  1024. + while (0)
  1025. +
  1026. +#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
  1027. +
  1028. +/* In the configure stage we may use options --enable-default-relax,
  1029. + --enable-Os-default-ifc and --enable-Os-default-ex9. They effect
  1030. + the default spec of passing --relax, --mifc, and --mex9 to linker.
  1031. + We use NDS32_RELAX_SPEC, NDS32_IFC_SPEC, and NDS32_EX9_SPEC
  1032. + so that we can customize them conveniently. */
  1033. +#define LINK_SPEC \
  1034. + " %{G*}" \
  1035. + " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
  1036. + "%{shared:-shared} \
  1037. + %{!shared: \
  1038. + %{!static: \
  1039. + %{rdynamic:-export-dynamic} \
  1040. + -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
  1041. + %{static:-static}}" \
  1042. + NDS32_RELAX_SPEC \
  1043. + NDS32_IFC_SPEC \
  1044. + NDS32_EX9_SPEC
  1045. +
  1046. +#define LINK_PIE_SPEC "%{pie:%{!fno-pie:%{!fno-PIE:%{!static:-pie}}}} "
  1047. +
  1048. +
  1049. +/* The SYNC operations are implemented as library functions, not
  1050. + INSN patterns. As a result, the HAVE defines for the patterns are
  1051. + not defined. We need to define them to generate the corresponding
  1052. + __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* and __GCC_ATOMIC_*_LOCK_FREE
  1053. + defines.
  1054. + Ref: https://sourceware.org/ml/libc-alpha/2014-09/msg00322.html */
  1055. +#define HAVE_sync_compare_and_swapqi 1
  1056. +#define HAVE_sync_compare_and_swaphi 1
  1057. +#define HAVE_sync_compare_and_swapsi 1
  1058. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32.c gcc-4.9.4/gcc/config/nds32/nds32.c
  1059. --- gcc-4.9.4.orig/gcc/config/nds32/nds32.c 2014-02-14 07:02:16.000000000 +0100
  1060. +++ gcc-4.9.4/gcc/config/nds32/nds32.c 2016-08-08 20:37:45.586273189 +0200
  1061. @@ -1,5 +1,5 @@
  1062. /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
  1063. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  1064. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  1065. Contributed by Andes Technology Corporation.
  1066. This file is part of GCC.
  1067. @@ -18,13 +18,14 @@
  1068. along with GCC; see the file COPYING3. If not see
  1069. <http://www.gnu.org/licenses/>. */
  1070. -
  1071. +/* ------------------------------------------------------------------------ */
  1072. #include "config.h"
  1073. #include "system.h"
  1074. #include "coretypes.h"
  1075. #include "tm.h"
  1076. #include "tree.h"
  1077. +#include "stringpool.h"
  1078. #include "stor-layout.h"
  1079. #include "varasm.h"
  1080. #include "calls.h"
  1081. @@ -50,34 +51,58 @@
  1082. #include "target-def.h"
  1083. #include "langhooks.h" /* For add_builtin_function(). */
  1084. #include "ggc.h"
  1085. +#include "tree-pass.h"
  1086. +#include "basic-block.h"
  1087. +#include "cfgloop.h"
  1088. +#include "context.h"
  1089. +#include "params.h"
  1090. +#include "cpplib.h"
  1091. +#include "hw-doloop.h"
  1092. /* ------------------------------------------------------------------------ */
  1093. -/* This file is divided into five parts:
  1094. +/* This file is divided into six parts:
  1095. - PART 1: Auxiliary static variable definitions and
  1096. - target hook static variable definitions.
  1097. + PART 1: Auxiliary external function and variable declarations.
  1098. - PART 2: Auxiliary static function definitions.
  1099. + PART 2: Auxiliary static variable definitions and
  1100. + target hook static variable definitions.
  1101. - PART 3: Implement target hook stuff definitions.
  1102. + PART 3: Auxiliary static function definitions.
  1103. - PART 4: Implemet extern function definitions,
  1104. - the prototype is in nds32-protos.h.
  1105. + PART 4: Implement target hook stuff definitions.
  1106. - PART 5: Initialize target hook structure and definitions. */
  1107. + PART 5: Implemet extern function definitions,
  1108. + the prototype is in nds32-protos.h.
  1109. +
  1110. + PART 6: Initialize target hook structure and definitions. */
  1111. /* ------------------------------------------------------------------------ */
  1112. -/* PART 1: Auxiliary static variable definitions and
  1113. - target hook static variable definitions. */
  1114. +/* PART 1: Auxiliary function and variable declarations. */
  1115. +
  1116. +namespace nds32 {
  1117. +namespace scheduling {
  1118. +
  1119. +extern unsigned int nds32_print_stalls (void);
  1120. +rtl_opt_pass *make_pass_nds32_print_stalls (gcc::context *);
  1121. +
  1122. +} // namespace scheduling
  1123. +} // namespace nds32
  1124. +
  1125. +rtl_opt_pass *make_pass_nds32_fp_as_gp (gcc::context *);
  1126. +rtl_opt_pass *make_pass_nds32_load_store_opt (gcc::context *);
  1127. +rtl_opt_pass *make_pass_nds32_soft_fp_arith_comm_opt(gcc::context *);
  1128. +rtl_opt_pass *make_pass_nds32_regrename_opt (gcc::context *);
  1129. +rtl_opt_pass *make_pass_nds32_gcse_opt (gcc::context *);
  1130. +rtl_opt_pass *make_pass_nds32_relax_opt (gcc::context *);
  1131. +rtl_opt_pass *make_pass_nds32_hwloop1_opt (gcc::context *);
  1132. +rtl_opt_pass *make_pass_nds32_hwloop2_opt (gcc::context *);
  1133. +
  1134. +/* ------------------------------------------------------------------------ */
  1135. -/* Refer to nds32.h, there are maximum 73 isr vectors in nds32 architecture.
  1136. - 0 for reset handler with __attribute__((reset())),
  1137. - 1-8 for exception handler with __attribute__((exception(1,...,8))),
  1138. - and 9-72 for interrupt handler with __attribute__((interrupt(0,...,63))).
  1139. - We use an array to record essential information for each vector. */
  1140. -static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS];
  1141. +/* PART 2: Auxiliary static variable definitions and
  1142. + target hook static variable definitions. */
  1143. /* Define intrinsic register names.
  1144. Please refer to nds32_intrinsic.h file, the index is corresponding to
  1145. @@ -85,14 +110,210 @@
  1146. NOTE that the base value starting from 1024. */
  1147. static const char * const nds32_intrinsic_register_names[] =
  1148. {
  1149. - "$PSW", "$IPSW", "$ITYPE", "$IPC"
  1150. + "$CPU_VER",
  1151. + "$ICM_CFG",
  1152. + "$DCM_CFG",
  1153. + "$MMU_CFG",
  1154. + "$MSC_CFG",
  1155. + "$MSC_CFG2",
  1156. + "$CORE_ID",
  1157. + "$FUCOP_EXIST",
  1158. +
  1159. + "$PSW",
  1160. + "$IPSW",
  1161. + "$P_IPSW",
  1162. + "$IVB",
  1163. + "$EVA",
  1164. + "$P_EVA",
  1165. + "$ITYPE",
  1166. + "$P_ITYPE",
  1167. +
  1168. + "$MERR",
  1169. + "$IPC",
  1170. + "$P_IPC",
  1171. + "$OIPC",
  1172. + "$P_P0",
  1173. + "$P_P1",
  1174. +
  1175. + "$INT_MASK",
  1176. + "$INT_MASK2",
  1177. + "$INT_PEND",
  1178. + "$INT_PEND2",
  1179. + "$SP_USR",
  1180. + "$SP_PRIV",
  1181. + "$INT_PRI",
  1182. + "$INT_PRI2",
  1183. + "$INT_CTRL",
  1184. + "$INT_TRIGGER",
  1185. + "$INT_GPR_PUSH_DIS",
  1186. +
  1187. + "$MMU_CTL",
  1188. + "$L1_PPTB",
  1189. + "$TLB_VPN",
  1190. + "$TLB_DATA",
  1191. + "$TLB_MISC",
  1192. + "$VLPT_IDX",
  1193. + "$ILMB",
  1194. + "$DLMB",
  1195. +
  1196. + "$CACHE_CTL",
  1197. + "$HSMP_SADDR",
  1198. + "$HSMP_EADDR",
  1199. + "$SDZ_CTL",
  1200. + "$N12MISC_CTL",
  1201. + "$MISC_CTL",
  1202. + "$ECC_MISC",
  1203. +
  1204. + "$BPC0",
  1205. + "$BPC1",
  1206. + "$BPC2",
  1207. + "$BPC3",
  1208. + "$BPC4",
  1209. + "$BPC5",
  1210. + "$BPC6",
  1211. + "$BPC7",
  1212. +
  1213. + "$BPA0",
  1214. + "$BPA1",
  1215. + "$BPA2",
  1216. + "$BPA3",
  1217. + "$BPA4",
  1218. + "$BPA5",
  1219. + "$BPA6",
  1220. + "$BPA7",
  1221. +
  1222. + "$BPAM0",
  1223. + "$BPAM1",
  1224. + "$BPAM2",
  1225. + "$BPAM3",
  1226. + "$BPAM4",
  1227. + "$BPAM5",
  1228. + "$BPAM6",
  1229. + "$BPAM7",
  1230. +
  1231. + "$BPV0",
  1232. + "$BPV1",
  1233. + "$BPV2",
  1234. + "$BPV3",
  1235. + "$BPV4",
  1236. + "$BPV5",
  1237. + "$BPV6",
  1238. + "$BPV7",
  1239. +
  1240. + "$BPCID0",
  1241. + "$BPCID1",
  1242. + "$BPCID2",
  1243. + "$BPCID3",
  1244. + "$BPCID4",
  1245. + "$BPCID5",
  1246. + "$BPCID6",
  1247. + "$BPCID7",
  1248. +
  1249. + "$EDM_CFG",
  1250. + "$EDMSW",
  1251. + "$EDM_CTL",
  1252. + "$EDM_DTR",
  1253. + "$BPMTC",
  1254. + "$DIMBR",
  1255. +
  1256. + "$TECR0",
  1257. + "$TECR1",
  1258. + "$PFMC0",
  1259. + "$PFMC1",
  1260. + "$PFMC2",
  1261. + "$PFM_CTL",
  1262. + "$PFT_CTL",
  1263. + "$HSP_CTL",
  1264. + "$SP_BOUND",
  1265. + "$SP_BOUND_PRIV",
  1266. + "$FUCOP_CTL",
  1267. + "$PRUSR_ACC_CTL",
  1268. +
  1269. + "$DMA_CFG",
  1270. + "$DMA_GCSW",
  1271. + "$DMA_CHNSEL",
  1272. + "$DMA_ACT",
  1273. + "$DMA_SETUP",
  1274. + "$DMA_ISADDR",
  1275. + "$DMA_ESADDR",
  1276. + "$DMA_TCNT",
  1277. + "$DMA_STATUS",
  1278. + "$DMA_2DSET",
  1279. + "$DMA_2DSCTL",
  1280. + "$DMA_RCNT",
  1281. + "$DMA_HSTATUS",
  1282. +
  1283. + "$PC",
  1284. + "$SP_USR1",
  1285. + "$SP_USR2",
  1286. + "$SP_USR3",
  1287. + "$SP_PRIV1",
  1288. + "$SP_PRIV2",
  1289. + "$SP_PRIV3",
  1290. + "$BG_REGION",
  1291. + "$SFCR",
  1292. + "$SIGN",
  1293. + "$ISIGN",
  1294. + "$P_ISIGN",
  1295. + "$IFC_LP",
  1296. + "$ITB"
  1297. +};
  1298. +
  1299. +/* Define instrinsic cctl names. */
  1300. +static const char * const nds32_cctl_names[] =
  1301. +{
  1302. + "L1D_VA_FILLCK",
  1303. + "L1D_VA_ULCK",
  1304. + "L1I_VA_FILLCK",
  1305. + "L1I_VA_ULCK",
  1306. +
  1307. + "L1D_IX_WBINVAL",
  1308. + "L1D_IX_INVAL",
  1309. + "L1D_IX_WB",
  1310. + "L1I_IX_INVAL",
  1311. +
  1312. + "L1D_VA_INVAL",
  1313. + "L1D_VA_WB",
  1314. + "L1D_VA_WBINVAL",
  1315. + "L1I_VA_INVAL",
  1316. +
  1317. + "L1D_IX_RTAG",
  1318. + "L1D_IX_RWD",
  1319. + "L1I_IX_RTAG",
  1320. + "L1I_IX_RWD",
  1321. +
  1322. + "L1D_IX_WTAG",
  1323. + "L1D_IX_WWD",
  1324. + "L1I_IX_WTAG",
  1325. + "L1I_IX_WWD"
  1326. +};
  1327. +
  1328. +static const char * const nds32_dpref_names[] =
  1329. +{
  1330. + "SRD",
  1331. + "MRD",
  1332. + "SWR",
  1333. + "MWR",
  1334. + "PTE",
  1335. + "CLWR"
  1336. +};
  1337. +
  1338. +/* Defining register allocation order for performance.
  1339. + We want to allocate callee-saved registers after others.
  1340. + It may be used by nds32_adjust_reg_alloc_order(). */
  1341. +static const int nds32_reg_alloc_order_for_speed[] =
  1342. +{
  1343. + 0, 1, 2, 3, 4, 5, 16, 17,
  1344. + 18, 19, 20, 21, 22, 23, 24, 25,
  1345. + 26, 27, 6, 7, 8, 9, 10, 11,
  1346. + 12, 13, 14, 15
  1347. };
  1348. /* Defining target-specific uses of __attribute__. */
  1349. static const struct attribute_spec nds32_attribute_table[] =
  1350. {
  1351. /* Syntax: { name, min_len, max_len, decl_required, type_required,
  1352. - function_type_required, handler, affects_type_identity } */
  1353. + function_type_required, handler, affects_type_identity } */
  1354. /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
  1355. { "interrupt", 1, 64, false, false, false, NULL, false },
  1356. @@ -105,6 +326,7 @@
  1357. { "nested", 0, 0, false, false, false, NULL, false },
  1358. { "not_nested", 0, 0, false, false, false, NULL, false },
  1359. { "nested_ready", 0, 0, false, false, false, NULL, false },
  1360. + { "critical", 0, 0, false, false, false, NULL, false },
  1361. /* The attributes describing isr register save scheme. */
  1362. { "save_all", 0, 0, false, false, false, NULL, false },
  1363. @@ -117,14 +339,26 @@
  1364. /* The attribute telling no prologue/epilogue. */
  1365. { "naked", 0, 0, false, false, false, NULL, false },
  1366. + /* The attribute is used to set signature. */
  1367. + { "signature", 0, 0, false, false, false, NULL, false },
  1368. +
  1369. + /* The attribute is used to tell this function to be ROM patch. */
  1370. + { "indirect_call",0, 0, false, false, false, NULL, false },
  1371. +
  1372. + /* FOR BACKWARD COMPATIBILITY,
  1373. + this attribute also tells no prologue/epilogue. */
  1374. + { "no_prologue", 0, 0, false, false, false, NULL, false },
  1375. +
  1376. + /* The attribute turn off hwloop optimization. */
  1377. + { "no_ext_zol", 0, 0, false, false, false, NULL, false},
  1378. +
  1379. /* The last attribute spec is set to be NULL. */
  1380. { NULL, 0, 0, false, false, false, NULL, false }
  1381. };
  1382. -
  1383. /* ------------------------------------------------------------------------ */
  1384. -/* PART 2: Auxiliary static function definitions. */
  1385. +/* PART 3: Auxiliary static function definitions. */
  1386. /* Function to save and restore machine-specific function data. */
  1387. static struct machine_function *
  1388. @@ -133,12 +367,22 @@
  1389. struct machine_function *machine;
  1390. machine = ggc_alloc_cleared_machine_function ();
  1391. + /* Initially assume this function does not use __builtin_eh_return. */
  1392. + machine->use_eh_return_p = 0;
  1393. +
  1394. /* Initially assume this function needs prologue/epilogue. */
  1395. machine->naked_p = 0;
  1396. /* Initially assume this function does NOT use fp_as_gp optimization. */
  1397. machine->fp_as_gp_p = 0;
  1398. + /* Initially this function is not under strictly aligned situation. */
  1399. + machine->strict_aligned_p = 0;
  1400. +
  1401. + /* Initially this function has no naked and no_prologue attributes. */
  1402. + machine->attr_naked_p = 0;
  1403. + machine->attr_no_prologue_p = 0;
  1404. +
  1405. return machine;
  1406. }
  1407. @@ -149,23 +393,77 @@
  1408. {
  1409. int r;
  1410. int block_size;
  1411. + bool v3pushpop_p;
  1412. /* Because nds32_compute_stack_frame() will be called from different place,
  1413. everytime we enter this function, we have to assume this function
  1414. needs prologue/epilogue. */
  1415. cfun->machine->naked_p = 0;
  1416. + /* We need to mark whether this function has naked and no_prologue
  1417. + attribute so that we can distinguish the difference if users applies
  1418. + -mret-in-naked-func option. */
  1419. + cfun->machine->attr_naked_p
  1420. + = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
  1421. + ? 1 : 0;
  1422. + cfun->machine->attr_no_prologue_p
  1423. + = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl))
  1424. + ? 1 : 0;
  1425. +
  1426. + /* If __builtin_eh_return is used, we better have frame pointer needed
  1427. + so that we can easily locate the stack slot of return address. */
  1428. + if (crtl->calls_eh_return)
  1429. + {
  1430. + frame_pointer_needed = 1;
  1431. +
  1432. + /* We need to mark eh data registers that need to be saved
  1433. + in the stack. */
  1434. + cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0);
  1435. + for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++)
  1436. + cfun->machine->eh_return_data_last_regno = r;
  1437. +
  1438. + cfun->machine->eh_return_data_regs_size
  1439. + = 4 * (cfun->machine->eh_return_data_last_regno
  1440. + - cfun->machine->eh_return_data_first_regno
  1441. + + 1);
  1442. + cfun->machine->use_eh_return_p = 1;
  1443. + }
  1444. + else
  1445. + {
  1446. + /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we
  1447. + do not need to handle __builtin_eh_return case in this function. */
  1448. + cfun->machine->eh_return_data_first_regno = SP_REGNUM;
  1449. + cfun->machine->eh_return_data_last_regno = SP_REGNUM;
  1450. +
  1451. + cfun->machine->eh_return_data_regs_size = 0;
  1452. + cfun->machine->use_eh_return_p = 0;
  1453. + }
  1454. +
  1455. /* Get variadic arguments size to prepare pretend arguments and
  1456. - push them into stack at prologue.
  1457. - Currently, we do not push variadic arguments by ourself.
  1458. - We have GCC handle all the works.
  1459. - The caller will push all corresponding nameless arguments into stack,
  1460. - and the callee is able to retrieve them without problems.
  1461. - These variables are still preserved in case one day
  1462. - we would like caller passing arguments with registers. */
  1463. - cfun->machine->va_args_size = 0;
  1464. - cfun->machine->va_args_first_regno = SP_REGNUM;
  1465. - cfun->machine->va_args_last_regno = SP_REGNUM;
  1466. + we will push them into stack at prologue by ourself. */
  1467. + cfun->machine->va_args_size = crtl->args.pretend_args_size;
  1468. + if (cfun->machine->va_args_size != 0)
  1469. + {
  1470. + cfun->machine->va_args_first_regno
  1471. + = NDS32_GPR_ARG_FIRST_REGNUM
  1472. + + NDS32_MAX_GPR_REGS_FOR_ARGS
  1473. + - (crtl->args.pretend_args_size / UNITS_PER_WORD);
  1474. + cfun->machine->va_args_last_regno
  1475. + = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1;
  1476. + }
  1477. + else
  1478. + {
  1479. + cfun->machine->va_args_first_regno = SP_REGNUM;
  1480. + cfun->machine->va_args_last_regno = SP_REGNUM;
  1481. + }
  1482. +
  1483. + /* Important: We need to make sure that varargs area is 8-byte alignment. */
  1484. + block_size = cfun->machine->va_args_size;
  1485. + if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
  1486. + {
  1487. + cfun->machine->va_args_area_padding_bytes
  1488. + = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size;
  1489. + }
  1490. /* Get local variables, incoming variables, and temporary variables size.
  1491. Note that we need to make sure it is 8-byte alignment because
  1492. @@ -181,19 +479,25 @@
  1493. /* If $gp value is required to be saved on stack, it needs 4 bytes space.
  1494. Check whether we are using PIC code genration. */
  1495. - cfun->machine->gp_size = (flag_pic) ? 4 : 0;
  1496. + cfun->machine->gp_size =
  1497. + (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0;
  1498. /* If $lp value is required to be saved on stack, it needs 4 bytes space.
  1499. Check whether $lp is ever live. */
  1500. - cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0;
  1501. + cfun->machine->lp_size
  1502. + = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0;
  1503. /* Initially there is no padding bytes. */
  1504. - cfun->machine->callee_saved_area_padding_bytes = 0;
  1505. + cfun->machine->callee_saved_area_gpr_padding_bytes = 0;
  1506. /* Calculate the bytes of saving callee-saved registers on stack. */
  1507. - cfun->machine->callee_saved_regs_size = 0;
  1508. - cfun->machine->callee_saved_regs_first_regno = SP_REGNUM;
  1509. - cfun->machine->callee_saved_regs_last_regno = SP_REGNUM;
  1510. + cfun->machine->callee_saved_gpr_regs_size = 0;
  1511. + cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM;
  1512. + cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM;
  1513. + cfun->machine->callee_saved_fpr_regs_size = 0;
  1514. + cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM;
  1515. + cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM;
  1516. +
  1517. /* Currently, there is no need to check $r28~$r31
  1518. because we will save them in another way. */
  1519. for (r = 0; r < 28; r++)
  1520. @@ -204,46 +508,83 @@
  1521. (only need to set it once).
  1522. If first regno == SP_REGNUM, we can tell that
  1523. it is the first time to be here. */
  1524. - if (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM)
  1525. - cfun->machine->callee_saved_regs_first_regno = r;
  1526. + if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM)
  1527. + cfun->machine->callee_saved_first_gpr_regno = r;
  1528. /* Mark the last required callee-saved register. */
  1529. - cfun->machine->callee_saved_regs_last_regno = r;
  1530. + cfun->machine->callee_saved_last_gpr_regno = r;
  1531. + }
  1532. + }
  1533. +
  1534. + /* Recording fpu callee-saved register. */
  1535. + if (TARGET_HARD_FLOAT)
  1536. + {
  1537. + for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++)
  1538. + {
  1539. + if (NDS32_REQUIRED_CALLEE_SAVED_P (r))
  1540. + {
  1541. + /* Mark the first required callee-saved register. */
  1542. + if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM)
  1543. + {
  1544. + /* Make first callee-saved number is even,
  1545. + bacause we use doubleword access, and this way
  1546. + promise 8-byte alignemt. */
  1547. + if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r))
  1548. + cfun->machine->callee_saved_first_fpr_regno = r - 1;
  1549. + else
  1550. + cfun->machine->callee_saved_first_fpr_regno = r;
  1551. + }
  1552. + cfun->machine->callee_saved_last_fpr_regno = r;
  1553. + }
  1554. }
  1555. +
  1556. + /* Make last callee-saved register number is odd,
  1557. + we hope callee-saved register is even. */
  1558. + int last_fpr = cfun->machine->callee_saved_last_fpr_regno;
  1559. + if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr))
  1560. + cfun->machine->callee_saved_last_fpr_regno++;
  1561. }
  1562. /* Check if this function can omit prologue/epilogue code fragment.
  1563. - If there is 'naked' attribute in this function,
  1564. + If there is 'no_prologue'/'naked' attribute in this function,
  1565. we can set 'naked_p' flag to indicate that
  1566. we do not have to generate prologue/epilogue.
  1567. Or, if all the following conditions succeed,
  1568. we can set this function 'naked_p' as well:
  1569. condition 1: first_regno == last_regno == SP_REGNUM,
  1570. - which means we do not have to save
  1571. - any callee-saved registers.
  1572. + which means we do not have to save
  1573. + any callee-saved registers.
  1574. condition 2: Both $lp and $fp are NOT live in this function,
  1575. - which means we do not need to save them.
  1576. + which means we do not need to save them and there
  1577. + is no outgoing size.
  1578. condition 3: There is no local_size, which means
  1579. - we do not need to adjust $sp. */
  1580. - if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
  1581. - || (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM
  1582. - && cfun->machine->callee_saved_regs_last_regno == SP_REGNUM
  1583. + we do not need to adjust $sp. */
  1584. + if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl))
  1585. + || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
  1586. + || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM
  1587. + && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM
  1588. + && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM
  1589. + && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM
  1590. && !df_regs_ever_live_p (FP_REGNUM)
  1591. && !df_regs_ever_live_p (LP_REGNUM)
  1592. - && cfun->machine->local_size == 0))
  1593. + && cfun->machine->local_size == 0
  1594. + && !flag_pic))
  1595. {
  1596. - /* Set this function 'naked_p' and
  1597. - other functions can check this flag. */
  1598. + /* Set this function 'naked_p' and other functions can check this flag.
  1599. + Note that in nds32 port, the 'naked_p = 1' JUST means there is no
  1600. + callee-saved, local size, and outgoing size.
  1601. + The varargs space and ret instruction may still present in
  1602. + the prologue/epilogue expanding. */
  1603. cfun->machine->naked_p = 1;
  1604. /* No need to save $fp, $gp, and $lp.
  1605. - We should set these value to be zero
  1606. - so that nds32_initial_elimination_offset() can work properly. */
  1607. + We should set these value to be zero
  1608. + so that nds32_initial_elimination_offset() can work properly. */
  1609. cfun->machine->fp_size = 0;
  1610. cfun->machine->gp_size = 0;
  1611. cfun->machine->lp_size = 0;
  1612. /* If stack usage computation is required,
  1613. - we need to provide the static stack size. */
  1614. + we need to provide the static stack size. */
  1615. if (flag_stack_usage_info)
  1616. current_function_static_stack_size = 0;
  1617. @@ -251,20 +592,23 @@
  1618. return;
  1619. }
  1620. + v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P;
  1621. +
  1622. /* Adjustment for v3push instructions:
  1623. If we are using v3push (push25/pop25) instructions,
  1624. we need to make sure Rb is $r6 and Re is
  1625. located on $r6, $r8, $r10, or $r14.
  1626. Some results above will be discarded and recomputed.
  1627. - Note that it is only available under V3/V3M ISA. */
  1628. - if (TARGET_V3PUSH)
  1629. + Note that it is only available under V3/V3M ISA and we
  1630. + DO NOT setup following stuff for isr or variadic function. */
  1631. + if (v3pushpop_p)
  1632. {
  1633. /* Recompute:
  1634. - cfun->machine->fp_size
  1635. - cfun->machine->gp_size
  1636. - cfun->machine->lp_size
  1637. - cfun->machine->callee_saved_regs_first_regno
  1638. - cfun->machine->callee_saved_regs_last_regno */
  1639. + cfun->machine->fp_size
  1640. + cfun->machine->gp_size
  1641. + cfun->machine->lp_size
  1642. + cfun->machine->callee_saved_first_gpr_regno
  1643. + cfun->machine->callee_saved_last_gpr_regno */
  1644. /* For v3push instructions, $fp, $gp, and $lp are always saved. */
  1645. cfun->machine->fp_size = 4;
  1646. @@ -272,33 +616,33 @@
  1647. cfun->machine->lp_size = 4;
  1648. /* Remember to set Rb = $r6. */
  1649. - cfun->machine->callee_saved_regs_first_regno = 6;
  1650. + cfun->machine->callee_saved_first_gpr_regno = 6;
  1651. - if (cfun->machine->callee_saved_regs_last_regno <= 6)
  1652. + if (cfun->machine->callee_saved_last_gpr_regno <= 6)
  1653. {
  1654. /* Re = $r6 */
  1655. - cfun->machine->callee_saved_regs_last_regno = 6;
  1656. + cfun->machine->callee_saved_last_gpr_regno = 6;
  1657. }
  1658. - else if (cfun->machine->callee_saved_regs_last_regno <= 8)
  1659. + else if (cfun->machine->callee_saved_last_gpr_regno <= 8)
  1660. {
  1661. /* Re = $r8 */
  1662. - cfun->machine->callee_saved_regs_last_regno = 8;
  1663. + cfun->machine->callee_saved_last_gpr_regno = 8;
  1664. }
  1665. - else if (cfun->machine->callee_saved_regs_last_regno <= 10)
  1666. + else if (cfun->machine->callee_saved_last_gpr_regno <= 10)
  1667. {
  1668. /* Re = $r10 */
  1669. - cfun->machine->callee_saved_regs_last_regno = 10;
  1670. + cfun->machine->callee_saved_last_gpr_regno = 10;
  1671. }
  1672. - else if (cfun->machine->callee_saved_regs_last_regno <= 14)
  1673. + else if (cfun->machine->callee_saved_last_gpr_regno <= 14)
  1674. {
  1675. /* Re = $r14 */
  1676. - cfun->machine->callee_saved_regs_last_regno = 14;
  1677. + cfun->machine->callee_saved_last_gpr_regno = 14;
  1678. }
  1679. - else if (cfun->machine->callee_saved_regs_last_regno == SP_REGNUM)
  1680. + else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM)
  1681. {
  1682. /* If last_regno is SP_REGNUM, which means
  1683. it is never changed, so set it to Re = $r6. */
  1684. - cfun->machine->callee_saved_regs_last_regno = 6;
  1685. + cfun->machine->callee_saved_last_gpr_regno = 6;
  1686. }
  1687. else
  1688. {
  1689. @@ -307,33 +651,78 @@
  1690. }
  1691. }
  1692. - /* We have correctly set callee_saved_regs_first_regno
  1693. - and callee_saved_regs_last_regno.
  1694. - Initially, the callee_saved_regs_size is supposed to be 0.
  1695. - As long as callee_saved_regs_last_regno is not SP_REGNUM,
  1696. - we can update callee_saved_regs_size with new size. */
  1697. - if (cfun->machine->callee_saved_regs_last_regno != SP_REGNUM)
  1698. + int sp_adjust = cfun->machine->local_size
  1699. + + cfun->machine->out_args_size
  1700. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  1701. + + cfun->machine->callee_saved_fpr_regs_size;
  1702. +
  1703. + if (!v3pushpop_p
  1704. + && nds32_memory_model_option == MEMORY_MODEL_FAST
  1705. + && sp_adjust == 0
  1706. + && !frame_pointer_needed)
  1707. + {
  1708. + block_size = cfun->machine->fp_size
  1709. + + cfun->machine->gp_size
  1710. + + cfun->machine->lp_size
  1711. + + (4 * (cfun->machine->callee_saved_last_gpr_regno
  1712. + - cfun->machine->callee_saved_first_gpr_regno
  1713. + + 1));
  1714. +
  1715. + if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
  1716. + {
  1717. + /* $r14 is last callee save register. */
  1718. + if (cfun->machine->callee_saved_last_gpr_regno
  1719. + < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM)
  1720. + {
  1721. + cfun->machine->callee_saved_last_gpr_regno++;
  1722. + }
  1723. + else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM)
  1724. + {
  1725. + cfun->machine->callee_saved_first_gpr_regno
  1726. + = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM;
  1727. + cfun->machine->callee_saved_last_gpr_regno
  1728. + = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM;
  1729. + }
  1730. + }
  1731. + }
  1732. +
  1733. + /* We have correctly set callee_saved_first_gpr_regno
  1734. + and callee_saved_last_gpr_regno.
  1735. + Initially, the callee_saved_gpr_regs_size is supposed to be 0.
  1736. + As long as callee_saved_last_gpr_regno is not SP_REGNUM,
  1737. + we can update callee_saved_gpr_regs_size with new size. */
  1738. + if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM)
  1739. {
  1740. /* Compute pushed size of callee-saved registers. */
  1741. - cfun->machine->callee_saved_regs_size
  1742. - = 4 * (cfun->machine->callee_saved_regs_last_regno
  1743. - - cfun->machine->callee_saved_regs_first_regno
  1744. + cfun->machine->callee_saved_gpr_regs_size
  1745. + = 4 * (cfun->machine->callee_saved_last_gpr_regno
  1746. + - cfun->machine->callee_saved_first_gpr_regno
  1747. + 1);
  1748. }
  1749. + if (TARGET_HARD_FLOAT)
  1750. + {
  1751. + /* Compute size of callee svaed floating-point registers. */
  1752. + if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM)
  1753. + {
  1754. + cfun->machine->callee_saved_fpr_regs_size
  1755. + = 4 * (cfun->machine->callee_saved_last_fpr_regno
  1756. + - cfun->machine->callee_saved_first_fpr_regno
  1757. + + 1);
  1758. + }
  1759. + }
  1760. +
  1761. /* Important: We need to make sure that
  1762. - (va_args_size + fp_size + gp_size
  1763. - + lp_size + callee_saved_regs_size)
  1764. - is 8-byte alignment.
  1765. - If it is not, calculate the padding bytes. */
  1766. - block_size = cfun->machine->va_args_size
  1767. - + cfun->machine->fp_size
  1768. + (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size)
  1769. + is 8-byte alignment.
  1770. + If it is not, calculate the padding bytes. */
  1771. + block_size = cfun->machine->fp_size
  1772. + cfun->machine->gp_size
  1773. + cfun->machine->lp_size
  1774. - + cfun->machine->callee_saved_regs_size;
  1775. + + cfun->machine->callee_saved_gpr_regs_size;
  1776. if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
  1777. {
  1778. - cfun->machine->callee_saved_area_padding_bytes
  1779. + cfun->machine->callee_saved_area_gpr_padding_bytes
  1780. = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size;
  1781. }
  1782. @@ -353,11 +742,12 @@
  1783. The overall concept are:
  1784. "push registers to memory",
  1785. "adjust stack pointer". */
  1786. -static rtx
  1787. -nds32_gen_stack_push_multiple (rtx Rb, rtx Re,
  1788. - rtx En4 ATTRIBUTE_UNUSED)
  1789. +static void
  1790. +nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re,
  1791. + bool save_fp_p, bool save_gp_p, bool save_lp_p,
  1792. + bool vaarg_p)
  1793. {
  1794. - int regno;
  1795. + unsigned regno;
  1796. int extra_count;
  1797. int num_use_regs;
  1798. int par_index;
  1799. @@ -368,39 +758,40 @@
  1800. rtx push_rtx;
  1801. rtx adjust_sp_rtx;
  1802. rtx parallel_insn;
  1803. + rtx dwarf;
  1804. /* We need to provide a customized rtx which contains
  1805. necessary information for data analysis,
  1806. so we create a parallel rtx like this:
  1807. (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
  1808. - (reg:SI Rb))
  1809. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  1810. - (reg:SI Rb+1))
  1811. - ...
  1812. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  1813. - (reg:SI Re))
  1814. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  1815. - (reg:SI FP_REGNUM))
  1816. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  1817. - (reg:SI GP_REGNUM))
  1818. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  1819. - (reg:SI LP_REGNUM))
  1820. - (set (reg:SI SP_REGNUM)
  1821. - (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
  1822. + (reg:SI Rb))
  1823. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  1824. + (reg:SI Rb+1))
  1825. + ...
  1826. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  1827. + (reg:SI Re))
  1828. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  1829. + (reg:SI FP_REGNUM))
  1830. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  1831. + (reg:SI GP_REGNUM))
  1832. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  1833. + (reg:SI LP_REGNUM))
  1834. + (set (reg:SI SP_REGNUM)
  1835. + (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
  1836. /* Calculate the number of registers that will be pushed. */
  1837. extra_count = 0;
  1838. - if (cfun->machine->fp_size)
  1839. + if (save_fp_p)
  1840. extra_count++;
  1841. - if (cfun->machine->gp_size)
  1842. + if (save_gp_p)
  1843. extra_count++;
  1844. - if (cfun->machine->lp_size)
  1845. + if (save_lp_p)
  1846. extra_count++;
  1847. /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
  1848. - if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM)
  1849. + if (Rb == SP_REGNUM && Re == SP_REGNUM)
  1850. num_use_regs = extra_count;
  1851. else
  1852. - num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count;
  1853. + num_use_regs = Re - Rb + 1 + extra_count;
  1854. /* In addition to used registers,
  1855. we need one more space for (set sp sp-x) rtx. */
  1856. @@ -412,12 +803,12 @@
  1857. offset = -(num_use_regs * 4);
  1858. /* Create (set mem regX) from Rb, Rb+1 up to Re. */
  1859. - for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
  1860. + for (regno = Rb; regno <= Re; regno++)
  1861. {
  1862. /* Rb and Re may be SP_REGNUM.
  1863. - We need to break this loop immediately. */
  1864. + We need to break this loop immediately. */
  1865. if (regno == SP_REGNUM)
  1866. - break;
  1867. + break;
  1868. reg = gen_rtx_REG (SImode, regno);
  1869. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  1870. @@ -431,7 +822,7 @@
  1871. }
  1872. /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
  1873. - if (cfun->machine->fp_size)
  1874. + if (save_fp_p)
  1875. {
  1876. reg = gen_rtx_REG (SImode, FP_REGNUM);
  1877. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  1878. @@ -443,7 +834,7 @@
  1879. offset = offset + 4;
  1880. par_index++;
  1881. }
  1882. - if (cfun->machine->gp_size)
  1883. + if (save_gp_p)
  1884. {
  1885. reg = gen_rtx_REG (SImode, GP_REGNUM);
  1886. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  1887. @@ -455,7 +846,7 @@
  1888. offset = offset + 4;
  1889. par_index++;
  1890. }
  1891. - if (cfun->machine->lp_size)
  1892. + if (save_lp_p)
  1893. {
  1894. reg = gen_rtx_REG (SImode, LP_REGNUM);
  1895. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  1896. @@ -479,7 +870,21 @@
  1897. XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
  1898. RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
  1899. - return parallel_insn;
  1900. + parallel_insn = emit_insn (parallel_insn);
  1901. +
  1902. + /* The insn rtx 'parallel_insn' will change frame layout.
  1903. + We need to use RTX_FRAME_RELATED_P so that GCC is able to
  1904. + generate CFI (Call Frame Information) stuff. */
  1905. + RTX_FRAME_RELATED_P (parallel_insn) = 1;
  1906. +
  1907. + /* Don't use GCC's logic for CFI info if we are generate a push for VAARG
  1908. + since we will not restore those register at epilogue. */
  1909. + if (vaarg_p)
  1910. + {
  1911. + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA,
  1912. + copy_rtx (adjust_sp_rtx), NULL_RTX);
  1913. + REG_NOTES (parallel_insn) = dwarf;
  1914. + }
  1915. }
  1916. /* Function to create a parallel rtx pattern
  1917. @@ -487,11 +892,11 @@
  1918. The overall concept are:
  1919. "pop registers from memory",
  1920. "adjust stack pointer". */
  1921. -static rtx
  1922. -nds32_gen_stack_pop_multiple (rtx Rb, rtx Re,
  1923. - rtx En4 ATTRIBUTE_UNUSED)
  1924. +static void
  1925. +nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re,
  1926. + bool save_fp_p, bool save_gp_p, bool save_lp_p)
  1927. {
  1928. - int regno;
  1929. + unsigned regno;
  1930. int extra_count;
  1931. int num_use_regs;
  1932. int par_index;
  1933. @@ -502,39 +907,40 @@
  1934. rtx pop_rtx;
  1935. rtx adjust_sp_rtx;
  1936. rtx parallel_insn;
  1937. + rtx dwarf = NULL_RTX;
  1938. /* We need to provide a customized rtx which contains
  1939. necessary information for data analysis,
  1940. so we create a parallel rtx like this:
  1941. (parallel [(set (reg:SI Rb)
  1942. - (mem (reg:SI SP_REGNUM)))
  1943. - (set (reg:SI Rb+1)
  1944. - (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  1945. - ...
  1946. - (set (reg:SI Re)
  1947. - (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  1948. - (set (reg:SI FP_REGNUM)
  1949. - (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  1950. - (set (reg:SI GP_REGNUM)
  1951. - (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  1952. - (set (reg:SI LP_REGNUM)
  1953. - (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  1954. - (set (reg:SI SP_REGNUM)
  1955. - (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
  1956. + (mem (reg:SI SP_REGNUM)))
  1957. + (set (reg:SI Rb+1)
  1958. + (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  1959. + ...
  1960. + (set (reg:SI Re)
  1961. + (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  1962. + (set (reg:SI FP_REGNUM)
  1963. + (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  1964. + (set (reg:SI GP_REGNUM)
  1965. + (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  1966. + (set (reg:SI LP_REGNUM)
  1967. + (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  1968. + (set (reg:SI SP_REGNUM)
  1969. + (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
  1970. /* Calculate the number of registers that will be poped. */
  1971. extra_count = 0;
  1972. - if (cfun->machine->fp_size)
  1973. + if (save_fp_p)
  1974. extra_count++;
  1975. - if (cfun->machine->gp_size)
  1976. + if (save_gp_p)
  1977. extra_count++;
  1978. - if (cfun->machine->lp_size)
  1979. + if (save_lp_p)
  1980. extra_count++;
  1981. /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
  1982. - if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM)
  1983. + if (Rb == SP_REGNUM && Re == SP_REGNUM)
  1984. num_use_regs = extra_count;
  1985. else
  1986. - num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count;
  1987. + num_use_regs = Re - Rb + 1 + extra_count;
  1988. /* In addition to used registers,
  1989. we need one more space for (set sp sp+x) rtx. */
  1990. @@ -546,12 +952,12 @@
  1991. offset = 0;
  1992. /* Create (set regX mem) from Rb, Rb+1 up to Re. */
  1993. - for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
  1994. + for (regno = Rb; regno <= Re; regno++)
  1995. {
  1996. /* Rb and Re may be SP_REGNUM.
  1997. - We need to break this loop immediately. */
  1998. + We need to break this loop immediately. */
  1999. if (regno == SP_REGNUM)
  2000. - break;
  2001. + break;
  2002. reg = gen_rtx_REG (SImode, regno);
  2003. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2004. @@ -562,10 +968,12 @@
  2005. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2006. offset = offset + 4;
  2007. par_index++;
  2008. +
  2009. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2010. }
  2011. /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
  2012. - if (cfun->machine->fp_size)
  2013. + if (save_fp_p)
  2014. {
  2015. reg = gen_rtx_REG (SImode, FP_REGNUM);
  2016. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2017. @@ -576,8 +984,10 @@
  2018. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2019. offset = offset + 4;
  2020. par_index++;
  2021. +
  2022. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2023. }
  2024. - if (cfun->machine->gp_size)
  2025. + if (save_gp_p)
  2026. {
  2027. reg = gen_rtx_REG (SImode, GP_REGNUM);
  2028. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2029. @@ -588,8 +998,10 @@
  2030. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2031. offset = offset + 4;
  2032. par_index++;
  2033. +
  2034. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2035. }
  2036. - if (cfun->machine->lp_size)
  2037. + if (save_lp_p)
  2038. {
  2039. reg = gen_rtx_REG (SImode, LP_REGNUM);
  2040. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2041. @@ -600,6 +1012,8 @@
  2042. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2043. offset = offset + 4;
  2044. par_index++;
  2045. +
  2046. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2047. }
  2048. /* Create (set sp sp+x). */
  2049. @@ -610,9 +1024,19 @@
  2050. stack_pointer_rtx,
  2051. plus_constant (Pmode, stack_pointer_rtx, offset));
  2052. XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
  2053. - RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
  2054. - return parallel_insn;
  2055. + /* Tell gcc we adjust SP in this insn. */
  2056. + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf);
  2057. +
  2058. + parallel_insn = emit_insn (parallel_insn);
  2059. +
  2060. + /* The insn rtx 'parallel_insn' will change frame layout.
  2061. + We need to use RTX_FRAME_RELATED_P so that GCC is able to
  2062. + generate CFI (Call Frame Information) stuff. */
  2063. + RTX_FRAME_RELATED_P (parallel_insn) = 1;
  2064. +
  2065. + /* Add CFI info by manual. */
  2066. + REG_NOTES (parallel_insn) = dwarf;
  2067. }
  2068. /* Function to create a parallel rtx pattern
  2069. @@ -620,13 +1044,12 @@
  2070. The overall concept are:
  2071. "push registers to memory",
  2072. "adjust stack pointer". */
  2073. -static rtx
  2074. -nds32_gen_stack_v3push (rtx Rb,
  2075. - rtx Re,
  2076. - rtx En4 ATTRIBUTE_UNUSED,
  2077. - rtx imm8u)
  2078. +static void
  2079. +nds32_emit_stack_v3push (unsigned Rb,
  2080. + unsigned Re,
  2081. + unsigned imm8u)
  2082. {
  2083. - int regno;
  2084. + unsigned regno;
  2085. int num_use_regs;
  2086. int par_index;
  2087. int offset;
  2088. @@ -640,29 +1063,28 @@
  2089. /* We need to provide a customized rtx which contains
  2090. necessary information for data analysis,
  2091. so we create a parallel rtx like this:
  2092. - (parallel [
  2093. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
  2094. - (reg:SI Rb))
  2095. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  2096. - (reg:SI Rb+1))
  2097. - ...
  2098. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  2099. - (reg:SI Re))
  2100. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  2101. - (reg:SI FP_REGNUM))
  2102. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  2103. - (reg:SI GP_REGNUM))
  2104. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  2105. - (reg:SI LP_REGNUM))
  2106. - (set (reg:SI SP_REGNUM)
  2107. - (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
  2108. + (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
  2109. + (reg:SI Rb))
  2110. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  2111. + (reg:SI Rb+1))
  2112. + ...
  2113. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  2114. + (reg:SI Re))
  2115. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  2116. + (reg:SI FP_REGNUM))
  2117. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  2118. + (reg:SI GP_REGNUM))
  2119. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  2120. + (reg:SI LP_REGNUM))
  2121. + (set (reg:SI SP_REGNUM)
  2122. + (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
  2123. /* Calculate the number of registers that will be pushed.
  2124. Since $fp, $gp, and $lp is always pushed with v3push instruction,
  2125. we need to count these three registers.
  2126. Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
  2127. So there is no need to worry about Rb=Re=SP_REGNUM case. */
  2128. - num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3;
  2129. + num_use_regs = Re - Rb + 1 + 3;
  2130. /* In addition to used registers,
  2131. we need one more space for (set sp sp-x-imm8u) rtx. */
  2132. @@ -676,7 +1098,7 @@
  2133. /* Create (set mem regX) from Rb, Rb+1 up to Re.
  2134. Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
  2135. So there is no need to worry about Rb=Re=SP_REGNUM case. */
  2136. - for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
  2137. + for (regno = Rb; regno <= Re; regno++)
  2138. {
  2139. reg = gen_rtx_REG (SImode, regno);
  2140. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2141. @@ -729,11 +1151,16 @@
  2142. stack_pointer_rtx,
  2143. plus_constant (Pmode,
  2144. stack_pointer_rtx,
  2145. - offset - INTVAL (imm8u)));
  2146. + offset - imm8u));
  2147. XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
  2148. RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
  2149. - return parallel_insn;
  2150. + parallel_insn = emit_insn (parallel_insn);
  2151. +
  2152. + /* The insn rtx 'parallel_insn' will change frame layout.
  2153. + We need to use RTX_FRAME_RELATED_P so that GCC is able to
  2154. + generate CFI (Call Frame Information) stuff. */
  2155. + RTX_FRAME_RELATED_P (parallel_insn) = 1;
  2156. }
  2157. /* Function to create a parallel rtx pattern
  2158. @@ -741,13 +1168,12 @@
  2159. The overall concept are:
  2160. "pop registers from memory",
  2161. "adjust stack pointer". */
  2162. -static rtx
  2163. -nds32_gen_stack_v3pop (rtx Rb,
  2164. - rtx Re,
  2165. - rtx En4 ATTRIBUTE_UNUSED,
  2166. - rtx imm8u)
  2167. +static void
  2168. +nds32_emit_stack_v3pop (unsigned Rb,
  2169. + unsigned Re,
  2170. + unsigned imm8u)
  2171. {
  2172. - int regno;
  2173. + unsigned regno;
  2174. int num_use_regs;
  2175. int par_index;
  2176. int offset;
  2177. @@ -757,32 +1183,33 @@
  2178. rtx pop_rtx;
  2179. rtx adjust_sp_rtx;
  2180. rtx parallel_insn;
  2181. + rtx dwarf = NULL_RTX;
  2182. /* We need to provide a customized rtx which contains
  2183. necessary information for data analysis,
  2184. so we create a parallel rtx like this:
  2185. (parallel [(set (reg:SI Rb)
  2186. - (mem (reg:SI SP_REGNUM)))
  2187. - (set (reg:SI Rb+1)
  2188. - (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  2189. - ...
  2190. - (set (reg:SI Re)
  2191. - (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  2192. - (set (reg:SI FP_REGNUM)
  2193. - (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  2194. - (set (reg:SI GP_REGNUM)
  2195. - (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  2196. - (set (reg:SI LP_REGNUM)
  2197. - (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  2198. - (set (reg:SI SP_REGNUM)
  2199. - (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
  2200. + (mem (reg:SI SP_REGNUM)))
  2201. + (set (reg:SI Rb+1)
  2202. + (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  2203. + ...
  2204. + (set (reg:SI Re)
  2205. + (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  2206. + (set (reg:SI FP_REGNUM)
  2207. + (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  2208. + (set (reg:SI GP_REGNUM)
  2209. + (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  2210. + (set (reg:SI LP_REGNUM)
  2211. + (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  2212. + (set (reg:SI SP_REGNUM)
  2213. + (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
  2214. /* Calculate the number of registers that will be poped.
  2215. Since $fp, $gp, and $lp is always poped with v3pop instruction,
  2216. we need to count these three registers.
  2217. Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
  2218. So there is no need to worry about Rb=Re=SP_REGNUM case. */
  2219. - num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3;
  2220. + num_use_regs = Re - Rb + 1 + 3;
  2221. /* In addition to used registers,
  2222. we need one more space for (set sp sp+x+imm8u) rtx. */
  2223. @@ -796,7 +1223,7 @@
  2224. /* Create (set regX mem) from Rb, Rb+1 up to Re.
  2225. Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
  2226. So there is no need to worry about Rb=Re=SP_REGNUM case. */
  2227. - for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
  2228. + for (regno = Rb; regno <= Re; regno++)
  2229. {
  2230. reg = gen_rtx_REG (SImode, regno);
  2231. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2232. @@ -807,6 +1234,8 @@
  2233. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2234. offset = offset + 4;
  2235. par_index++;
  2236. +
  2237. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2238. }
  2239. /* Create (set fp mem). */
  2240. @@ -819,6 +1248,8 @@
  2241. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2242. offset = offset + 4;
  2243. par_index++;
  2244. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2245. +
  2246. /* Create (set gp mem). */
  2247. reg = gen_rtx_REG (SImode, GP_REGNUM);
  2248. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2249. @@ -829,6 +1260,8 @@
  2250. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2251. offset = offset + 4;
  2252. par_index++;
  2253. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2254. +
  2255. /* Create (set lp mem ). */
  2256. reg = gen_rtx_REG (SImode, LP_REGNUM);
  2257. mem = gen_frame_mem (SImode, plus_constant (Pmode,
  2258. @@ -839,6 +1272,7 @@
  2259. RTX_FRAME_RELATED_P (pop_rtx) = 1;
  2260. offset = offset + 4;
  2261. par_index++;
  2262. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
  2263. /* Create (set sp sp+x+imm8u). */
  2264. @@ -848,509 +1282,60 @@
  2265. stack_pointer_rtx,
  2266. plus_constant (Pmode,
  2267. stack_pointer_rtx,
  2268. - offset + INTVAL (imm8u)));
  2269. + offset + imm8u));
  2270. XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
  2271. - RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
  2272. -
  2273. - return parallel_insn;
  2274. -}
  2275. -
  2276. -/* A subroutine that checks multiple load and store
  2277. - using consecutive registers.
  2278. - OP is a parallel rtx we would like to check.
  2279. - LOAD_P indicates whether we are checking load operation.
  2280. - PAR_INDEX is starting element of parallel rtx.
  2281. - FIRST_ELT_REGNO is used to tell starting register number.
  2282. - COUNT helps us to check consecutive register numbers. */
  2283. -static bool
  2284. -nds32_consecutive_registers_load_store_p (rtx op,
  2285. - bool load_p,
  2286. - int par_index,
  2287. - int first_elt_regno,
  2288. - int count)
  2289. -{
  2290. - int i;
  2291. - int check_regno;
  2292. - rtx elt;
  2293. - rtx elt_reg;
  2294. - rtx elt_mem;
  2295. -
  2296. - for (i = 0; i < count; i++)
  2297. - {
  2298. - /* Pick up each element from parallel rtx. */
  2299. - elt = XVECEXP (op, 0, i + par_index);
  2300. -
  2301. - /* If this element is not a 'set' rtx, return false immediately. */
  2302. - if (GET_CODE (elt) != SET)
  2303. - return false;
  2304. -
  2305. - /* Pick up reg and mem of this element. */
  2306. - elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
  2307. - elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
  2308. -
  2309. - /* If elt_reg is not a expected reg rtx, return false. */
  2310. - if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
  2311. - return false;
  2312. - /* If elt_mem is not a expected mem rtx, return false. */
  2313. - if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
  2314. - return false;
  2315. -
  2316. - /* The consecutive registers should be in (Rb,Rb+1...Re) order. */
  2317. - check_regno = first_elt_regno + i;
  2318. -
  2319. - /* If the register number is not continuous, return false. */
  2320. - if (REGNO (elt_reg) != (unsigned int) check_regno)
  2321. - return false;
  2322. - }
  2323. -
  2324. - return true;
  2325. -}
  2326. -
  2327. -/* A helper function to emit section head template. */
  2328. -static void
  2329. -nds32_emit_section_head_template (char section_name[],
  2330. - char symbol_name[],
  2331. - int align_value,
  2332. - bool object_p)
  2333. -{
  2334. - const char *flags_str;
  2335. - const char *type_str;
  2336. -
  2337. - flags_str = (object_p) ? "\"a\"" : "\"ax\"";
  2338. - type_str = (object_p) ? "@object" : "@function";
  2339. -
  2340. - fprintf (asm_out_file, "\t.section\t%s, %s\n", section_name, flags_str);
  2341. - fprintf (asm_out_file, "\t.align\t%d\n", align_value);
  2342. - fprintf (asm_out_file, "\t.global\t%s\n", symbol_name);
  2343. - fprintf (asm_out_file, "\t.type\t%s, %s\n", symbol_name, type_str);
  2344. - fprintf (asm_out_file, "%s:\n", symbol_name);
  2345. -}
  2346. -
  2347. -/* A helper function to emit section tail template. */
  2348. -static void
  2349. -nds32_emit_section_tail_template (char symbol_name[])
  2350. -{
  2351. - fprintf (asm_out_file, "\t.size\t%s, .-%s\n", symbol_name, symbol_name);
  2352. -}
  2353. -
  2354. -/* Function to emit isr jump table section. */
  2355. -static void
  2356. -nds32_emit_isr_jmptbl_section (int vector_id)
  2357. -{
  2358. - char section_name[100];
  2359. - char symbol_name[100];
  2360. - /* Prepare jmptbl section and symbol name. */
  2361. - snprintf (section_name, sizeof (section_name),
  2362. - ".nds32_jmptbl.%02d", vector_id);
  2363. - snprintf (symbol_name, sizeof (symbol_name),
  2364. - "_nds32_jmptbl_%02d", vector_id);
  2365. -
  2366. - nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  2367. - fprintf (asm_out_file, "\t.word\t%s\n",
  2368. - nds32_isr_vectors[vector_id].func_name);
  2369. - nds32_emit_section_tail_template (symbol_name);
  2370. -}
  2371. -
  2372. -/* Function to emit isr vector section. */
  2373. -static void
  2374. -nds32_emit_isr_vector_section (int vector_id)
  2375. -{
  2376. - unsigned int vector_number_offset = 0;
  2377. - const char *c_str = "CATEGORY";
  2378. - const char *sr_str = "SR";
  2379. - const char *nt_str = "NT";
  2380. - const char *vs_str = "VS";
  2381. - char first_level_handler_name[100];
  2382. - char section_name[100];
  2383. - char symbol_name[100];
  2384. -
  2385. - /* Set the vector number offset so that we can calculate
  2386. - the value that user specifies in the attribute.
  2387. - We also prepare the category string for first level handler name. */
  2388. - switch (nds32_isr_vectors[vector_id].category)
  2389. - {
  2390. - case NDS32_ISR_INTERRUPT:
  2391. - vector_number_offset = 9;
  2392. - c_str = "i";
  2393. - break;
  2394. - case NDS32_ISR_EXCEPTION:
  2395. - vector_number_offset = 0;
  2396. - c_str = "e";
  2397. - break;
  2398. - case NDS32_ISR_NONE:
  2399. - case NDS32_ISR_RESET:
  2400. - /* Normally it should not be here. */
  2401. - gcc_unreachable ();
  2402. - break;
  2403. - }
  2404. -
  2405. - /* Prepare save reg string for first level handler name. */
  2406. - switch (nds32_isr_vectors[vector_id].save_reg)
  2407. - {
  2408. - case NDS32_SAVE_ALL:
  2409. - sr_str = "sa";
  2410. - break;
  2411. - case NDS32_PARTIAL_SAVE:
  2412. - sr_str = "ps";
  2413. - break;
  2414. - }
  2415. -
  2416. - /* Prepare nested type string for first level handler name. */
  2417. - switch (nds32_isr_vectors[vector_id].nested_type)
  2418. + if (frame_pointer_needed)
  2419. {
  2420. - case NDS32_NESTED:
  2421. - nt_str = "ns";
  2422. - break;
  2423. - case NDS32_NOT_NESTED:
  2424. - nt_str = "nn";
  2425. - break;
  2426. - case NDS32_NESTED_READY:
  2427. - nt_str = "nr";
  2428. - break;
  2429. - }
  2430. -
  2431. - /* Currently we have 4-byte or 16-byte size for each vector.
  2432. - If it is 4-byte, the first level handler name has suffix string "_4b". */
  2433. - vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
  2434. -
  2435. - /* Now we can create first level handler name. */
  2436. - snprintf (first_level_handler_name, sizeof (first_level_handler_name),
  2437. - "_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str);
  2438. -
  2439. - /* Prepare vector section and symbol name. */
  2440. - snprintf (section_name, sizeof (section_name),
  2441. - ".nds32_vector.%02d", vector_id);
  2442. - snprintf (symbol_name, sizeof (symbol_name),
  2443. - "_nds32_vector_%02d%s", vector_id, vs_str);
  2444. -
  2445. -
  2446. - /* Everything is ready. We can start emit vector section content. */
  2447. - nds32_emit_section_head_template (section_name, symbol_name,
  2448. - floor_log2 (nds32_isr_vector_size), false);
  2449. -
  2450. - /* According to the vector size, the instructions in the
  2451. - vector section may be different. */
  2452. - if (nds32_isr_vector_size == 4)
  2453. - {
  2454. - /* This block is for 4-byte vector size.
  2455. - Hardware $VID support is necessary and only one instruction
  2456. - is needed in vector section. */
  2457. - fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
  2458. - first_level_handler_name);
  2459. + /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp)
  2460. + (const_int 0))
  2461. + mean reset frame pointer to $sp and reset to offset 0. */
  2462. + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
  2463. + const0_rtx);
  2464. + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
  2465. }
  2466. else
  2467. {
  2468. - /* This block is for 16-byte vector size.
  2469. - There is NO hardware $VID so that we need several instructions
  2470. - such as pushing GPRs and preparing software vid at vector section.
  2471. - For pushing GPRs, there are four variations for
  2472. - 16-byte vector content and we have to handle each combination.
  2473. - For preparing software vid, note that the vid need to
  2474. - be substracted vector_number_offset. */
  2475. - if (TARGET_REDUCED_REGS)
  2476. - {
  2477. - if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
  2478. - {
  2479. - /* Case of reduced set registers and save_all attribute. */
  2480. - fprintf (asm_out_file, "\t! reduced set regs + save_all\n");
  2481. - fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0xf\n");
  2482. - fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r10, 0x0\n");
  2483. + /* Tell gcc we adjust SP in this insn. */
  2484. + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA,
  2485. + copy_rtx (adjust_sp_rtx), dwarf);
  2486. + }
  2487. - }
  2488. - else
  2489. - {
  2490. - /* Case of reduced set registers and partial_save attribute. */
  2491. - fprintf (asm_out_file, "\t! reduced set regs + partial_save\n");
  2492. - fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0x2\n");
  2493. - fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
  2494. - }
  2495. - }
  2496. - else
  2497. - {
  2498. - if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
  2499. - {
  2500. - /* Case of full set registers and save_all attribute. */
  2501. - fprintf (asm_out_file, "\t! full set regs + save_all\n");
  2502. - fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r27, 0xf\n");
  2503. - }
  2504. - else
  2505. - {
  2506. - /* Case of full set registers and partial_save attribute. */
  2507. - fprintf (asm_out_file, "\t! full set regs + partial_save\n");
  2508. - fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r27, 0x2\n");
  2509. - fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
  2510. - }
  2511. - }
  2512. + parallel_insn = emit_insn (parallel_insn);
  2513. - fprintf (asm_out_file, "\tmovi\t$r0, %d ! preparing software vid\n",
  2514. - vector_id - vector_number_offset);
  2515. - fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
  2516. - first_level_handler_name);
  2517. - }
  2518. + /* The insn rtx 'parallel_insn' will change frame layout.
  2519. + We need to use RTX_FRAME_RELATED_P so that GCC is able to
  2520. + generate CFI (Call Frame Information) stuff. */
  2521. + RTX_FRAME_RELATED_P (parallel_insn) = 1;
  2522. - nds32_emit_section_tail_template (symbol_name);
  2523. + /* Add CFI info by manual. */
  2524. + REG_NOTES (parallel_insn) = dwarf;
  2525. }
  2526. -/* Function to emit isr reset handler content.
  2527. - Including all jmptbl/vector references, jmptbl section,
  2528. - vector section, nmi handler section, and warm handler section. */
  2529. -static void
  2530. -nds32_emit_isr_reset_content (void)
  2531. -{
  2532. - unsigned int i;
  2533. - unsigned int total_n_vectors;
  2534. - const char *vs_str;
  2535. - char reset_handler_name[100];
  2536. - char section_name[100];
  2537. - char symbol_name[100];
  2538. -
  2539. - total_n_vectors = nds32_isr_vectors[0].total_n_vectors;
  2540. - vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
  2541. -
  2542. - fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n");
  2543. -
  2544. - /* Create references in .rodata according to total number of vectors. */
  2545. - fprintf (asm_out_file, "\t.section\t.rodata\n");
  2546. - fprintf (asm_out_file, "\t.align\t2\n");
  2547. -
  2548. - /* Emit jmptbl references. */
  2549. - fprintf (asm_out_file, "\t ! references to jmptbl section entries\n");
  2550. - for (i = 0; i < total_n_vectors; i++)
  2551. - fprintf (asm_out_file, "\t.word\t_nds32_jmptbl_%02d\n", i);
  2552. -
  2553. - /* Emit vector references. */
  2554. - fprintf (asm_out_file, "\t ! references to vector section entries\n");
  2555. - for (i = 0; i < total_n_vectors; i++)
  2556. - fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str);
  2557. -
  2558. - /* Emit jmptbl_00 section. */
  2559. - snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00");
  2560. - snprintf (symbol_name, sizeof (symbol_name), "_nds32_jmptbl_00");
  2561. -
  2562. - fprintf (asm_out_file, "\t! ....................................\n");
  2563. - nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  2564. - fprintf (asm_out_file, "\t.word\t%s\n",
  2565. - nds32_isr_vectors[0].func_name);
  2566. - nds32_emit_section_tail_template (symbol_name);
  2567. -
  2568. - /* Emit vector_00 section. */
  2569. - snprintf (section_name, sizeof (section_name), ".nds32_vector.00");
  2570. - snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str);
  2571. - snprintf (reset_handler_name, sizeof (reset_handler_name),
  2572. - "_nds32_reset%s", vs_str);
  2573. -
  2574. - fprintf (asm_out_file, "\t! ....................................\n");
  2575. - nds32_emit_section_head_template (section_name, symbol_name,
  2576. - floor_log2 (nds32_isr_vector_size), false);
  2577. - fprintf (asm_out_file, "\tj\t%s ! jump to reset handler\n",
  2578. - reset_handler_name);
  2579. - nds32_emit_section_tail_template (symbol_name);
  2580. -
  2581. - /* Emit nmi handler section. */
  2582. - snprintf (section_name, sizeof (section_name), ".nds32_nmih");
  2583. - snprintf (symbol_name, sizeof (symbol_name), "_nds32_nmih");
  2584. -
  2585. - fprintf (asm_out_file, "\t! ....................................\n");
  2586. - nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  2587. - fprintf (asm_out_file, "\t.word\t%s\n",
  2588. - (strlen (nds32_isr_vectors[0].nmi_name) == 0)
  2589. - ? "0"
  2590. - : nds32_isr_vectors[0].nmi_name);
  2591. - nds32_emit_section_tail_template (symbol_name);
  2592. -
  2593. - /* Emit warm handler section. */
  2594. - snprintf (section_name, sizeof (section_name), ".nds32_wrh");
  2595. - snprintf (symbol_name, sizeof (symbol_name), "_nds32_wrh");
  2596. -
  2597. - fprintf (asm_out_file, "\t! ....................................\n");
  2598. - nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  2599. - fprintf (asm_out_file, "\t.word\t%s\n",
  2600. - (strlen (nds32_isr_vectors[0].warm_name) == 0)
  2601. - ? "0"
  2602. - : nds32_isr_vectors[0].warm_name);
  2603. - nds32_emit_section_tail_template (symbol_name);
  2604. -
  2605. - fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - END !\n");
  2606. -}
  2607. -
  2608. -/* Function for nds32_merge_decl_attributes() and nds32_insert_attributes()
  2609. - to check if there are any conflict isr-specific attributes being set.
  2610. - We need to check:
  2611. - 1. Only 'save_all' or 'partial_save' in the attributes.
  2612. - 2. Only 'nested', 'not_nested', or 'nested_ready' in the attributes.
  2613. - 3. Only 'interrupt', 'exception', or 'reset' in the attributes. */
  2614. -static void
  2615. -nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
  2616. -{
  2617. - int save_all_p, partial_save_p;
  2618. - int nested_p, not_nested_p, nested_ready_p;
  2619. - int intr_p, excp_p, reset_p;
  2620. -
  2621. - /* Initialize variables. */
  2622. - save_all_p = partial_save_p = 0;
  2623. - nested_p = not_nested_p = nested_ready_p = 0;
  2624. - intr_p = excp_p = reset_p = 0;
  2625. -
  2626. - /* We must check at MOST one attribute to set save-reg. */
  2627. - if (lookup_attribute ("save_all", func_attrs))
  2628. - save_all_p = 1;
  2629. - if (lookup_attribute ("partial_save", func_attrs))
  2630. - partial_save_p = 1;
  2631. -
  2632. - if ((save_all_p + partial_save_p) > 1)
  2633. - error ("multiple save reg attributes to function %qD", func_decl);
  2634. -
  2635. - /* We must check at MOST one attribute to set nested-type. */
  2636. - if (lookup_attribute ("nested", func_attrs))
  2637. - nested_p = 1;
  2638. - if (lookup_attribute ("not_nested", func_attrs))
  2639. - not_nested_p = 1;
  2640. - if (lookup_attribute ("nested_ready", func_attrs))
  2641. - nested_ready_p = 1;
  2642. -
  2643. - if ((nested_p + not_nested_p + nested_ready_p) > 1)
  2644. - error ("multiple nested types attributes to function %qD", func_decl);
  2645. -
  2646. - /* We must check at MOST one attribute to
  2647. - set interrupt/exception/reset. */
  2648. - if (lookup_attribute ("interrupt", func_attrs))
  2649. - intr_p = 1;
  2650. - if (lookup_attribute ("exception", func_attrs))
  2651. - excp_p = 1;
  2652. - if (lookup_attribute ("reset", func_attrs))
  2653. - reset_p = 1;
  2654. -
  2655. - if ((intr_p + excp_p + reset_p) > 1)
  2656. - error ("multiple interrupt attributes to function %qD", func_decl);
  2657. -}
  2658. -
  2659. -/* Function to construct isr vectors information array.
  2660. - We DO NOT HAVE TO check if the attributes are valid
  2661. - because those works are supposed to be done on
  2662. - nds32_merge_decl_attributes() and nds32_insert_attributes(). */
  2663. static void
  2664. -nds32_construct_isr_vectors_information (tree func_attrs,
  2665. - const char *func_name)
  2666. +nds32_emit_load_gp (void)
  2667. {
  2668. - tree save_all, partial_save;
  2669. - tree nested, not_nested, nested_ready;
  2670. - tree intr, excp, reset;
  2671. -
  2672. - save_all = lookup_attribute ("save_all", func_attrs);
  2673. - partial_save = lookup_attribute ("partial_save", func_attrs);
  2674. -
  2675. - nested = lookup_attribute ("nested", func_attrs);
  2676. - not_nested = lookup_attribute ("not_nested", func_attrs);
  2677. - nested_ready = lookup_attribute ("nested_ready", func_attrs);
  2678. -
  2679. - intr = lookup_attribute ("interrupt", func_attrs);
  2680. - excp = lookup_attribute ("exception", func_attrs);
  2681. - reset = lookup_attribute ("reset", func_attrs);
  2682. -
  2683. - /* If there is no interrupt/exception/reset, we can return immediately. */
  2684. - if (!intr && !excp && !reset)
  2685. - return;
  2686. -
  2687. - /* If we are here, either we have interrupt/exception,
  2688. - or reset attribute. */
  2689. - if (intr || excp)
  2690. - {
  2691. - tree id_list;
  2692. -
  2693. - /* Prepare id list so that we can traverse and set vector id. */
  2694. - id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp));
  2695. -
  2696. - while (id_list)
  2697. - {
  2698. - tree id;
  2699. - int vector_id;
  2700. - unsigned int vector_number_offset;
  2701. -
  2702. - /* The way to handle interrupt or exception is the same,
  2703. - we just need to take care of actual vector number.
  2704. - For interrupt(0..63), the actual vector number is (9..72).
  2705. - For exception(1..8), the actual vector number is (1..8). */
  2706. - vector_number_offset = (intr) ? (9) : (0);
  2707. -
  2708. - /* Pick up each vector id value. */
  2709. - id = TREE_VALUE (id_list);
  2710. - /* Add vector_number_offset to get actual vector number. */
  2711. - vector_id = TREE_INT_CST_LOW (id) + vector_number_offset;
  2712. -
  2713. - /* Enable corresponding vector and set function name. */
  2714. - nds32_isr_vectors[vector_id].category = (intr)
  2715. - ? (NDS32_ISR_INTERRUPT)
  2716. - : (NDS32_ISR_EXCEPTION);
  2717. - strcpy (nds32_isr_vectors[vector_id].func_name, func_name);
  2718. -
  2719. - /* Set register saving scheme. */
  2720. - if (save_all)
  2721. - nds32_isr_vectors[vector_id].save_reg = NDS32_SAVE_ALL;
  2722. - else if (partial_save)
  2723. - nds32_isr_vectors[vector_id].save_reg = NDS32_PARTIAL_SAVE;
  2724. -
  2725. - /* Set nested type. */
  2726. - if (nested)
  2727. - nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED;
  2728. - else if (not_nested)
  2729. - nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED;
  2730. - else if (nested_ready)
  2731. - nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY;
  2732. -
  2733. - /* Advance to next id. */
  2734. - id_list = TREE_CHAIN (id_list);
  2735. - }
  2736. - }
  2737. - else
  2738. - {
  2739. - tree id_list;
  2740. - tree id;
  2741. - tree nmi, warm;
  2742. + rtx got_symbol, pat;
  2743. - /* Deal with reset attribute. Its vector number is always 0. */
  2744. - nds32_isr_vectors[0].category = NDS32_ISR_RESET;
  2745. -
  2746. - /* Prepare id_list and identify id value so that
  2747. - we can set total number of vectors. */
  2748. - id_list = TREE_VALUE (reset);
  2749. - id = TREE_VALUE (id_list);
  2750. -
  2751. - /* The total vectors = interrupt + exception numbers + reset.
  2752. - There are 8 exception and 1 reset in nds32 architecture. */
  2753. - nds32_isr_vectors[0].total_n_vectors = TREE_INT_CST_LOW (id) + 8 + 1;
  2754. - strcpy (nds32_isr_vectors[0].func_name, func_name);
  2755. -
  2756. - /* Retrieve nmi and warm function. */
  2757. - nmi = lookup_attribute ("nmi", func_attrs);
  2758. - warm = lookup_attribute ("warm", func_attrs);
  2759. -
  2760. - if (nmi != NULL_TREE)
  2761. - {
  2762. - tree nmi_func_list;
  2763. - tree nmi_func;
  2764. -
  2765. - nmi_func_list = TREE_VALUE (nmi);
  2766. - nmi_func = TREE_VALUE (nmi_func_list);
  2767. -
  2768. - /* Record nmi function name. */
  2769. - strcpy (nds32_isr_vectors[0].nmi_name,
  2770. - IDENTIFIER_POINTER (nmi_func));
  2771. - }
  2772. + /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
  2773. + emit_insn (gen_blockage ());
  2774. - if (warm != NULL_TREE)
  2775. - {
  2776. - tree warm_func_list;
  2777. - tree warm_func;
  2778. + got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
  2779. + /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */
  2780. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT);
  2781. + pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8)));
  2782. + emit_insn (gen_sethi (pic_offset_table_rtx,pat));
  2783. +
  2784. + /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */
  2785. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT);
  2786. + pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4)));
  2787. + emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat));
  2788. - warm_func_list = TREE_VALUE (warm);
  2789. - warm_func = TREE_VALUE (warm_func_list);
  2790. + /* add5.pc $gp */
  2791. + emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx));
  2792. - /* Record warm function name. */
  2793. - strcpy (nds32_isr_vectors[0].warm_name,
  2794. - IDENTIFIER_POINTER (warm_func));
  2795. - }
  2796. - }
  2797. + /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
  2798. + emit_insn (gen_blockage ());
  2799. }
  2800. /* Function that may creates more instructions
  2801. @@ -1362,74 +1347,65 @@
  2802. the adjustment value is not able to be fit in the 'addi' instruction.
  2803. One solution is to move value into a register
  2804. and then use 'add' instruction.
  2805. - In practice, we use TA_REGNUM ($r15) to accomplish this purpose.
  2806. - Also, we need to return zero for sp adjustment so that
  2807. - proglogue/epilogue knows there is no need to create 'addi' instruction. */
  2808. -static int
  2809. -nds32_force_addi_stack_int (int full_value)
  2810. + In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */
  2811. +static void
  2812. +nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value)
  2813. {
  2814. - int adjust_value;
  2815. -
  2816. rtx tmp_reg;
  2817. - rtx sp_adjust_insn;
  2818. + rtx frame_adjust_insn;
  2819. + rtx adjust_value_rtx = GEN_INT (adjust_value);
  2820. - if (!satisfies_constraint_Is15 (GEN_INT (full_value)))
  2821. + if (adjust_value == 0)
  2822. + return;
  2823. +
  2824. + if (!satisfies_constraint_Is15 (adjust_value_rtx))
  2825. {
  2826. /* The value is not able to fit in single addi instruction.
  2827. - Create more instructions of moving value into a register
  2828. - and then add stack pointer with it. */
  2829. + Create more instructions of moving value into a register
  2830. + and then add stack pointer with it. */
  2831. /* $r15 is going to be temporary register to hold the value. */
  2832. tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  2833. /* Create one more instruction to move value
  2834. - into the temporary register. */
  2835. - emit_move_insn (tmp_reg, GEN_INT (full_value));
  2836. + into the temporary register. */
  2837. + emit_move_insn (tmp_reg, adjust_value_rtx);
  2838. /* Create new 'add' rtx. */
  2839. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  2840. - stack_pointer_rtx,
  2841. - tmp_reg);
  2842. + frame_adjust_insn = gen_addsi3 (to_reg,
  2843. + from_reg,
  2844. + tmp_reg);
  2845. /* Emit rtx into insn list and receive its transformed insn rtx. */
  2846. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  2847. + frame_adjust_insn = emit_insn (frame_adjust_insn);
  2848. - /* At prologue, we need to tell GCC that this is frame related insn,
  2849. - so that we can consider this instruction to output debug information.
  2850. - If full_value is NEGATIVE, it means this function
  2851. - is invoked by expand_prologue. */
  2852. - if (full_value < 0)
  2853. - {
  2854. - /* Because (tmp_reg <- full_value) may be split into two
  2855. - rtl patterns, we can not set its RTX_FRAME_RELATED_P.
  2856. - We need to construct another (sp <- sp + full_value)
  2857. - and then insert it into sp_adjust_insn's reg note to
  2858. - represent a frame related expression.
  2859. - GCC knows how to refer it and output debug information. */
  2860. -
  2861. - rtx plus_rtx;
  2862. - rtx set_rtx;
  2863. -
  2864. - plus_rtx = plus_constant (Pmode, stack_pointer_rtx, full_value);
  2865. - set_rtx = gen_rtx_SET (VOIDmode, stack_pointer_rtx, plus_rtx);
  2866. - add_reg_note (sp_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx);
  2867. -
  2868. - RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
  2869. - }
  2870. -
  2871. - /* We have used alternative way to adjust stack pointer value.
  2872. - Return zero so that prologue/epilogue
  2873. - will not generate other instructions. */
  2874. - return 0;
  2875. + /* Because (tmp_reg <- full_value) may be split into two
  2876. + rtl patterns, we can not set its RTX_FRAME_RELATED_P.
  2877. + We need to construct another (sp <- sp + full_value)
  2878. + and then insert it into sp_adjust_insn's reg note to
  2879. + represent a frame related expression.
  2880. + GCC knows how to refer it and output debug information. */
  2881. +
  2882. + rtx plus_rtx;
  2883. + rtx set_rtx;
  2884. +
  2885. + plus_rtx = plus_constant (Pmode, from_reg, adjust_value);
  2886. + set_rtx = gen_rtx_SET (VOIDmode, to_reg, plus_rtx);
  2887. + add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx);
  2888. }
  2889. else
  2890. {
  2891. - /* The value is able to fit in addi instruction.
  2892. - However, remember to make it to be positive value
  2893. - because we want to return 'adjustment' result. */
  2894. - adjust_value = (full_value < 0) ? (-full_value) : (full_value);
  2895. -
  2896. - return adjust_value;
  2897. + /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
  2898. + frame_adjust_insn = gen_addsi3 (to_reg,
  2899. + from_reg,
  2900. + adjust_value_rtx);
  2901. + /* Emit rtx into instructions list and receive INSN rtx form. */
  2902. + frame_adjust_insn = emit_insn (frame_adjust_insn);
  2903. }
  2904. +
  2905. + /* The insn rtx 'sp_adjust_insn' will change frame layout.
  2906. + We need to use RTX_FRAME_RELATED_P so that GCC is able to
  2907. + generate CFI (Call Frame Information) stuff. */
  2908. + RTX_FRAME_RELATED_P (frame_adjust_insn) = 1;
  2909. }
  2910. /* Return true if MODE/TYPE need double word alignment. */
  2911. @@ -1444,18 +1420,25 @@
  2912. return (align > PARM_BOUNDARY);
  2913. }
  2914. -/* Return true if FUNC is a naked function. */
  2915. -static bool
  2916. +bool
  2917. nds32_naked_function_p (tree func)
  2918. {
  2919. - tree t;
  2920. + /* FOR BACKWARD COMPATIBILITY,
  2921. + we need to support 'no_prologue' attribute as well. */
  2922. + tree t_naked;
  2923. + tree t_no_prologue;
  2924. if (TREE_CODE (func) != FUNCTION_DECL)
  2925. abort ();
  2926. - t = lookup_attribute ("naked", DECL_ATTRIBUTES (func));
  2927. + /* We have to use lookup_attribute() to check attributes.
  2928. + Because attr_naked_p and attr_no_prologue_p are set in
  2929. + nds32_compute_stack_frame() and the function has not been
  2930. + invoked yet. */
  2931. + t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func));
  2932. + t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func));
  2933. - return (t != NULL_TREE);
  2934. + return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE));
  2935. }
  2936. /* Function that check if 'X' is a valid address register.
  2937. @@ -1464,7 +1447,7 @@
  2938. STRICT : true
  2939. => We are in reload pass or after reload pass.
  2940. - The register number should be strictly limited in general registers.
  2941. + The register number should be strictly limited in general registers.
  2942. STRICT : false
  2943. => Before reload pass, we are free to use any register number. */
  2944. @@ -1487,7 +1470,7 @@
  2945. /* Function that check if 'INDEX' is valid to be a index rtx for address.
  2946. OUTER_MODE : Machine mode of outer address rtx.
  2947. - INDEX : Check if this rtx is valid to be a index for address.
  2948. + INDEX : Check if this rtx is valid to be a index for address.
  2949. STRICT : If it is true, we are in reload pass or after reload pass. */
  2950. static bool
  2951. nds32_legitimate_index_p (enum machine_mode outer_mode,
  2952. @@ -1503,7 +1486,7 @@
  2953. case REG:
  2954. regno = REGNO (index);
  2955. /* If we are in reload pass or after reload pass,
  2956. - we need to limit it to general register. */
  2957. + we need to limit it to general register. */
  2958. if (strict)
  2959. return REGNO_OK_FOR_INDEX_P (regno);
  2960. else
  2961. @@ -1511,45 +1494,73 @@
  2962. case CONST_INT:
  2963. /* The alignment of the integer value is determined by 'outer_mode'. */
  2964. - if (GET_MODE_SIZE (outer_mode) == 1)
  2965. + switch (GET_MODE_SIZE (outer_mode))
  2966. {
  2967. + case 1:
  2968. /* Further check if the value is legal for the 'outer_mode'. */
  2969. - if (!satisfies_constraint_Is15 (index))
  2970. - return false;
  2971. + if (satisfies_constraint_Is15 (index))
  2972. + return true;
  2973. + break;
  2974. - /* Pass all test, the value is valid, return true. */
  2975. - return true;
  2976. - }
  2977. - if (GET_MODE_SIZE (outer_mode) == 2
  2978. - && NDS32_HALF_WORD_ALIGN_P (INTVAL (index)))
  2979. - {
  2980. + case 2:
  2981. /* Further check if the value is legal for the 'outer_mode'. */
  2982. - if (!satisfies_constraint_Is16 (index))
  2983. - return false;
  2984. + if (satisfies_constraint_Is16 (index))
  2985. + {
  2986. + /* If it is not under strictly aligned situation,
  2987. + we can return true without checking alignment. */
  2988. + if (!cfun->machine->strict_aligned_p)
  2989. + return true;
  2990. + /* Make sure address is half word alignment. */
  2991. + else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index)))
  2992. + return true;
  2993. + }
  2994. + break;
  2995. - /* Pass all test, the value is valid, return true. */
  2996. - return true;
  2997. - }
  2998. - if (GET_MODE_SIZE (outer_mode) == 4
  2999. - && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
  3000. - {
  3001. + case 4:
  3002. /* Further check if the value is legal for the 'outer_mode'. */
  3003. - if (!satisfies_constraint_Is17 (index))
  3004. - return false;
  3005. + if (satisfies_constraint_Is17 (index))
  3006. + {
  3007. + if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
  3008. + {
  3009. + if (!satisfies_constraint_Is14 (index))
  3010. + return false;
  3011. + }
  3012. +
  3013. + /* If it is not under strictly aligned situation,
  3014. + we can return true without checking alignment. */
  3015. + if (!cfun->machine->strict_aligned_p)
  3016. + return true;
  3017. + /* Make sure address is word alignment. */
  3018. + else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
  3019. + return true;
  3020. + }
  3021. + break;
  3022. - /* Pass all test, the value is valid, return true. */
  3023. - return true;
  3024. - }
  3025. - if (GET_MODE_SIZE (outer_mode) == 8
  3026. - && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
  3027. - {
  3028. - /* Further check if the value is legal for the 'outer_mode'. */
  3029. - if (!satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4,
  3030. - SImode)))
  3031. - return false;
  3032. + case 8:
  3033. + if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4,
  3034. + SImode)))
  3035. + {
  3036. + if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
  3037. + {
  3038. + if (!satisfies_constraint_Is14 (index))
  3039. + return false;
  3040. + }
  3041. +
  3042. + /* If it is not under strictly aligned situation,
  3043. + we can return true without checking alignment. */
  3044. + if (!cfun->machine->strict_aligned_p)
  3045. + return true;
  3046. + /* Make sure address is word alignment.
  3047. + Currently we do not have 64-bit load/store yet,
  3048. + so we will use two 32-bit load/store instructions to do
  3049. + memory access and they are single word alignment. */
  3050. + else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
  3051. + return true;
  3052. + }
  3053. + break;
  3054. - /* Pass all test, the value is valid, return true. */
  3055. - return true;
  3056. + default:
  3057. + return false;
  3058. }
  3059. return false;
  3060. @@ -1563,9 +1574,10 @@
  3061. int multiplier;
  3062. multiplier = INTVAL (op1);
  3063. - /* We only allow (mult reg const_int_1)
  3064. - or (mult reg const_int_2) or (mult reg const_int_4). */
  3065. - if (multiplier != 1 && multiplier != 2 && multiplier != 4)
  3066. + /* We only allow (mult reg const_int_1), (mult reg const_int_2),
  3067. + (mult reg const_int_4) or (mult reg const_int_8). */
  3068. + if (multiplier != 1 && multiplier != 2
  3069. + && multiplier != 4 && multiplier != 8)
  3070. return false;
  3071. regno = REGNO (op0);
  3072. @@ -1590,8 +1602,9 @@
  3073. sv = INTVAL (op1);
  3074. /* We only allow (ashift reg const_int_0)
  3075. - or (ashift reg const_int_1) or (ashift reg const_int_2). */
  3076. - if (sv != 0 && sv != 1 && sv !=2)
  3077. + or (ashift reg const_int_1) or (ashift reg const_int_2) or
  3078. + (ashift reg const_int_3). */
  3079. + if (sv != 0 && sv != 1 && sv !=2 && sv != 3)
  3080. return false;
  3081. regno = REGNO (op0);
  3082. @@ -1610,135 +1623,265 @@
  3083. }
  3084. }
  3085. -/* Function to expand builtin function for
  3086. - '[(unspec_volatile [(reg)])]'. */
  3087. -static rtx
  3088. -nds32_expand_builtin_null_ftype_reg (enum insn_code icode,
  3089. - tree exp, rtx target)
  3090. +static void
  3091. +nds32_insert_innermost_loop (void)
  3092. {
  3093. - /* Mapping:
  3094. - ops[0] <--> value0 <--> arg0 */
  3095. - struct expand_operand ops[1];
  3096. - tree arg0;
  3097. - rtx value0;
  3098. + struct loop *loop;
  3099. + basic_block *bbs, bb;
  3100. - /* Grab the incoming arguments and extract its rtx. */
  3101. - arg0 = CALL_EXPR_ARG (exp, 0);
  3102. - value0 = expand_normal (arg0);
  3103. + compute_bb_for_insn ();
  3104. + /* initial loop structure */
  3105. + loop_optimizer_init (0);
  3106. - /* Create operands. */
  3107. - create_input_operand (&ops[0], value0, TYPE_MODE (TREE_TYPE (arg0)));
  3108. -
  3109. - /* Emit new instruction. */
  3110. - if (!maybe_expand_insn (icode, 1, ops))
  3111. - error ("invalid argument to built-in function");
  3112. + /* Scan all inner most loops. */
  3113. + FOR_EACH_LOOP (loop, LI_ONLY_INNERMOST)
  3114. + {
  3115. + bbs = get_loop_body (loop);
  3116. + bb = *bbs;
  3117. + free (bbs);
  3118. - return target;
  3119. -}
  3120. + emit_insn_before (gen_innermost_loop_begin (),
  3121. + BB_HEAD (bb));
  3122. -/* Function to expand builtin function for
  3123. - '[(set (reg) (unspec_volatile [(imm)]))]'. */
  3124. -static rtx
  3125. -nds32_expand_builtin_reg_ftype_imm (enum insn_code icode,
  3126. - tree exp, rtx target)
  3127. -{
  3128. - /* Mapping:
  3129. - ops[0] <--> target <--> exp
  3130. - ops[1] <--> value0 <--> arg0 */
  3131. - struct expand_operand ops[2];
  3132. - tree arg0;
  3133. - rtx value0;
  3134. + /* Find the final basic block in the loop. */
  3135. + while (bb)
  3136. + {
  3137. + if (bb->next_bb == NULL)
  3138. + break;
  3139. - /* Grab the incoming arguments and extract its rtx. */
  3140. - arg0 = CALL_EXPR_ARG (exp, 0);
  3141. - value0 = expand_normal (arg0);
  3142. + if (bb->next_bb->loop_father != loop)
  3143. + break;
  3144. - /* Create operands. */
  3145. - create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
  3146. - create_input_operand (&ops[1], value0, TYPE_MODE (TREE_TYPE (arg0)));
  3147. + bb = bb->next_bb;
  3148. + }
  3149. - /* Emit new instruction. */
  3150. - if (!maybe_expand_insn (icode, 2, ops))
  3151. - error ("invalid argument to built-in function");
  3152. + emit_insn_before (gen_innermost_loop_end (),
  3153. + BB_END (bb));
  3154. + }
  3155. - return target;
  3156. + /* release loop structre */
  3157. + loop_optimizer_finalize ();
  3158. }
  3159. -/* Function to expand builtin function for
  3160. - '[(unspec_volatile [(reg) (imm)])]' pattern. */
  3161. -static rtx
  3162. -nds32_expand_builtin_null_ftype_reg_imm (enum insn_code icode,
  3163. - tree exp, rtx target)
  3164. +/* Insert isps for function with signature attribute. */
  3165. +static void
  3166. +nds32_insert_isps (void)
  3167. {
  3168. - /* Mapping:
  3169. - ops[0] <--> value0 <--> arg0
  3170. - ops[1] <--> value1 <--> arg1 */
  3171. - struct expand_operand ops[2];
  3172. - tree arg0, arg1;
  3173. - rtx value0, value1;
  3174. -
  3175. - /* Grab the incoming arguments and extract its rtx. */
  3176. - arg0 = CALL_EXPR_ARG (exp, 0);
  3177. - arg1 = CALL_EXPR_ARG (exp, 1);
  3178. - value0 = expand_normal (arg0);
  3179. - value1 = expand_normal (arg1);
  3180. -
  3181. - /* Create operands. */
  3182. - create_input_operand (&ops[0], value0, TYPE_MODE (TREE_TYPE (arg0)));
  3183. - create_input_operand (&ops[1], value1, TYPE_MODE (TREE_TYPE (arg1)));
  3184. -
  3185. - /* Emit new instruction. */
  3186. - if (!maybe_expand_insn (icode, 2, ops))
  3187. - error ("invalid argument to built-in function");
  3188. -
  3189. - return target;
  3190. -}
  3191. -
  3192. -/* A helper function to return character based on byte size. */
  3193. -static char
  3194. -nds32_byte_to_size (int byte)
  3195. -{
  3196. - switch (byte)
  3197. - {
  3198. - case 4:
  3199. - return 'w';
  3200. - case 2:
  3201. - return 'h';
  3202. - case 1:
  3203. - return 'b';
  3204. - default:
  3205. - /* Normally it should not be here. */
  3206. - gcc_unreachable ();
  3207. + rtx insn;
  3208. + unsigned first = 0;
  3209. +
  3210. + if (!lookup_attribute ("signature", DECL_ATTRIBUTES (current_function_decl)))
  3211. + return;
  3212. +
  3213. + insn = get_insns ();
  3214. + while (insn)
  3215. + {
  3216. + /* In order to ensure protect whole function, emit the first
  3217. + isps here rather than in prologue.*/
  3218. + if (!first && INSN_P (insn))
  3219. + {
  3220. + emit_insn_before (gen_unspec_signature_begin (), insn);
  3221. + first = 1;
  3222. + }
  3223. +
  3224. + if (LABEL_P (insn) || CALL_P (insn) || any_condjump_p (insn)
  3225. + || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
  3226. + && (XINT (PATTERN (insn), 1) == UNSPEC_VOLATILE_SYSCALL
  3227. + || XINT (PATTERN (insn), 1) == UNSPEC_VOLATILE_TRAP
  3228. + || XINT (PATTERN (insn), 1) == UNSPEC_VOLATILE_TEQZ
  3229. + || XINT (PATTERN (insn), 1) == UNSPEC_VOLATILE_TNEZ)))
  3230. + {
  3231. + emit_insn_after (gen_unspec_signature_begin (), insn);
  3232. + }
  3233. + insn = NEXT_INSN (insn);
  3234. }
  3235. }
  3236. -/* A helper function to check if this function should contain prologue. */
  3237. -static int
  3238. -nds32_have_prologue_p (void)
  3239. +static void
  3240. +nds32_register_pass (
  3241. + rtl_opt_pass *(*make_pass_func) (gcc::context *),
  3242. + enum pass_positioning_ops pass_pos,
  3243. + const char *ref_pass_name)
  3244. {
  3245. - int i;
  3246. + opt_pass *new_opt_pass = make_pass_func (g);
  3247. +
  3248. + struct register_pass_info insert_pass =
  3249. + {
  3250. + new_opt_pass, /* pass */
  3251. + ref_pass_name, /* reference_pass_name */
  3252. + 1, /* ref_pass_instance_number */
  3253. + pass_pos /* po_op */
  3254. + };
  3255. +
  3256. + register_pass (&insert_pass);
  3257. +}
  3258. - for (i = 0; i < 28; i++)
  3259. - if (NDS32_REQUIRED_CALLEE_SAVED_P (i))
  3260. - return 1;
  3261. -
  3262. - return (flag_pic
  3263. - || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
  3264. - || NDS32_REQUIRED_CALLEE_SAVED_P (LP_REGNUM));
  3265. +/* This function is called from nds32_option_override ().
  3266. + All new passes should be registered here. */
  3267. +static void
  3268. +nds32_register_passes (void)
  3269. +{
  3270. + nds32_register_pass (
  3271. + make_pass_nds32_fp_as_gp,
  3272. + PASS_POS_INSERT_BEFORE,
  3273. + "ira");
  3274. +
  3275. + nds32_register_pass (
  3276. + make_pass_nds32_relax_opt,
  3277. + PASS_POS_INSERT_AFTER,
  3278. + "mach");
  3279. +
  3280. + nds32_register_pass (
  3281. + make_pass_nds32_hwloop2_opt,
  3282. + PASS_POS_INSERT_BEFORE,
  3283. + "mach");
  3284. +
  3285. + nds32_register_pass (
  3286. + make_pass_nds32_load_store_opt,
  3287. + PASS_POS_INSERT_AFTER,
  3288. + "mach");
  3289. +
  3290. + nds32_register_pass (
  3291. + make_pass_nds32_soft_fp_arith_comm_opt,
  3292. + PASS_POS_INSERT_BEFORE,
  3293. + "ira");
  3294. +
  3295. + nds32_register_pass (
  3296. + make_pass_nds32_regrename_opt,
  3297. + PASS_POS_INSERT_AFTER,
  3298. + "mach");
  3299. +
  3300. + nds32_register_pass (
  3301. + make_pass_nds32_gcse_opt,
  3302. + PASS_POS_INSERT_BEFORE,
  3303. + "cprop_hardreg");
  3304. +
  3305. + nds32_register_pass (
  3306. + make_pass_cprop_hardreg,
  3307. + PASS_POS_INSERT_AFTER,
  3308. + "mach");
  3309. +
  3310. + nds32_register_pass (
  3311. + make_pass_nds32_hwloop1_opt,
  3312. + PASS_POS_INSERT_BEFORE,
  3313. + "ira");
  3314. +
  3315. + if (TARGET_PRINT_STALLS)
  3316. + nds32_register_pass (
  3317. + nds32::scheduling::make_pass_nds32_print_stalls,
  3318. + PASS_POS_INSERT_BEFORE,
  3319. + "final");
  3320. }
  3321. /* ------------------------------------------------------------------------ */
  3322. -/* PART 3: Implement target hook stuff definitions. */
  3323. +/* PART 4: Implement target hook stuff definitions. */
  3324. +
  3325. +
  3326. +/* Computing the Length of an Insn.
  3327. + Modifies the length assigned to instruction INSN.
  3328. + LEN is the initially computed length of the insn. */
  3329. +int
  3330. +nds32_adjust_insn_length (rtx insn, int length)
  3331. +{
  3332. + int adjust_value = 0;
  3333. + switch (recog_memoized (insn))
  3334. + {
  3335. + case CODE_FOR_call_immediate_align:
  3336. + case CODE_FOR_call_value_immediate_align:
  3337. + case CODE_FOR_call_register_align:
  3338. + case CODE_FOR_call_value_register_align:
  3339. + {
  3340. + rtx next_insn = next_active_insn (insn);
  3341. + if (next_insn && get_attr_length (next_insn) != 2)
  3342. + adjust_value += 2;
  3343. + }
  3344. + /* FALLTHRU */
  3345. + case CODE_FOR_call_immediate:
  3346. + case CODE_FOR_call_value_immediate:
  3347. + case CODE_FOR_call_register:
  3348. + case CODE_FOR_call_value_register:
  3349. + {
  3350. + /* We need insert a nop after a noretun function call
  3351. + to prevent software breakpoint corrupt the next function. */
  3352. + if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
  3353. + {
  3354. + if (TARGET_16_BIT)
  3355. + adjust_value += 2;
  3356. + else
  3357. + adjust_value += 4;
  3358. + }
  3359. + }
  3360. + return length + adjust_value;
  3361. +
  3362. + default:
  3363. + return length;
  3364. + }
  3365. +}
  3366. +
  3367. +/* Storage Layout. */
  3368. +
  3369. +/* This function will be called just before expansion into rtl. */
  3370. +static void
  3371. +nds32_expand_to_rtl_hook (void)
  3372. +{
  3373. + /* We need to set strictly aligned situation.
  3374. + After that, the memory address checking in nds32_legitimate_address_p()
  3375. + will take alignment offset into consideration so that it will not create
  3376. + unaligned [base + offset] access during the rtl optimization. */
  3377. + cfun->machine->strict_aligned_p = 1;
  3378. +}
  3379. +
  3380. +
  3381. +/* Register Usage. */
  3382. +
  3383. +static void
  3384. +nds32_conditional_register_usage (void)
  3385. +{
  3386. + int regno;
  3387. +
  3388. + if (TARGET_LINUX_ABI)
  3389. + fixed_regs[TP_REGNUM] = 1;
  3390. +
  3391. + if (TARGET_HARD_FLOAT)
  3392. + {
  3393. + for (regno = NDS32_FIRST_FPR_REGNUM;
  3394. + regno <= NDS32_LAST_FPR_REGNUM; regno++)
  3395. + {
  3396. + fixed_regs[regno] = 0;
  3397. + if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
  3398. + call_used_regs[regno] = 1;
  3399. + else if (regno >= NDS32_FIRST_FPR_REGNUM + 22
  3400. + && regno < NDS32_FIRST_FPR_REGNUM + 48)
  3401. + call_used_regs[regno] = 1;
  3402. + else
  3403. + call_used_regs[regno] = 0;
  3404. + }
  3405. + }
  3406. + else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  3407. + {
  3408. + for (regno = NDS32_FIRST_FPR_REGNUM;
  3409. + regno <= NDS32_LAST_FPR_REGNUM;
  3410. + regno++)
  3411. + fixed_regs[regno] = 0;
  3412. + }
  3413. +}
  3414. +
  3415. /* Register Classes. */
  3416. +static reg_class_t
  3417. +nds32_preferred_rename_class (reg_class_t rclass)
  3418. +{
  3419. + return nds32_preferred_rename_class_impl (rclass);
  3420. +}
  3421. +
  3422. static unsigned char
  3423. nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED,
  3424. enum machine_mode mode)
  3425. {
  3426. /* Return the maximum number of consecutive registers
  3427. - needed to represent "mode" in a register of "rclass". */
  3428. + needed to represent MODE in a register of RCLASS. */
  3429. return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
  3430. }
  3431. @@ -1746,9 +1889,24 @@
  3432. nds32_register_priority (int hard_regno)
  3433. {
  3434. /* Encourage to use r0-r7 for LRA when optimize for size. */
  3435. - if (optimize_size && hard_regno < 8)
  3436. - return 4;
  3437. - return 3;
  3438. + if (optimize_size)
  3439. + {
  3440. + if (hard_regno < 8)
  3441. + return 4;
  3442. + else if (hard_regno < 16)
  3443. + return 3;
  3444. + else if (hard_regno < 28)
  3445. + return 2;
  3446. + else
  3447. + return 1;
  3448. + }
  3449. + else
  3450. + {
  3451. + if (hard_regno > 27)
  3452. + return 1;
  3453. + else
  3454. + return 4;
  3455. + }
  3456. }
  3457. @@ -1768,8 +1926,8 @@
  3458. 2. return address
  3459. 3. callee-saved registers
  3460. 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
  3461. - and save it at
  3462. - cfun->machine->callee_saved_area_padding_bytes)
  3463. + and save it at
  3464. + cfun->machine->callee_saved_area_padding_bytes)
  3465. [Block B]
  3466. 1. local variables
  3467. @@ -1787,36 +1945,37 @@
  3468. By applying the basic frame/stack/argument pointers concept,
  3469. the layout of a stack frame shoule be like this:
  3470. - | |
  3471. + | |
  3472. old stack pointer -> ----
  3473. - | | \
  3474. - | | saved arguments for
  3475. - | | vararg functions
  3476. - | | /
  3477. + | | \
  3478. + | | saved arguments for
  3479. + | | vararg functions
  3480. + | | /
  3481. hard frame pointer -> --
  3482. & argument pointer | | \
  3483. - | | previous hardware frame pointer
  3484. - | | return address
  3485. - | | callee-saved registers
  3486. - | | /
  3487. - frame pointer -> --
  3488. - | | \
  3489. - | | local variables
  3490. - | | and incoming arguments
  3491. - | | /
  3492. - --
  3493. - | | \
  3494. - | | outgoing
  3495. - | | arguments
  3496. - | | /
  3497. - stack pointer -> ----
  3498. + | | previous hardware frame pointer
  3499. + | | return address
  3500. + | | callee-saved registers
  3501. + | | /
  3502. + frame pointer -> --
  3503. + | | \
  3504. + | | local variables
  3505. + | | and incoming arguments
  3506. + | | /
  3507. + --
  3508. + | | \
  3509. + | | outgoing
  3510. + | | arguments
  3511. + | | /
  3512. + stack pointer -> ----
  3513. $SFP and $AP are used to represent frame pointer and arguments pointer,
  3514. which will be both eliminated as hard frame pointer. */
  3515. /* -- Eliminating Frame Pointer and Arg Pointer. */
  3516. -static bool nds32_can_eliminate (const int from_reg, const int to_reg)
  3517. +static bool
  3518. +nds32_can_eliminate (const int from_reg, const int to_reg)
  3519. {
  3520. if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
  3521. return true;
  3522. @@ -1839,6 +1998,7 @@
  3523. nds32_function_arg (cumulative_args_t ca, enum machine_mode mode,
  3524. const_tree type, bool named)
  3525. {
  3526. + unsigned int regno;
  3527. CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
  3528. /* The last time this hook is called,
  3529. @@ -1846,25 +2006,131 @@
  3530. if (mode == VOIDmode)
  3531. return NULL_RTX;
  3532. - /* For nameless arguments, they are passed on the stack. */
  3533. + /* For nameless arguments, we need to take care it individually. */
  3534. if (!named)
  3535. - return NULL_RTX;
  3536. -
  3537. - /* If there are still registers available, return it. */
  3538. - if (NDS32_ARG_PASS_IN_REG_P (cum->reg_offset, mode, type))
  3539. {
  3540. - /* Pick up the next available register number. */
  3541. - unsigned int regno;
  3542. + /* If we are under hard float abi, we have arguments passed on the
  3543. + stack and all situation can be handled by GCC itself. */
  3544. + if (TARGET_HARD_FLOAT)
  3545. + return NULL_RTX;
  3546. +
  3547. + if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type))
  3548. + {
  3549. + /* If we still have enough registers to pass argument, pick up
  3550. + next available register number. */
  3551. + regno
  3552. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
  3553. + return gen_rtx_REG (mode, regno);
  3554. + }
  3555. +
  3556. + /* No register available, return NULL_RTX.
  3557. + The compiler will use stack to pass argument instead. */
  3558. + return NULL_RTX;
  3559. + }
  3560. - regno = NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, mode, type);
  3561. - return gen_rtx_REG (mode, regno);
  3562. + /* The following is to handle named argument.
  3563. + Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT
  3564. + are different. */
  3565. + if (TARGET_HARD_FLOAT)
  3566. + {
  3567. + /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR
  3568. + to pass argument. We have to further check TYPE and MODE so
  3569. + that we can determine which kind of register we shall use. */
  3570. +
  3571. + /* Note that we need to pass argument entirely in registers under
  3572. + hard float abi. */
  3573. + if (GET_MODE_CLASS (mode) == MODE_FLOAT
  3574. + && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type))
  3575. + {
  3576. + /* Pick up the next available FPR register number. */
  3577. + regno
  3578. + = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type);
  3579. + return gen_rtx_REG (mode, regno);
  3580. + }
  3581. + else if (GET_MODE_CLASS (mode) != MODE_FLOAT
  3582. + && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type))
  3583. + {
  3584. + /* Pick up the next available GPR register number. */
  3585. + regno
  3586. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
  3587. + return gen_rtx_REG (mode, regno);
  3588. + }
  3589. }
  3590. else
  3591. {
  3592. - /* No register available, return NULL_RTX.
  3593. - The compiler will use stack to pass argument instead. */
  3594. - return NULL_RTX;
  3595. + /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass
  3596. + argument. Since we allow to pass argument partially in registers,
  3597. + we can just return it if there are still registers available. */
  3598. + if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type))
  3599. + {
  3600. + /* Pick up the next available register number. */
  3601. + regno
  3602. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
  3603. + return gen_rtx_REG (mode, regno);
  3604. + }
  3605. +
  3606. }
  3607. +
  3608. + /* No register available, return NULL_RTX.
  3609. + The compiler will use stack to pass argument instead. */
  3610. + return NULL_RTX;
  3611. +}
  3612. +
  3613. +static bool
  3614. +nds32_must_pass_in_stack (enum machine_mode mode, const_tree type)
  3615. +{
  3616. + /* Return true if a type must be passed in memory.
  3617. + If it is NOT using hard float abi, small aggregates can be
  3618. + passed in a register even we are calling a variadic function.
  3619. + So there is no need to take padding into consideration. */
  3620. + if (TARGET_HARD_FLOAT)
  3621. + return must_pass_in_stack_var_size_or_pad (mode, type);
  3622. + else
  3623. + return must_pass_in_stack_var_size (mode, type);
  3624. +}
  3625. +
  3626. +static int
  3627. +nds32_arg_partial_bytes (cumulative_args_t ca, enum machine_mode mode,
  3628. + tree type, bool named ATTRIBUTE_UNUSED)
  3629. +{
  3630. + /* Returns the number of bytes at the beginning of an argument that
  3631. + must be put in registers. The value must be zero for arguments that are
  3632. + passed entirely in registers or that are entirely pushed on the stack.
  3633. + Besides, TARGET_FUNCTION_ARG for these arguments should return the
  3634. + first register to be used by the caller for this argument. */
  3635. + unsigned int needed_reg_count;
  3636. + unsigned int remaining_reg_count;
  3637. + CUMULATIVE_ARGS *cum;
  3638. +
  3639. + cum = get_cumulative_args (ca);
  3640. +
  3641. + /* Under hard float abi, we better have argument entirely passed in
  3642. + registers or pushed on the stack so that we can reduce the complexity
  3643. + of dealing with cum->gpr_offset and cum->fpr_offset. */
  3644. + if (TARGET_HARD_FLOAT)
  3645. + return 0;
  3646. +
  3647. + /* If we have already runned out of argument registers, return zero
  3648. + so that the argument will be entirely pushed on the stack. */
  3649. + if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
  3650. + >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
  3651. + return 0;
  3652. +
  3653. + /* Calculate how many registers do we need for this argument. */
  3654. + needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  3655. +
  3656. + /* Calculate how many argument registers have left for passing argument.
  3657. + Note that we should count it from next available register number. */
  3658. + remaining_reg_count
  3659. + = NDS32_MAX_GPR_REGS_FOR_ARGS
  3660. + - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
  3661. + - NDS32_GPR_ARG_FIRST_REGNUM);
  3662. +
  3663. + /* Note that we have to return the nubmer of bytes, not registers count. */
  3664. + if (needed_reg_count > remaining_reg_count)
  3665. + return remaining_reg_count * UNITS_PER_WORD;
  3666. +
  3667. + return 0;
  3668. }
  3669. static void
  3670. @@ -1873,14 +2139,40 @@
  3671. {
  3672. CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
  3673. - /* Advance next register for use.
  3674. - Only named argument could be advanced. */
  3675. if (named)
  3676. {
  3677. - cum->reg_offset
  3678. - = NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, mode, type)
  3679. - - NDS32_GPR_ARG_FIRST_REGNUM
  3680. - + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  3681. + /* We need to further check TYPE and MODE so that we can determine
  3682. + which kind of register we shall advance. */
  3683. +
  3684. + /* Under hard float abi, we may advance FPR registers. */
  3685. + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
  3686. + {
  3687. + cum->fpr_offset
  3688. + = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type)
  3689. + - NDS32_FPR_ARG_FIRST_REGNUM
  3690. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  3691. + }
  3692. + else
  3693. + {
  3694. + cum->gpr_offset
  3695. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
  3696. + - NDS32_GPR_ARG_FIRST_REGNUM
  3697. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  3698. + }
  3699. + }
  3700. + else
  3701. + {
  3702. + /* If this nameless argument is NOT under TARGET_HARD_FLOAT,
  3703. + we can advance next register as well so that caller is
  3704. + able to pass arguments in registers and callee must be
  3705. + in charge of pushing all of them into stack. */
  3706. + if (!TARGET_HARD_FLOAT)
  3707. + {
  3708. + cum->gpr_offset
  3709. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
  3710. + - NDS32_GPR_ARG_FIRST_REGNUM
  3711. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  3712. + }
  3713. }
  3714. }
  3715. @@ -1892,6 +2184,16 @@
  3716. : PARM_BOUNDARY);
  3717. }
  3718. +bool
  3719. +nds32_vector_mode_supported_p (enum machine_mode mode)
  3720. +{
  3721. + if (mode == V4QImode
  3722. + || mode == V2HImode)
  3723. + return NDS32_EXT_DSP_P ();
  3724. +
  3725. + return false;
  3726. +}
  3727. +
  3728. /* -- How Scalar Function Values Are Returned. */
  3729. static rtx
  3730. @@ -1905,22 +2207,62 @@
  3731. mode = TYPE_MODE (ret_type);
  3732. unsignedp = TYPE_UNSIGNED (ret_type);
  3733. - mode = promote_mode (ret_type, mode, &unsignedp);
  3734. + if (INTEGRAL_TYPE_P (ret_type))
  3735. + mode = promote_mode (ret_type, mode, &unsignedp);
  3736. - return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
  3737. + if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
  3738. + return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM);
  3739. + else
  3740. + return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
  3741. }
  3742. static rtx
  3743. nds32_libcall_value (enum machine_mode mode,
  3744. const_rtx fun ATTRIBUTE_UNUSED)
  3745. {
  3746. + if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
  3747. + return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM);
  3748. +
  3749. return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
  3750. }
  3751. static bool
  3752. nds32_function_value_regno_p (const unsigned int regno)
  3753. {
  3754. - return (regno == NDS32_GPR_RET_FIRST_REGNUM);
  3755. + if (regno == NDS32_GPR_RET_FIRST_REGNUM
  3756. + || (TARGET_HARD_FLOAT
  3757. + && regno == NDS32_FPR_RET_FIRST_REGNUM))
  3758. + return true;
  3759. +
  3760. + return false;
  3761. +}
  3762. +
  3763. +/* -- How Large Values Are Returned. */
  3764. +
  3765. +static bool
  3766. +nds32_return_in_memory (const_tree type,
  3767. + const_tree fntype ATTRIBUTE_UNUSED)
  3768. +{
  3769. + /* Note that int_size_in_bytes can return -1 if the size can vary
  3770. + or is larger than an integer. */
  3771. + HOST_WIDE_INT size = int_size_in_bytes (type);
  3772. +
  3773. + /* For COMPLEX_TYPE, if the total size cannot be hold within two registers,
  3774. + the return value is supposed to be in memory. We need to be aware of
  3775. + that the size may be -1. */
  3776. + if (TREE_CODE (type) == COMPLEX_TYPE)
  3777. + if (size < 0 || size > 2 * UNITS_PER_WORD)
  3778. + return true;
  3779. +
  3780. + /* If it is BLKmode and the total size cannot be hold within two registers,
  3781. + the return value is supposed to be in memory. We need to be aware of
  3782. + that the size may be -1. */
  3783. + if (TYPE_MODE (type) == BLKmode)
  3784. + if (size < 0 || size > 2 * UNITS_PER_WORD)
  3785. + return true;
  3786. +
  3787. + /* For other cases, having result in memory is unnecessary. */
  3788. + return false;
  3789. }
  3790. /* -- Function Entry and Exit. */
  3791. @@ -1951,7 +2293,7 @@
  3792. /* Use df_regs_ever_live_p() to detect if the register
  3793. is ever used in the current function. */
  3794. fprintf (file, "\t! registers ever_live: ");
  3795. - for (r = 0; r < 32; r++)
  3796. + for (r = 0; r < 65; r++)
  3797. {
  3798. if (df_regs_ever_live_p (r))
  3799. fprintf (file, "%s, ", reg_names[r]);
  3800. @@ -1983,6 +2325,10 @@
  3801. attrs = TREE_CHAIN (attrs);
  3802. }
  3803. fputc ('\n', file);
  3804. +
  3805. + /* If there is any critical isr in this file, disable linker ifc. */
  3806. + if (nds32_isr_function_critical_p (current_function_decl))
  3807. + fprintf (file, "\t.no_relax ifc\n");
  3808. }
  3809. /* After rtl prologue has been expanded, this function is used. */
  3810. @@ -1990,56 +2336,12 @@
  3811. nds32_asm_function_end_prologue (FILE *file)
  3812. {
  3813. fprintf (file, "\t! END PROLOGUE\n");
  3814. -
  3815. - /* If frame pointer is NOT needed and -mfp-as-gp is issued,
  3816. - we can generate special directive: ".omit_fp_begin"
  3817. - to guide linker doing fp-as-gp optimization.
  3818. - However, for a naked function, which means
  3819. - it should not have prologue/epilogue,
  3820. - using fp-as-gp still requires saving $fp by push/pop behavior and
  3821. - there is no benefit to use fp-as-gp on such small function.
  3822. - So we need to make sure this function is NOT naked as well. */
  3823. - if (!frame_pointer_needed
  3824. - && !cfun->machine->naked_p
  3825. - && cfun->machine->fp_as_gp_p)
  3826. - {
  3827. - fprintf (file, "\t! ----------------------------------------\n");
  3828. - fprintf (file, "\t! Guide linker to do "
  3829. - "link time optimization: fp-as-gp\n");
  3830. - fprintf (file, "\t! We add one more instruction to "
  3831. - "initialize $fp near to $gp location.\n");
  3832. - fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n");
  3833. - fprintf (file, "\t! this extra instruction should be "
  3834. - "eliminated at link stage.\n");
  3835. - fprintf (file, "\t.omit_fp_begin\n");
  3836. - fprintf (file, "\tla\t$fp,_FP_BASE_\n");
  3837. - fprintf (file, "\t! ----------------------------------------\n");
  3838. - }
  3839. }
  3840. /* Before rtl epilogue has been expanded, this function is used. */
  3841. static void
  3842. nds32_asm_function_begin_epilogue (FILE *file)
  3843. {
  3844. - /* If frame pointer is NOT needed and -mfp-as-gp is issued,
  3845. - we can generate special directive: ".omit_fp_end"
  3846. - to claim fp-as-gp optimization range.
  3847. - However, for a naked function,
  3848. - which means it should not have prologue/epilogue,
  3849. - using fp-as-gp still requires saving $fp by push/pop behavior and
  3850. - there is no benefit to use fp-as-gp on such small function.
  3851. - So we need to make sure this function is NOT naked as well. */
  3852. - if (!frame_pointer_needed
  3853. - && !cfun->machine->naked_p
  3854. - && cfun->machine->fp_as_gp_p)
  3855. - {
  3856. - fprintf (file, "\t! ----------------------------------------\n");
  3857. - fprintf (file, "\t! Claim the range of fp-as-gp "
  3858. - "link time optimization\n");
  3859. - fprintf (file, "\t.omit_fp_end\n");
  3860. - fprintf (file, "\t! ----------------------------------------\n");
  3861. - }
  3862. -
  3863. fprintf (file, "\t! BEGIN EPILOGUE\n");
  3864. }
  3865. @@ -2067,53 +2369,157 @@
  3866. ? 1
  3867. : 0);
  3868. + if (flag_pic)
  3869. + {
  3870. + fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n");
  3871. + fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n",
  3872. + reg_names [PIC_OFFSET_TABLE_REGNUM]);
  3873. + fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n",
  3874. + reg_names [PIC_OFFSET_TABLE_REGNUM],
  3875. + reg_names [PIC_OFFSET_TABLE_REGNUM]);
  3876. +
  3877. + if (TARGET_ISA_V3)
  3878. + fprintf (file, "\tadd5.pc\t$gp\n");
  3879. + else
  3880. + {
  3881. + fprintf (file, "\tmfusr\t$ta, $pc\n");
  3882. + fprintf (file, "\tadd\t%s, $ta, %s\n",
  3883. + reg_names [PIC_OFFSET_TABLE_REGNUM],
  3884. + reg_names [PIC_OFFSET_TABLE_REGNUM]);
  3885. + }
  3886. + }
  3887. +
  3888. if (delta != 0)
  3889. {
  3890. if (satisfies_constraint_Is15 (GEN_INT (delta)))
  3891. {
  3892. - fprintf (file, "\taddi\t$r%d, $r%d, %ld\n",
  3893. + fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n",
  3894. this_regno, this_regno, delta);
  3895. }
  3896. else if (satisfies_constraint_Is20 (GEN_INT (delta)))
  3897. {
  3898. - fprintf (file, "\tmovi\t$ta, %ld\n", delta);
  3899. + fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta);
  3900. fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
  3901. }
  3902. else
  3903. {
  3904. - fprintf (file, "\tsethi\t$ta, hi20(%ld)\n", delta);
  3905. - fprintf (file, "\tori\t$ta, $ta, lo12(%ld)\n", delta);
  3906. + fprintf (file,
  3907. + "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n",
  3908. + delta);
  3909. + fprintf (file,
  3910. + "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n",
  3911. + delta);
  3912. fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
  3913. }
  3914. }
  3915. - fprintf (file, "\tb\t");
  3916. - assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
  3917. - fprintf (file, "\n");
  3918. + if (flag_pic)
  3919. + {
  3920. + fprintf (file, "\tla\t$ta, ");
  3921. + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
  3922. + fprintf (file, "@PLT\n");
  3923. + fprintf (file, "\t! epilogue\n");
  3924. + fprintf (file, "\tlwi.bi\t%s, [%s], 4\n",
  3925. + reg_names[PIC_OFFSET_TABLE_REGNUM],
  3926. + reg_names[STACK_POINTER_REGNUM]);
  3927. + fprintf (file, "\tbr\t$ta\n");
  3928. + }
  3929. + else
  3930. + {
  3931. + fprintf (file, "\tb\t");
  3932. + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
  3933. + fprintf (file, "\n");
  3934. + }
  3935. final_end_function ();
  3936. }
  3937. /* -- Permitting tail calls. */
  3938. +/* Return true if it is ok to do sibling call optimization. */
  3939. +static bool
  3940. +nds32_function_ok_for_sibcall (tree decl,
  3941. + tree exp ATTRIBUTE_UNUSED)
  3942. +{
  3943. + /* The DECL is NULL if it is an indirect call. */
  3944. +
  3945. + /* 1. Do not apply sibling call if -mv3push is enabled,
  3946. + because pop25 instruction also represents return behavior.
  3947. + 2. If this function is a isr function, do not apply sibling call
  3948. + because it may perform the behavior that user does not expect.
  3949. + 3. If this function is a variadic function, do not apply sibling call
  3950. + because the stack layout may be a mess.
  3951. + 4. We don't want to apply sibling call optimization for indirect
  3952. + sibcall because the pop behavior in epilogue may pollute the
  3953. + content of caller-saved regsiter when the register is used for
  3954. + indirect sibcall.
  3955. + 5. In pic mode, it may use some registers for PLT call. */
  3956. + return (!TARGET_V3PUSH
  3957. + && !nds32_isr_function_p (current_function_decl)
  3958. + && (cfun->machine->va_args_size == 0)
  3959. + && decl
  3960. + && !flag_pic);
  3961. +}
  3962. +
  3963. /* Determine whether we need to enable warning for function return check. */
  3964. static bool
  3965. nds32_warn_func_return (tree decl)
  3966. {
  3967. -/* Naked functions are implemented entirely in assembly, including the
  3968. - return sequence, so suppress warnings about this. */
  3969. + /* Naked functions are implemented entirely in assembly, including the
  3970. + return sequence, so suppress warnings about this. */
  3971. return !nds32_naked_function_p (decl);
  3972. }
  3973. /* Implementing the Varargs Macros. */
  3974. +static void
  3975. +nds32_setup_incoming_varargs (cumulative_args_t ca,
  3976. + enum machine_mode mode,
  3977. + tree type,
  3978. + int *pretend_args_size,
  3979. + int second_time ATTRIBUTE_UNUSED)
  3980. +{
  3981. + unsigned int total_args_regs;
  3982. + unsigned int num_of_used_regs;
  3983. + unsigned int remaining_reg_count;
  3984. + CUMULATIVE_ARGS *cum;
  3985. +
  3986. + /* If we are under hard float abi, we do not need to set *pretend_args_size.
  3987. + So that all nameless arguments are pushed by caller and all situation
  3988. + can be handled by GCC itself. */
  3989. + if (TARGET_HARD_FLOAT)
  3990. + return;
  3991. +
  3992. + /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
  3993. + counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
  3994. + However, for nameless(anonymous) arguments, we should push them on the
  3995. + stack so that all the nameless arguments appear to have been passed
  3996. + consecutively in the memory for accessing. Hence, we need to check and
  3997. + exclude the registers that are used for named arguments. */
  3998. +
  3999. + cum = get_cumulative_args (ca);
  4000. +
  4001. + /* The MODE and TYPE describe the last argument.
  4002. + We need those information to determine the remaining registers
  4003. + for varargs. */
  4004. + total_args_regs
  4005. + = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM;
  4006. + num_of_used_regs
  4007. + = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
  4008. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
  4009. +
  4010. + remaining_reg_count = total_args_regs - num_of_used_regs;
  4011. + *pretend_args_size = remaining_reg_count * UNITS_PER_WORD;
  4012. +
  4013. + return;
  4014. +}
  4015. +
  4016. static bool
  4017. nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
  4018. {
  4019. - /* Return true so that all the named arguments for FUNCTION_ARG have named=1.
  4020. - If return false, for the variadic function, all named arguments EXCEPT
  4021. - the last are treated as named. */
  4022. + /* If this hook returns true, the named argument of FUNCTION_ARG is always
  4023. + true for named arguments, and false for unnamed arguments. */
  4024. return true;
  4025. }
  4026. @@ -2183,7 +2589,7 @@
  4027. sorry ("a nested function is not supported for reduced registers");
  4028. /* STEP 1: Copy trampoline code template into stack,
  4029. - fill up essential data into stack. */
  4030. + fill up essential data into stack. */
  4031. /* Extract nested function address rtx. */
  4032. fnaddr = XEXP (DECL_RTL (fndecl), 0);
  4033. @@ -2219,8 +2625,8 @@
  4034. && (tramp_align_in_bytes % nds32_cache_block_size) == 0)
  4035. {
  4036. /* Under this condition, the starting address of trampoline
  4037. - must be aligned to the starting address of each cache block
  4038. - and we do not have to worry about cross-boundary issue. */
  4039. + must be aligned to the starting address of each cache block
  4040. + and we do not have to worry about cross-boundary issue. */
  4041. for (i = 0;
  4042. i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
  4043. / nds32_cache_block_size;
  4044. @@ -2235,10 +2641,10 @@
  4045. else if (TRAMPOLINE_SIZE > nds32_cache_block_size)
  4046. {
  4047. /* The starting address of trampoline code
  4048. - may not be aligned to the cache block,
  4049. - so the trampoline code may be across two cache block.
  4050. - We need to sync the last element, which is 4-byte size,
  4051. - of trampoline template. */
  4052. + may not be aligned to the cache block,
  4053. + so the trampoline code may be across two cache block.
  4054. + We need to sync the last element, which is 4-byte size,
  4055. + of trampoline template. */
  4056. for (i = 0;
  4057. i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
  4058. / nds32_cache_block_size;
  4059. @@ -2259,16 +2665,16 @@
  4060. else
  4061. {
  4062. /* This is the simplest case.
  4063. - Because TRAMPOLINE_SIZE is less than or
  4064. - equal to nds32_cache_block_size,
  4065. - we can just sync start address and
  4066. - the last element of trampoline code. */
  4067. + Because TRAMPOLINE_SIZE is less than or
  4068. + equal to nds32_cache_block_size,
  4069. + we can just sync start address and
  4070. + the last element of trampoline code. */
  4071. /* Sync starting address of tampoline code. */
  4072. emit_move_insn (tmp_reg, sync_cache_addr);
  4073. emit_insn (isync_insn);
  4074. /* Sync the last element, which is 4-byte size,
  4075. - of trampoline template. */
  4076. + of trampoline template. */
  4077. emit_move_insn (tmp_reg,
  4078. plus_constant (Pmode, sync_cache_addr,
  4079. TRAMPOLINE_SIZE - 4));
  4080. @@ -2286,9 +2692,50 @@
  4081. static bool
  4082. nds32_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
  4083. {
  4084. + if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  4085. + {
  4086. + /* When using floating-point instructions,
  4087. + we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
  4088. + if (mode == DFmode
  4089. + && (GET_CODE (x) == SYMBOL_REF
  4090. + || GET_CODE(x) == CONST))
  4091. + return false;
  4092. +
  4093. + /* Allow [post_modify] addressing mode, when using FPU instructions. */
  4094. + if (GET_CODE (x) == POST_MODIFY
  4095. + && mode == DFmode)
  4096. + {
  4097. + if (GET_CODE (XEXP (x, 0)) == REG
  4098. + && GET_CODE (XEXP (x, 1)) == PLUS)
  4099. + {
  4100. + rtx plus_op = XEXP (x, 1);
  4101. + rtx op0 = XEXP (plus_op, 0);
  4102. + rtx op1 = XEXP (plus_op, 1);
  4103. +
  4104. + if (nds32_address_register_rtx_p (op0, strict)
  4105. + && CONST_INT_P (op1))
  4106. + {
  4107. + if (satisfies_constraint_Is14 (op1))
  4108. + {
  4109. + /* If it is not under strictly aligned situation,
  4110. + we can return true without checking alignment. */
  4111. + if (!cfun->machine->strict_aligned_p)
  4112. + return true;
  4113. + /* Make sure address is word alignment.
  4114. + Currently we do not have 64-bit load/store yet,
  4115. + so we will use two 32-bit load/store instructions to do
  4116. + memory access and they are single word alignment. */
  4117. + else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1)))
  4118. + return true;
  4119. + }
  4120. + }
  4121. + }
  4122. + }
  4123. + }
  4124. +
  4125. /* For (mem:DI addr) or (mem:DF addr) case,
  4126. we only allow 'addr' to be [reg], [symbol_ref],
  4127. - [const], or [reg + const_int] pattern. */
  4128. + [const], or [reg + const_int] pattern. */
  4129. if (mode == DImode || mode == DFmode)
  4130. {
  4131. /* Allow [Reg + const_int] addressing mode. */
  4132. @@ -2298,13 +2745,19 @@
  4133. && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)
  4134. && CONST_INT_P (XEXP (x, 1)))
  4135. return true;
  4136. -
  4137. else if (nds32_address_register_rtx_p (XEXP (x, 1), strict)
  4138. && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)
  4139. && CONST_INT_P (XEXP (x, 0)))
  4140. return true;
  4141. }
  4142. + /* Allow [post_inc] and [post_dec] addressing mode. */
  4143. + if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC)
  4144. + {
  4145. + if (nds32_address_register_rtx_p (XEXP (x, 0), strict))
  4146. + return true;
  4147. + }
  4148. +
  4149. /* Now check [reg], [symbol_ref], and [const]. */
  4150. if (GET_CODE (x) != REG
  4151. && GET_CODE (x) != SYMBOL_REF
  4152. @@ -2320,26 +2773,34 @@
  4153. return nds32_address_register_rtx_p (x, strict);
  4154. case SYMBOL_REF:
  4155. + /* (mem (symbol_ref A)) => [symbol_ref] */
  4156. +
  4157. + if (flag_pic || SYMBOL_REF_TLS_MODEL (x))
  4158. + return false;
  4159. - if (!TARGET_GP_DIRECT
  4160. + /* If -mcmodel=large, the 'symbol_ref' is not a valid address
  4161. + during or after LRA/reload phase. */
  4162. + if (TARGET_CMODEL_LARGE
  4163. && (reload_completed
  4164. || reload_in_progress
  4165. || lra_in_progress))
  4166. return false;
  4167. -
  4168. - /* (mem (symbol_ref A)) => [symbol_ref] */
  4169. - return !currently_expanding_to_rtl;
  4170. -
  4171. - case CONST:
  4172. -
  4173. - if (!TARGET_GP_DIRECT
  4174. + /* If -mcmodel=medium and the symbol references to rodata section,
  4175. + the 'symbol_ref' is not a valid address during or after
  4176. + LRA/reload phase. */
  4177. + if (TARGET_CMODEL_MEDIUM
  4178. + && (NDS32_SYMBOL_REF_RODATA_P (x)
  4179. + || CONSTANT_POOL_ADDRESS_P (x))
  4180. && (reload_completed
  4181. || reload_in_progress
  4182. || lra_in_progress))
  4183. return false;
  4184. + return true;
  4185. +
  4186. + case CONST:
  4187. /* (mem (const (...)))
  4188. - => [ + const_addr ], where const_addr = symbol_ref + const_int */
  4189. + => [ + const_addr ], where const_addr = symbol_ref + const_int */
  4190. if (GET_CODE (XEXP (x, 0)) == PLUS)
  4191. {
  4192. rtx plus_op = XEXP (x, 0);
  4193. @@ -2348,18 +2809,43 @@
  4194. rtx op1 = XEXP (plus_op, 1);
  4195. if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
  4196. - return true;
  4197. - else
  4198. - return false;
  4199. + {
  4200. + /* Now we see the [ + const_addr ] pattern, but we need
  4201. + some further checking. */
  4202. +
  4203. + if (flag_pic)
  4204. + return false;
  4205. +
  4206. + /* If -mcmodel=large, the 'const_addr' is not a valid address
  4207. + during or after LRA/reload phase. */
  4208. + if (TARGET_CMODEL_LARGE
  4209. + && (reload_completed
  4210. + || reload_in_progress
  4211. + || lra_in_progress))
  4212. + return false;
  4213. + /* If -mcmodel=medium and the symbol references to rodata section,
  4214. + the 'const_addr' is not a valid address during or after
  4215. + LRA/reload phase. */
  4216. + if (TARGET_CMODEL_MEDIUM
  4217. + && NDS32_SYMBOL_REF_RODATA_P (op0)
  4218. + && (reload_completed
  4219. + || reload_in_progress
  4220. + || lra_in_progress))
  4221. + return false;
  4222. +
  4223. + /* At this point we can make sure 'const_addr' is a
  4224. + valid address. */
  4225. + return true;
  4226. + }
  4227. }
  4228. return false;
  4229. case POST_MODIFY:
  4230. /* (mem (post_modify (reg) (plus (reg) (reg))))
  4231. - => [Ra], Rb */
  4232. + => [Ra], Rb */
  4233. /* (mem (post_modify (reg) (plus (reg) (const_int))))
  4234. - => [Ra], const_int */
  4235. + => [Ra], const_int */
  4236. if (GET_CODE (XEXP (x, 0)) == REG
  4237. && GET_CODE (XEXP (x, 1)) == PLUS)
  4238. {
  4239. @@ -2382,7 +2868,7 @@
  4240. /* (mem (post_inc reg)) => [Ra], 1/2/4 */
  4241. /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
  4242. /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
  4243. - We only need to deal with register Ra. */
  4244. + We only need to deal with register Ra. */
  4245. if (nds32_address_register_rtx_p (XEXP (x, 0), strict))
  4246. return true;
  4247. else
  4248. @@ -2390,11 +2876,11 @@
  4249. case PLUS:
  4250. /* (mem (plus reg const_int))
  4251. - => [Ra + imm] */
  4252. + => [Ra + imm] */
  4253. /* (mem (plus reg reg))
  4254. - => [Ra + Rb] */
  4255. + => [Ra + Rb] */
  4256. /* (mem (plus (mult reg const_int) reg))
  4257. - => [Ra + Rb << sv] */
  4258. + => [Ra + Rb << sv] */
  4259. if (nds32_address_register_rtx_p (XEXP (x, 0), strict)
  4260. && nds32_legitimate_index_p (mode, XEXP (x, 1), strict))
  4261. return true;
  4262. @@ -2405,245 +2891,450 @@
  4263. return false;
  4264. case LO_SUM:
  4265. - if (!TARGET_GP_DIRECT)
  4266. - return true;
  4267. + /* (mem (lo_sum (reg) (symbol_ref))) */
  4268. + /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */
  4269. + /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */
  4270. + /* The LO_SUM is a valid address if and only if we would like to
  4271. + generate 32-bit full address memory access with any of following
  4272. + circumstance:
  4273. + 1. -mcmodel=large.
  4274. + 2. -mcmodel=medium and the symbol_ref references to rodata. */
  4275. + {
  4276. + rtx sym = NULL_RTX;
  4277. +
  4278. + if (flag_pic)
  4279. + return false;
  4280. +
  4281. + if (!REG_P (XEXP (x, 0)))
  4282. + return false;
  4283. +
  4284. + if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
  4285. + sym = XEXP (x, 1);
  4286. + else if (GET_CODE (XEXP (x, 1)) == CONST)
  4287. + {
  4288. + rtx plus = XEXP(XEXP (x, 1), 0);
  4289. + if (GET_CODE (plus) == PLUS)
  4290. + sym = XEXP (plus, 0);
  4291. + else if (GET_CODE (plus) == UNSPEC)
  4292. + sym = XEXP(XEXP (plus, 0), 0);
  4293. + }
  4294. + else
  4295. + return false;
  4296. +
  4297. + gcc_assert (GET_CODE (sym) == SYMBOL_REF);
  4298. +
  4299. + if (TARGET_CMODEL_LARGE)
  4300. + return true;
  4301. + else if (TARGET_CMODEL_MEDIUM
  4302. + && NDS32_SYMBOL_REF_RODATA_P (sym))
  4303. + return true;
  4304. + else
  4305. + return false;
  4306. + }
  4307. default:
  4308. return false;
  4309. }
  4310. }
  4311. -
  4312. -/* Describing Relative Costs of Operations. */
  4313. +/* Convert a non-PIC address in `x' to a PIC address using @GOT or
  4314. + @GOTOFF.
  4315. -static int nds32_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
  4316. - reg_class_t from,
  4317. - reg_class_t to)
  4318. + Example for @GOTOFF:
  4319. + lw $r0, symbol@GOTOFF
  4320. + -> sethi $ta, hi20(symbol@GOTOFF)
  4321. + ori $ta, $ta, lo12(symbol@GOTOFF)
  4322. + lw $r0, [$ta + $gp]
  4323. +
  4324. + Example for @GOT:
  4325. + lw $r0, symbol@GOT
  4326. + -> sethi $ta, hi20(symbol@GOT)
  4327. + ori $ta, $ta, lo12(symbol@GOT)
  4328. + lw $ta, [$ta + $gp]
  4329. + lw $r0, [$ta] */
  4330. +static rtx
  4331. +nds32_legitimize_pic_address (rtx x)
  4332. {
  4333. - if (from == HIGH_REGS || to == HIGH_REGS)
  4334. - return 6;
  4335. + rtx addr = x;
  4336. + rtx reg = gen_reg_rtx (Pmode);
  4337. - return 2;
  4338. + if (GET_CODE (x) == LABEL_REF
  4339. + || (GET_CODE (x) == SYMBOL_REF
  4340. + && (CONSTANT_POOL_ADDRESS_P (x)
  4341. + || SYMBOL_REF_LOCAL_P (x))))
  4342. + {
  4343. + addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOTOFF);
  4344. + addr = gen_rtx_CONST (SImode, addr);
  4345. + emit_insn (gen_sethi (reg, addr));
  4346. + emit_insn (gen_lo_sum (reg, reg, addr));
  4347. + x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, reg);
  4348. + }
  4349. + else if (GET_CODE (x) == SYMBOL_REF)
  4350. + {
  4351. + addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOT);
  4352. + addr = gen_rtx_CONST (SImode, addr);
  4353. + emit_insn (gen_sethi (reg, addr));
  4354. + emit_insn (gen_lo_sum (reg, reg, addr));
  4355. +
  4356. + /* lw $ta, [$ta + $gp] */
  4357. + rtx got_addr = gen_frame_mem (SImode, gen_rtx_PLUS (Pmode,
  4358. + pic_offset_table_rtx,
  4359. + reg));
  4360. + emit_move_insn (reg, got_addr);
  4361. + x = reg;
  4362. + }
  4363. + else if (GET_CODE (x) == CONST)
  4364. + {
  4365. + addr = XEXP (x, 0);
  4366. + gcc_assert (GET_CODE (addr) == PLUS);
  4367. +
  4368. + rtx op0 = XEXP (addr, 0);
  4369. + rtx op1 = XEXP (addr, 1);
  4370. +
  4371. + if ((GET_CODE (op0) == LABEL_REF
  4372. + || (GET_CODE (op0) == SYMBOL_REF
  4373. + && (CONSTANT_POOL_ADDRESS_P (op0)
  4374. + || SYMBOL_REF_LOCAL_P (op0))))
  4375. + && GET_CODE (op1) == CONST_INT)
  4376. + {
  4377. + addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF);
  4378. + addr = gen_rtx_CONST (Pmode, addr);
  4379. + emit_insn (gen_sethi (reg, addr));
  4380. + emit_insn (gen_lo_sum (reg, reg, addr));
  4381. + emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
  4382. + emit_insn (gen_addsi3 (reg, reg, op1));
  4383. + x = reg;
  4384. + }
  4385. + else if (GET_CODE (op0) == SYMBOL_REF
  4386. + && GET_CODE (op1) == CONST_INT)
  4387. + {
  4388. + /* This is a constant offset from a @GOT symbol reference. */
  4389. + addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT);
  4390. + addr = gen_rtx_CONST (SImode, addr);
  4391. + emit_insn (gen_sethi (reg, addr));
  4392. + emit_insn (gen_lo_sum (reg, reg, addr));
  4393. +
  4394. + /* lw $ta, [$ta + $gp] */
  4395. + rtx got_addr = gen_frame_mem (SImode,
  4396. + gen_rtx_PLUS (Pmode,
  4397. + pic_offset_table_rtx,
  4398. + reg));
  4399. + emit_move_insn (reg, got_addr);
  4400. + emit_insn (gen_addsi3 (reg, reg, op1));
  4401. + x = reg;
  4402. + }
  4403. + else
  4404. + {
  4405. + /* Don't handle this pattern. */
  4406. + debug_rtx (x);
  4407. + gcc_unreachable ();
  4408. + }
  4409. + }
  4410. + return x;
  4411. }
  4412. -static int nds32_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
  4413. - reg_class_t rclass ATTRIBUTE_UNUSED,
  4414. - bool in ATTRIBUTE_UNUSED)
  4415. -{
  4416. - return 8;
  4417. +static rtx
  4418. +nds32_legitimize_address (rtx x,
  4419. + rtx oldx ATTRIBUTE_UNUSED,
  4420. + enum machine_mode mode ATTRIBUTE_UNUSED)
  4421. +{
  4422. + if (nds32_tls_referenced_p (x))
  4423. + x = nds32_legitimize_tls_address (x);
  4424. + else if (flag_pic && SYMBOLIC_CONST_P (x))
  4425. + x = nds32_legitimize_pic_address (x);
  4426. +
  4427. + return x;
  4428. }
  4429. -/* This target hook describes the relative costs of RTL expressions.
  4430. - Return 'true' when all subexpressions of x have been processed.
  4431. - Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
  4432. - Refer to gcc/rtlanal.c for more information. */
  4433. static bool
  4434. -nds32_rtx_costs (rtx x,
  4435. - int code,
  4436. - int outer_code,
  4437. - int opno ATTRIBUTE_UNUSED,
  4438. - int *total,
  4439. - bool speed)
  4440. +nds32_legitimate_constant_p (enum machine_mode mode, rtx x)
  4441. {
  4442. - /* According to 'speed', goto suitable cost model section. */
  4443. - if (speed)
  4444. - goto performance_cost;
  4445. - else
  4446. - goto size_cost;
  4447. -
  4448. -
  4449. -performance_cost:
  4450. - /* This is section for performance cost model. */
  4451. -
  4452. - /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
  4453. - We treat it as 4-cycle cost for each instruction
  4454. - under performance consideration. */
  4455. - switch (code)
  4456. + switch (GET_CODE (x))
  4457. {
  4458. - case SET:
  4459. - /* For 'SET' rtx, we need to return false
  4460. - so that it can recursively calculate costs. */
  4461. - return false;
  4462. -
  4463. - case USE:
  4464. - /* Used in combine.c as a marker. */
  4465. - *total = 0;
  4466. + case CONST_DOUBLE:
  4467. + if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  4468. + && (mode == DFmode || mode == SFmode))
  4469. + return false;
  4470. break;
  4471. + case CONST:
  4472. + x = XEXP (x, 0);
  4473. - case MULT:
  4474. - *total = COSTS_N_INSNS (1);
  4475. - break;
  4476. + if (GET_CODE (x) == PLUS)
  4477. + {
  4478. + if (! CONST_INT_P (XEXP (x, 1)))
  4479. + return false;
  4480. + x = XEXP (x, 0);
  4481. + }
  4482. - case DIV:
  4483. - case UDIV:
  4484. - case MOD:
  4485. - case UMOD:
  4486. - *total = COSTS_N_INSNS (7);
  4487. + if (GET_CODE (x) == UNSPEC)
  4488. + {
  4489. + switch (XINT (x, 1))
  4490. + {
  4491. + case UNSPEC_GOT:
  4492. + case UNSPEC_GOTOFF:
  4493. + case UNSPEC_PLT:
  4494. + case UNSPEC_TLSGD:
  4495. + case UNSPEC_TLSLD:
  4496. + case UNSPEC_TLSIE:
  4497. + case UNSPEC_TLSLE:
  4498. + return false;
  4499. + default:
  4500. + return true;
  4501. + }
  4502. + }
  4503. break;
  4504. -
  4505. - default:
  4506. - *total = COSTS_N_INSNS (1);
  4507. + case SYMBOL_REF:
  4508. + /* TLS symbols need a call to resolve in
  4509. + precompute_register_parameters. */
  4510. + if (SYMBOL_REF_TLS_MODEL (x))
  4511. + return false;
  4512. break;
  4513. + default:
  4514. + return true;
  4515. }
  4516. return true;
  4517. +}
  4518. +/* Reorgnize the UNSPEC CONST and return its direct symbol. */
  4519. +static rtx
  4520. +nds32_delegitimize_address (rtx x)
  4521. +{
  4522. + x = delegitimize_mem_from_attrs (x);
  4523. -size_cost:
  4524. - /* This is section for size cost model. */
  4525. -
  4526. - /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
  4527. - We treat it as 4-byte cost for each instruction
  4528. - under code size consideration. */
  4529. - switch (code)
  4530. + if (GET_CODE(x) == CONST)
  4531. {
  4532. - case SET:
  4533. - /* For 'SET' rtx, we need to return false
  4534. - so that it can recursively calculate costs. */
  4535. - return false;
  4536. + rtx inner = XEXP (x, 0);
  4537. - case USE:
  4538. - /* Used in combine.c as a marker. */
  4539. - *total = 0;
  4540. - break;
  4541. + /* Handle for GOTOFF. */
  4542. + if (GET_CODE (inner) == PLUS)
  4543. + inner = XEXP (inner, 0);
  4544. - case CONST_INT:
  4545. - /* All instructions involving constant operation
  4546. - need to be considered for cost evaluation. */
  4547. - if (outer_code == SET)
  4548. - {
  4549. - /* (set X imm5s), use movi55, 2-byte cost.
  4550. - (set X imm20s), use movi, 4-byte cost.
  4551. - (set X BIG_INT), use sethi/ori, 8-byte cost. */
  4552. - if (satisfies_constraint_Is05 (x))
  4553. - *total = COSTS_N_INSNS (1) - 2;
  4554. - else if (satisfies_constraint_Is20 (x))
  4555. - *total = COSTS_N_INSNS (1);
  4556. - else
  4557. - *total = COSTS_N_INSNS (2);
  4558. - }
  4559. - else if (outer_code == PLUS || outer_code == MINUS)
  4560. - {
  4561. - /* Possible addi333/subi333 or subi45/addi45, 2-byte cost.
  4562. - General case, cost 1 instruction with 4-byte. */
  4563. - if (satisfies_constraint_Iu05 (x))
  4564. - *total = COSTS_N_INSNS (1) - 2;
  4565. - else
  4566. - *total = COSTS_N_INSNS (1);
  4567. - }
  4568. - else if (outer_code == ASHIFT)
  4569. + if (GET_CODE (inner) == UNSPEC)
  4570. {
  4571. - /* Possible slli333, 2-byte cost.
  4572. - General case, cost 1 instruction with 4-byte. */
  4573. - if (satisfies_constraint_Iu03 (x))
  4574. - *total = COSTS_N_INSNS (1) - 2;
  4575. - else
  4576. - *total = COSTS_N_INSNS (1);
  4577. - }
  4578. - else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
  4579. - {
  4580. - /* Possible srai45 or srli45, 2-byte cost.
  4581. - General case, cost 1 instruction with 4-byte. */
  4582. - if (satisfies_constraint_Iu05 (x))
  4583. - *total = COSTS_N_INSNS (1) - 2;
  4584. - else
  4585. - *total = COSTS_N_INSNS (1);
  4586. + switch (XINT (inner, 1))
  4587. + {
  4588. + case UNSPEC_GOTINIT:
  4589. + case UNSPEC_GOT:
  4590. + case UNSPEC_GOTOFF:
  4591. + case UNSPEC_PLT:
  4592. + case UNSPEC_TLSGD:
  4593. + case UNSPEC_TLSLD:
  4594. + case UNSPEC_TLSIE:
  4595. + case UNSPEC_TLSLE:
  4596. + x = XVECEXP (inner, 0, 0);
  4597. + break;
  4598. + default:
  4599. + break;
  4600. + }
  4601. }
  4602. - else
  4603. + }
  4604. + return x;
  4605. +}
  4606. +
  4607. +static enum machine_mode
  4608. +nds32_vectorize_preferred_simd_mode (enum machine_mode mode)
  4609. +{
  4610. + if (!NDS32_EXT_DSP_P ())
  4611. + return word_mode;
  4612. +
  4613. + switch (mode)
  4614. + {
  4615. + case QImode:
  4616. + return V4QImode;
  4617. + case HImode:
  4618. + return V2HImode;
  4619. + default:
  4620. + return word_mode;
  4621. + }
  4622. +}
  4623. +
  4624. +static bool
  4625. +nds32_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
  4626. +{
  4627. + switch (GET_CODE (x))
  4628. + {
  4629. + case CONST:
  4630. + x = XEXP (x, 0);
  4631. + if (GET_CODE (x) == UNSPEC)
  4632. {
  4633. - /* For other cases, simply set it 4-byte cost. */
  4634. - *total = COSTS_N_INSNS (1);
  4635. + switch (XINT (x, 1))
  4636. + {
  4637. + case UNSPEC_GOT:
  4638. + case UNSPEC_GOTOFF:
  4639. + case UNSPEC_PLT:
  4640. + case UNSPEC_TLSGD:
  4641. + case UNSPEC_TLSLD:
  4642. + case UNSPEC_TLSIE:
  4643. + case UNSPEC_TLSLE:
  4644. + return true;
  4645. + default:
  4646. + return false;
  4647. + }
  4648. }
  4649. break;
  4650. -
  4651. - case CONST_DOUBLE:
  4652. - /* It requires high part and low part processing, set it 8-byte cost. */
  4653. - *total = COSTS_N_INSNS (2);
  4654. + case SYMBOL_REF:
  4655. + /* We don't want to force symbol as constant pool in .text section,
  4656. + because we use the gp-relatived instruction to load in small
  4657. + or medium model. */
  4658. + if (SYMBOL_REF_TLS_MODEL (x)
  4659. + || TARGET_CMODEL_SMALL
  4660. + || TARGET_CMODEL_MEDIUM)
  4661. + return true;
  4662. break;
  4663. -
  4664. default:
  4665. - /* For other cases, generally we set it 4-byte cost
  4666. - and stop resurively traversing. */
  4667. - *total = COSTS_N_INSNS (1);
  4668. - break;
  4669. + return false;
  4670. }
  4671. + return false;
  4672. +}
  4673. - return true;
  4674. +
  4675. +/* Condition Code Status. */
  4676. +
  4677. +/* -- Representation of condition codes using registers. */
  4678. +
  4679. +static void
  4680. +nds32_canonicalize_comparison (int *code,
  4681. + rtx *op0 ATTRIBUTE_UNUSED,
  4682. + rtx *op1,
  4683. + bool op0_preserve_value ATTRIBUTE_UNUSED)
  4684. +{
  4685. + /* When the instruction combination pass tries to combine a comparison insn
  4686. + with its previous insns, it also transforms the operator in order to
  4687. + minimize its constant field. For example, it tries to transform a
  4688. + comparison insn from
  4689. + (set (reg:SI 54)
  4690. + (ltu:SI (reg:SI 52)
  4691. + (const_int 10 [0xa])))
  4692. + to
  4693. + (set (reg:SI 54)
  4694. + (leu:SI (reg:SI 52)
  4695. + (const_int 9 [0x9])))
  4696. +
  4697. + However, the nds32 target only provides instructions supporting the LTU
  4698. + operation directly, and the implementation of the pattern "cbranchsi4"
  4699. + only expands the LTU form. In order to handle the non-LTU operations
  4700. + generated from passes other than the RTL expansion pass, we have to
  4701. + implement this hook to revert those changes. Since we only expand the LTU
  4702. + operator in the RTL expansion pass, we might only need to handle the LEU
  4703. + case, unless we find other optimization passes perform more aggressive
  4704. + transformations. */
  4705. +
  4706. + if (*code == LEU && CONST_INT_P (*op1))
  4707. + {
  4708. + *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode);
  4709. + *code = LTU;
  4710. + }
  4711. +}
  4712. +
  4713. +
  4714. +/* Describing Relative Costs of Operations. */
  4715. +
  4716. +static int
  4717. +nds32_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
  4718. + reg_class_t from,
  4719. + reg_class_t to)
  4720. +{
  4721. + if ((from == FP_REGS && to != FP_REGS)
  4722. + || (from != FP_REGS && to == FP_REGS))
  4723. + return 9;
  4724. + else if (from == HIGH_REGS || to == HIGH_REGS)
  4725. + return optimize_size ? 6 : 2;
  4726. + else
  4727. + return 2;
  4728. }
  4729. -static int nds32_address_cost (rtx address,
  4730. - enum machine_mode mode ATTRIBUTE_UNUSED,
  4731. - addr_space_t as ATTRIBUTE_UNUSED,
  4732. - bool speed)
  4733. -{
  4734. - rtx plus0, plus1;
  4735. - enum rtx_code code;
  4736. -
  4737. - code = GET_CODE (address);
  4738. -
  4739. - /* According to 'speed', goto suitable cost model section. */
  4740. - if (speed)
  4741. - goto performance_cost;
  4742. +static int
  4743. +nds32_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
  4744. + reg_class_t rclass ATTRIBUTE_UNUSED,
  4745. + bool in ATTRIBUTE_UNUSED)
  4746. +{
  4747. + /* Memory access is only need 1 cycle in our low-end processor,
  4748. + however memory access is most 4-byte instruction,
  4749. + so let it 8 for optimize_size, otherwise be 2. */
  4750. + if (nds32_memory_model_option == MEMORY_MODEL_FAST)
  4751. + return optimize_size ? 8 : 4;
  4752. else
  4753. - goto size_cost;
  4754. + return 8;
  4755. +}
  4756. +
  4757. +/* This target hook describes the relative costs of RTL expressions.
  4758. + Return 'true' when all subexpressions of x have been processed.
  4759. + Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
  4760. + Refer to gcc/rtlanal.c for more information. */
  4761. +static bool
  4762. +nds32_rtx_costs (rtx x,
  4763. + int code,
  4764. + int outer_code,
  4765. + int opno,
  4766. + int *total,
  4767. + bool speed)
  4768. +{
  4769. + return nds32_rtx_costs_impl (x, code, outer_code, opno, total, speed);
  4770. +}
  4771. -performance_cost:
  4772. - /* This is section for performance cost model. */
  4773. +static int
  4774. +nds32_address_cost (rtx address,
  4775. + enum machine_mode mode,
  4776. + addr_space_t as,
  4777. + bool speed)
  4778. +{
  4779. + return nds32_address_cost_impl (address, mode, as, speed);
  4780. +}
  4781. - /* FALLTHRU, currently we use same cost model as size_cost. */
  4782. +
  4783. +/* Adjusting the Instruction Scheduler. */
  4784. -size_cost:
  4785. - /* This is section for size cost model. */
  4786. +static int
  4787. +nds32_sched_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
  4788. +{
  4789. + if (REG_NOTE_KIND (link) == REG_DEP_ANTI
  4790. + || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
  4791. + return 0;
  4792. - switch (code)
  4793. - {
  4794. - case POST_MODIFY:
  4795. - case POST_INC:
  4796. - case POST_DEC:
  4797. - /* We encourage that rtx contains
  4798. - POST_MODIFY/POST_INC/POST_DEC behavior. */
  4799. - return 0;
  4800. + if (INSN_CODE (insn) < 0 || INSN_CODE (dep) < 0)
  4801. + return cost;
  4802. - case SYMBOL_REF:
  4803. - /* We can have gp-relative load/store for symbol_ref.
  4804. - Have it 4-byte cost. */
  4805. - return COSTS_N_INSNS (1);
  4806. + return cost;
  4807. +}
  4808. - case CONST:
  4809. - /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
  4810. - Have it 4-byte cost. */
  4811. - return COSTS_N_INSNS (1);
  4812. +
  4813. +/* Dividing the Output into Sections (Texts, Data, . . . ). */
  4814. - case REG:
  4815. - /* Simply return 4-byte costs. */
  4816. - return COSTS_N_INSNS (1);
  4817. +/* If references to a symbol or a constant must be treated differently
  4818. + depending on something about the variable or function named by the symbol
  4819. + (such as what section it is in), we use this hook to store flags
  4820. + in symbol_ref rtx. */
  4821. +static void
  4822. +nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p)
  4823. +{
  4824. + default_encode_section_info (decl, rtl, new_decl_p);
  4825. - case PLUS:
  4826. - /* We do not need to check if the address is a legitimate address,
  4827. - because this hook is never called with an invalid address.
  4828. - But we better check the range of
  4829. - const_int value for cost, if it exists. */
  4830. - plus0 = XEXP (address, 0);
  4831. - plus1 = XEXP (address, 1);
  4832. -
  4833. - if (REG_P (plus0) && CONST_INT_P (plus1))
  4834. - {
  4835. - /* If it is possible to be lwi333/swi333 form,
  4836. - make it 2-byte cost. */
  4837. - if (satisfies_constraint_Iu05 (plus1))
  4838. - return (COSTS_N_INSNS (1) - 2);
  4839. - else
  4840. - return COSTS_N_INSNS (1);
  4841. - }
  4842. + /* For the memory rtx, if it references to rodata section, we can store
  4843. + NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the
  4844. + nds32_legitimate_address_p() can determine how to treat such symbol_ref
  4845. + based on -mcmodel=X and this information. */
  4846. + if (MEM_P (rtl) && MEM_READONLY_P (rtl))
  4847. + {
  4848. + rtx addr = XEXP (rtl, 0);
  4849. - /* For other 'plus' situation, make it cost 4-byte. */
  4850. - return COSTS_N_INSNS (1);
  4851. + if (GET_CODE (addr) == SYMBOL_REF)
  4852. + {
  4853. + /* For (mem (symbol_ref X)) case. */
  4854. + SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA;
  4855. + }
  4856. + else if (GET_CODE (addr) == CONST
  4857. + && GET_CODE (XEXP (addr, 0)) == PLUS)
  4858. + {
  4859. + /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */
  4860. + rtx plus_op = XEXP (addr, 0);
  4861. + rtx op0 = XEXP (plus_op, 0);
  4862. + rtx op1 = XEXP (plus_op, 1);
  4863. - default:
  4864. - break;
  4865. + if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
  4866. + SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA;
  4867. + }
  4868. }
  4869. -
  4870. - return COSTS_N_INSNS (4);
  4871. }
  4872. @@ -2654,33 +3345,50 @@
  4873. static void
  4874. nds32_asm_file_start (void)
  4875. {
  4876. - int i;
  4877. -
  4878. default_file_start ();
  4879. + if (flag_pic)
  4880. + fprintf (asm_out_file, "\t.pic\n");
  4881. +
  4882. /* Tell assembler which ABI we are using. */
  4883. fprintf (asm_out_file, "\t! ABI version\n");
  4884. - fprintf (asm_out_file, "\t.abi_2\n");
  4885. + if (TARGET_HARD_FLOAT)
  4886. + fprintf (asm_out_file, "\t.abi_2fp_plus\n");
  4887. + else
  4888. + fprintf (asm_out_file, "\t.abi_2\n");
  4889. /* Tell assembler that this asm code is generated by compiler. */
  4890. fprintf (asm_out_file, "\t! This asm file is generated by compiler\n");
  4891. fprintf (asm_out_file, "\t.flag\tverbatim\n");
  4892. - /* Give assembler the size of each vector for interrupt handler. */
  4893. - fprintf (asm_out_file, "\t! This vector size directive is required "
  4894. - "for checking inconsistency on interrupt handler\n");
  4895. - fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size);
  4896. +
  4897. + /* We need to provide the size of each vector for interrupt handler
  4898. + under elf toolchain. */
  4899. + if (!TARGET_LINUX_ABI)
  4900. + {
  4901. + fprintf (asm_out_file, "\t! This vector size directive is required "
  4902. + "for checking inconsistency on interrupt handler\n");
  4903. + fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size);
  4904. + }
  4905. /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
  4906. the compiler may produce 'la $fp,_FP_BASE_' instruction
  4907. at prologue for fp-as-gp optimization.
  4908. We should emit weak reference of _FP_BASE_ to avoid undefined reference
  4909. in case user does not pass '--relax' option to linker. */
  4910. - if (TARGET_FORCE_FP_AS_GP || optimize_size)
  4911. + if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size))
  4912. {
  4913. fprintf (asm_out_file, "\t! This weak reference is required to do "
  4914. "fp-as-gp link time optimization\n");
  4915. fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n");
  4916. }
  4917. + /* If user enables '-mifc', we should emit relaxation directive
  4918. + to tell linker that this file is allowed to do ifc optimization. */
  4919. + if (TARGET_IFC)
  4920. + {
  4921. + fprintf (asm_out_file, "\t! This relaxation directive is required "
  4922. + "to do ifc link time optimization\n");
  4923. + fprintf (asm_out_file, "\t.relax\tifc\n");
  4924. + }
  4925. /* If user enables '-mex9', we should emit relaxation directive
  4926. to tell linker that this file is allowed to do ex9 optimization. */
  4927. if (TARGET_EX9)
  4928. @@ -2699,9 +3407,34 @@
  4929. if (TARGET_ISA_V3M)
  4930. fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M");
  4931. + if (TARGET_PIPELINE_N8)
  4932. + fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8");
  4933. + if (TARGET_PIPELINE_N10)
  4934. + fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10");
  4935. + if (TARGET_PIPELINE_N12)
  4936. + fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N12");
  4937. + if (TARGET_PIPELINE_SIMPLE)
  4938. + fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE");
  4939. +
  4940. + if (TARGET_CMODEL_SMALL)
  4941. + fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL");
  4942. + if (TARGET_CMODEL_MEDIUM)
  4943. + fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM");
  4944. + if (TARGET_CMODEL_LARGE)
  4945. + fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE");
  4946. +
  4947. fprintf (asm_out_file, "\t! Endian setting\t: %s\n",
  4948. ((TARGET_BIG_ENDIAN) ? "big-endian"
  4949. : "little-endian"));
  4950. + fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n",
  4951. + ((TARGET_FPU_SINGLE) ? "Yes"
  4952. + : "No"));
  4953. + fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n",
  4954. + ((TARGET_FPU_DOUBLE) ? "Yes"
  4955. + : "No"));
  4956. + fprintf (asm_out_file, "\t! ABI version\t\t: %s\n",
  4957. + ((TARGET_HARD_FLOAT) ? "ABI2FP+"
  4958. + : "ABI2"));
  4959. fprintf (asm_out_file, "\t! ------------------------------------\n");
  4960. @@ -2709,8 +3442,14 @@
  4961. ((TARGET_CMOV) ? "Yes"
  4962. : "No"));
  4963. fprintf (asm_out_file, "\t! Use performance extension\t: %s\n",
  4964. - ((TARGET_PERF_EXT) ? "Yes"
  4965. + ((TARGET_EXT_PERF) ? "Yes"
  4966. : "No"));
  4967. + fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n",
  4968. + ((TARGET_EXT_PERF2) ? "Yes"
  4969. + : "No"));
  4970. + fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n",
  4971. + ((TARGET_EXT_STRING) ? "Yes"
  4972. + : "No"));
  4973. fprintf (asm_out_file, "\t! ------------------------------------\n");
  4974. @@ -2720,9 +3459,6 @@
  4975. fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n",
  4976. ((TARGET_16_BIT) ? "Yes"
  4977. : "No"));
  4978. - fprintf (asm_out_file, "\t! GP base access\t: %s\n",
  4979. - ((TARGET_GP_DIRECT) ? "Yes"
  4980. - : "No"));
  4981. fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n",
  4982. ((TARGET_REDUCED_REGS) ? "Yes"
  4983. : "No"));
  4984. @@ -2731,6 +3467,10 @@
  4985. if (optimize_size)
  4986. fprintf (asm_out_file, "\t! Optimization level\t: -Os\n");
  4987. + else if (optimize_fast)
  4988. + fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n");
  4989. + else if (optimize_debug)
  4990. + fprintf (asm_out_file, "\t! Optimization level\t: -Og\n");
  4991. else
  4992. fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize);
  4993. @@ -2741,63 +3481,61 @@
  4994. fprintf (asm_out_file, "\t! ------------------------------------\n");
  4995. - /* Initialize isr vector information array before compiling functions. */
  4996. - for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
  4997. - {
  4998. - nds32_isr_vectors[i].category = NDS32_ISR_NONE;
  4999. - strcpy (nds32_isr_vectors[i].func_name, "");
  5000. - nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE;
  5001. - nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED;
  5002. - nds32_isr_vectors[i].total_n_vectors = 0;
  5003. - strcpy (nds32_isr_vectors[i].nmi_name, "");
  5004. - strcpy (nds32_isr_vectors[i].warm_name, "");
  5005. - }
  5006. + nds32_asm_file_start_for_isr ();
  5007. }
  5008. static void
  5009. nds32_asm_file_end (void)
  5010. {
  5011. - int i;
  5012. -
  5013. - /* If all the vectors are NDS32_ISR_NONE, we can return immediately. */
  5014. - for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
  5015. - if (nds32_isr_vectors[i].category != NDS32_ISR_NONE)
  5016. - break;
  5017. -
  5018. - if (i == NDS32_N_ISR_VECTORS)
  5019. - return;
  5020. -
  5021. - /* At least one vector is NOT NDS32_ISR_NONE,
  5022. - we should output isr vector information. */
  5023. - fprintf (asm_out_file, "\t! ------------------------------------\n");
  5024. - fprintf (asm_out_file, "\t! The isr vector information:\n");
  5025. + nds32_asm_file_end_for_isr ();
  5026. fprintf (asm_out_file, "\t! ------------------------------------\n");
  5027. +}
  5028. - /* Check reset handler first. Its vector number is always 0. */
  5029. - if (nds32_isr_vectors[0].category == NDS32_ISR_RESET)
  5030. +static bool
  5031. +nds32_asm_output_addr_const_extra (FILE *file, rtx x)
  5032. +{
  5033. + if (GET_CODE (x) == UNSPEC)
  5034. {
  5035. - nds32_emit_isr_reset_content ();
  5036. - fprintf (asm_out_file, "\t! ------------------------------------\n");
  5037. - }
  5038. -
  5039. - /* Check other vectors, starting from vector number 1. */
  5040. - for (i = 1; i < NDS32_N_ISR_VECTORS; i++)
  5041. - {
  5042. - if (nds32_isr_vectors[i].category == NDS32_ISR_INTERRUPT
  5043. - || nds32_isr_vectors[i].category == NDS32_ISR_EXCEPTION)
  5044. - {
  5045. - /* Found one vector which is interupt or exception.
  5046. - Output its jmptbl and vector section content. */
  5047. - fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i);
  5048. - fprintf (asm_out_file, "\t! ------------------------------------\n");
  5049. - nds32_emit_isr_jmptbl_section (i);
  5050. - fprintf (asm_out_file, "\t! ....................................\n");
  5051. - nds32_emit_isr_vector_section (i);
  5052. - fprintf (asm_out_file, "\t! ------------------------------------\n");
  5053. + switch (XINT (x, 1))
  5054. + {
  5055. + case UNSPEC_GOTINIT:
  5056. + output_addr_const (file, XVECEXP (x, 0, 0));
  5057. + break;
  5058. + case UNSPEC_GOTOFF:
  5059. + output_addr_const (file, XVECEXP (x, 0, 0));
  5060. + fputs ("@GOTOFF", file);
  5061. + break;
  5062. + case UNSPEC_GOT:
  5063. + output_addr_const (file, XVECEXP (x, 0, 0));
  5064. + fputs ("@GOT", file);
  5065. + break;
  5066. + case UNSPEC_PLT:
  5067. + output_addr_const (file, XVECEXP (x, 0, 0));
  5068. + fputs ("@PLT", file);
  5069. + break;
  5070. + case UNSPEC_TLSGD:
  5071. + output_addr_const (file, XVECEXP (x, 0, 0));
  5072. + fputs ("@TLSDESC", file);
  5073. + break;
  5074. + case UNSPEC_TLSLD:
  5075. + output_addr_const (file, XVECEXP (x, 0, 0));
  5076. + fputs ("@TLSDESC", file);
  5077. + break;
  5078. + case UNSPEC_TLSIE:
  5079. + output_addr_const (file, XVECEXP (x, 0, 0));
  5080. + fputs ("@GOTTPOFF", file);
  5081. + break;
  5082. + case UNSPEC_TLSLE:
  5083. + output_addr_const (file, XVECEXP (x, 0, 0));
  5084. + fputs ("@TPOFF", file);
  5085. + break;
  5086. + default:
  5087. + return false;
  5088. }
  5089. + return true;
  5090. }
  5091. -
  5092. - fprintf (asm_out_file, "\t! ------------------------------------\n");
  5093. + else
  5094. + return false;
  5095. }
  5096. /* -- Output and Generation of Labels. */
  5097. @@ -2815,7 +3553,15 @@
  5098. static void
  5099. nds32_print_operand (FILE *stream, rtx x, int code)
  5100. {
  5101. - int op_value;
  5102. + HOST_WIDE_INT op_value = 0;
  5103. + HOST_WIDE_INT one_position;
  5104. + HOST_WIDE_INT zero_position;
  5105. + bool pick_lsb_p = false;
  5106. + bool pick_msb_p = false;
  5107. + int regno;
  5108. +
  5109. + if (CONST_INT_P (x))
  5110. + op_value = INTVAL (x);
  5111. switch (code)
  5112. {
  5113. @@ -2823,22 +3569,75 @@
  5114. /* Do nothing special. */
  5115. break;
  5116. + case 'b':
  5117. + /* Use exact_log2() to search the 0-bit position. */
  5118. + gcc_assert (CONST_INT_P (x));
  5119. + zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode));
  5120. + gcc_assert (zero_position != -1);
  5121. + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position);
  5122. +
  5123. + /* No need to handle following process, so return immediately. */
  5124. + return;
  5125. +
  5126. + case 'e':
  5127. + gcc_assert (MEM_P (x)
  5128. + && GET_CODE (XEXP (x, 0)) == PLUS
  5129. + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
  5130. + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1)));
  5131. +
  5132. + /* No need to handle following process, so return immediately. */
  5133. + return;
  5134. +
  5135. + case 'v':
  5136. + gcc_assert (CONST_INT_P (x)
  5137. + && (INTVAL (x) == 0
  5138. + || INTVAL (x) == 8
  5139. + || INTVAL (x) == 16
  5140. + || INTVAL (x) == 24));
  5141. + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
  5142. +
  5143. + /* No need to handle following process, so return immediately. */
  5144. + return;
  5145. +
  5146. + case 'B':
  5147. + /* Use exact_log2() to search the 1-bit position. */
  5148. + gcc_assert (CONST_INT_P (x));
  5149. + one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode));
  5150. + gcc_assert (one_position != -1);
  5151. + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position);
  5152. +
  5153. + /* No need to handle following process, so return immediately. */
  5154. + return;
  5155. +
  5156. + case 'L':
  5157. + /* X is supposed to be REG rtx. */
  5158. + gcc_assert (REG_P (x));
  5159. + /* Claim that we are going to pick LSB part of X. */
  5160. + pick_lsb_p = true;
  5161. + break;
  5162. +
  5163. + case 'H':
  5164. + /* X is supposed to be REG rtx. */
  5165. + gcc_assert (REG_P (x));
  5166. + /* Claim that we are going to pick MSB part of X. */
  5167. + pick_msb_p = true;
  5168. + break;
  5169. +
  5170. case 'V':
  5171. - /* 'x' is supposed to be CONST_INT, get the value. */
  5172. + /* X is supposed to be CONST_INT, get the value. */
  5173. gcc_assert (CONST_INT_P (x));
  5174. - op_value = INTVAL (x);
  5175. /* According to the Andes architecture,
  5176. - the system/user register index range is 0 ~ 1023.
  5177. - In order to avoid conflict between user-specified-integer value
  5178. - and enum-specified-register value,
  5179. - the 'enum nds32_intrinsic_registers' value
  5180. - in nds32_intrinsic.h starts from 1024. */
  5181. + the system/user register index range is 0 ~ 1023.
  5182. + In order to avoid conflict between user-specified-integer value
  5183. + and enum-specified-register value,
  5184. + the 'enum nds32_intrinsic_registers' value
  5185. + in nds32_intrinsic.h starts from 1024. */
  5186. if (op_value < 1024 && op_value >= 0)
  5187. {
  5188. /* If user gives integer value directly (0~1023),
  5189. we just print out the value. */
  5190. - fprintf (stream, "%d", op_value);
  5191. + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value);
  5192. }
  5193. else if (op_value < 0
  5194. || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names)
  5195. @@ -2858,6 +3657,45 @@
  5196. /* No need to handle following process, so return immediately. */
  5197. return;
  5198. + case 'R': /* cctl valck */
  5199. + /* Note the cctl divide to 5 group and share the same name table. */
  5200. + if (op_value < 0 || op_value > 4)
  5201. + error ("CCTL intrinsic function subtype out of range!");
  5202. + fprintf (stream, "%s", nds32_cctl_names[op_value]);
  5203. + return;
  5204. +
  5205. + case 'T': /* cctl idxwbinv */
  5206. + /* Note the cctl divide to 5 group and share the same name table. */
  5207. + if (op_value < 0 || op_value > 4)
  5208. + error ("CCTL intrinsic function subtype out of range!");
  5209. + fprintf (stream, "%s", nds32_cctl_names[op_value + 4]);
  5210. + return;
  5211. +
  5212. + case 'U': /* cctl vawbinv */
  5213. + /* Note the cctl divide to 5 group and share the same name table. */
  5214. + if (op_value < 0 || op_value > 4)
  5215. + error ("CCTL intrinsic function subtype out of range!");
  5216. + fprintf (stream, "%s", nds32_cctl_names[op_value + 8]);
  5217. + return;
  5218. +
  5219. + case 'X': /* cctl idxread */
  5220. + /* Note the cctl divide to 5 group and share the same name table. */
  5221. + if (op_value < 0 || op_value > 4)
  5222. + error ("CCTL intrinsic function subtype out of range!");
  5223. + fprintf (stream, "%s", nds32_cctl_names[op_value + 12]);
  5224. + return;
  5225. +
  5226. + case 'W': /* cctl idxwitre */
  5227. + /* Note the cctl divide to 5 group and share the same name table. */
  5228. + if (op_value < 0 || op_value > 4)
  5229. + error ("CCTL intrinsic function subtype out of range!");
  5230. + fprintf (stream, "%s", nds32_cctl_names[op_value + 16]);
  5231. + return;
  5232. +
  5233. + case 'Z': /* dpref */
  5234. + fprintf (stream, "%s", nds32_dpref_names[op_value]);
  5235. + return;
  5236. +
  5237. default :
  5238. /* Unknown flag. */
  5239. output_operand_lossage ("invalid operand output code");
  5240. @@ -2867,35 +3705,113 @@
  5241. switch (GET_CODE (x))
  5242. {
  5243. case LABEL_REF:
  5244. + output_addr_const (stream, x);
  5245. + break;
  5246. +
  5247. case SYMBOL_REF:
  5248. output_addr_const (stream, x);
  5249. +
  5250. + if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x))
  5251. + fprintf (stream, "@ICT");
  5252. +
  5253. break;
  5254. case REG:
  5255. + /* Print a Double-precision register name. */
  5256. + if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
  5257. + && NDS32_IS_FPR_REGNUM (REGNO (x)))
  5258. + {
  5259. + regno = REGNO (x);
  5260. + if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno))
  5261. + {
  5262. + output_operand_lossage ("invalid operand for code '%c'", code);
  5263. + break;
  5264. + }
  5265. + fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1);
  5266. + break;
  5267. + }
  5268. +
  5269. + /* Print LSB or MSB part of register pair if the
  5270. + constraint modifier 'L' or 'H' is specified. */
  5271. + if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
  5272. + && NDS32_IS_GPR_REGNUM (REGNO (x)))
  5273. + {
  5274. + if ((pick_lsb_p && WORDS_BIG_ENDIAN)
  5275. + || (pick_msb_p && !WORDS_BIG_ENDIAN))
  5276. + {
  5277. + /* If we would like to print out LSB register under big-endian,
  5278. + or print out MSB register under little-endian, we need to
  5279. + increase register number. */
  5280. + regno = REGNO (x);
  5281. + regno++;
  5282. + fputs (reg_names[regno], stream);
  5283. + break;
  5284. + }
  5285. + }
  5286. +
  5287. /* Forbid using static chain register ($r16)
  5288. - on reduced-set registers configuration. */
  5289. + on reduced-set registers configuration. */
  5290. if (TARGET_REDUCED_REGS
  5291. && REGNO (x) == STATIC_CHAIN_REGNUM)
  5292. sorry ("a nested function is not supported for reduced registers");
  5293. /* Normal cases, print out register name. */
  5294. - fputs (reg_names[REGNO (x)], stream);
  5295. + regno = REGNO (x);
  5296. + fputs (reg_names[regno], stream);
  5297. break;
  5298. case MEM:
  5299. output_address (XEXP (x, 0));
  5300. break;
  5301. + case HIGH:
  5302. + if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE)
  5303. + {
  5304. + REAL_VALUE_TYPE rv;
  5305. + long val;
  5306. + gcc_assert (GET_MODE (x) == SFmode);
  5307. +
  5308. + REAL_VALUE_FROM_CONST_DOUBLE (rv, XEXP (x, 0));
  5309. + REAL_VALUE_TO_TARGET_SINGLE (rv, val);
  5310. +
  5311. + fprintf (stream, "hi20(0x%lx)", val);
  5312. + }
  5313. + else
  5314. + gcc_unreachable ();
  5315. + break;
  5316. +
  5317. + case CONST_DOUBLE:
  5318. + REAL_VALUE_TYPE rv;
  5319. + long val;
  5320. + gcc_assert (GET_MODE (x) == SFmode);
  5321. +
  5322. + REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
  5323. + REAL_VALUE_TO_TARGET_SINGLE (rv, val);
  5324. +
  5325. + fprintf (stream, "0x%lx", val);
  5326. + break;
  5327. +
  5328. case CODE_LABEL:
  5329. case CONST_INT:
  5330. case CONST:
  5331. output_addr_const (stream, x);
  5332. break;
  5333. + case CONST_VECTOR:
  5334. + fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x));
  5335. + break;
  5336. +
  5337. + case LO_SUM:
  5338. + /* This is a special case for inline assembly using memory address 'p'.
  5339. + The inline assembly code is expected to use pesudo instruction
  5340. + for the operand. EX: la */
  5341. + output_addr_const (stream, XEXP(x, 1));
  5342. + break;
  5343. +
  5344. default:
  5345. /* Generally, output_addr_const () is able to handle most cases.
  5346. - We want to see what CODE could appear,
  5347. - so we use gcc_unreachable() to stop it. */
  5348. + We want to see what CODE could appear,
  5349. + so we use gcc_unreachable() to stop it. */
  5350. debug_rtx (x);
  5351. gcc_unreachable ();
  5352. break;
  5353. @@ -2918,15 +3834,25 @@
  5354. fputs ("]", stream);
  5355. break;
  5356. + case LO_SUM:
  5357. + /* This is a special case for inline assembly using memory operand 'm'.
  5358. + The inline assembly code is expected to use pesudo instruction
  5359. + for the operand. EX: [ls].[bhw] */
  5360. + fputs ("[ + ", stream);
  5361. + op1 = XEXP (x, 1);
  5362. + output_addr_const (stream, op1);
  5363. + fputs ("]", stream);
  5364. + break;
  5365. +
  5366. case REG:
  5367. /* Forbid using static chain register ($r16)
  5368. - on reduced-set registers configuration. */
  5369. + on reduced-set registers configuration. */
  5370. if (TARGET_REDUCED_REGS
  5371. && REGNO (x) == STATIC_CHAIN_REGNUM)
  5372. sorry ("a nested function is not supported for reduced registers");
  5373. /* [Ra] */
  5374. - fprintf (stream, "[%s]", reg_names[REGNO (x)]);
  5375. + fprintf (stream, "[%s + 0]", reg_names[REGNO (x)]);
  5376. break;
  5377. case PLUS:
  5378. @@ -2934,13 +3860,13 @@
  5379. op1 = XEXP (x, 1);
  5380. /* Checking op0, forbid using static chain register ($r16)
  5381. - on reduced-set registers configuration. */
  5382. + on reduced-set registers configuration. */
  5383. if (TARGET_REDUCED_REGS
  5384. && REG_P (op0)
  5385. && REGNO (op0) == STATIC_CHAIN_REGNUM)
  5386. sorry ("a nested function is not supported for reduced registers");
  5387. /* Checking op1, forbid using static chain register ($r16)
  5388. - on reduced-set registers configuration. */
  5389. + on reduced-set registers configuration. */
  5390. if (TARGET_REDUCED_REGS
  5391. && REG_P (op1)
  5392. && REGNO (op1) == STATIC_CHAIN_REGNUM)
  5393. @@ -2949,8 +3875,8 @@
  5394. if (REG_P (op0) && CONST_INT_P (op1))
  5395. {
  5396. /* [Ra + imm] */
  5397. - fprintf (stream, "[%s + (%d)]",
  5398. - reg_names[REGNO (op0)], (int)INTVAL (op1));
  5399. + fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]",
  5400. + reg_names[REGNO (op0)], INTVAL (op1));
  5401. }
  5402. else if (REG_P (op0) && REG_P (op1))
  5403. {
  5404. @@ -2963,8 +3889,8 @@
  5405. /* [Ra + Rb << sv]
  5406. From observation, the pattern looks like:
  5407. (plus:SI (mult:SI (reg:SI 58)
  5408. - (const_int 4 [0x4]))
  5409. - (reg/f:SI 57)) */
  5410. + (const_int 4 [0x4]))
  5411. + (reg/f:SI 57)) */
  5412. int sv;
  5413. /* We need to set sv to output shift value. */
  5414. @@ -2974,6 +3900,8 @@
  5415. sv = 1;
  5416. else if (INTVAL (XEXP (op0, 1)) == 4)
  5417. sv = 2;
  5418. + else if (INTVAL (XEXP (op0, 1)) == 8)
  5419. + sv = 3;
  5420. else
  5421. gcc_unreachable ();
  5422. @@ -2993,20 +3921,20 @@
  5423. case POST_MODIFY:
  5424. /* (post_modify (regA) (plus (regA) (regB)))
  5425. - (post_modify (regA) (plus (regA) (const_int)))
  5426. - We would like to extract
  5427. - regA and regB (or const_int) from plus rtx. */
  5428. + (post_modify (regA) (plus (regA) (const_int)))
  5429. + We would like to extract
  5430. + regA and regB (or const_int) from plus rtx. */
  5431. op0 = XEXP (XEXP (x, 1), 0);
  5432. op1 = XEXP (XEXP (x, 1), 1);
  5433. /* Checking op0, forbid using static chain register ($r16)
  5434. - on reduced-set registers configuration. */
  5435. + on reduced-set registers configuration. */
  5436. if (TARGET_REDUCED_REGS
  5437. && REG_P (op0)
  5438. && REGNO (op0) == STATIC_CHAIN_REGNUM)
  5439. sorry ("a nested function is not supported for reduced registers");
  5440. /* Checking op1, forbid using static chain register ($r16)
  5441. - on reduced-set registers configuration. */
  5442. + on reduced-set registers configuration. */
  5443. if (TARGET_REDUCED_REGS
  5444. && REG_P (op1)
  5445. && REGNO (op1) == STATIC_CHAIN_REGNUM)
  5446. @@ -3021,8 +3949,8 @@
  5447. else if (REG_P (op0) && CONST_INT_P (op1))
  5448. {
  5449. /* [Ra], imm */
  5450. - fprintf (stream, "[%s], %d",
  5451. - reg_names[REGNO (op0)], (int)INTVAL (op1));
  5452. + fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC,
  5453. + reg_names[REGNO (op0)], INTVAL (op1));
  5454. }
  5455. else
  5456. {
  5457. @@ -3038,7 +3966,7 @@
  5458. op0 = XEXP (x, 0);
  5459. /* Checking op0, forbid using static chain register ($r16)
  5460. - on reduced-set registers configuration. */
  5461. + on reduced-set registers configuration. */
  5462. if (TARGET_REDUCED_REGS
  5463. && REG_P (op0)
  5464. && REGNO (op0) == STATIC_CHAIN_REGNUM)
  5465. @@ -3062,14 +3990,83 @@
  5466. default :
  5467. /* Generally, output_addr_const () is able to handle most cases.
  5468. - We want to see what CODE could appear,
  5469. - so we use gcc_unreachable() to stop it. */
  5470. + We want to see what CODE could appear,
  5471. + so we use gcc_unreachable() to stop it. */
  5472. debug_rtx (x);
  5473. gcc_unreachable ();
  5474. break;
  5475. }
  5476. }
  5477. +/* -- Assembler Commands for Exception Regions. */
  5478. +
  5479. +static rtx
  5480. +nds32_dwarf_register_span (rtx reg)
  5481. +{
  5482. + rtx dwarf_high, dwarf_low;
  5483. + rtx dwarf_single;
  5484. + enum machine_mode mode;
  5485. + int regno;
  5486. +
  5487. + mode = GET_MODE (reg);
  5488. + regno = REGNO (reg);
  5489. +
  5490. + /* We need to adjust dwarf register information for floating-point registers
  5491. + rather than using default register number mapping. */
  5492. + if (regno >= NDS32_FIRST_FPR_REGNUM
  5493. + && regno <= NDS32_LAST_FPR_REGNUM)
  5494. + {
  5495. + /* The nds32 port in GDB maintains a mapping between dwarf register
  5496. + number and displayed register name. For backward compatibility to
  5497. + previous toolchain, currently our gdb still has four registers
  5498. + (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler
  5499. + does not count those four registers in its register number table.
  5500. + So we have to add 4 on its register number and then create new
  5501. + dwarf information. Hopefully we can discard such workaround
  5502. + in the future. */
  5503. + regno += 4;
  5504. +
  5505. + if (mode == DFmode || mode == SCmode)
  5506. + {
  5507. + /* By default, GCC maps increasing register numbers to increasing
  5508. + memory locations, but paired FPRs in NDS32 target are always
  5509. + big-endian, i.e.:
  5510. +
  5511. + fd0 : fs0 fs1
  5512. + (MSB) (LSB)
  5513. +
  5514. + We must return parallel rtx to represent such layout. */
  5515. + dwarf_high = gen_rtx_REG (word_mode, regno);
  5516. + dwarf_low = gen_rtx_REG (word_mode, regno + 1);
  5517. + return gen_rtx_PARALLEL (VOIDmode,
  5518. + gen_rtvec (2, dwarf_low, dwarf_high));
  5519. + }
  5520. + else if (mode == DCmode)
  5521. + {
  5522. + rtx dwarf_high_re = gen_rtx_REG (word_mode, regno);
  5523. + rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1);
  5524. + rtx dwarf_high_im = gen_rtx_REG (word_mode, regno);
  5525. + rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1);
  5526. + return gen_rtx_PARALLEL (VOIDmode,
  5527. + gen_rtvec (4, dwarf_low_re, dwarf_high_re,
  5528. + dwarf_high_im, dwarf_low_im));
  5529. + }
  5530. + else if (mode == SFmode || mode == SImode)
  5531. + {
  5532. + /* Create new dwarf information with adjusted register number. */
  5533. + dwarf_single = gen_rtx_REG (word_mode, regno);
  5534. + return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, dwarf_single));
  5535. + }
  5536. + else
  5537. + {
  5538. + /* We should not be here. */
  5539. + gcc_unreachable ();
  5540. + }
  5541. + }
  5542. +
  5543. + return NULL_RTX;
  5544. +}
  5545. +
  5546. /* Defining target-specific uses of __attribute__. */
  5547. @@ -3098,6 +4095,27 @@
  5548. static void
  5549. nds32_insert_attributes (tree decl, tree *attributes)
  5550. {
  5551. + /* A "indirect_call" function attribute implies "noinline" and "noclone"
  5552. + for elf toolchain to support ROM patch mechanism. */
  5553. + if (TREE_CODE (decl) == FUNCTION_DECL
  5554. + && lookup_attribute ("indirect_call", *attributes) != NULL)
  5555. + {
  5556. + tree new_attrs = *attributes;
  5557. +
  5558. + if (TARGET_LINUX_ABI)
  5559. + error("cannot use indirect_call attribute under linux toolchain");
  5560. +
  5561. + if (lookup_attribute ("noinline", new_attrs) == NULL)
  5562. + new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs);
  5563. + if (lookup_attribute ("noclone", new_attrs) == NULL)
  5564. + new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs);
  5565. +
  5566. + if (!TREE_PUBLIC (decl))
  5567. + error("indirect_call attribute can't apply for static function");
  5568. +
  5569. + *attributes = new_attrs;
  5570. + }
  5571. +
  5572. /* For function declaration, we need to check isr-specific attributes:
  5573. 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
  5574. 2. Check valid integer value for interrupt/exception.
  5575. @@ -3115,14 +4133,46 @@
  5576. nds32_check_isr_attrs_conflict (decl, func_attrs);
  5577. /* Now we are starting to check valid id value
  5578. - for interrupt/exception/reset.
  5579. - Note that we ONLY check its validity here.
  5580. - To construct isr vector information, it is still performed
  5581. - by nds32_construct_isr_vectors_information(). */
  5582. + for interrupt/exception/reset.
  5583. + Note that we ONLY check its validity here.
  5584. + To construct isr vector information, it is still performed
  5585. + by nds32_construct_isr_vectors_information(). */
  5586. intr = lookup_attribute ("interrupt", func_attrs);
  5587. excp = lookup_attribute ("exception", func_attrs);
  5588. reset = lookup_attribute ("reset", func_attrs);
  5589. + /* The following code may use attribute arguments. If there is no
  5590. + argument from source code, it will cause segmentation fault.
  5591. + Therefore, return dircetly and report error message later. */
  5592. + if ((intr && TREE_VALUE (intr) == NULL)
  5593. + || (excp && TREE_VALUE (excp) == NULL)
  5594. + || (reset && TREE_VALUE (reset) == NULL))
  5595. + return;
  5596. +
  5597. + /* ------------------------------------------------------------- */
  5598. + /* FIXME:
  5599. + FOR BACKWARD COMPATIBILITY, we need to support following patterns:
  5600. +
  5601. + __attribute__((interrupt("XXX;YYY;id=ZZZ")))
  5602. + __attribute__((exception("XXX;YYY;id=ZZZ")))
  5603. + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
  5604. +
  5605. + If interrupt/exception/reset appears and its argument is a
  5606. + STRING_CST, we will use other functions to parse string in the
  5607. + nds32_construct_isr_vectors_information() and then set necessary
  5608. + isr information in the nds32_isr_vectors[] array. Here we can
  5609. + just return immediately to avoid new-syntax checking. */
  5610. + if (intr != NULL_TREE
  5611. + && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST)
  5612. + return;
  5613. + if (excp != NULL_TREE
  5614. + && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST)
  5615. + return;
  5616. + if (reset != NULL_TREE
  5617. + && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST)
  5618. + return;
  5619. + /* ------------------------------------------------------------- */
  5620. +
  5621. if (intr || excp)
  5622. {
  5623. /* Deal with interrupt/exception. */
  5624. @@ -3239,17 +4289,37 @@
  5625. {
  5626. /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
  5627. target_flags &= ~MASK_V3PUSH;
  5628. + /* Under V2 ISA, we need to strictly disable TARGET_IFC. */
  5629. + target_flags &= ~MASK_IFC;
  5630. + /* Under V2 ISA, we need to strictly disable TARGET_EX9. */
  5631. + target_flags &= ~MASK_EX9;
  5632. + /* If this is ARCH_V2J, we need to enable TARGET_REDUCED_REGS. */
  5633. + if (nds32_arch_option == ARCH_V2J)
  5634. + target_flags |= MASK_REDUCED_REGS;
  5635. }
  5636. if (TARGET_ISA_V3)
  5637. {
  5638. - /* Under V3 ISA, currently nothing should be strictly set. */
  5639. + /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */
  5640. + if (nds32_arch_option == ARCH_V3J)
  5641. + target_flags |= MASK_REDUCED_REGS;
  5642. }
  5643. if (TARGET_ISA_V3M)
  5644. {
  5645. /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
  5646. target_flags |= MASK_REDUCED_REGS;
  5647. - /* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT. */
  5648. - target_flags &= ~MASK_PERF_EXT;
  5649. + /* Under V3M ISA, we need to strictly disable TARGET_IFC. */
  5650. + target_flags &= ~MASK_IFC;
  5651. + /* Under V3M ISA, we need to strictly disable TARGET_EX9. */
  5652. + target_flags &= ~MASK_EX9;
  5653. + /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
  5654. + target_flags &= ~MASK_EXT_PERF;
  5655. + /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
  5656. + target_flags &= ~MASK_EXT_PERF2;
  5657. + /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
  5658. + target_flags &= ~MASK_EXT_STRING;
  5659. +
  5660. + if (flag_pic)
  5661. + error ("not support -fpic option for v3m toolchain");
  5662. }
  5663. /* See if we are using reduced-set registers:
  5664. @@ -3260,7 +4330,7 @@
  5665. int r;
  5666. /* Prevent register allocator from
  5667. - choosing it as doing register allocation. */
  5668. + choosing it as doing register allocation. */
  5669. for (r = 11; r <= 14; r++)
  5670. fixed_regs[r] = call_used_regs[r] = 1;
  5671. for (r = 16; r <= 27; r++)
  5672. @@ -3279,127 +4349,495 @@
  5673. target_flags &= ~MASK_V3PUSH;
  5674. }
  5675. - /* Currently, we don't support PIC code generation yet. */
  5676. - if (flag_pic)
  5677. + if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
  5678. + {
  5679. + if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F)
  5680. + error ("Disable FPU ISA, "
  5681. + "the ABI option must be enable '-mfloat-abi=soft'");
  5682. + else
  5683. + error ("'-mfloat-abi=hard' option just support FPU ISA, "
  5684. + "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'");
  5685. + }
  5686. +
  5687. + /* ELF toolchain don't support PIC code generation. */
  5688. + if (!TARGET_LINUX_ABI && flag_pic)
  5689. sorry ("not support -fpic");
  5690. +
  5691. + nds32_register_passes ();
  5692. +
  5693. + nds32_init_rtx_costs ();
  5694. +
  5695. + /* This is magic hack for our Coremark score... */
  5696. + if (global_options.x_flag_tree_switch_shortcut)
  5697. + {
  5698. + maybe_set_param_value
  5699. + (PARAM_MAX_AVERAGE_UNROLLED_INSNS,
  5700. + 200,
  5701. + global_options.x_param_values, global_options_set.x_param_values);
  5702. +
  5703. + maybe_set_param_value
  5704. + (PARAM_MAX_GROW_COPY_BB_INSNS,
  5705. + 16,
  5706. + global_options.x_param_values, global_options_set.x_param_values);
  5707. + }
  5708. }
  5709. /* Miscellaneous Parameters. */
  5710. +static tree
  5711. +nds32_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
  5712. + tree inputs ATTRIBUTE_UNUSED,
  5713. + tree clobbers)
  5714. +{
  5715. + clobbers = tree_cons (NULL_TREE, build_string (3, "$ta"),
  5716. + clobbers);
  5717. + return clobbers;
  5718. +}
  5719. +/* Insert end_label and check loop body whether is empty. */
  5720. +static bool
  5721. +nds32_hwloop_insert_end_label (rtx loop_id, rtx end_label)
  5722. +{
  5723. + rtx insn = NULL_RTX;
  5724. + basic_block bb;
  5725. + rtx cfg_id, last_insn;
  5726. +
  5727. + FOR_EACH_BB_FN (bb, cfun)
  5728. + {
  5729. + FOR_BB_INSNS (bb, insn)
  5730. + {
  5731. + if (NOTE_P (insn))
  5732. + continue;
  5733. +
  5734. + if (recog_memoized (insn) == CODE_FOR_hwloop_cfg
  5735. + && INSN_P (insn))
  5736. + {
  5737. + cfg_id = XVECEXP (XVECEXP (PATTERN (insn), 0, 5), 0, 0);
  5738. + if (cfg_id == loop_id)
  5739. + {
  5740. + for (last_insn = PREV_INSN (insn); last_insn != BB_HEAD (bb);
  5741. + last_insn = PREV_INSN (last_insn))
  5742. + {
  5743. + if (NONDEBUG_INSN_P (last_insn))
  5744. + {
  5745. + emit_label_before (end_label, last_insn);
  5746. + /* The last_insn don't do ifcall. */
  5747. + emit_insn_before (gen_no_ifc_begin (), last_insn);
  5748. + emit_insn_after (gen_no_ifc_end (), last_insn);
  5749. + /* The last_insn don't do ex9. */
  5750. + emit_insn_before (gen_no_ex9_begin (), last_insn);
  5751. + emit_insn_after (gen_no_ex9_end (), last_insn);
  5752. + return true;
  5753. + }
  5754. + }
  5755. +
  5756. + if (NOTE_INSN_BASIC_BLOCK_P (last_insn))
  5757. + {
  5758. + rtx nop = emit_insn_before (gen_unspec_nop (), last_insn);
  5759. + emit_label_before (end_label, nop);
  5760. + /* The last_insn don't do ifcall. */
  5761. + emit_insn_before (gen_no_ifc_begin (), last_insn);
  5762. + emit_insn_after (gen_no_ifc_end (), last_insn);
  5763. + /* The last_insn don't do ex9. */
  5764. + emit_insn_before (gen_no_ex9_begin (), last_insn);
  5765. + emit_insn_after (gen_no_ex9_end (), last_insn);
  5766. + return true;
  5767. + }
  5768. + }
  5769. + }
  5770. + }
  5771. + }
  5772. +
  5773. + if (insn != NULL_RTX)
  5774. + delete_insn (insn);
  5775. + return false;
  5776. +}
  5777. +
  5778. static void
  5779. -nds32_init_builtins (void)
  5780. +nds32_hwloop_remove (rtx loop_id)
  5781. +{
  5782. + rtx insn, le_id;
  5783. + basic_block bb;
  5784. +
  5785. + FOR_EACH_BB_FN (bb, cfun)
  5786. + {
  5787. + FOR_BB_INSNS (bb, insn)
  5788. + {
  5789. + if (NOTE_P (insn))
  5790. + continue;
  5791. +
  5792. + if (recog_memoized (insn) == CODE_FOR_init_lc
  5793. + && INSN_P (insn))
  5794. + {
  5795. + le_id = XVECEXP (XVECEXP (PATTERN (insn), 0, 1), 0, 0);
  5796. + if (loop_id == le_id)
  5797. + {
  5798. + delete_insn (insn);
  5799. + return;
  5800. + }
  5801. + }
  5802. + }
  5803. + }
  5804. +}
  5805. +
  5806. +/* Insert isb instruction for hwloop. */
  5807. +static void
  5808. +nds32_hwloop_insert_isb (rtx loop_id)
  5809. +{
  5810. + rtx insn, le_id;
  5811. + basic_block bb;
  5812. +
  5813. + FOR_EACH_BB_FN (bb, cfun)
  5814. + {
  5815. + FOR_BB_INSNS (bb, insn)
  5816. + {
  5817. + if (NOTE_P (insn))
  5818. + continue;
  5819. +
  5820. + if (recog_memoized (insn) == CODE_FOR_init_lc
  5821. + && INSN_P (insn))
  5822. + {
  5823. + le_id = XVECEXP (XVECEXP (PATTERN (insn), 0, 1), 0, 0);
  5824. + if (loop_id == le_id)
  5825. + {
  5826. + emit_insn_after (gen_unspec_volatile_isb (), insn);
  5827. + return;
  5828. + }
  5829. + }
  5830. + }
  5831. + }
  5832. +}
  5833. +/* Insert mtlei instruction for hwloop. */
  5834. +static void
  5835. +nds32_hwloop_insert_init_end ()
  5836. +{
  5837. + rtx insn;
  5838. + basic_block bb;
  5839. + rtx loop_id, end_label;
  5840. + bool hwloop_p;
  5841. +
  5842. + FOR_EACH_BB_FN (bb, cfun)
  5843. + {
  5844. + FOR_BB_INSNS (bb, insn)
  5845. + {
  5846. + if (NOTE_P (insn))
  5847. + continue;
  5848. +
  5849. + if (recog_memoized (insn) == CODE_FOR_mtlbi_hint
  5850. + && INSN_P (insn))
  5851. + {
  5852. + end_label = gen_label_rtx ();
  5853. + loop_id = XVECEXP (XVECEXP (PATTERN (insn), 0, 1), 0, 0);
  5854. + hwloop_p = nds32_hwloop_insert_end_label (loop_id, end_label);
  5855. +
  5856. + if (!hwloop_p)
  5857. + {
  5858. + delete_insn (insn);
  5859. + nds32_hwloop_remove (loop_id);
  5860. + }
  5861. + else
  5862. + {
  5863. + emit_insn_after (gen_mtlei (gen_rtx_LABEL_REF (Pmode, end_label)), insn);
  5864. + nds32_hwloop_insert_isb (loop_id);
  5865. + }
  5866. + }
  5867. + }
  5868. + }
  5869. +}
  5870. +
  5871. +/* Perform machine-dependent processing. */
  5872. +static void
  5873. +nds32_machine_dependent_reorg (void)
  5874. {
  5875. - tree pointer_type_node = build_pointer_type (integer_type_node);
  5876. + /* We are freeing block_for_insn in the toplev to keep compatibility
  5877. + with old MDEP_REORGS that are not CFG based. Recompute it
  5878. + now. */
  5879. + compute_bb_for_insn ();
  5880. + df_analyze ();
  5881. +
  5882. + if (TARGET_HWLOOP)
  5883. + nds32_hwloop_insert_init_end ();
  5884. +
  5885. + if (flag_var_tracking)
  5886. + {
  5887. + timevar_push (TV_VAR_TRACKING);
  5888. + variable_tracking_main ();
  5889. + timevar_pop (TV_VAR_TRACKING);
  5890. + df_finish_pass (false);
  5891. + }
  5892. +
  5893. + /* Use -minnermost-loop to enable,
  5894. + need more testing to verify result. */
  5895. + if (TARGET_INNERMOST_LOOP)
  5896. + nds32_insert_innermost_loop ();
  5897. +
  5898. + nds32_insert_isps ();
  5899. +}
  5900. - tree void_ftype_void = build_function_type (void_type_node,
  5901. - void_list_node);
  5902. +static void
  5903. +nds32_init_builtins (void)
  5904. +{
  5905. + nds32_init_builtins_impl ();
  5906. +}
  5907. - tree void_ftype_pint = build_function_type_list (void_type_node,
  5908. - pointer_type_node,
  5909. - NULL_TREE);
  5910. -
  5911. - tree int_ftype_int = build_function_type_list (integer_type_node,
  5912. - integer_type_node,
  5913. - NULL_TREE);
  5914. -
  5915. - tree void_ftype_int_int = build_function_type_list (void_type_node,
  5916. - integer_type_node,
  5917. - integer_type_node,
  5918. - NULL_TREE);
  5919. -
  5920. - /* Cache. */
  5921. - add_builtin_function ("__builtin_nds32_isync", void_ftype_pint,
  5922. - NDS32_BUILTIN_ISYNC,
  5923. - BUILT_IN_MD, NULL, NULL_TREE);
  5924. - add_builtin_function ("__builtin_nds32_isb", void_ftype_void,
  5925. - NDS32_BUILTIN_ISB,
  5926. - BUILT_IN_MD, NULL, NULL_TREE);
  5927. -
  5928. - /* Register Transfer. */
  5929. - add_builtin_function ("__builtin_nds32_mfsr", int_ftype_int,
  5930. - NDS32_BUILTIN_MFSR,
  5931. - BUILT_IN_MD, NULL, NULL_TREE);
  5932. - add_builtin_function ("__builtin_nds32_mfusr", int_ftype_int,
  5933. - NDS32_BUILTIN_MFUSR,
  5934. - BUILT_IN_MD, NULL, NULL_TREE);
  5935. - add_builtin_function ("__builtin_nds32_mtsr", void_ftype_int_int,
  5936. - NDS32_BUILTIN_MTSR,
  5937. - BUILT_IN_MD, NULL, NULL_TREE);
  5938. - add_builtin_function ("__builtin_nds32_mtusr", void_ftype_int_int,
  5939. - NDS32_BUILTIN_MTUSR,
  5940. - BUILT_IN_MD, NULL, NULL_TREE);
  5941. -
  5942. - /* Interrupt. */
  5943. - add_builtin_function ("__builtin_nds32_setgie_en", void_ftype_void,
  5944. - NDS32_BUILTIN_SETGIE_EN,
  5945. - BUILT_IN_MD, NULL, NULL_TREE);
  5946. - add_builtin_function ("__builtin_nds32_setgie_dis", void_ftype_void,
  5947. - NDS32_BUILTIN_SETGIE_DIS,
  5948. - BUILT_IN_MD, NULL, NULL_TREE);
  5949. +static tree
  5950. +nds32_builtin_decl (unsigned code, bool initialize_p)
  5951. +{
  5952. + /* Implement in nds32-intrinsic.c. */
  5953. + return nds32_builtin_decl_impl (code, initialize_p);
  5954. }
  5955. static rtx
  5956. nds32_expand_builtin (tree exp,
  5957. rtx target,
  5958. - rtx subtarget ATTRIBUTE_UNUSED,
  5959. - enum machine_mode mode ATTRIBUTE_UNUSED,
  5960. - int ignore ATTRIBUTE_UNUSED)
  5961. -{
  5962. - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
  5963. -
  5964. - int fcode = DECL_FUNCTION_CODE (fndecl);
  5965. -
  5966. - switch (fcode)
  5967. - {
  5968. - /* Cache. */
  5969. - case NDS32_BUILTIN_ISYNC:
  5970. - return nds32_expand_builtin_null_ftype_reg
  5971. - (CODE_FOR_unspec_volatile_isync, exp, target);
  5972. - case NDS32_BUILTIN_ISB:
  5973. - /* Since there are no result and operands for isb instruciton,
  5974. - we can simply emit this rtx. */
  5975. - emit_insn (gen_unspec_volatile_isb ());
  5976. - return target;
  5977. -
  5978. - /* Register Transfer. */
  5979. - case NDS32_BUILTIN_MFSR:
  5980. - return nds32_expand_builtin_reg_ftype_imm
  5981. - (CODE_FOR_unspec_volatile_mfsr, exp, target);
  5982. - case NDS32_BUILTIN_MFUSR:
  5983. - return nds32_expand_builtin_reg_ftype_imm
  5984. - (CODE_FOR_unspec_volatile_mfusr, exp, target);
  5985. - case NDS32_BUILTIN_MTSR:
  5986. - return nds32_expand_builtin_null_ftype_reg_imm
  5987. - (CODE_FOR_unspec_volatile_mtsr, exp, target);
  5988. - case NDS32_BUILTIN_MTUSR:
  5989. - return nds32_expand_builtin_null_ftype_reg_imm
  5990. - (CODE_FOR_unspec_volatile_mtusr, exp, target);
  5991. -
  5992. - /* Interrupt. */
  5993. - case NDS32_BUILTIN_SETGIE_EN:
  5994. - /* Since there are no result and operands for setgie.e instruciton,
  5995. - we can simply emit this rtx. */
  5996. - emit_insn (gen_unspec_volatile_setgie_en ());
  5997. - return target;
  5998. - case NDS32_BUILTIN_SETGIE_DIS:
  5999. - /* Since there are no result and operands for setgie.d instruciton,
  6000. - we can simply emit this rtx. */
  6001. - emit_insn (gen_unspec_volatile_setgie_dis ());
  6002. - return target;
  6003. + rtx subtarget,
  6004. + enum machine_mode mode,
  6005. + int ignore)
  6006. +{
  6007. + /* Implement in nds32-intrinsic.c. */
  6008. + return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore);
  6009. +}
  6010. - default:
  6011. - gcc_unreachable ();
  6012. - }
  6013. +static bool
  6014. +nds32_have_conditional_execution (void)
  6015. +{
  6016. + /* Lie to gcc that we have conditional execution for change optimization flow
  6017. + in if-conversion, LRA and scheduling phase.
  6018. + In our experiment result show that cand reduce about 2% code size with very
  6019. + minor performance degradation in average. */
  6020. + return optimize_size;
  6021. +}
  6022. - return NULL_RTX;
  6023. +/* Implement TARGET_INIT_LIBFUNCS. */
  6024. +static void
  6025. +nds32_init_libfuncs (void)
  6026. +{
  6027. + if (TARGET_LINUX_ABI)
  6028. + init_sync_libfuncs (UNITS_PER_WORD);
  6029. +}
  6030. +
  6031. +/* Implement TARGET_CAN_USE_DOLOOP_P. */
  6032. +static bool
  6033. +nds32_can_use_doloop_p (double_int, double_int iterations_max,
  6034. + unsigned int, bool entered_at_top)
  6035. +{
  6036. + /* Using hwloop must be entered from the top. */
  6037. + if (!entered_at_top)
  6038. + return false;
  6039. +
  6040. + if (lookup_attribute ("no_ext_zol", DECL_ATTRIBUTES (current_function_decl)))
  6041. + return false;
  6042. +
  6043. + /* Initial hardware loops too costly, so we must avoid to
  6044. + generate a hardware loops when loop count less then 8. */
  6045. + if (!NDS32_HW_LOOP_P ()
  6046. + || iterations_max.low < 8)
  6047. + return false;
  6048. + return true;
  6049. }
  6050. +/* NULL if INSN insn is valid within a low-overhead loop.
  6051. + Otherwise return why doloop cannot be applied. */
  6052. +static const char *
  6053. +nds32_invalid_within_doloop (const_rtx insn)
  6054. +{
  6055. + if (CALL_P (insn))
  6056. + return "Function call in the loop.";
  6057. + else if (INSN_CODE (insn) == CODE_FOR_pop25return
  6058. + || INSN_CODE (insn) == CODE_FOR_return_internal)
  6059. + return "Simple return in the loop.";
  6060. +
  6061. + return NULL;
  6062. +}
  6063. /* ------------------------------------------------------------------------ */
  6064. -/* PART 4: Implemet extern function definitions,
  6065. - the prototype is in nds32-protos.h. */
  6066. +/* PART 5: Implemet extern function definitions,
  6067. + the prototype is in nds32-protos.h. */
  6068. +
  6069. +/* Run-time Target Specification. */
  6070. +
  6071. +void
  6072. +nds32_cpu_cpp_builtins(struct cpp_reader *pfile)
  6073. +{
  6074. +#define builtin_define(TXT) cpp_define (pfile, TXT)
  6075. +#define builtin_assert(TXT) cpp_assert (pfile, TXT)
  6076. + builtin_define ("__nds32__");
  6077. + builtin_define ("__NDS32__");
  6078. +
  6079. + /* We need to provide builtin macro to describe the size of
  6080. + each vector for interrupt handler under elf toolchain. */
  6081. + if (!TARGET_LINUX_ABI)
  6082. + {
  6083. + if (TARGET_ISR_VECTOR_SIZE_4_BYTE)
  6084. + builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__");
  6085. + else
  6086. + builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__");
  6087. + }
  6088. +
  6089. + if (TARGET_HARD_FLOAT)
  6090. + builtin_define ("__NDS32_ABI_2FP_PLUS__");
  6091. + else
  6092. + builtin_define ("__NDS32_ABI_2__");
  6093. +
  6094. + if (TARGET_ISA_V2)
  6095. + builtin_define ("__NDS32_ISA_V2__");
  6096. + if (TARGET_ISA_V3)
  6097. + builtin_define ("__NDS32_ISA_V3__");
  6098. + if (TARGET_ISA_V3M)
  6099. + builtin_define ("__NDS32_ISA_V3M__");
  6100. +
  6101. + if (TARGET_FPU_SINGLE)
  6102. + builtin_define ("__NDS32_EXT_FPU_SP__");
  6103. + if (TARGET_FPU_DOUBLE)
  6104. + builtin_define ("__NDS32_EXT_FPU_DP__");
  6105. +
  6106. + if (TARGET_EXT_FPU_FMA)
  6107. + builtin_define ("__NDS32_EXT_FPU_FMA__");
  6108. + if (NDS32_EXT_FPU_DOT_E)
  6109. + builtin_define ("__NDS32_EXT_FPU_DOT_E__");
  6110. + if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  6111. + {
  6112. + switch (nds32_fp_regnum)
  6113. + {
  6114. + case 0:
  6115. + case 4:
  6116. + builtin_define ("__NDS32_EXT_FPU_CONFIG_0__");
  6117. + break;
  6118. + case 1:
  6119. + case 5:
  6120. + builtin_define ("__NDS32_EXT_FPU_CONFIG_1__");
  6121. + break;
  6122. + case 2:
  6123. + case 6:
  6124. + builtin_define ("__NDS32_EXT_FPU_CONFIG_2__");
  6125. + break;
  6126. + case 3:
  6127. + case 7:
  6128. + builtin_define ("__NDS32_EXT_FPU_CONFIG_3__");
  6129. + break;
  6130. + default:
  6131. + abort ();
  6132. + }
  6133. + }
  6134. +
  6135. + if (TARGET_BIG_ENDIAN)
  6136. + builtin_define ("__NDS32_EB__");
  6137. + else
  6138. + builtin_define ("__NDS32_EL__");
  6139. +
  6140. + if (TARGET_REDUCED_REGS)
  6141. + builtin_define ("__NDS32_REDUCED_REGS__");
  6142. + if (TARGET_CMOV)
  6143. + builtin_define ("__NDS32_CMOV__");
  6144. + if (TARGET_EXT_PERF)
  6145. + builtin_define ("__NDS32_EXT_PERF__");
  6146. + if (TARGET_EXT_PERF2)
  6147. + builtin_define ("__NDS32_EXT_PERF2__");
  6148. + if (TARGET_EXT_STRING)
  6149. + builtin_define ("__NDS32_EXT_STRING__");
  6150. + if (TARGET_16_BIT)
  6151. + builtin_define ("__NDS32_16_BIT__");
  6152. + if (TARGET_GP_DIRECT)
  6153. + builtin_define ("__NDS32_GP_DIRECT__");
  6154. + if (TARGET_VH)
  6155. + builtin_define ("__NDS32_VH__");
  6156. + if (NDS32_EXT_DSP_P ())
  6157. + builtin_define ("__NDS32_EXT_DSP__");
  6158. + if (NDS32_HW_LOOP_P ())
  6159. + builtin_define ("__NDS32_EXT_ZOL__");
  6160. +
  6161. + /* Extra builtin macros. */
  6162. + if (TARGET_ISA_V3)
  6163. + builtin_define ("__NDS32_EXT_IFC__");
  6164. + if (TARGET_ISA_V3)
  6165. + builtin_define ("__NDS32_EXT_EX9__");
  6166. + if (TARGET_BIG_ENDIAN)
  6167. + builtin_define ("__big_endian__");
  6168. +
  6169. + builtin_assert ("cpu=nds32");
  6170. + builtin_assert ("machine=nds32");
  6171. +
  6172. + /* FOR BACKWARD COMPATIBILITY. */
  6173. + if (TARGET_ISA_V2)
  6174. + builtin_define ("__NDS32_BASELINE_V2__");
  6175. + if (TARGET_ISA_V3)
  6176. + builtin_define ("__NDS32_BASELINE_V3__");
  6177. + if (TARGET_ISA_V3M)
  6178. + builtin_define ("__NDS32_BASELINE_V3M__");
  6179. + if (TARGET_REDUCED_REGS)
  6180. + builtin_define ("__NDS32_REDUCE_REGS__");
  6181. +
  6182. + if (TARGET_ISA_V2)
  6183. + builtin_define ("NDS32_BASELINE_V2");
  6184. + if (TARGET_ISA_V3)
  6185. + builtin_define ("NDS32_BASELINE_V3");
  6186. + if (TARGET_ISA_V3M)
  6187. + builtin_define ("NDS32_BASELINE_V3M");
  6188. + if (TARGET_REDUCED_REGS)
  6189. + builtin_define ("NDS32_REDUCE_REGS");
  6190. + if (TARGET_FPU_SINGLE)
  6191. + builtin_define ("NDS32_EXT_FPU_SP");
  6192. + if (TARGET_FPU_DOUBLE)
  6193. + builtin_define ("NDS32_EXT_FPU_DP");
  6194. + if (TARGET_EXT_PERF)
  6195. + builtin_define ("NDS32_EXT_PERF");
  6196. + if (TARGET_EXT_PERF2)
  6197. + builtin_define ("NDS32_EXT_PERF2");
  6198. + if (TARGET_EXT_STRING)
  6199. + builtin_define ("NDS32_EXT_STRING");
  6200. + if (TARGET_ISA_V3)
  6201. + builtin_define ("NDS32_EXT_IFC");
  6202. + if (TARGET_ISA_V3)
  6203. + builtin_define ("NDS32_EXT_EX9");
  6204. +
  6205. + if (TARGET_HARD_FLOAT)
  6206. + builtin_define ("NDS32_ABI_2FP_PLUS");
  6207. + else
  6208. + builtin_define ("NDS32_ABI_2");
  6209. +
  6210. + if (TARGET_BIG_ENDIAN)
  6211. + builtin_define ("NDS32_EB");
  6212. + else
  6213. + builtin_define ("NDS32_EL");
  6214. +
  6215. + if (TARGET_ISA_V2)
  6216. + builtin_define ("__NDS32_BASELINE_V2");
  6217. + if (TARGET_ISA_V3)
  6218. + builtin_define ("__NDS32_BASELINE_V3");
  6219. + if (TARGET_ISA_V3M)
  6220. + builtin_define ("__NDS32_BASELINE_V3M");
  6221. + if (TARGET_REDUCED_REGS)
  6222. + builtin_define ("__NDS32_REDUCE_REGS");
  6223. + if (TARGET_FPU_SINGLE)
  6224. + builtin_define ("__NDS32_EXT_FPU_SP");
  6225. + if (TARGET_FPU_DOUBLE)
  6226. + builtin_define ("__NDS32_EXT_FPU_DP");
  6227. + if (TARGET_EXT_PERF)
  6228. + builtin_define ("__NDS32_EXT_PERF");
  6229. + if (TARGET_EXT_PERF2)
  6230. + builtin_define ("__NDS32_EXT_PERF2");
  6231. + if (TARGET_EXT_STRING)
  6232. + builtin_define ("__NDS32_EXT_STRING");
  6233. + if (TARGET_ISA_V3)
  6234. + builtin_define ("__NDS32_EXT_IFC");
  6235. +
  6236. + if (TARGET_ISA_V3)
  6237. + builtin_define ("__NDS32_EXT_EX9");
  6238. +
  6239. + if (TARGET_HARD_FLOAT)
  6240. + builtin_define ("__NDS32_ABI_2FP_PLUS");
  6241. + else
  6242. + builtin_define ("__NDS32_ABI_2");
  6243. +
  6244. + if (TARGET_BIG_ENDIAN)
  6245. + builtin_define ("__NDS32_EB");
  6246. + else
  6247. + builtin_define ("__NDS32_EL");
  6248. +#undef builtin_define
  6249. +#undef builtin_assert
  6250. +}
  6251. +
  6252. /* Defining Data Structures for Per-function Information. */
  6253. @@ -3413,6 +4851,25 @@
  6254. /* Register Usage. */
  6255. +/* -- Order of Allocation of Registers. */
  6256. +
  6257. +void
  6258. +nds32_adjust_reg_alloc_order (void)
  6259. +{
  6260. + const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER;
  6261. +
  6262. + /* Copy the default register allocation order, which is designed
  6263. + to optimize for code size. */
  6264. + memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order));
  6265. +
  6266. + /* Adjust few register allocation order when optimizing for speed. */
  6267. + if (!optimize_size)
  6268. + {
  6269. + memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed,
  6270. + sizeof (nds32_reg_alloc_order_for_speed));
  6271. + }
  6272. +}
  6273. +
  6274. /* -- How Values Fit in Registers. */
  6275. int
  6276. @@ -3425,12 +4882,27 @@
  6277. int
  6278. nds32_hard_regno_mode_ok (int regno, enum machine_mode mode)
  6279. {
  6280. + if (regno > FIRST_PSEUDO_REGISTER)
  6281. + return true;
  6282. +
  6283. + if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno))
  6284. + {
  6285. + if (NDS32_IS_EXT_FPR_REGNUM(regno))
  6286. + return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode));
  6287. + else if (mode == SFmode || mode == SImode)
  6288. + return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno);
  6289. + else if (mode == DFmode)
  6290. + return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno);
  6291. +
  6292. + return false;
  6293. + }
  6294. +
  6295. /* Restrict double-word quantities to even register pairs. */
  6296. - if (HARD_REGNO_NREGS (regno, mode) == 1
  6297. - || !((regno) & 1))
  6298. - return 1;
  6299. + if (regno <= NDS32_LAST_GPR_REGNUM)
  6300. + return (HARD_REGNO_NREGS (regno, mode) == 1
  6301. + || !((regno) & 1));
  6302. - return 0;
  6303. + return false;
  6304. }
  6305. @@ -3454,7 +4926,16 @@
  6306. else if (regno >= 20 && regno <= 31)
  6307. return HIGH_REGS;
  6308. else if (regno == 32 || regno == 33)
  6309. - return FRAME_REGS;
  6310. + {
  6311. + /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't
  6312. + know how to allocate register for $SFP and $AP, just tell IRA they
  6313. + are GENERAL_REGS, and ARM do this hack too. */
  6314. + return GENERAL_REGS;
  6315. + }
  6316. + else if (regno >= 34 && regno <= 97)
  6317. + return FP_REGS;
  6318. + else if (regno >= 98 && regno <= 100)
  6319. + return LOOP_REGS;
  6320. else
  6321. return NO_REGS;
  6322. }
  6323. @@ -3465,14 +4946,39 @@
  6324. /* -- Basic Stack Layout. */
  6325. rtx
  6326. +nds32_dynamic_chain_address (rtx frameaddr)
  6327. +{
  6328. + if (TARGET_V3PUSH)
  6329. + {
  6330. + /* If -mv3push is specified, we push $fp, $gp, and $lp into stack.
  6331. + We can access dynamic chain address from stack by [$fp - 12]. */
  6332. + return plus_constant (Pmode, frameaddr, -12);
  6333. + }
  6334. + else
  6335. + {
  6336. + /* For general case we push $fp and $lp into stack at prologue.
  6337. + We can access dynamic chain address from stack by [$fp - 8]. */
  6338. + return plus_constant (Pmode, frameaddr, -8);
  6339. + }
  6340. +}
  6341. +
  6342. +rtx
  6343. nds32_return_addr_rtx (int count,
  6344. - rtx frameaddr ATTRIBUTE_UNUSED)
  6345. + rtx frameaddr)
  6346. {
  6347. - /* There is no way to determine the return address
  6348. - if frameaddr is the frame that has 'count' steps
  6349. - up from current frame. */
  6350. + int offset;
  6351. + rtx addr;
  6352. +
  6353. if (count != 0)
  6354. - return NULL_RTX;
  6355. + {
  6356. + /* In nds32 ABI design, we can expect that $lp is always available
  6357. + from stack by [$fp - 4] location. */
  6358. + offset = -4;
  6359. + addr = plus_constant (Pmode, frameaddr, offset);
  6360. + addr = memory_address (Pmode, addr);
  6361. +
  6362. + return gen_rtx_MEM (Pmode, addr);
  6363. + }
  6364. /* If count == 0, it means we are at current frame,
  6365. the return address is $r30 ($lp). */
  6366. @@ -3491,15 +4997,18 @@
  6367. nds32_compute_stack_frame ();
  6368. /* Remember to consider
  6369. - cfun->machine->callee_saved_area_padding_bytes
  6370. + cfun->machine->callee_saved_area_gpr_padding_bytes and
  6371. + cfun->machine->eh_return_data_regs_size
  6372. when calculating offset. */
  6373. if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
  6374. {
  6375. offset = (cfun->machine->fp_size
  6376. - + cfun->machine->gp_size
  6377. + + cfun->machine->gp_size
  6378. + cfun->machine->lp_size
  6379. - + cfun->machine->callee_saved_regs_size
  6380. - + cfun->machine->callee_saved_area_padding_bytes
  6381. + + cfun->machine->callee_saved_gpr_regs_size
  6382. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  6383. + + cfun->machine->callee_saved_fpr_regs_size
  6384. + + cfun->machine->eh_return_data_regs_size
  6385. + cfun->machine->local_size
  6386. + cfun->machine->out_args_size);
  6387. }
  6388. @@ -3519,8 +5028,10 @@
  6389. offset = (-1) * (cfun->machine->fp_size
  6390. + cfun->machine->gp_size
  6391. + cfun->machine->lp_size
  6392. - + cfun->machine->callee_saved_regs_size
  6393. - + cfun->machine->callee_saved_area_padding_bytes);
  6394. + + cfun->machine->callee_saved_gpr_regs_size
  6395. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  6396. + + cfun->machine->callee_saved_fpr_regs_size
  6397. + + cfun->machine->eh_return_data_regs_size);
  6398. }
  6399. else
  6400. {
  6401. @@ -3539,10 +5050,11 @@
  6402. tree fndecl ATTRIBUTE_UNUSED,
  6403. int n_named_args ATTRIBUTE_UNUSED)
  6404. {
  6405. - /* Initial available registers
  6406. - (in offset, corresponding to NDS32_GPR_ARG_FIRST_REGNUM)
  6407. + /* Initial available registers. The values are offset against
  6408. + NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM
  6409. for passing arguments. */
  6410. - cum->reg_offset = 0;
  6411. + cum->gpr_offset = 0;
  6412. + cum->fpr_offset = 0;
  6413. }
  6414. /* -- Function Entry and Exit. */
  6415. @@ -3553,57 +5065,71 @@
  6416. {
  6417. int fp_adjust;
  6418. int sp_adjust;
  6419. - int en4_const;
  6420. -
  6421. - rtx Rb, Re;
  6422. - rtx push_insn;
  6423. - rtx fp_adjust_insn, sp_adjust_insn;
  6424. -
  6425. - /* Before computing everything for stack frame size,
  6426. - we check if it is still worth to use fp_as_gp optimization.
  6427. - If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
  6428. - so that $fp will be saved on stack. */
  6429. - cfun->machine->fp_as_gp_p = nds32_fp_as_gp_check_available ();
  6430. + unsigned Rb, Re;
  6431. /* Compute and setup stack frame size.
  6432. The result will be in cfun->machine. */
  6433. nds32_compute_stack_frame ();
  6434. + /* Check frame_pointer_needed again to prevent fp is need after reload. */
  6435. + if (frame_pointer_needed)
  6436. + cfun->machine->fp_as_gp_p = false;
  6437. +
  6438. + /* If this is a variadic function, first we need to push argument
  6439. + registers that hold the unnamed argument value. */
  6440. + if (cfun->machine->va_args_size != 0)
  6441. + {
  6442. + Rb = cfun->machine->va_args_first_regno;
  6443. + Re = cfun->machine->va_args_last_regno;
  6444. + /* No need to push $fp, $gp, or $lp. */
  6445. + nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true);
  6446. +
  6447. + /* We may also need to adjust stack pointer for padding bytes
  6448. + because varargs may cause $sp not 8-byte aligned. */
  6449. + if (cfun->machine->va_args_area_padding_bytes)
  6450. + {
  6451. + /* Generate sp adjustment instruction. */
  6452. + sp_adjust = cfun->machine->va_args_area_padding_bytes;
  6453. +
  6454. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6455. + stack_pointer_rtx,
  6456. + -1 * sp_adjust);
  6457. + }
  6458. + }
  6459. +
  6460. /* If the function is 'naked',
  6461. we do not have to generate prologue code fragment. */
  6462. - if (cfun->machine->naked_p)
  6463. + if (cfun->machine->naked_p && !flag_pic)
  6464. return;
  6465. /* Get callee_first_regno and callee_last_regno. */
  6466. - Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
  6467. - Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
  6468. -
  6469. - /* push_insn = gen_stack_push_multiple(first_regno, last_regno),
  6470. - the pattern 'stack_push_multiple' is implemented in nds32.md.
  6471. - For En4 field, we have to calculate its constant value.
  6472. - Refer to Andes ISA for more information. */
  6473. - en4_const = 0;
  6474. - if (cfun->machine->fp_size)
  6475. - en4_const += 8;
  6476. - if (cfun->machine->gp_size)
  6477. - en4_const += 4;
  6478. - if (cfun->machine->lp_size)
  6479. - en4_const += 2;
  6480. + Rb = cfun->machine->callee_saved_first_gpr_regno;
  6481. + Re = cfun->machine->callee_saved_last_gpr_regno;
  6482. /* If $fp, $gp, $lp, and all callee-save registers are NOT required
  6483. to be saved, we don't have to create multiple push instruction.
  6484. Otherwise, a multiple push instruction is needed. */
  6485. - if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0))
  6486. + if (!(Rb == SP_REGNUM && Re == SP_REGNUM
  6487. + && cfun->machine->fp_size == 0
  6488. + && cfun->machine->gp_size == 0
  6489. + && cfun->machine->lp_size == 0))
  6490. {
  6491. /* Create multiple push instruction rtx. */
  6492. - push_insn = nds32_gen_stack_push_multiple (Rb, Re, GEN_INT (en4_const));
  6493. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6494. - push_insn = emit_insn (push_insn);
  6495. + nds32_emit_stack_push_multiple (
  6496. + Rb, Re,
  6497. + cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size,
  6498. + false);
  6499. + }
  6500. +
  6501. + /* Save eh data registers. */
  6502. + if (cfun->machine->use_eh_return_p)
  6503. + {
  6504. + Rb = cfun->machine->eh_return_data_first_regno;
  6505. + Re = cfun->machine->eh_return_data_last_regno;
  6506. - /* The insn rtx 'push_insn' will change frame layout.
  6507. - We need to use RTX_FRAME_RELATED_P so that GCC is able to
  6508. - generate CFI (Call Frame Information) stuff. */
  6509. - RTX_FRAME_RELATED_P (push_insn) = 1;
  6510. + /* No need to push $fp, $gp, or $lp.
  6511. + Also, this is not variadic arguments push. */
  6512. + nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false);
  6513. }
  6514. /* Check frame_pointer_needed to see
  6515. @@ -3611,1824 +5137,830 @@
  6516. if (frame_pointer_needed)
  6517. {
  6518. /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
  6519. - + (4 * callee-saved-registers)
  6520. - Note: No need to adjust
  6521. - cfun->machine->callee_saved_area_padding_bytes,
  6522. - because, at this point, stack pointer is just
  6523. - at the position after push instruction. */
  6524. + + (4 * callee-saved-registers)
  6525. + + (4 * exception-handling-data-registers)
  6526. + Note: No need to adjust
  6527. + cfun->machine->callee_saved_area_gpr_padding_bytes,
  6528. + because, at this point, stack pointer is just
  6529. + at the position after push instruction. */
  6530. fp_adjust = cfun->machine->fp_size
  6531. + cfun->machine->gp_size
  6532. + cfun->machine->lp_size
  6533. - + cfun->machine->callee_saved_regs_size;
  6534. - fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
  6535. - stack_pointer_rtx,
  6536. - GEN_INT (fp_adjust));
  6537. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6538. - fp_adjust_insn = emit_insn (fp_adjust_insn);
  6539. + + cfun->machine->callee_saved_gpr_regs_size
  6540. + + cfun->machine->eh_return_data_regs_size;
  6541. +
  6542. + nds32_emit_adjust_frame (hard_frame_pointer_rtx,
  6543. + stack_pointer_rtx,
  6544. + fp_adjust);
  6545. }
  6546. - /* Adjust $sp = $sp - local_size - out_args_size
  6547. - - callee_saved_area_padding_bytes. */
  6548. - sp_adjust = cfun->machine->local_size
  6549. - + cfun->machine->out_args_size
  6550. - + cfun->machine->callee_saved_area_padding_bytes;
  6551. - /* sp_adjust value may be out of range of the addi instruction,
  6552. - create alternative add behavior with TA_REGNUM if necessary,
  6553. - using NEGATIVE value to tell that we are decreasing address. */
  6554. - sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust);
  6555. - if (sp_adjust)
  6556. + /* Save fpu registers. */
  6557. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  6558. {
  6559. - /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
  6560. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  6561. + /* When $sp moved to bottom of stack, we need to check whether
  6562. + the range of offset in the FPU instruction. */
  6563. + int fpr_offset = cfun->machine->local_size
  6564. + + cfun->machine->out_args_size
  6565. + + cfun->machine->callee_saved_fpr_regs_size;
  6566. +
  6567. + /* Check FPU instruction offset imm14s. */
  6568. + if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset)))
  6569. + {
  6570. + int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
  6571. + + cfun->machine->callee_saved_fpr_regs_size;
  6572. +
  6573. + /* Save fpu registers, need to allocate stack space
  6574. + for fpu callee registers. And now $sp position
  6575. + on callee saved fpr registers. */
  6576. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6577. stack_pointer_rtx,
  6578. - GEN_INT (-1 * sp_adjust));
  6579. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6580. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  6581. + -1 * fpr_space);
  6582. +
  6583. + /* Emit fpu store instruction, using [$sp + offset] store
  6584. + fpu registers. */
  6585. + nds32_emit_push_fpr_callee_saved (0);
  6586. +
  6587. + /* Adjust $sp = $sp - local_size - out_args_size. */
  6588. + sp_adjust = cfun->machine->local_size
  6589. + + cfun->machine->out_args_size;
  6590. +
  6591. + /* Allocate stack space for local size and out args size. */
  6592. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6593. + stack_pointer_rtx,
  6594. + -1 * sp_adjust);
  6595. + }
  6596. + else
  6597. + {
  6598. + /* Offset range in Is14, so $sp moved to bottom of stack. */
  6599. +
  6600. + /* Adjust $sp = $sp - local_size - out_args_size
  6601. + - callee_saved_area_gpr_padding_bytes
  6602. + - callee_saved_fpr_regs_size. */
  6603. + sp_adjust = cfun->machine->local_size
  6604. + + cfun->machine->out_args_size
  6605. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  6606. + + cfun->machine->callee_saved_fpr_regs_size;
  6607. +
  6608. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6609. + stack_pointer_rtx,
  6610. + -1 * sp_adjust);
  6611. - /* The insn rtx 'sp_adjust_insn' will change frame layout.
  6612. - We need to use RTX_FRAME_RELATED_P so that GCC is able to
  6613. - generate CFI (Call Frame Information) stuff. */
  6614. - RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
  6615. + /* Emit fpu store instruction, using [$sp + offset] store
  6616. + fpu registers. */
  6617. + int fpr_position = cfun->machine->out_args_size
  6618. + + cfun->machine->local_size;
  6619. + nds32_emit_push_fpr_callee_saved (fpr_position);
  6620. + }
  6621. }
  6622. + else
  6623. + {
  6624. + /* Adjust $sp = $sp - local_size - out_args_size
  6625. + - callee_saved_area_gpr_padding_bytes. */
  6626. + sp_adjust = cfun->machine->local_size
  6627. + + cfun->machine->out_args_size
  6628. + + cfun->machine->callee_saved_area_gpr_padding_bytes;
  6629. - /* Prevent the instruction scheduler from
  6630. - moving instructions across the boundary. */
  6631. - emit_insn (gen_blockage ());
  6632. + /* sp_adjust value may be out of range of the addi instruction,
  6633. + create alternative add behavior with TA_REGNUM if necessary,
  6634. + using NEGATIVE value to tell that we are decreasing address. */
  6635. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6636. + stack_pointer_rtx,
  6637. + -1 * sp_adjust);
  6638. + }
  6639. +
  6640. + /* Emit gp setup instructions for -fpic. */
  6641. + if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
  6642. + nds32_emit_load_gp ();
  6643. +
  6644. + /* If user applies -mno-sched-prolog-epilog option,
  6645. + we need to prevent instructions of function body from being
  6646. + scheduled with stack adjustment in prologue. */
  6647. + if (!flag_sched_prolog_epilog)
  6648. + emit_insn (gen_blockage ());
  6649. }
  6650. /* Function for normal multiple pop epilogue. */
  6651. void
  6652. -nds32_expand_epilogue (void)
  6653. +nds32_expand_epilogue (bool sibcall_p)
  6654. {
  6655. int sp_adjust;
  6656. - int en4_const;
  6657. -
  6658. - rtx Rb, Re;
  6659. - rtx pop_insn;
  6660. - rtx sp_adjust_insn;
  6661. + unsigned Rb, Re;
  6662. /* Compute and setup stack frame size.
  6663. The result will be in cfun->machine. */
  6664. nds32_compute_stack_frame ();
  6665. - /* Prevent the instruction scheduler from
  6666. - moving instructions across the boundary. */
  6667. - emit_insn (gen_blockage ());
  6668. + /* If user applies -mno-sched-prolog-epilog option,
  6669. + we need to prevent instructions of function body from being
  6670. + scheduled with stack adjustment in epilogue. */
  6671. + if (!flag_sched_prolog_epilog)
  6672. + emit_insn (gen_blockage ());
  6673. /* If the function is 'naked', we do not have to generate
  6674. - epilogue code fragment BUT 'ret' instruction. */
  6675. + epilogue code fragment BUT 'ret' instruction.
  6676. + However, if this function is also a variadic function,
  6677. + we need to create adjust stack pointer before 'ret' instruction. */
  6678. if (cfun->machine->naked_p)
  6679. {
  6680. - /* Generate return instruction by using
  6681. - unspec_volatile_func_return pattern.
  6682. - Make sure this instruction is after gen_blockage().
  6683. - NOTE that $lp will become 'live'
  6684. - after this instruction has been emitted. */
  6685. - emit_insn (gen_unspec_volatile_func_return ());
  6686. + /* If this is a variadic function, we do not have to restore argument
  6687. + registers but need to adjust stack pointer back to previous stack
  6688. + frame location before return. */
  6689. + if (cfun->machine->va_args_size != 0)
  6690. + {
  6691. + /* Generate sp adjustment instruction.
  6692. + We need to consider padding bytes here. */
  6693. + sp_adjust = cfun->machine->va_args_size
  6694. + + cfun->machine->va_args_area_padding_bytes;
  6695. +
  6696. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6697. + stack_pointer_rtx,
  6698. + sp_adjust);
  6699. + }
  6700. +
  6701. + /* Generate return instruction by using 'return_internal' pattern.
  6702. + Make sure this instruction is after gen_blockage().
  6703. + First we need to check this is a function without sibling call. */
  6704. + if (!sibcall_p)
  6705. + {
  6706. + /* We need to further check attributes to determine whether
  6707. + there should be return instruction at epilogue.
  6708. + If the attribute naked exists but -mno-ret-in-naked-func
  6709. + is issued, there is NO need to generate return instruction. */
  6710. + if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func)
  6711. + return;
  6712. +
  6713. + emit_jump_insn (gen_return_internal ());
  6714. + }
  6715. return;
  6716. }
  6717. if (frame_pointer_needed)
  6718. {
  6719. - /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
  6720. - - (4 * callee-saved-registers)
  6721. - Note: No need to adjust
  6722. - cfun->machine->callee_saved_area_padding_bytes,
  6723. - because we want to adjust stack pointer
  6724. - to the position for pop instruction. */
  6725. - sp_adjust = cfun->machine->fp_size
  6726. - + cfun->machine->gp_size
  6727. - + cfun->machine->lp_size
  6728. - + cfun->machine->callee_saved_regs_size;
  6729. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  6730. - hard_frame_pointer_rtx,
  6731. - GEN_INT (-1 * sp_adjust));
  6732. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6733. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  6734. - }
  6735. - else
  6736. - {
  6737. - /* If frame pointer is NOT needed,
  6738. - we cannot calculate the sp adjustment from frame pointer.
  6739. - Instead, we calculate the adjustment by local_size,
  6740. - out_args_size, and callee_saved_area_padding_bytes.
  6741. - Notice that such sp adjustment value may be out of range,
  6742. - so we have to deal with it as well. */
  6743. -
  6744. - /* Adjust $sp = $sp + local_size + out_args_size
  6745. - + callee_saved_area_padding_bytes. */
  6746. - sp_adjust = cfun->machine->local_size
  6747. - + cfun->machine->out_args_size
  6748. - + cfun->machine->callee_saved_area_padding_bytes;
  6749. - /* sp_adjust value may be out of range of the addi instruction,
  6750. - create alternative add behavior with TA_REGNUM if necessary,
  6751. - using POSITIVE value to tell that we are increasing address. */
  6752. - sp_adjust = nds32_force_addi_stack_int (sp_adjust);
  6753. - if (sp_adjust)
  6754. - {
  6755. - /* Generate sp adjustment instruction
  6756. - if and only if sp_adjust != 0. */
  6757. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  6758. - stack_pointer_rtx,
  6759. - GEN_INT (sp_adjust));
  6760. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6761. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  6762. - }
  6763. - }
  6764. -
  6765. - /* Get callee_first_regno and callee_last_regno. */
  6766. - Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
  6767. - Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
  6768. -
  6769. - /* pop_insn = gen_stack_pop_multiple(first_regno, last_regno),
  6770. - the pattern 'stack_pop_multiple' is implementad in nds32.md.
  6771. - For En4 field, we have to calculate its constant value.
  6772. - Refer to Andes ISA for more information. */
  6773. - en4_const = 0;
  6774. - if (cfun->machine->fp_size)
  6775. - en4_const += 8;
  6776. - if (cfun->machine->gp_size)
  6777. - en4_const += 4;
  6778. - if (cfun->machine->lp_size)
  6779. - en4_const += 2;
  6780. -
  6781. - /* If $fp, $gp, $lp, and all callee-save registers are NOT required
  6782. - to be saved, we don't have to create multiple pop instruction.
  6783. - Otherwise, a multiple pop instruction is needed. */
  6784. - if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0))
  6785. - {
  6786. - /* Create multiple pop instruction rtx. */
  6787. - pop_insn = nds32_gen_stack_pop_multiple (Rb, Re, GEN_INT (en4_const));
  6788. - /* Emit pop instruction. */
  6789. - emit_insn (pop_insn);
  6790. - }
  6791. -
  6792. - /* Generate return instruction by using
  6793. - unspec_volatile_func_return pattern. */
  6794. - emit_insn (gen_unspec_volatile_func_return ());
  6795. -}
  6796. -
  6797. -/* Function for v3push prologue. */
  6798. -void
  6799. -nds32_expand_prologue_v3push (void)
  6800. -{
  6801. - int fp_adjust;
  6802. - int sp_adjust;
  6803. -
  6804. - rtx Rb, Re;
  6805. - rtx push_insn;
  6806. - rtx fp_adjust_insn, sp_adjust_insn;
  6807. -
  6808. - /* Before computing everything for stack frame size,
  6809. - we check if it is still worth to use fp_as_gp optimization.
  6810. - If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
  6811. - so that $fp will be saved on stack. */
  6812. - cfun->machine->fp_as_gp_p = nds32_fp_as_gp_check_available ();
  6813. -
  6814. - /* Compute and setup stack frame size.
  6815. - The result will be in cfun->machine. */
  6816. - nds32_compute_stack_frame ();
  6817. -
  6818. - /* If the function is 'naked',
  6819. - we do not have to generate prologue code fragment. */
  6820. - if (cfun->machine->naked_p)
  6821. - return;
  6822. -
  6823. - /* Get callee_first_regno and callee_last_regno. */
  6824. - Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
  6825. - Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
  6826. -
  6827. - /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
  6828. - where imm8u has to be 8-byte alignment. */
  6829. - sp_adjust = cfun->machine->local_size
  6830. - + cfun->machine->out_args_size
  6831. - + cfun->machine->callee_saved_area_padding_bytes;
  6832. -
  6833. - if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  6834. - && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
  6835. - {
  6836. - /* We can use 'push25 Re,imm8u'. */
  6837. -
  6838. - /* push_insn = gen_stack_v3push(last_regno, sp_adjust),
  6839. - the pattern 'stack_v3push' is implemented in nds32.md.
  6840. - The (const_int 14) means v3push always push { $fp $gp $lp }. */
  6841. - push_insn = nds32_gen_stack_v3push (Rb, Re,
  6842. - GEN_INT (14), GEN_INT (sp_adjust));
  6843. - /* emit rtx into instructions list and receive INSN rtx form */
  6844. - push_insn = emit_insn (push_insn);
  6845. -
  6846. - /* The insn rtx 'push_insn' will change frame layout.
  6847. - We need to use RTX_FRAME_RELATED_P so that GCC is able to
  6848. - generate CFI (Call Frame Information) stuff. */
  6849. - RTX_FRAME_RELATED_P (push_insn) = 1;
  6850. -
  6851. - /* Check frame_pointer_needed to see
  6852. - if we shall emit fp adjustment instruction. */
  6853. - if (frame_pointer_needed)
  6854. + /* Restore fpu registers. */
  6855. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  6856. {
  6857. - /* adjust $fp = $sp + 4 ($fp size)
  6858. - + 4 ($gp size)
  6859. - + 4 ($lp size)
  6860. - + (4 * n) (callee-saved registers)
  6861. - + sp_adjust ('push25 Re,imm8u')
  6862. - Note: Since we use 'push25 Re,imm8u',
  6863. - the position of stack pointer is further
  6864. - changed after push instruction.
  6865. - Hence, we need to take sp_adjust value
  6866. - into consideration. */
  6867. - fp_adjust = cfun->machine->fp_size
  6868. + int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes;
  6869. +
  6870. + /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
  6871. + - (4 * callee-saved-registers)
  6872. + - (4 * exception-handling-data-registers)
  6873. + - (4 * callee-saved-gpr-registers padding byte)
  6874. + - (4 * callee-saved-fpr-registers)
  6875. + Note: we want to adjust stack pointer
  6876. + to the position for callee-saved fpr register,
  6877. + And restore fpu register use .bi instruction to adjust $sp
  6878. + from callee-saved fpr register to pop instruction. */
  6879. + sp_adjust = cfun->machine->fp_size
  6880. + cfun->machine->gp_size
  6881. + cfun->machine->lp_size
  6882. - + cfun->machine->callee_saved_regs_size
  6883. - + sp_adjust;
  6884. - fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
  6885. - stack_pointer_rtx,
  6886. - GEN_INT (fp_adjust));
  6887. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6888. - fp_adjust_insn = emit_insn (fp_adjust_insn);
  6889. - }
  6890. - }
  6891. - else
  6892. - {
  6893. - /* We have to use 'push25 Re,0' and
  6894. - expand one more instruction to adjust $sp later. */
  6895. -
  6896. - /* push_insn = gen_stack_v3push(last_regno, sp_adjust),
  6897. - the pattern 'stack_v3push' is implemented in nds32.md.
  6898. - The (const_int 14) means v3push always push { $fp $gp $lp }. */
  6899. - push_insn = nds32_gen_stack_v3push (Rb, Re,
  6900. - GEN_INT (14), GEN_INT (0));
  6901. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6902. - push_insn = emit_insn (push_insn);
  6903. + + cfun->machine->callee_saved_gpr_regs_size
  6904. + + cfun->machine->eh_return_data_regs_size
  6905. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  6906. + + cfun->machine->callee_saved_fpr_regs_size;
  6907. - /* The insn rtx 'push_insn' will change frame layout.
  6908. - We need to use RTX_FRAME_RELATED_P so that GCC is able to
  6909. - generate CFI (Call Frame Information) stuff. */
  6910. - RTX_FRAME_RELATED_P (push_insn) = 1;
  6911. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6912. + hard_frame_pointer_rtx,
  6913. + -1 * sp_adjust);
  6914. - /* Check frame_pointer_needed to see
  6915. - if we shall emit fp adjustment instruction. */
  6916. - if (frame_pointer_needed)
  6917. + /* Emit fpu load instruction, using .bi instruction
  6918. + load fpu registers. */
  6919. + nds32_emit_pop_fpr_callee_saved (gpr_padding);
  6920. + }
  6921. + else
  6922. {
  6923. - /* adjust $fp = $sp + 4 ($fp size)
  6924. - + 4 ($gp size)
  6925. - + 4 ($lp size)
  6926. - + (4 * n) (callee-saved registers)
  6927. - Note: Since we use 'push25 Re,0',
  6928. - the stack pointer is just at the position
  6929. - after push instruction.
  6930. - No need to take sp_adjust into consideration. */
  6931. - fp_adjust = cfun->machine->fp_size
  6932. + /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
  6933. + - (4 * callee-saved-registers)
  6934. + - (4 * exception-handling-data-registers)
  6935. + Note: No need to adjust
  6936. + cfun->machine->callee_saved_area_gpr_padding_bytes,
  6937. + because we want to adjust stack pointer
  6938. + to the position for pop instruction. */
  6939. + sp_adjust = cfun->machine->fp_size
  6940. + cfun->machine->gp_size
  6941. + cfun->machine->lp_size
  6942. - + cfun->machine->callee_saved_regs_size;
  6943. - fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
  6944. - stack_pointer_rtx,
  6945. - GEN_INT (fp_adjust));
  6946. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6947. - fp_adjust_insn = emit_insn (fp_adjust_insn);
  6948. - }
  6949. + + cfun->machine->callee_saved_gpr_regs_size
  6950. + + cfun->machine->eh_return_data_regs_size;
  6951. - /* Because we use 'push25 Re,0',
  6952. - we need to expand one more instruction to adjust $sp.
  6953. - However, sp_adjust value may be out of range of the addi instruction,
  6954. - create alternative add behavior with TA_REGNUM if necessary,
  6955. - using NEGATIVE value to tell that we are decreasing address. */
  6956. - sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust);
  6957. - if (sp_adjust)
  6958. - {
  6959. - /* Generate sp adjustment instruction
  6960. - if and only if sp_adjust != 0. */
  6961. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  6962. - stack_pointer_rtx,
  6963. - GEN_INT (-1 * sp_adjust));
  6964. - /* Emit rtx into instructions list and receive INSN rtx form. */
  6965. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  6966. -
  6967. - /* The insn rtx 'sp_adjust_insn' will change frame layout.
  6968. - We need to use RTX_FRAME_RELATED_P so that GCC is able to
  6969. - generate CFI (Call Frame Information) stuff. */
  6970. - RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
  6971. + nds32_emit_adjust_frame (stack_pointer_rtx,
  6972. + hard_frame_pointer_rtx,
  6973. + -1 * sp_adjust);
  6974. }
  6975. }
  6976. -
  6977. - /* Prevent the instruction scheduler from
  6978. - moving instructions across the boundary. */
  6979. - emit_insn (gen_blockage ());
  6980. -}
  6981. -
  6982. -/* Function for v3pop epilogue. */
  6983. -void
  6984. -nds32_expand_epilogue_v3pop (void)
  6985. -{
  6986. - int sp_adjust;
  6987. -
  6988. - rtx Rb, Re;
  6989. - rtx pop_insn;
  6990. - rtx sp_adjust_insn;
  6991. -
  6992. - /* Compute and setup stack frame size.
  6993. - The result will be in cfun->machine. */
  6994. - nds32_compute_stack_frame ();
  6995. -
  6996. - /* Prevent the instruction scheduler from
  6997. - moving instructions across the boundary. */
  6998. - emit_insn (gen_blockage ());
  6999. -
  7000. - /* If the function is 'naked', we do not have to generate
  7001. - epilogue code fragment BUT 'ret' instruction. */
  7002. - if (cfun->machine->naked_p)
  7003. - {
  7004. - /* Generate return instruction by using
  7005. - unspec_volatile_func_return pattern.
  7006. - Make sure this instruction is after gen_blockage().
  7007. - NOTE that $lp will become 'live'
  7008. - after this instruction has been emitted. */
  7009. - emit_insn (gen_unspec_volatile_func_return ());
  7010. - return;
  7011. - }
  7012. -
  7013. - /* Get callee_first_regno and callee_last_regno. */
  7014. - Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
  7015. - Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
  7016. -
  7017. - /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
  7018. - where imm8u has to be 8-byte alignment. */
  7019. - sp_adjust = cfun->machine->local_size
  7020. - + cfun->machine->out_args_size
  7021. - + cfun->machine->callee_saved_area_padding_bytes;
  7022. -
  7023. - /* We have to consider alloca issue as well.
  7024. - If the function does call alloca(), the stack pointer is not fixed.
  7025. - In that case, we cannot use 'pop25 Re,imm8u' directly.
  7026. - We have to caculate stack pointer from frame pointer
  7027. - and then use 'pop25 Re,0'.
  7028. - Of course, the frame_pointer_needed should be nonzero
  7029. - if the function calls alloca(). */
  7030. - if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  7031. - && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  7032. - && !cfun->calls_alloca)
  7033. + else
  7034. {
  7035. - /* We can use 'pop25 Re,imm8u'. */
  7036. + /* Restore fpu registers. */
  7037. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  7038. + {
  7039. + int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes;
  7040. - /* pop_insn = gen_stack_v3pop(last_regno, sp_adjust),
  7041. - the pattern 'stack_v3pop' is implementad in nds32.md.
  7042. - The (const_int 14) means v3pop always pop { $fp $gp $lp }. */
  7043. - pop_insn = nds32_gen_stack_v3pop (Rb, Re,
  7044. - GEN_INT (14), GEN_INT (sp_adjust));
  7045. + /* Adjust $sp = $sp + local_size + out_args_size. */
  7046. + sp_adjust = cfun->machine->local_size
  7047. + + cfun->machine->out_args_size;
  7048. - /* Emit pop instruction. */
  7049. - emit_insn (pop_insn);
  7050. - }
  7051. - else
  7052. - {
  7053. - /* We have to use 'pop25 Re,0', and prior to it,
  7054. - we must expand one more instruction to adjust $sp. */
  7055. + nds32_emit_adjust_frame (stack_pointer_rtx,
  7056. + stack_pointer_rtx,
  7057. + sp_adjust);
  7058. - if (frame_pointer_needed)
  7059. - {
  7060. - /* adjust $sp = $fp - 4 ($fp size)
  7061. - - 4 ($gp size)
  7062. - - 4 ($lp size)
  7063. - - (4 * n) (callee-saved registers)
  7064. - Note: No need to adjust
  7065. - cfun->machine->callee_saved_area_padding_bytes,
  7066. - because we want to adjust stack pointer
  7067. - to the position for pop instruction. */
  7068. - sp_adjust = cfun->machine->fp_size
  7069. - + cfun->machine->gp_size
  7070. - + cfun->machine->lp_size
  7071. - + cfun->machine->callee_saved_regs_size;
  7072. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  7073. - hard_frame_pointer_rtx,
  7074. - GEN_INT (-1 * sp_adjust));
  7075. - /* Emit rtx into instructions list and receive INSN rtx form. */
  7076. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  7077. + /* Emit fpu load instruction, using .bi instruction
  7078. + load fpu registers, and adjust $sp from callee-saved fpr register
  7079. + to callee-saved gpr register. */
  7080. + nds32_emit_pop_fpr_callee_saved (gpr_padding);
  7081. }
  7082. else
  7083. {
  7084. /* If frame pointer is NOT needed,
  7085. we cannot calculate the sp adjustment from frame pointer.
  7086. Instead, we calculate the adjustment by local_size,
  7087. - out_args_size, and callee_saved_area_padding_bytes.
  7088. + out_args_size, and callee_saved_area_gpr_padding_bytes.
  7089. Notice that such sp adjustment value may be out of range,
  7090. so we have to deal with it as well. */
  7091. /* Adjust $sp = $sp + local_size + out_args_size
  7092. - + callee_saved_area_padding_bytes. */
  7093. + + callee_saved_area_gpr_padding_bytes. */
  7094. sp_adjust = cfun->machine->local_size
  7095. + cfun->machine->out_args_size
  7096. - + cfun->machine->callee_saved_area_padding_bytes;
  7097. - /* sp_adjust value may be out of range of the addi instruction,
  7098. - create alternative add behavior with TA_REGNUM if necessary,
  7099. - using POSITIVE value to tell that we are increasing address. */
  7100. - sp_adjust = nds32_force_addi_stack_int (sp_adjust);
  7101. - if (sp_adjust)
  7102. - {
  7103. - /* Generate sp adjustment instruction
  7104. - if and only if sp_adjust != 0. */
  7105. - sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
  7106. - stack_pointer_rtx,
  7107. - GEN_INT (sp_adjust));
  7108. - /* Emit rtx into instructions list and receive INSN rtx form. */
  7109. - sp_adjust_insn = emit_insn (sp_adjust_insn);
  7110. - }
  7111. - }
  7112. -
  7113. - /* pop_insn = gen_stack_v3pop(last_regno, sp_adjust),
  7114. - the pattern 'stack_v3pop' is implementad in nds32.md. */
  7115. - /* The (const_int 14) means v3pop always pop { $fp $gp $lp }. */
  7116. - pop_insn = nds32_gen_stack_v3pop (Rb, Re,
  7117. - GEN_INT (14), GEN_INT (0));
  7118. + + cfun->machine->callee_saved_area_gpr_padding_bytes;
  7119. - /* Emit pop instruction. */
  7120. - emit_insn (pop_insn);
  7121. + nds32_emit_adjust_frame (stack_pointer_rtx,
  7122. + stack_pointer_rtx,
  7123. + sp_adjust);
  7124. + }
  7125. }
  7126. -}
  7127. -/* ------------------------------------------------------------------------ */
  7128. -
  7129. -/* Function to test 333-form for load/store instructions.
  7130. - This is auxiliary extern function for auxiliary macro in nds32.h.
  7131. - Because it is a little complicated, we use function instead of macro. */
  7132. -bool
  7133. -nds32_ls_333_p (rtx rt, rtx ra, rtx imm, enum machine_mode mode)
  7134. -{
  7135. - if (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS
  7136. - && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  7137. + /* Restore eh data registers. */
  7138. + if (cfun->machine->use_eh_return_p)
  7139. {
  7140. - if (GET_MODE_SIZE (mode) == 4)
  7141. - return satisfies_constraint_Iu05 (imm);
  7142. + Rb = cfun->machine->eh_return_data_first_regno;
  7143. + Re = cfun->machine->eh_return_data_last_regno;
  7144. - if (GET_MODE_SIZE (mode) == 2)
  7145. - return satisfies_constraint_Iu04 (imm);
  7146. -
  7147. - if (GET_MODE_SIZE (mode) == 1)
  7148. - return satisfies_constraint_Iu03 (imm);
  7149. + /* No need to pop $fp, $gp, or $lp. */
  7150. + nds32_emit_stack_pop_multiple (Rb, Re, false, false, false);
  7151. }
  7152. - return false;
  7153. -}
  7154. -
  7155. -
  7156. -/* Functions to expand load_multiple and store_multiple.
  7157. - They are auxiliary extern functions to help create rtx template.
  7158. - Check nds32-multiple.md file for the patterns. */
  7159. -rtx
  7160. -nds32_expand_load_multiple (int base_regno, int count,
  7161. - rtx base_addr, rtx basemem)
  7162. -{
  7163. - int par_index;
  7164. - int offset;
  7165. - rtx result;
  7166. - rtx new_addr, mem, reg;
  7167. -
  7168. - /* Create the pattern that is presented in nds32-multiple.md. */
  7169. -
  7170. - result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  7171. + /* Get callee_first_regno and callee_last_regno. */
  7172. + Rb = cfun->machine->callee_saved_first_gpr_regno;
  7173. + Re = cfun->machine->callee_saved_last_gpr_regno;
  7174. - for (par_index = 0; par_index < count; par_index++)
  7175. + /* If $fp, $gp, $lp, and all callee-save registers are NOT required
  7176. + to be saved, we don't have to create multiple pop instruction.
  7177. + Otherwise, a multiple pop instruction is needed. */
  7178. + if (!(Rb == SP_REGNUM && Re == SP_REGNUM
  7179. + && cfun->machine->fp_size == 0
  7180. + && cfun->machine->gp_size == 0
  7181. + && cfun->machine->lp_size == 0))
  7182. {
  7183. - offset = par_index * 4;
  7184. - /* 4-byte for loading data to each register. */
  7185. - new_addr = plus_constant (Pmode, base_addr, offset);
  7186. - mem = adjust_automodify_address_nv (basemem, SImode,
  7187. - new_addr, offset);
  7188. - reg = gen_rtx_REG (SImode, base_regno + par_index);
  7189. -
  7190. - XVECEXP (result, 0, par_index) = gen_rtx_SET (VOIDmode, reg, mem);
  7191. + /* Create multiple pop instruction rtx. */
  7192. + nds32_emit_stack_pop_multiple (
  7193. + Rb, Re,
  7194. + cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size);
  7195. }
  7196. - return result;
  7197. -}
  7198. -
  7199. -rtx
  7200. -nds32_expand_store_multiple (int base_regno, int count,
  7201. - rtx base_addr, rtx basemem)
  7202. -{
  7203. - int par_index;
  7204. - int offset;
  7205. - rtx result;
  7206. - rtx new_addr, mem, reg;
  7207. -
  7208. - /* Create the pattern that is presented in nds32-multiple.md. */
  7209. -
  7210. - result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  7211. -
  7212. - for (par_index = 0; par_index < count; par_index++)
  7213. + /* If this is a variadic function, we do not have to restore argument
  7214. + registers but need to adjust stack pointer back to previous stack
  7215. + frame location before return. */
  7216. + if (cfun->machine->va_args_size != 0)
  7217. {
  7218. - offset = par_index * 4;
  7219. - /* 4-byte for storing data to memory. */
  7220. - new_addr = plus_constant (Pmode, base_addr, offset);
  7221. - mem = adjust_automodify_address_nv (basemem, SImode,
  7222. - new_addr, offset);
  7223. - reg = gen_rtx_REG (SImode, base_regno + par_index);
  7224. + /* Generate sp adjustment instruction.
  7225. + We need to consider padding bytes here. */
  7226. + sp_adjust = cfun->machine->va_args_size
  7227. + + cfun->machine->va_args_area_padding_bytes;
  7228. - XVECEXP (result, 0, par_index) = gen_rtx_SET (VOIDmode, mem, reg);
  7229. + nds32_emit_adjust_frame (stack_pointer_rtx,
  7230. + stack_pointer_rtx,
  7231. + sp_adjust);
  7232. }
  7233. - return result;
  7234. -}
  7235. -
  7236. -/* Function to move block memory content by
  7237. - using load_multiple and store_multiple.
  7238. - This is auxiliary extern function to help create rtx template.
  7239. - Check nds32-multiple.md file for the patterns. */
  7240. -int
  7241. -nds32_expand_movmemqi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
  7242. -{
  7243. - HOST_WIDE_INT in_words, out_words;
  7244. - rtx dst_base_reg, src_base_reg;
  7245. - int maximum_bytes;
  7246. -
  7247. - /* Because reduced-set regsiters has few registers
  7248. - (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31'
  7249. - cannot be used for register allocation),
  7250. - using 8 registers (32 bytes) for moving memory block
  7251. - may easily consume all of them.
  7252. - It makes register allocation/spilling hard to work.
  7253. - So we only allow maximum=4 registers (16 bytes) for
  7254. - moving memory block under reduced-set registers. */
  7255. - if (TARGET_REDUCED_REGS)
  7256. - maximum_bytes = 16;
  7257. - else
  7258. - maximum_bytes = 32;
  7259. -
  7260. - /* 1. Total_bytes is integer for sure.
  7261. - 2. Alignment is integer for sure.
  7262. - 3. Maximum 4 or 8 registers, 4 * 4 = 16 bytes, 8 * 4 = 32 bytes.
  7263. - 4. Requires (n * 4) block size.
  7264. - 5. Requires 4-byte alignment. */
  7265. - if (GET_CODE (total_bytes) != CONST_INT
  7266. - || GET_CODE (alignment) != CONST_INT
  7267. - || INTVAL (total_bytes) > maximum_bytes
  7268. - || INTVAL (total_bytes) & 3
  7269. - || INTVAL (alignment) & 3)
  7270. - return 0;
  7271. -
  7272. - dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
  7273. - src_base_reg = copy_to_mode_reg (SImode, XEXP (srcmem, 0));
  7274. -
  7275. - out_words = in_words = INTVAL (total_bytes) / UNITS_PER_WORD;
  7276. -
  7277. - emit_insn (nds32_expand_load_multiple (0, in_words, src_base_reg, srcmem));
  7278. - emit_insn (nds32_expand_store_multiple (0, out_words, dst_base_reg, dstmem));
  7279. -
  7280. - /* Successfully create patterns, return 1. */
  7281. - return 1;
  7282. -}
  7283. -
  7284. -/* Function to check whether the OP is a valid load/store operation.
  7285. - This is a helper function for the predicates:
  7286. - 'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
  7287. - in predicates.md file.
  7288. -
  7289. - The OP is supposed to be a parallel rtx.
  7290. - For each element within this parallel rtx:
  7291. - (set (reg) (mem addr)) is the form for load operation.
  7292. - (set (mem addr) (reg)) is the form for store operation.
  7293. - We have to extract reg and mem of every element and
  7294. - check if the information is valid for multiple load/store operation. */
  7295. -bool
  7296. -nds32_valid_multiple_load_store (rtx op, bool load_p)
  7297. -{
  7298. - int count;
  7299. - int first_elt_regno;
  7300. - rtx elt;
  7301. -
  7302. - /* Get the counts of elements in the parallel rtx. */
  7303. - count = XVECLEN (op, 0);
  7304. - /* Pick up the first element. */
  7305. - elt = XVECEXP (op, 0, 0);
  7306. -
  7307. - /* Perform some quick check for the first element in the parallel rtx. */
  7308. - if (GET_CODE (elt) != SET
  7309. - || count <= 1
  7310. - || count > 8)
  7311. - return false;
  7312. -
  7313. - /* Pick up regno of first element for further detail checking.
  7314. - Note that the form is different between load and store operation. */
  7315. - if (load_p)
  7316. - {
  7317. - if (GET_CODE (SET_DEST (elt)) != REG
  7318. - || GET_CODE (SET_SRC (elt)) != MEM)
  7319. - return false;
  7320. -
  7321. - first_elt_regno = REGNO (SET_DEST (elt));
  7322. - }
  7323. - else
  7324. + /* If this function uses __builtin_eh_return, make stack adjustment
  7325. + for exception handler. */
  7326. + if (cfun->machine->use_eh_return_p)
  7327. {
  7328. - if (GET_CODE (SET_SRC (elt)) != REG
  7329. - || GET_CODE (SET_DEST (elt)) != MEM)
  7330. - return false;
  7331. -
  7332. - first_elt_regno = REGNO (SET_SRC (elt));
  7333. - }
  7334. -
  7335. - /* Perform detail check for each element.
  7336. - Refer to nds32-multiple.md for more information
  7337. - about following checking.
  7338. - The starting element of parallel rtx is index 0. */
  7339. - if (!nds32_consecutive_registers_load_store_p (op, load_p, 0,
  7340. - first_elt_regno,
  7341. - count))
  7342. - return false;
  7343. -
  7344. - /* Pass all test, this is a valid rtx. */
  7345. - return true;
  7346. -}
  7347. -
  7348. -/* Function to check whether the OP is a valid stack push/pop operation.
  7349. - For a valid stack operation, it must satisfy following conditions:
  7350. - 1. Consecutive registers push/pop operations.
  7351. - 2. Valid $fp/$gp/$lp push/pop operations.
  7352. - 3. The last element must be stack adjustment rtx.
  7353. - See the prologue/epilogue implementation for details. */
  7354. -bool
  7355. -nds32_valid_stack_push_pop (rtx op, bool push_p)
  7356. -{
  7357. - int index;
  7358. - int total_count;
  7359. - int rest_count;
  7360. - int first_regno;
  7361. - rtx elt;
  7362. - rtx elt_reg;
  7363. - rtx elt_mem;
  7364. - rtx elt_plus;
  7365. + /* We need to unwind the stack by the offset computed by
  7366. + EH_RETURN_STACKADJ_RTX. However, at this point the CFA is
  7367. + based on SP. Ideally we would update the SP and define the
  7368. + CFA along the lines of:
  7369. - /* Get the counts of elements in the parallel rtx. */
  7370. - total_count = XVECLEN (op, 0);
  7371. + SP = SP + EH_RETURN_STACKADJ_RTX
  7372. + (regnote CFA = SP - EH_RETURN_STACKADJ_RTX)
  7373. - /* Perform some quick check for that every element should be 'set'. */
  7374. - for (index = 0; index < total_count; index++)
  7375. - {
  7376. - elt = XVECEXP (op, 0, index);
  7377. - if (GET_CODE (elt) != SET)
  7378. - return false;
  7379. - }
  7380. + However the dwarf emitter only understands a constant
  7381. + register offset.
  7382. - /* For push operation, the parallel rtx looks like:
  7383. - (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
  7384. - (reg:SI Rb))
  7385. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  7386. - (reg:SI Rb+1))
  7387. - ...
  7388. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  7389. - (reg:SI Re))
  7390. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  7391. - (reg:SI FP_REGNUM))
  7392. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  7393. - (reg:SI GP_REGNUM))
  7394. - (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  7395. - (reg:SI LP_REGNUM))
  7396. - (set (reg:SI SP_REGNUM)
  7397. - (plus (reg:SI SP_REGNUM) (const_int -32)))])
  7398. + The solution chosen here is to use the otherwise $ta ($r15)
  7399. + as a temporary register to hold the current SP value. The
  7400. + CFA is described using $ta then SP is modified. */
  7401. - For pop operation, the parallel rtx looks like:
  7402. - (parallel [(set (reg:SI Rb)
  7403. - (mem (reg:SI SP_REGNUM)))
  7404. - (set (reg:SI Rb+1)
  7405. - (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  7406. - ...
  7407. - (set (reg:SI Re)
  7408. - (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  7409. - (set (reg:SI FP_REGNUM)
  7410. - (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  7411. - (set (reg:SI GP_REGNUM)
  7412. - (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  7413. - (set (reg:SI LP_REGNUM)
  7414. - (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  7415. - (set (reg:SI SP_REGNUM)
  7416. - (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
  7417. -
  7418. - /* 1. Consecutive registers push/pop operations.
  7419. - We need to calculate how many registers should be consecutive.
  7420. - The $sp adjustment rtx, $fp push rtx, $gp push rtx,
  7421. - and $lp push rtx are excluded. */
  7422. -
  7423. - /* Exclude last $sp adjustment rtx. */
  7424. - rest_count = total_count - 1;
  7425. - /* Exclude $fp, $gp, and $lp if they are in the parallel rtx. */
  7426. - if (cfun->machine->fp_size)
  7427. - rest_count--;
  7428. - if (cfun->machine->gp_size)
  7429. - rest_count--;
  7430. - if (cfun->machine->lp_size)
  7431. - rest_count--;
  7432. -
  7433. - if (rest_count > 0)
  7434. - {
  7435. - elt = XVECEXP (op, 0, 0);
  7436. - /* Pick up register element. */
  7437. - elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  7438. - first_regno = REGNO (elt_reg);
  7439. -
  7440. - /* The 'push' operation is a kind of store operation.
  7441. - The 'pop' operation is a kind of load operation.
  7442. - Pass corresponding false/true as second argument (bool load_p).
  7443. - The par_index is supposed to start with index 0. */
  7444. - if (!nds32_consecutive_registers_load_store_p (op,
  7445. - !push_p ? true : false,
  7446. - 0,
  7447. - first_regno,
  7448. - rest_count))
  7449. - return false;
  7450. - }
  7451. -
  7452. - /* 2. Valid $fp/$gp/$lp push/pop operations.
  7453. - Remember to set start index for checking them. */
  7454. -
  7455. - /* The rest_count is the start index for checking $fp/$gp/$lp. */
  7456. - index = rest_count;
  7457. - /* If index < 0, this parallel rtx is definitely
  7458. - not a valid stack push/pop operation. */
  7459. - if (index < 0)
  7460. - return false;
  7461. + rtx ta_reg;
  7462. + rtx insn;
  7463. - /* Check $fp/$gp/$lp one by one.
  7464. - We use 'push_p' to pick up reg rtx and mem rtx. */
  7465. - if (cfun->machine->fp_size)
  7466. - {
  7467. - elt = XVECEXP (op, 0, index);
  7468. - elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  7469. - elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  7470. - index++;
  7471. -
  7472. - if (GET_CODE (elt_mem) != MEM
  7473. - || GET_CODE (elt_reg) != REG
  7474. - || REGNO (elt_reg) != FP_REGNUM)
  7475. - return false;
  7476. - }
  7477. - if (cfun->machine->gp_size)
  7478. - {
  7479. - elt = XVECEXP (op, 0, index);
  7480. - elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  7481. - elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  7482. - index++;
  7483. -
  7484. - if (GET_CODE (elt_mem) != MEM
  7485. - || GET_CODE (elt_reg) != REG
  7486. - || REGNO (elt_reg) != GP_REGNUM)
  7487. - return false;
  7488. - }
  7489. - if (cfun->machine->lp_size)
  7490. - {
  7491. - elt = XVECEXP (op, 0, index);
  7492. - elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  7493. - elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  7494. - index++;
  7495. -
  7496. - if (GET_CODE (elt_mem) != MEM
  7497. - || GET_CODE (elt_reg) != REG
  7498. - || REGNO (elt_reg) != LP_REGNUM)
  7499. - return false;
  7500. - }
  7501. -
  7502. - /* 3. The last element must be stack adjustment rtx.
  7503. - Its form of rtx should be:
  7504. - (set (reg:SI SP_REGNUM)
  7505. - (plus (reg:SI SP_REGNUM) (const_int X)))
  7506. - The X could be positive or negative value. */
  7507. -
  7508. - /* Pick up the last element. */
  7509. - elt = XVECEXP (op, 0, total_count - 1);
  7510. -
  7511. - /* Extract its destination and source rtx. */
  7512. - elt_reg = SET_DEST (elt);
  7513. - elt_plus = SET_SRC (elt);
  7514. -
  7515. - /* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
  7516. - if (GET_CODE (elt_reg) != REG
  7517. - || GET_CODE (elt_plus) != PLUS
  7518. - || REGNO (elt_reg) != SP_REGNUM)
  7519. - return false;
  7520. + ta_reg = gen_rtx_REG (SImode, TA_REGNUM);
  7521. - /* Pass all test, this is a valid rtx. */
  7522. - return true;
  7523. -}
  7524. + insn = emit_move_insn (ta_reg, stack_pointer_rtx);
  7525. + add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg);
  7526. + RTX_FRAME_RELATED_P (insn) = 1;
  7527. -/* Computing the Length of an Insn.
  7528. - Modifies the length assigned to instruction INSN.
  7529. - LEN is the initially computed length of the insn. */
  7530. -int
  7531. -nds32_adjust_insn_length (rtx insn, int length)
  7532. -{
  7533. - rtx src, dst;
  7534. -
  7535. - switch (recog_memoized (insn))
  7536. - {
  7537. - case CODE_FOR_move_df:
  7538. - case CODE_FOR_move_di:
  7539. - /* Adjust length of movd44 to 2. */
  7540. - src = XEXP (PATTERN (insn), 1);
  7541. - dst = XEXP (PATTERN (insn), 0);
  7542. -
  7543. - if (REG_P (src)
  7544. - && REG_P (dst)
  7545. - && (REGNO (src) % 2) == 0
  7546. - && (REGNO (dst) % 2) == 0)
  7547. - length = 2;
  7548. - break;
  7549. + emit_insn (gen_addsi3 (stack_pointer_rtx,
  7550. + stack_pointer_rtx,
  7551. + EH_RETURN_STACKADJ_RTX));
  7552. - default:
  7553. - break;
  7554. + /* Ensure the assignment to $ta does not get optimized away. */
  7555. + emit_use (ta_reg);
  7556. }
  7557. - return length;
  7558. -}
  7559. -
  7560. -
  7561. -/* Function to check if 'bclr' instruction can be used with IVAL. */
  7562. -int
  7563. -nds32_can_use_bclr_p (int ival)
  7564. -{
  7565. - int one_bit_count;
  7566. -
  7567. - /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
  7568. - it means the original ival has only one 0-bit,
  7569. - So it is ok to perform 'bclr' operation. */
  7570. -
  7571. - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
  7572. -
  7573. - /* 'bclr' is a performance extension instruction. */
  7574. - return (TARGET_PERF_EXT && (one_bit_count == 1));
  7575. -}
  7576. -
  7577. -/* Function to check if 'bset' instruction can be used with IVAL. */
  7578. -int
  7579. -nds32_can_use_bset_p (int ival)
  7580. -{
  7581. - int one_bit_count;
  7582. -
  7583. - /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
  7584. - it is ok to perform 'bset' operation. */
  7585. -
  7586. - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
  7587. -
  7588. - /* 'bset' is a performance extension instruction. */
  7589. - return (TARGET_PERF_EXT && (one_bit_count == 1));
  7590. + /* Generate return instruction. */
  7591. + if (!sibcall_p)
  7592. + emit_jump_insn (gen_return_internal ());
  7593. }
  7594. -/* Function to check if 'btgl' instruction can be used with IVAL. */
  7595. -int
  7596. -nds32_can_use_btgl_p (int ival)
  7597. -{
  7598. - int one_bit_count;
  7599. -
  7600. - /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
  7601. - it is ok to perform 'btgl' operation. */
  7602. -
  7603. - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
  7604. -
  7605. - /* 'btgl' is a performance extension instruction. */
  7606. - return (TARGET_PERF_EXT && (one_bit_count == 1));
  7607. -}
  7608. -
  7609. -/* Function to check if 'bitci' instruction can be used with IVAL. */
  7610. -int
  7611. -nds32_can_use_bitci_p (int ival)
  7612. +/* Function for v3push prologue. */
  7613. +void
  7614. +nds32_expand_prologue_v3push (void)
  7615. {
  7616. - /* If we are using V3 ISA, we have 'bitci' instruction.
  7617. - Try to see if we can present 'andi' semantic with
  7618. - such 'bit-clear-immediate' operation.
  7619. - For example, 'andi $r0,$r0,0xfffffffc' can be
  7620. - presented with 'bitci $r0,$r0,3'. */
  7621. - return (TARGET_ISA_V3
  7622. - && (ival < 0)
  7623. - && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
  7624. -}
  7625. -
  7626. + int fp_adjust;
  7627. + int sp_adjust;
  7628. + int fpr_space = 0;
  7629. + unsigned Rb, Re;
  7630. -/* Return true if is load/store with SYMBOL_REF addressing mode
  7631. - and memory mode is SImode. */
  7632. -bool
  7633. -nds32_symbol_load_store_p (rtx insn)
  7634. -{
  7635. - rtx mem_src = NULL_RTX;
  7636. + /* Compute and setup stack frame size.
  7637. + The result will be in cfun->machine. */
  7638. + nds32_compute_stack_frame ();
  7639. - switch (get_attr_type (insn))
  7640. - {
  7641. - case TYPE_LOAD:
  7642. - mem_src = SET_SRC (PATTERN (insn));
  7643. - break;
  7644. - case TYPE_STORE:
  7645. - mem_src = SET_DEST (PATTERN (insn));
  7646. - break;
  7647. - default:
  7648. - break;
  7649. - }
  7650. + if (cfun->machine->callee_saved_gpr_regs_size > 0)
  7651. + df_set_regs_ever_live (FP_REGNUM, 1);
  7652. - /* Find load/store insn with addressing mode is SYMBOL_REF. */
  7653. - if (mem_src != NULL_RTX)
  7654. - {
  7655. - if ((GET_CODE (mem_src) == ZERO_EXTEND)
  7656. - || (GET_CODE (mem_src) == SIGN_EXTEND))
  7657. - mem_src = XEXP (mem_src, 0);
  7658. + /* Check frame_pointer_needed again to prevent fp is need after reload. */
  7659. + if (frame_pointer_needed)
  7660. + cfun->machine->fp_as_gp_p = false;
  7661. - if ((GET_CODE (XEXP (mem_src, 0)) == SYMBOL_REF)
  7662. - || (GET_CODE (XEXP (mem_src, 0)) == LO_SUM))
  7663. - return true;
  7664. - }
  7665. + /* If the function is 'naked',
  7666. + we do not have to generate prologue code fragment. */
  7667. + if (cfun->machine->naked_p && !flag_pic)
  7668. + return;
  7669. - return false;
  7670. -}
  7671. + /* Get callee_first_regno and callee_last_regno. */
  7672. + Rb = cfun->machine->callee_saved_first_gpr_regno;
  7673. + Re = cfun->machine->callee_saved_last_gpr_regno;
  7674. -/* Function to determine whether it is worth to do fp_as_gp optimization.
  7675. - Return 0: It is NOT worth to do fp_as_gp optimization.
  7676. - Return 1: It is APPROXIMATELY worth to do fp_as_gp optimization.
  7677. - Note that if it is worth to do fp_as_gp optimization,
  7678. - we MUST set FP_REGNUM ever live in this function. */
  7679. -int
  7680. -nds32_fp_as_gp_check_available (void)
  7681. -{
  7682. - /* If there exists ANY of following conditions,
  7683. - we DO NOT perform fp_as_gp optimization:
  7684. - 1. TARGET_FORBID_FP_AS_GP is set
  7685. - regardless of the TARGET_FORCE_FP_AS_GP.
  7686. - 2. User explicitly uses 'naked' attribute.
  7687. - 3. Not optimize for size.
  7688. - 4. Need frame pointer.
  7689. - 5. If $fp is already required to be saved,
  7690. - it means $fp is already choosen by register allocator.
  7691. - Thus we better not to use it for fp_as_gp optimization.
  7692. - 6. This function is a vararg function.
  7693. - DO NOT apply fp_as_gp optimization on this function
  7694. - because it may change and break stack frame.
  7695. - 7. The epilogue is empty.
  7696. - This happens when the function uses exit()
  7697. - or its attribute is no_return.
  7698. - In that case, compiler will not expand epilogue
  7699. - so that we have no chance to output .omit_fp_end directive. */
  7700. - if (TARGET_FORBID_FP_AS_GP
  7701. - || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
  7702. - || !optimize_size
  7703. - || frame_pointer_needed
  7704. - || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
  7705. - || (cfun->stdarg == 1)
  7706. - || (find_fallthru_edge (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == NULL))
  7707. - return 0;
  7708. + /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
  7709. + where imm8u has to be 8-byte alignment. */
  7710. + sp_adjust = cfun->machine->local_size
  7711. + + cfun->machine->out_args_size
  7712. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  7713. + + cfun->machine->callee_saved_fpr_regs_size;
  7714. - /* Now we can check the possibility of using fp_as_gp optimization. */
  7715. - if (TARGET_FORCE_FP_AS_GP)
  7716. - {
  7717. - /* User explicitly issues -mforce-fp-as-gp option. */
  7718. - df_set_regs_ever_live (FP_REGNUM, 1);
  7719. - return 1;
  7720. - }
  7721. - else
  7722. + if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  7723. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
  7724. {
  7725. - /* In the following we are going to evaluate whether
  7726. - it is worth to do fp_as_gp optimization. */
  7727. - int good_gain = 0;
  7728. - int symbol_count = 0;
  7729. -
  7730. - int threshold;
  7731. - rtx insn;
  7732. -
  7733. - /* We check if there already requires prologue.
  7734. - Note that $gp will be saved in prologue for PIC code generation.
  7735. - After that, we can set threshold by the existence of prologue.
  7736. - Each fp-implied instruction will gain 2-byte code size
  7737. - from gp-aware instruction, so we have following heuristics. */
  7738. - if (flag_pic
  7739. - || nds32_have_prologue_p ())
  7740. - {
  7741. - /* Have-prologue:
  7742. - Compiler already intends to generate prologue content,
  7743. - so the fp_as_gp optimization will only insert
  7744. - 'la $fp,_FP_BASE_' instruction, which will be
  7745. - converted into 4-byte instruction at link time.
  7746. - The threshold is "3" symbol accesses, 2 + 2 + 2 > 4. */
  7747. - threshold = 3;
  7748. - }
  7749. - else
  7750. - {
  7751. - /* None-prologue:
  7752. - Compiler originally does not generate prologue content,
  7753. - so the fp_as_gp optimization will NOT ONLY insert
  7754. - 'la $fp,_FP_BASE' instruction, but also causes
  7755. - push/pop instructions.
  7756. - If we are using v3push (push25/pop25),
  7757. - the threshold is "5" symbol accesses, 5*2 > 4 + 2 + 2;
  7758. - If we are using normal push (smw/lmw),
  7759. - the threshold is "5+2" symbol accesses 7*2 > 4 + 4 + 4. */
  7760. - threshold = 5 + (TARGET_V3PUSH ? 0 : 2);
  7761. - }
  7762. -
  7763. - /* We would like to traverse every instruction in this function.
  7764. - So we need to have push_topmost_sequence()/pop_topmost_sequence()
  7765. - surrounding our for-loop evaluation. */
  7766. - push_topmost_sequence ();
  7767. - /* Counting the insn number which the addressing mode is symbol. */
  7768. - for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
  7769. - {
  7770. - if (single_set (insn) && nds32_symbol_load_store_p (insn))
  7771. - symbol_count++;
  7772. + /* We can use 'push25 Re,imm8u'. */
  7773. - if (symbol_count == threshold)
  7774. - {
  7775. - good_gain = 1;
  7776. - break;
  7777. - }
  7778. + /* nds32_emit_stack_v3push(last_regno, sp_adjust),
  7779. + the pattern 'stack_v3push' is implemented in nds32.md. */
  7780. + nds32_emit_stack_v3push (Rb, Re, sp_adjust);
  7781. +
  7782. + /* Save fpu registers. */
  7783. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  7784. + {
  7785. + /* Calculate fpr position. */
  7786. + int fpr_position = cfun->machine->local_size
  7787. + + cfun->machine->out_args_size;
  7788. + /* Emit fpu store instruction, using [$sp + offset] store
  7789. + fpu registers. */
  7790. + nds32_emit_push_fpr_callee_saved (fpr_position);
  7791. }
  7792. - pop_topmost_sequence ();
  7793. - /* Enable fp_as_gp optimization when potential gain is good enough. */
  7794. - if (good_gain)
  7795. + /* Check frame_pointer_needed to see
  7796. + if we shall emit fp adjustment instruction. */
  7797. + if (frame_pointer_needed)
  7798. {
  7799. - df_set_regs_ever_live (FP_REGNUM, 1);
  7800. - return 1;
  7801. - }
  7802. - }
  7803. -
  7804. - /* By default we return 0. */
  7805. - return 0;
  7806. -}
  7807. -
  7808. -
  7809. -/* Function to generate PC relative jump table.
  7810. - Refer to nds32.md for more details.
  7811. -
  7812. - The following is the sample for the case that diff value
  7813. - can be presented in '.short' size.
  7814. -
  7815. - addi $r1, $r1, -(case_lower_bound)
  7816. - slti $ta, $r1, (case_number)
  7817. - beqz $ta, .L_skip_label
  7818. -
  7819. - la $ta, .L35 ! get jump table address
  7820. - lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry
  7821. - addi $ta, $r1, $ta
  7822. - jr5 $ta
  7823. -
  7824. - ! jump table entry
  7825. - L35:
  7826. - .short .L25-.L35
  7827. - .short .L26-.L35
  7828. - .short .L27-.L35
  7829. - .short .L28-.L35
  7830. - .short .L29-.L35
  7831. - .short .L30-.L35
  7832. - .short .L31-.L35
  7833. - .short .L32-.L35
  7834. - .short .L33-.L35
  7835. - .short .L34-.L35 */
  7836. -const char *
  7837. -nds32_output_casesi_pc_relative (rtx *operands)
  7838. -{
  7839. - enum machine_mode mode;
  7840. - rtx diff_vec;
  7841. -
  7842. - diff_vec = PATTERN (NEXT_INSN (operands[1]));
  7843. -
  7844. - gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
  7845. -
  7846. - /* Step C: "t <-- operands[1]". */
  7847. - output_asm_insn ("la\t$ta, %l1", operands);
  7848. -
  7849. - /* Get the mode of each element in the difference vector. */
  7850. - mode = GET_MODE (diff_vec);
  7851. + /* adjust $fp = $sp + 4 ($fp size)
  7852. + + 4 ($gp size)
  7853. + + 4 ($lp size)
  7854. + + (4 * n) (callee-saved registers)
  7855. + + sp_adjust ('push25 Re,imm8u')
  7856. + Note: Since we use 'push25 Re,imm8u',
  7857. + the position of stack pointer is further
  7858. + changed after push instruction.
  7859. + Hence, we need to take sp_adjust value
  7860. + into consideration. */
  7861. + fp_adjust = cfun->machine->fp_size
  7862. + + cfun->machine->gp_size
  7863. + + cfun->machine->lp_size
  7864. + + cfun->machine->callee_saved_gpr_regs_size
  7865. + + sp_adjust;
  7866. - /* Step D: "z <-- (mem (plus (operands[0] << m) t))",
  7867. - where m is 0, 1, or 2 to load address-diff value from table. */
  7868. - switch (mode)
  7869. - {
  7870. - case QImode:
  7871. - output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
  7872. - break;
  7873. - case HImode:
  7874. - output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
  7875. - break;
  7876. - case SImode:
  7877. - output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
  7878. - break;
  7879. - default:
  7880. - gcc_unreachable ();
  7881. + nds32_emit_adjust_frame (hard_frame_pointer_rtx,
  7882. + stack_pointer_rtx,
  7883. + fp_adjust);
  7884. + }
  7885. }
  7886. -
  7887. - /* Step E: "t <-- z + t".
  7888. - Add table label_ref with address-diff value to
  7889. - obtain target case address. */
  7890. - output_asm_insn ("add\t$ta, %2, $ta", operands);
  7891. -
  7892. - /* Step F: jump to target with register t. */
  7893. - if (TARGET_16_BIT)
  7894. - return "jr5\t$ta";
  7895. - else
  7896. - return "jr\t$ta";
  7897. -}
  7898. -
  7899. -/* Function to generate normal jump table. */
  7900. -const char *
  7901. -nds32_output_casesi (rtx *operands)
  7902. -{
  7903. - /* Step C: "t <-- operands[1]". */
  7904. - output_asm_insn ("la\t$ta, %l1", operands);
  7905. -
  7906. - /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */
  7907. - output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
  7908. -
  7909. - /* No need to perform Step E, which is only used for
  7910. - pc relative jump table. */
  7911. -
  7912. - /* Step F: jump to target with register z. */
  7913. - if (TARGET_16_BIT)
  7914. - return "jr5\t%2";
  7915. else
  7916. - return "jr\t%2";
  7917. -}
  7918. -
  7919. -
  7920. -/* Function to return memory format. */
  7921. -enum nds32_16bit_address_type
  7922. -nds32_mem_format (rtx op)
  7923. -{
  7924. - enum machine_mode mode_test;
  7925. - int val;
  7926. - int regno;
  7927. -
  7928. - if (!TARGET_16_BIT)
  7929. - return ADDRESS_NOT_16BIT_FORMAT;
  7930. -
  7931. - mode_test = GET_MODE (op);
  7932. -
  7933. - op = XEXP (op, 0);
  7934. -
  7935. - /* 45 format. */
  7936. - if (GET_CODE (op) == REG && (mode_test == SImode))
  7937. - return ADDRESS_REG;
  7938. -
  7939. - /* 333 format for QI/HImode. */
  7940. - if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
  7941. - return ADDRESS_LO_REG_IMM3U;
  7942. -
  7943. - /* post_inc 333 format. */
  7944. - if ((GET_CODE (op) == POST_INC) && (mode_test == SImode))
  7945. {
  7946. - regno = REGNO(XEXP (op, 0));
  7947. -
  7948. - if (regno < 8)
  7949. - return ADDRESS_POST_INC_LO_REG_IMM3U;
  7950. - }
  7951. -
  7952. - /* post_inc 333 format. */
  7953. - if ((GET_CODE (op) == POST_MODIFY)
  7954. - && (mode_test == SImode)
  7955. - && (REG_P (XEXP (XEXP (op, 1), 0)))
  7956. - && (CONST_INT_P (XEXP (XEXP (op, 1), 1))))
  7957. - {
  7958. - regno = REGNO (XEXP (XEXP (op, 1), 0));
  7959. - val = INTVAL (XEXP (XEXP (op, 1), 1));
  7960. - if (regno < 8 && val < 32)
  7961. - return ADDRESS_POST_INC_LO_REG_IMM3U;
  7962. - }
  7963. -
  7964. - if ((GET_CODE (op) == PLUS)
  7965. - && (GET_CODE (XEXP (op, 0)) == REG)
  7966. - && (GET_CODE (XEXP (op, 1)) == CONST_INT))
  7967. - {
  7968. - val = INTVAL (XEXP (op, 1));
  7969. -
  7970. - regno = REGNO(XEXP (op, 0));
  7971. -
  7972. - if (regno > 7
  7973. - && regno != SP_REGNUM
  7974. - && regno != FP_REGNUM)
  7975. - return ADDRESS_NOT_16BIT_FORMAT;
  7976. -
  7977. - switch (mode_test)
  7978. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  7979. {
  7980. - case QImode:
  7981. - /* 333 format. */
  7982. - if (val >= 0 && val < 8 && regno < 8)
  7983. - return ADDRESS_LO_REG_IMM3U;
  7984. - break;
  7985. -
  7986. - case HImode:
  7987. - /* 333 format. */
  7988. - if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
  7989. - return ADDRESS_LO_REG_IMM3U;
  7990. - break;
  7991. -
  7992. - case SImode:
  7993. - case SFmode:
  7994. - case DFmode:
  7995. - /* fp imply 37 format. */
  7996. - if ((regno == FP_REGNUM) &&
  7997. - (val >= 0 && val < 512 && (val % 4 == 0)))
  7998. - return ADDRESS_FP_IMM7U;
  7999. - /* sp imply 37 format. */
  8000. - else if ((regno == SP_REGNUM) &&
  8001. - (val >= 0 && val < 512 && (val % 4 == 0)))
  8002. - return ADDRESS_SP_IMM7U;
  8003. - /* 333 format. */
  8004. - else if (val >= 0 && val < 32 && (val % 4 == 0) && regno < 8)
  8005. - return ADDRESS_LO_REG_IMM3U;
  8006. - break;
  8007. -
  8008. - default:
  8009. - break;
  8010. + /* Calculate fpr space. */
  8011. + fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
  8012. + + cfun->machine->callee_saved_fpr_regs_size;
  8013. +
  8014. + /* We have to use 'push25 Re, fpr_space', to pre-allocate
  8015. + callee saved fpr registers space. */
  8016. + nds32_emit_stack_v3push (Rb, Re, fpr_space);
  8017. + nds32_emit_push_fpr_callee_saved (0);
  8018. }
  8019. - }
  8020. -
  8021. - return ADDRESS_NOT_16BIT_FORMAT;
  8022. -}
  8023. -
  8024. -/* Output 16-bit store. */
  8025. -const char *
  8026. -nds32_output_16bit_store (rtx *operands, int byte)
  8027. -{
  8028. - char pattern[100];
  8029. - char size;
  8030. - rtx code = XEXP (operands[0], 0);
  8031. -
  8032. - size = nds32_byte_to_size (byte);
  8033. -
  8034. - switch (nds32_mem_format (operands[0]))
  8035. - {
  8036. - case ADDRESS_REG:
  8037. - operands[0] = code;
  8038. - output_asm_insn ("swi450\t%1, [%0]", operands);
  8039. - break;
  8040. - case ADDRESS_LO_REG_IMM3U:
  8041. - snprintf (pattern, sizeof (pattern), "s%ci333\t%%1, %%0", size);
  8042. - output_asm_insn (pattern, operands);
  8043. - break;
  8044. - case ADDRESS_POST_INC_LO_REG_IMM3U:
  8045. - snprintf (pattern, sizeof (pattern), "s%ci333.bi\t%%1, %%0", size);
  8046. - output_asm_insn (pattern, operands);
  8047. - break;
  8048. - case ADDRESS_FP_IMM7U:
  8049. - output_asm_insn ("swi37\t%1, %0", operands);
  8050. - break;
  8051. - case ADDRESS_SP_IMM7U:
  8052. - /* Get immediate value and set back to operands[1]. */
  8053. - operands[0] = XEXP (code, 1);
  8054. - output_asm_insn ("swi37.sp\t%1, [ + (%0)]", operands);
  8055. - break;
  8056. - default:
  8057. - break;
  8058. - }
  8059. -
  8060. - return "";
  8061. -}
  8062. -
  8063. -/* Output 16-bit load. */
  8064. -const char *
  8065. -nds32_output_16bit_load (rtx *operands, int byte)
  8066. -{
  8067. - char pattern[100];
  8068. - unsigned char size;
  8069. - rtx code = XEXP (operands[1], 0);
  8070. -
  8071. - size = nds32_byte_to_size (byte);
  8072. -
  8073. - switch (nds32_mem_format (operands[1]))
  8074. - {
  8075. - case ADDRESS_REG:
  8076. - operands[1] = code;
  8077. - output_asm_insn ("lwi450\t%0, [%1]", operands);
  8078. - break;
  8079. - case ADDRESS_LO_REG_IMM3U:
  8080. - snprintf (pattern, sizeof (pattern), "l%ci333\t%%0, %%1", size);
  8081. - output_asm_insn (pattern, operands);
  8082. - break;
  8083. - case ADDRESS_POST_INC_LO_REG_IMM3U:
  8084. - snprintf (pattern, sizeof (pattern), "l%ci333.bi\t%%0, %%1", size);
  8085. - output_asm_insn (pattern, operands);
  8086. - break;
  8087. - case ADDRESS_FP_IMM7U:
  8088. - output_asm_insn ("lwi37\t%0, %1", operands);
  8089. - break;
  8090. - case ADDRESS_SP_IMM7U:
  8091. - /* Get immediate value and set back to operands[0]. */
  8092. - operands[1] = XEXP (code, 1);
  8093. - output_asm_insn ("lwi37.sp\t%0, [ + (%1)]", operands);
  8094. - break;
  8095. - default:
  8096. - break;
  8097. - }
  8098. -
  8099. - return "";
  8100. -}
  8101. -
  8102. -/* Output 32-bit store. */
  8103. -const char *
  8104. -nds32_output_32bit_store (rtx *operands, int byte)
  8105. -{
  8106. - char pattern[100];
  8107. - unsigned char size;
  8108. - rtx code = XEXP (operands[0], 0);
  8109. -
  8110. - size = nds32_byte_to_size (byte);
  8111. -
  8112. - switch (GET_CODE (code))
  8113. - {
  8114. - case REG:
  8115. - /* (mem (reg X))
  8116. - => access location by using register,
  8117. - use "sbi / shi / swi" */
  8118. - snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
  8119. - break;
  8120. + else
  8121. + {
  8122. + /* We have to use 'push25 Re,0' and
  8123. + expand one more instruction to adjust $sp later. */
  8124. - case SYMBOL_REF:
  8125. - case CONST:
  8126. - /* (mem (symbol_ref X))
  8127. - (mem (const (...)))
  8128. - => access global variables,
  8129. - use "sbi.gp / shi.gp / swi.gp" */
  8130. - operands[0] = XEXP (operands[0], 0);
  8131. - snprintf (pattern, sizeof (pattern), "s%ci.gp\t%%1, [ + %%0]", size);
  8132. - break;
  8133. + /* nds32_emit_stack_v3push(last_regno, sp_adjust),
  8134. + the pattern 'stack_v3push' is implemented in nds32.md. */
  8135. + nds32_emit_stack_v3push (Rb, Re, 0);
  8136. + }
  8137. - case POST_INC:
  8138. - /* (mem (post_inc reg))
  8139. - => access location by using register which will be post increment,
  8140. - use "sbi.bi / shi.bi / swi.bi" */
  8141. - snprintf (pattern, sizeof (pattern),
  8142. - "s%ci.bi\t%%1, %%0, %d", size, byte);
  8143. - break;
  8144. + /* Check frame_pointer_needed to see
  8145. + if we shall emit fp adjustment instruction. */
  8146. + if (frame_pointer_needed)
  8147. + {
  8148. + /* adjust $fp = $sp + 4 ($fp size)
  8149. + + 4 ($gp size)
  8150. + + 4 ($lp size)
  8151. + + (4 * n) (callee-saved registers)
  8152. + Note: Since we use 'push25 Re,0',
  8153. + the stack pointer is just at the position
  8154. + after push instruction.
  8155. + No need to take sp_adjust into consideration. */
  8156. + fp_adjust = cfun->machine->fp_size
  8157. + + cfun->machine->gp_size
  8158. + + cfun->machine->lp_size
  8159. + + cfun->machine->callee_saved_gpr_regs_size;
  8160. - case POST_DEC:
  8161. - /* (mem (post_dec reg))
  8162. - => access location by using register which will be post decrement,
  8163. - use "sbi.bi / shi.bi / swi.bi" */
  8164. - snprintf (pattern, sizeof (pattern),
  8165. - "s%ci.bi\t%%1, %%0, -%d", size, byte);
  8166. - break;
  8167. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8168. + {
  8169. + /* We use 'push25 Re, fpr_space', the $sp is
  8170. + on callee saved fpr position, so need to consider
  8171. + fpr space. */
  8172. + fp_adjust = fp_adjust + fpr_space;
  8173. + }
  8174. - case POST_MODIFY:
  8175. - switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  8176. - {
  8177. - case REG:
  8178. - case SUBREG:
  8179. - /* (mem (post_modify (reg) (plus (reg) (reg))))
  8180. - => access location by using register which will be
  8181. - post modified with reg,
  8182. - use "sb.bi/ sh.bi / sw.bi" */
  8183. - snprintf (pattern, sizeof (pattern), "s%c.bi\t%%1, %%0", size);
  8184. - break;
  8185. - case CONST_INT:
  8186. - /* (mem (post_modify (reg) (plus (reg) (const_int))))
  8187. - => access location by using register which will be
  8188. - post modified with const_int,
  8189. - use "sbi.bi/ shi.bi / swi.bi" */
  8190. - snprintf (pattern, sizeof (pattern), "s%ci.bi\t%%1, %%0", size);
  8191. - break;
  8192. - default:
  8193. - abort ();
  8194. + nds32_emit_adjust_frame (hard_frame_pointer_rtx,
  8195. + stack_pointer_rtx,
  8196. + fp_adjust);
  8197. }
  8198. - break;
  8199. - case PLUS:
  8200. - switch (GET_CODE (XEXP (code, 1)))
  8201. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8202. {
  8203. - case REG:
  8204. - case SUBREG:
  8205. - /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  8206. - => access location by adding two registers,
  8207. - use "sb / sh / sw" */
  8208. - snprintf (pattern, sizeof (pattern), "s%c\t%%1, %%0", size);
  8209. - break;
  8210. - case CONST_INT:
  8211. - /* (mem (plus reg const_int))
  8212. - => access location by adding one register with const_int,
  8213. - use "sbi / shi / swi" */
  8214. - snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
  8215. - break;
  8216. - default:
  8217. - abort ();
  8218. + /* We use 'push25 Re, fpr_space',
  8219. + the $sp is on callee saved fpr position,
  8220. + no need to consider fpr space. */
  8221. + sp_adjust = sp_adjust - fpr_space;
  8222. }
  8223. - break;
  8224. -
  8225. - case LO_SUM:
  8226. - operands[2] = XEXP (code, 1);
  8227. - operands[0] = XEXP (code, 0);
  8228. - snprintf (pattern, sizeof (pattern),
  8229. - "s%ci\t%%1, [%%0 + lo12(%%2)]", size);
  8230. - break;
  8231. - default:
  8232. - abort ();
  8233. + /* Because we use 'push25 Re,0',
  8234. + we need to expand one more instruction to adjust $sp.
  8235. + using NEGATIVE value to tell that we are decreasing address. */
  8236. + nds32_emit_adjust_frame (stack_pointer_rtx,
  8237. + stack_pointer_rtx,
  8238. + -1 * sp_adjust);
  8239. }
  8240. - output_asm_insn (pattern, operands);
  8241. - return "";
  8242. + /* Emit gp setup instructions for -fpic. */
  8243. + if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
  8244. + nds32_emit_load_gp ();
  8245. +
  8246. + /* Prevent the instruction scheduler from
  8247. + moving instructions across the boundary. */
  8248. + emit_insn (gen_blockage ());
  8249. }
  8250. -/* Output 32-bit load. */
  8251. -const char *
  8252. -nds32_output_32bit_load (rtx *operands, int byte)
  8253. +/* Function for v3pop epilogue. */
  8254. +void
  8255. +nds32_expand_epilogue_v3pop (bool sibcall_p)
  8256. {
  8257. - char pattern[100];
  8258. - unsigned char size;
  8259. - rtx code;
  8260. + int sp_adjust;
  8261. + unsigned Rb, Re;
  8262. - code = XEXP (operands[1], 0);
  8263. + /* Compute and setup stack frame size.
  8264. + The result will be in cfun->machine. */
  8265. + nds32_compute_stack_frame ();
  8266. - size = nds32_byte_to_size (byte);
  8267. + /* Prevent the instruction scheduler from
  8268. + moving instructions across the boundary. */
  8269. + emit_insn (gen_blockage ());
  8270. - switch (GET_CODE (code))
  8271. + /* If the function is 'naked', we do not have to generate
  8272. + epilogue code fragment BUT 'ret' instruction. */
  8273. + if (cfun->machine->naked_p)
  8274. {
  8275. - case REG:
  8276. - /* (mem (reg X))
  8277. - => access location by using register,
  8278. - use "lbi / lhi / lwi" */
  8279. - snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
  8280. - break;
  8281. + /* Generate return instruction by using 'return_internal' pattern.
  8282. + Make sure this instruction is after gen_blockage().
  8283. + First we need to check this is a function without sibling call. */
  8284. + if (!sibcall_p)
  8285. + {
  8286. + /* We need to further check attributes to determine whether
  8287. + there should be return instruction at epilogue.
  8288. + If the attribute naked exists but -mno-ret-in-naked-func
  8289. + is issued, there is NO need to generate return instruction. */
  8290. + if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func)
  8291. + return;
  8292. - case SYMBOL_REF:
  8293. - case CONST:
  8294. - /* (mem (symbol_ref X))
  8295. - (mem (const (...)))
  8296. - => access global variables,
  8297. - use "lbi.gp / lhi.gp / lwi.gp" */
  8298. - operands[1] = XEXP (operands[1], 0);
  8299. - snprintf (pattern, sizeof (pattern), "l%ci.gp\t%%0, [ + %%1]", size);
  8300. - break;
  8301. -
  8302. - case POST_INC:
  8303. - /* (mem (post_inc reg))
  8304. - => access location by using register which will be post increment,
  8305. - use "lbi.bi / lhi.bi / lwi.bi" */
  8306. - snprintf (pattern, sizeof (pattern),
  8307. - "l%ci.bi\t%%0, %%1, %d", size, byte);
  8308. - break;
  8309. + emit_jump_insn (gen_return_internal ());
  8310. + }
  8311. + return;
  8312. + }
  8313. - case POST_DEC:
  8314. - /* (mem (post_dec reg))
  8315. - => access location by using register which will be post decrement,
  8316. - use "lbi.bi / lhi.bi / lwi.bi" */
  8317. - snprintf (pattern, sizeof (pattern),
  8318. - "l%ci.bi\t%%0, %%1, -%d", size, byte);
  8319. - break;
  8320. + /* Get callee_first_regno and callee_last_regno. */
  8321. + Rb = cfun->machine->callee_saved_first_gpr_regno;
  8322. + Re = cfun->machine->callee_saved_last_gpr_regno;
  8323. - case POST_MODIFY:
  8324. - switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  8325. - {
  8326. - case REG:
  8327. - case SUBREG:
  8328. - /* (mem (post_modify (reg) (plus (reg) (reg))))
  8329. - => access location by using register which will be
  8330. - post modified with reg,
  8331. - use "lb.bi/ lh.bi / lw.bi" */
  8332. - snprintf (pattern, sizeof (pattern), "l%c.bi\t%%0, %%1", size);
  8333. - break;
  8334. - case CONST_INT:
  8335. - /* (mem (post_modify (reg) (plus (reg) (const_int))))
  8336. - => access location by using register which will be
  8337. - post modified with const_int,
  8338. - use "lbi.bi/ lhi.bi / lwi.bi" */
  8339. - snprintf (pattern, sizeof (pattern), "l%ci.bi\t%%0, %%1", size);
  8340. - break;
  8341. - default:
  8342. - abort ();
  8343. - }
  8344. - break;
  8345. + /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
  8346. + where imm8u has to be 8-byte alignment. */
  8347. + sp_adjust = cfun->machine->local_size
  8348. + + cfun->machine->out_args_size
  8349. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  8350. + + cfun->machine->callee_saved_fpr_regs_size;
  8351. - case PLUS:
  8352. - switch (GET_CODE (XEXP (code, 1)))
  8353. + /* We have to consider alloca issue as well.
  8354. + If the function does call alloca(), the stack pointer is not fixed.
  8355. + In that case, we cannot use 'pop25 Re,imm8u' directly.
  8356. + We have to caculate stack pointer from frame pointer
  8357. + and then use 'pop25 Re,0'.
  8358. + Of course, the frame_pointer_needed should be nonzero
  8359. + if the function calls alloca(). */
  8360. + if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  8361. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  8362. + && !cfun->calls_alloca)
  8363. + {
  8364. + /* Restore fpu registers. */
  8365. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8366. {
  8367. - case REG:
  8368. - case SUBREG:
  8369. - /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  8370. - use "lb / lh / lw" */
  8371. - snprintf (pattern, sizeof (pattern), "l%c\t%%0, %%1", size);
  8372. - break;
  8373. - case CONST_INT:
  8374. - /* (mem (plus reg const_int))
  8375. - => access location by adding one register with const_int,
  8376. - use "lbi / lhi / lwi" */
  8377. - snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
  8378. - break;
  8379. - default:
  8380. - abort ();
  8381. + int fpr_position = cfun->machine->local_size
  8382. + + cfun->machine->out_args_size;
  8383. + /* Emit fpu load instruction, using [$sp + offset] restore
  8384. + fpu registers. */
  8385. + nds32_emit_v3pop_fpr_callee_saved (fpr_position);
  8386. }
  8387. - break;
  8388. - case LO_SUM:
  8389. - operands[2] = XEXP (code, 1);
  8390. - operands[1] = XEXP (code, 0);
  8391. - snprintf (pattern, sizeof (pattern),
  8392. - "l%ci\t%%0, [%%1 + lo12(%%2)]", size);
  8393. - break;
  8394. + /* We can use 'pop25 Re,imm8u'. */
  8395. - default:
  8396. - abort ();
  8397. + /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
  8398. + the pattern 'stack_v3pop' is implementad in nds32.md. */
  8399. + nds32_emit_stack_v3pop (Rb, Re, sp_adjust);
  8400. }
  8401. + else
  8402. + {
  8403. + /* We have to use 'pop25 Re,0', and prior to it,
  8404. + we must expand one more instruction to adjust $sp. */
  8405. - output_asm_insn (pattern, operands);
  8406. - return "";
  8407. -}
  8408. + if (frame_pointer_needed)
  8409. + {
  8410. + /* adjust $sp = $fp - 4 ($fp size)
  8411. + - 4 ($gp size)
  8412. + - 4 ($lp size)
  8413. + - (4 * n) (callee-saved registers)
  8414. + Note: No need to adjust
  8415. + cfun->machine->callee_saved_area_gpr_padding_bytes,
  8416. + because we want to adjust stack pointer
  8417. + to the position for pop instruction. */
  8418. + sp_adjust = cfun->machine->fp_size
  8419. + + cfun->machine->gp_size
  8420. + + cfun->machine->lp_size
  8421. + + cfun->machine->callee_saved_gpr_regs_size;
  8422. -/* Output 32-bit load with signed extension. */
  8423. -const char *
  8424. -nds32_output_32bit_load_s (rtx *operands, int byte)
  8425. -{
  8426. - char pattern[100];
  8427. - unsigned char size;
  8428. - rtx code;
  8429. + /* Restore fpu registers. */
  8430. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8431. + {
  8432. + /* Set $sp to callee saved fpr position, we need to restore
  8433. + fpr registers. */
  8434. + sp_adjust = sp_adjust
  8435. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  8436. + + cfun->machine->callee_saved_fpr_regs_size;
  8437. - code = XEXP (operands[1], 0);
  8438. + nds32_emit_adjust_frame (stack_pointer_rtx,
  8439. + hard_frame_pointer_rtx,
  8440. + -1 * sp_adjust);
  8441. - size = nds32_byte_to_size (byte);
  8442. + /* Emit fpu load instruction, using [$sp + offset] restore
  8443. + fpu registers. */
  8444. + nds32_emit_v3pop_fpr_callee_saved (0);
  8445. + }
  8446. + else
  8447. + {
  8448. + nds32_emit_adjust_frame (stack_pointer_rtx,
  8449. + hard_frame_pointer_rtx,
  8450. + -1 * sp_adjust);
  8451. + }
  8452. + }
  8453. + else
  8454. + {
  8455. + /* If frame pointer is NOT needed,
  8456. + we cannot calculate the sp adjustment from frame pointer.
  8457. + Instead, we calculate the adjustment by local_size,
  8458. + out_args_size, and callee_saved_area_padding_bytes.
  8459. + Notice that such sp adjustment value may be out of range,
  8460. + so we have to deal with it as well. */
  8461. - switch (GET_CODE (code))
  8462. - {
  8463. - case REG:
  8464. - /* (mem (reg X))
  8465. - => access location by using register,
  8466. - use "lbsi / lhsi" */
  8467. - snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
  8468. - break;
  8469. + /* Adjust $sp = $sp + local_size + out_args_size
  8470. + + callee_saved_area_gpr_padding_bytes
  8471. + + callee_saved_fpr_regs_size. */
  8472. + sp_adjust = cfun->machine->local_size
  8473. + + cfun->machine->out_args_size
  8474. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  8475. + + cfun->machine->callee_saved_fpr_regs_size;
  8476. - case SYMBOL_REF:
  8477. - case CONST:
  8478. - /* (mem (symbol_ref X))
  8479. - (mem (const (...)))
  8480. - => access global variables,
  8481. - use "lbsi.gp / lhsi.gp" */
  8482. - operands[1] = XEXP (operands[1], 0);
  8483. - snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
  8484. - break;
  8485. + /* Restore fpu registers. */
  8486. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8487. + {
  8488. + /* Set $sp to callee saved fpr position, we need to restore
  8489. + fpr registers. */
  8490. + sp_adjust = sp_adjust
  8491. + - cfun->machine->callee_saved_area_gpr_padding_bytes
  8492. + - cfun->machine->callee_saved_fpr_regs_size;
  8493. - case POST_INC:
  8494. - /* (mem (post_inc reg))
  8495. - => access location by using register which will be post increment,
  8496. - use "lbsi.bi / lhsi.bi" */
  8497. - snprintf (pattern, sizeof (pattern),
  8498. - "l%csi.bi\t%%0, %%1, %d", size, byte);
  8499. - break;
  8500. + nds32_emit_adjust_frame (stack_pointer_rtx,
  8501. + stack_pointer_rtx,
  8502. + sp_adjust);
  8503. - case POST_DEC:
  8504. - /* (mem (post_dec reg))
  8505. - => access location by using register which will be post decrement,
  8506. - use "lbsi.bi / lhsi.bi" */
  8507. - snprintf (pattern, sizeof (pattern),
  8508. - "l%csi.bi\t%%0, %%1, -%d", size, byte);
  8509. - break;
  8510. + /* Emit fpu load instruction, using [$sp + offset] restore
  8511. + fpu registers. */
  8512. + nds32_emit_v3pop_fpr_callee_saved (0);
  8513. + }
  8514. + else
  8515. + {
  8516. + /* sp_adjust value may be out of range of the addi instruction,
  8517. + create alternative add behavior with TA_REGNUM if necessary,
  8518. + using POSITIVE value to tell that we are increasing
  8519. + address. */
  8520. + nds32_emit_adjust_frame (stack_pointer_rtx,
  8521. + stack_pointer_rtx,
  8522. + sp_adjust);
  8523. + }
  8524. + }
  8525. - case POST_MODIFY:
  8526. - switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  8527. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  8528. {
  8529. - case REG:
  8530. - case SUBREG:
  8531. - /* (mem (post_modify (reg) (plus (reg) (reg))))
  8532. - => access location by using register which will be
  8533. - post modified with reg,
  8534. - use "lbs.bi/ lhs.bi" */
  8535. - snprintf (pattern, sizeof (pattern), "l%cs.bi\t%%0, %%1", size);
  8536. - break;
  8537. - case CONST_INT:
  8538. - /* (mem (post_modify (reg) (plus (reg) (const_int))))
  8539. - => access location by using register which will be
  8540. - post modified with const_int,
  8541. - use "lbsi.bi/ lhsi.bi" */
  8542. - snprintf (pattern, sizeof (pattern), "l%csi.bi\t%%0, %%1", size);
  8543. - break;
  8544. - default:
  8545. - abort ();
  8546. + /* We have fpr need to restore, so $sp is set on callee saved fpr
  8547. + position. And we use 'pop25 Re, fpr_space' to adjust $sp. */
  8548. + int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
  8549. + + cfun->machine->callee_saved_fpr_regs_size;
  8550. + nds32_emit_stack_v3pop (Rb, Re, fpr_space);
  8551. }
  8552. - break;
  8553. -
  8554. - case PLUS:
  8555. - switch (GET_CODE (XEXP (code, 1)))
  8556. + else
  8557. {
  8558. - case REG:
  8559. - case SUBREG:
  8560. - /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  8561. - use "lbs / lhs" */
  8562. - snprintf (pattern, sizeof (pattern), "l%cs\t%%0, %%1", size);
  8563. - break;
  8564. - case CONST_INT:
  8565. - /* (mem (plus reg const_int))
  8566. - => access location by adding one register with const_int,
  8567. - use "lbsi / lhsi" */
  8568. - snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
  8569. - break;
  8570. - default:
  8571. - abort ();
  8572. + /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
  8573. + the pattern 'stack_v3pop' is implementad in nds32.md. */
  8574. + nds32_emit_stack_v3pop (Rb, Re, 0);
  8575. }
  8576. - break;
  8577. -
  8578. - case LO_SUM:
  8579. - operands[2] = XEXP (code, 1);
  8580. - operands[1] = XEXP (code, 0);
  8581. - snprintf (pattern, sizeof (pattern),
  8582. - "l%csi\t%%0, [%%1 + lo12(%%2)]", size);
  8583. - break;
  8584. -
  8585. - default:
  8586. - abort ();
  8587. }
  8588. -
  8589. - output_asm_insn (pattern, operands);
  8590. - return "";
  8591. + /* Generate return instruction. */
  8592. + emit_jump_insn (gen_pop25return ());
  8593. }
  8594. -/* Function to output stack push operation.
  8595. - We need to deal with normal stack push multiple or stack v3push. */
  8596. -const char *
  8597. -nds32_output_stack_push (void)
  8598. +/* Return nonzero if this function is known to have a null epilogue.
  8599. + This allows the optimizer to omit jumps to jumps if no stack
  8600. + was created. */
  8601. +int
  8602. +nds32_can_use_return_insn (void)
  8603. {
  8604. - /* A string pattern for output_asm_insn(). */
  8605. - char pattern[100];
  8606. - /* The operands array which will be used in output_asm_insn(). */
  8607. - rtx operands[3];
  8608. - /* Pick up callee-saved first regno and last regno for further use. */
  8609. - int rb_regno = cfun->machine->callee_saved_regs_first_regno;
  8610. - int re_regno = cfun->machine->callee_saved_regs_last_regno;
  8611. + int sp_adjust;
  8612. - if (TARGET_V3PUSH)
  8613. - {
  8614. - /* For stack v3push:
  8615. - operands[0]: Re
  8616. - operands[1]: imm8u */
  8617. + /* Prior to reloading, we can't tell how many registers must be saved.
  8618. + Thus we can not determine whether this function has null epilogue. */
  8619. + if (!reload_completed)
  8620. + return 0;
  8621. - /* This variable is to check if 'push25 Re,imm8u' is available. */
  8622. - int sp_adjust;
  8623. + /* If attribute 'naked' appears but -mno-ret-in-naked-func is used,
  8624. + we cannot use return instruction. */
  8625. + if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func)
  8626. + return 0;
  8627. - /* Set operands[0]. */
  8628. - operands[0] = gen_rtx_REG (SImode, re_regno);
  8629. + sp_adjust = cfun->machine->local_size
  8630. + + cfun->machine->out_args_size
  8631. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  8632. + + cfun->machine->callee_saved_fpr_regs_size;
  8633. + if (!cfun->machine->fp_as_gp_p
  8634. + && satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  8635. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  8636. + && !cfun->calls_alloca
  8637. + && NDS32_V3PUSH_AVAILABLE_P
  8638. + && !(TARGET_HARD_FLOAT
  8639. + && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)))
  8640. + return 1;
  8641. - /* Check if we can generate 'push25 Re,imm8u',
  8642. - otherwise, generate 'push25 Re,0'. */
  8643. - sp_adjust = cfun->machine->local_size
  8644. - + cfun->machine->out_args_size
  8645. - + cfun->machine->callee_saved_area_padding_bytes;
  8646. - if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  8647. - && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
  8648. - operands[1] = GEN_INT (sp_adjust);
  8649. - else
  8650. - operands[1] = GEN_INT (0);
  8651. + /* If no stack was created, two conditions must be satisfied:
  8652. + 1. This is a naked function.
  8653. + So there is no callee-saved, local size, or outgoing size.
  8654. + 2. This is NOT a variadic function.
  8655. + So there is no pushing arguement registers into the stack. */
  8656. + return ((cfun->machine->naked_p && (cfun->machine->va_args_size == 0)));
  8657. +}
  8658. - /* Create assembly code pattern. */
  8659. - snprintf (pattern, sizeof (pattern), "push25\t%%0, %%1");
  8660. - }
  8661. +enum machine_mode
  8662. +nds32_case_vector_shorten_mode (int min_offset, int max_offset,
  8663. + rtx body ATTRIBUTE_UNUSED)
  8664. +{
  8665. + if (min_offset < 0 || max_offset >= 0x2000)
  8666. + return SImode;
  8667. else
  8668. {
  8669. - /* For normal stack push multiple:
  8670. - operands[0]: Rb
  8671. - operands[1]: Re
  8672. - operands[2]: En4 */
  8673. -
  8674. - /* This variable is used to check if we only need to generate En4 field.
  8675. - As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
  8676. - int push_en4_only_p = 0;
  8677. -
  8678. - /* Set operands[0] and operands[1]. */
  8679. - operands[0] = gen_rtx_REG (SImode, rb_regno);
  8680. - operands[1] = gen_rtx_REG (SImode, re_regno);
  8681. -
  8682. - /* 'smw.adm $sp,[$sp],$sp,0' means push nothing. */
  8683. - if (!cfun->machine->fp_size
  8684. - && !cfun->machine->gp_size
  8685. - && !cfun->machine->lp_size
  8686. - && REGNO (operands[0]) == SP_REGNUM
  8687. - && REGNO (operands[1]) == SP_REGNUM)
  8688. - {
  8689. - /* No need to generate instruction. */
  8690. - return "";
  8691. - }
  8692. - else
  8693. - {
  8694. - /* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
  8695. - if (REGNO (operands[0]) == SP_REGNUM
  8696. - && REGNO (operands[1]) == SP_REGNUM)
  8697. - push_en4_only_p = 1;
  8698. -
  8699. - /* Create assembly code pattern.
  8700. - We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
  8701. - snprintf (pattern, sizeof (pattern),
  8702. - "push.s\t%s{%s%s%s }",
  8703. - push_en4_only_p ? "" : "%0, %1, ",
  8704. - cfun->machine->fp_size ? " $fp" : "",
  8705. - cfun->machine->gp_size ? " $gp" : "",
  8706. - cfun->machine->lp_size ? " $lp" : "");
  8707. - }
  8708. - }
  8709. -
  8710. - /* We use output_asm_insn() to output assembly code by ourself. */
  8711. - output_asm_insn (pattern, operands);
  8712. - return "";
  8713. -}
  8714. -
  8715. -/* Function to output stack pop operation.
  8716. - We need to deal with normal stack pop multiple or stack v3pop. */
  8717. -const char *
  8718. -nds32_output_stack_pop (void)
  8719. -{
  8720. - /* A string pattern for output_asm_insn(). */
  8721. - char pattern[100];
  8722. - /* The operands array which will be used in output_asm_insn(). */
  8723. - rtx operands[3];
  8724. - /* Pick up callee-saved first regno and last regno for further use. */
  8725. - int rb_regno = cfun->machine->callee_saved_regs_first_regno;
  8726. - int re_regno = cfun->machine->callee_saved_regs_last_regno;
  8727. -
  8728. - if (TARGET_V3PUSH)
  8729. - {
  8730. - /* For stack v3pop:
  8731. - operands[0]: Re
  8732. - operands[1]: imm8u */
  8733. -
  8734. - /* This variable is to check if 'pop25 Re,imm8u' is available. */
  8735. - int sp_adjust;
  8736. -
  8737. - /* Set operands[0]. */
  8738. - operands[0] = gen_rtx_REG (SImode, re_regno);
  8739. -
  8740. - /* Check if we can generate 'pop25 Re,imm8u',
  8741. - otherwise, generate 'pop25 Re,0'.
  8742. - We have to consider alloca issue as well.
  8743. - If the function does call alloca(), the stack pointer is not fixed.
  8744. - In that case, we cannot use 'pop25 Re,imm8u' directly.
  8745. - We have to caculate stack pointer from frame pointer
  8746. - and then use 'pop25 Re,0'. */
  8747. - sp_adjust = cfun->machine->local_size
  8748. - + cfun->machine->out_args_size
  8749. - + cfun->machine->callee_saved_area_padding_bytes;
  8750. - if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  8751. - && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  8752. - && !cfun->calls_alloca)
  8753. - operands[1] = GEN_INT (sp_adjust);
  8754. + /* The jump table maybe need to 2 byte alignment,
  8755. + so reserved 1 byte for check max_offset. */
  8756. + if (max_offset >= 0xff)
  8757. + return HImode;
  8758. else
  8759. - operands[1] = GEN_INT (0);
  8760. -
  8761. - /* Create assembly code pattern. */
  8762. - snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
  8763. + return QImode;
  8764. }
  8765. - else
  8766. - {
  8767. - /* For normal stack pop multiple:
  8768. - operands[0]: Rb
  8769. - operands[1]: Re
  8770. - operands[2]: En4 */
  8771. -
  8772. - /* This variable is used to check if we only need to generate En4 field.
  8773. - As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
  8774. - int pop_en4_only_p = 0;
  8775. -
  8776. - /* Set operands[0] and operands[1]. */
  8777. - operands[0] = gen_rtx_REG (SImode, rb_regno);
  8778. - operands[1] = gen_rtx_REG (SImode, re_regno);
  8779. -
  8780. - /* 'lmw.bim $sp,[$sp],$sp,0' means pop nothing. */
  8781. - if (!cfun->machine->fp_size
  8782. - && !cfun->machine->gp_size
  8783. - && !cfun->machine->lp_size
  8784. - && REGNO (operands[0]) == SP_REGNUM
  8785. - && REGNO (operands[1]) == SP_REGNUM)
  8786. - {
  8787. - /* No need to generate instruction. */
  8788. - return "";
  8789. - }
  8790. - else
  8791. - {
  8792. - /* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
  8793. - if (REGNO (operands[0]) == SP_REGNUM
  8794. - && REGNO (operands[1]) == SP_REGNUM)
  8795. - pop_en4_only_p = 1;
  8796. +}
  8797. - /* Create assembly code pattern.
  8798. - We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
  8799. - snprintf (pattern, sizeof (pattern),
  8800. - "pop.s\t%s{%s%s%s }",
  8801. - pop_en4_only_p ? "" : "%0, %1, ",
  8802. - cfun->machine->fp_size ? " $fp" : "",
  8803. - cfun->machine->gp_size ? " $gp" : "",
  8804. - cfun->machine->lp_size ? " $lp" : "");
  8805. - }
  8806. - }
  8807. +static bool
  8808. +nds32_cannot_copy_insn_p (rtx insn)
  8809. +{
  8810. + /* The hwloop_cfg insn cannot be copied. */
  8811. + if (recog_memoized (insn) == CODE_FOR_hwloop_cfg)
  8812. + return true;
  8813. - /* We use output_asm_insn() to output assembly code by ourself. */
  8814. - output_asm_insn (pattern, operands);
  8815. - return "";
  8816. + return false;
  8817. }
  8818. -/* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */
  8819. +/* Return alignment for the label. */
  8820. int
  8821. nds32_target_alignment (rtx label)
  8822. {
  8823. rtx insn;
  8824. - if (optimize_size)
  8825. + if (!NDS32_ALIGN_P ())
  8826. return 0;
  8827. insn = next_active_insn (label);
  8828. - if (insn == 0)
  8829. + /* Always align to 4 byte when first instruction after label is jump
  8830. + instruction since length for that might changed, so let's always align
  8831. + it for make sure we don't lose any perfomance here. */
  8832. + if (insn == 0
  8833. + || (get_attr_length (insn) == 2
  8834. + && !JUMP_P (insn) && !CALL_P (insn)))
  8835. return 0;
  8836. - else if ((get_attr_length (insn) % 4) == 0)
  8837. + else
  8838. return 2;
  8839. +}
  8840. +
  8841. +/* Return alignment for data. */
  8842. +unsigned int
  8843. +nds32_data_alignment (tree data,
  8844. + unsigned int basic_align)
  8845. +{
  8846. + if ((basic_align < BITS_PER_WORD)
  8847. + && (TREE_CODE (data) == ARRAY_TYPE
  8848. + || TREE_CODE (data) == UNION_TYPE
  8849. + || TREE_CODE (data) == RECORD_TYPE))
  8850. + return BITS_PER_WORD;
  8851. else
  8852. - return 0;
  8853. + return basic_align;
  8854. +}
  8855. +
  8856. +/* Return alignment for constant value. */
  8857. +unsigned int
  8858. +nds32_constant_alignment (tree constant,
  8859. + unsigned int basic_align)
  8860. +{
  8861. + /* Make string literal and constant for constructor to word align. */
  8862. + if (((TREE_CODE (constant) == STRING_CST
  8863. + || TREE_CODE (constant) == CONSTRUCTOR
  8864. + || TREE_CODE (constant) == UNION_TYPE
  8865. + || TREE_CODE (constant) == RECORD_TYPE
  8866. + || TREE_CODE (constant) == ARRAY_TYPE)
  8867. + && basic_align < BITS_PER_WORD))
  8868. + return BITS_PER_WORD;
  8869. + else
  8870. + return basic_align;
  8871. +}
  8872. +
  8873. +/* Return alignment for local variable. */
  8874. +unsigned int
  8875. +nds32_local_alignment (tree local ATTRIBUTE_UNUSED,
  8876. + unsigned int basic_align)
  8877. +{
  8878. + bool at_least_align_to_word = false;
  8879. + /* Make local array, struct and union at least align to word for make
  8880. + sure it can unroll memcpy when initialize by constant. */
  8881. + switch (TREE_CODE (local))
  8882. + {
  8883. + case ARRAY_TYPE:
  8884. + case RECORD_TYPE:
  8885. + case UNION_TYPE:
  8886. + at_least_align_to_word = true;
  8887. + break;
  8888. + default:
  8889. + at_least_align_to_word = false;
  8890. + break;
  8891. + }
  8892. + if (at_least_align_to_word
  8893. + && (basic_align < BITS_PER_WORD))
  8894. + return BITS_PER_WORD;
  8895. + else
  8896. + return basic_align;
  8897. }
  8898. /* ------------------------------------------------------------------------ */
  8899. -/* PART 5: Initialize target hook structure and definitions. */
  8900. +/* PART 6: Initialize target hook structure and definitions. */
  8901. /* Controlling the Compilation Driver. */
  8902. @@ -5445,6 +5977,9 @@
  8903. #define TARGET_PROMOTE_FUNCTION_MODE \
  8904. default_promote_function_mode_always_promote
  8905. +#undef TARGET_EXPAND_TO_RTL_HOOK
  8906. +#define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook
  8907. +
  8908. /* Layout of Source Language Data Types. */
  8909. @@ -5453,6 +5988,9 @@
  8910. /* -- Basic Characteristics of Registers. */
  8911. +#undef TARGET_CONDITIONAL_REGISTER_USAGE
  8912. +#define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage
  8913. +
  8914. /* -- Order of Allocation of Registers. */
  8915. /* -- How Values Fit in Registers. */
  8916. @@ -5464,6 +6002,9 @@
  8917. /* Register Classes. */
  8918. +#undef TARGET_PREFERRED_RENAME_CLASS
  8919. +#define TARGET_PREFERRED_RENAME_CLASS nds32_preferred_rename_class
  8920. +
  8921. #undef TARGET_CLASS_MAX_NREGS
  8922. #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
  8923. @@ -5499,12 +6040,21 @@
  8924. #undef TARGET_FUNCTION_ARG
  8925. #define TARGET_FUNCTION_ARG nds32_function_arg
  8926. +#undef TARGET_MUST_PASS_IN_STACK
  8927. +#define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack
  8928. +
  8929. +#undef TARGET_ARG_PARTIAL_BYTES
  8930. +#define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes
  8931. +
  8932. #undef TARGET_FUNCTION_ARG_ADVANCE
  8933. #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
  8934. #undef TARGET_FUNCTION_ARG_BOUNDARY
  8935. #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
  8936. +#undef TARGET_VECTOR_MODE_SUPPORTED_P
  8937. +#define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p
  8938. +
  8939. /* -- How Scalar Function Values Are Returned. */
  8940. #undef TARGET_FUNCTION_VALUE
  8941. @@ -5518,6 +6068,9 @@
  8942. /* -- How Large Values Are Returned. */
  8943. +#undef TARGET_RETURN_IN_MEMORY
  8944. +#define TARGET_RETURN_IN_MEMORY nds32_return_in_memory
  8945. +
  8946. /* -- Caller-Saves Register Allocation. */
  8947. /* -- Function Entry and Exit. */
  8948. @@ -5544,6 +6097,9 @@
  8949. /* -- Permitting tail calls. */
  8950. +#undef TARGET_FUNCTION_OK_FOR_SIBCALL
  8951. +#define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall
  8952. +
  8953. #undef TARGET_WARN_FUNC_RETURN
  8954. #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
  8955. @@ -5552,6 +6108,9 @@
  8956. /* Implementing the Varargs Macros. */
  8957. +#undef TARGET_SETUP_INCOMING_VARARGS
  8958. +#define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
  8959. +
  8960. #undef TARGET_STRICT_ARGUMENT_NAMING
  8961. #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
  8962. @@ -5573,6 +6132,21 @@
  8963. #undef TARGET_LEGITIMATE_ADDRESS_P
  8964. #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
  8965. +#undef TARGET_LEGITIMIZE_ADDRESS
  8966. +#define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address
  8967. +
  8968. +#undef TARGET_LEGITIMATE_CONSTANT_P
  8969. +#define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p
  8970. +
  8971. +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
  8972. +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode
  8973. +
  8974. +#undef TARGET_CANNOT_FORCE_CONST_MEM
  8975. +#define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem
  8976. +
  8977. +#undef TARGET_DELEGITIMIZE_ADDRESS
  8978. +#define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address
  8979. +
  8980. /* Anchored Addresses. */
  8981. @@ -5583,6 +6157,9 @@
  8982. /* -- Representation of condition codes using registers. */
  8983. +#undef TARGET_CANONICALIZE_COMPARISON
  8984. +#define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison
  8985. +
  8986. /* -- Macros to control conditional execution. */
  8987. @@ -5603,9 +6180,15 @@
  8988. /* Adjusting the Instruction Scheduler. */
  8989. +#undef TARGET_SCHED_ADJUST_COST
  8990. +#define TARGET_SCHED_ADJUST_COST nds32_sched_adjust_cost
  8991. +
  8992. /* Dividing the Output into Sections (Texts, Data, . . . ). */
  8993. +#undef TARGET_ENCODE_SECTION_INFO
  8994. +#define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info
  8995. +
  8996. /* Position Independent Code. */
  8997. @@ -5627,6 +6210,9 @@
  8998. #undef TARGET_ASM_ALIGNED_SI_OP
  8999. #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
  9000. +#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
  9001. +#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra
  9002. +
  9003. /* -- Output of Uninitialized Variables. */
  9004. /* -- Output and Generation of Labels. */
  9005. @@ -5649,6 +6235,9 @@
  9006. /* -- Assembler Commands for Exception Regions. */
  9007. +#undef TARGET_DWARF_REGISTER_SPAN
  9008. +#define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span
  9009. +
  9010. /* -- Assembler Commands for Alignment. */
  9011. @@ -5664,6 +6253,11 @@
  9012. /* -- Macros for SDB and DWARF Output. */
  9013. +/* Variable tracking should be run after all optimizations which
  9014. + change order of insns. It also needs a valid CFG. */
  9015. +#undef TARGET_DELAY_VARTRACK
  9016. +#define TARGET_DELAY_VARTRACK true
  9017. +
  9018. /* -- Macros for VMS Debug Format. */
  9019. @@ -5693,6 +6287,9 @@
  9020. /* Emulating TLS. */
  9021. +#undef TARGET_HAVE_TLS
  9022. +#define TARGET_HAVE_TLS TARGET_LINUX_ABI
  9023. +
  9024. /* Defining coprocessor specifics for MIPS targets. */
  9025. @@ -5708,12 +6305,36 @@
  9026. /* Miscellaneous Parameters. */
  9027. +#undef TARGET_MD_ASM_CLOBBERS
  9028. +#define TARGET_MD_ASM_CLOBBERS nds32_md_asm_clobbers
  9029. +
  9030. +#undef TARGET_MACHINE_DEPENDENT_REORG
  9031. +#define TARGET_MACHINE_DEPENDENT_REORG nds32_machine_dependent_reorg
  9032. +
  9033. #undef TARGET_INIT_BUILTINS
  9034. #define TARGET_INIT_BUILTINS nds32_init_builtins
  9035. +#undef TARGET_BUILTIN_DECL
  9036. +#define TARGET_BUILTIN_DECL nds32_builtin_decl
  9037. +
  9038. #undef TARGET_EXPAND_BUILTIN
  9039. #define TARGET_EXPAND_BUILTIN nds32_expand_builtin
  9040. +#undef TARGET_HAVE_CONDITIONAL_EXECUTION
  9041. +#define TARGET_HAVE_CONDITIONAL_EXECUTION nds32_have_conditional_execution
  9042. +
  9043. +#undef TARGET_INIT_LIBFUNCS
  9044. +#define TARGET_INIT_LIBFUNCS nds32_init_libfuncs
  9045. +
  9046. +#undef TARGET_CAN_USE_DOLOOP_P
  9047. +#define TARGET_CAN_USE_DOLOOP_P nds32_can_use_doloop_p
  9048. +
  9049. +#undef TARGET_INVALID_WITHIN_DOLOOP
  9050. +#define TARGET_INVALID_WITHIN_DOLOOP nds32_invalid_within_doloop
  9051. +
  9052. +#undef TARGET_CANNOT_COPY_INSN_P
  9053. +#define TARGET_CANNOT_COPY_INSN_P nds32_cannot_copy_insn_p
  9054. +
  9055. /* ------------------------------------------------------------------------ */
  9056. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-cost.c gcc-4.9.4/gcc/config/nds32/nds32-cost.c
  9057. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-cost.c 1970-01-01 01:00:00.000000000 +0100
  9058. +++ gcc-4.9.4/gcc/config/nds32/nds32-cost.c 2016-08-08 20:37:45.498269782 +0200
  9059. @@ -0,0 +1,734 @@
  9060. +/* Subroutines used for calculate rtx costs of Andes NDS32 cpu for GNU compiler
  9061. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  9062. + Contributed by Andes Technology Corporation.
  9063. +
  9064. + This file is part of GCC.
  9065. +
  9066. + GCC is free software; you can redistribute it and/or modify it
  9067. + under the terms of the GNU General Public License as published
  9068. + by the Free Software Foundation; either version 3, or (at your
  9069. + option) any later version.
  9070. +
  9071. + GCC is distributed in the hope that it will be useful, but WITHOUT
  9072. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  9073. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  9074. + License for more details.
  9075. +
  9076. + You should have received a copy of the GNU General Public License
  9077. + along with GCC; see the file COPYING3. If not see
  9078. + <http://www.gnu.org/licenses/>. */
  9079. +
  9080. +/* ------------------------------------------------------------------------ */
  9081. +
  9082. +#include "config.h"
  9083. +#include "system.h"
  9084. +#include "coretypes.h"
  9085. +#include "tm.h"
  9086. +#include "tree.h"
  9087. +#include "rtl.h"
  9088. +#include "regs.h"
  9089. +#include "hard-reg-set.h"
  9090. +#include "insn-config.h" /* Required by recog.h. */
  9091. +#include "conditions.h"
  9092. +#include "output.h"
  9093. +#include "insn-attr.h" /* For DFA state_t. */
  9094. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  9095. +#include "reload.h" /* For push_reload(). */
  9096. +#include "flags.h"
  9097. +#include "function.h"
  9098. +#include "expr.h"
  9099. +#include "recog.h"
  9100. +#include "diagnostic-core.h"
  9101. +#include "df.h"
  9102. +#include "tm_p.h"
  9103. +#include "tm-constrs.h"
  9104. +#include "optabs.h" /* For GEN_FCN. */
  9105. +#include "target.h"
  9106. +#include "target-def.h"
  9107. +#include "langhooks.h" /* For add_builtin_function(). */
  9108. +#include "ggc.h"
  9109. +#include "tree-pass.h"
  9110. +
  9111. +/* ------------------------------------------------------------------------ */
  9112. +
  9113. +typedef bool (*rtx_cost_func) (rtx, int, int, int, int*);
  9114. +
  9115. +struct rtx_cost_model_t {
  9116. + rtx_cost_func speed_prefer;
  9117. + rtx_cost_func size_prefer;
  9118. +};
  9119. +
  9120. +static rtx_cost_model_t rtx_cost_model;
  9121. +
  9122. +static int insn_size_16bit; /* Initial at nds32_init_rtx_costs. */
  9123. +static const int insn_size_32bit = 4;
  9124. +
  9125. +static bool
  9126. +nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
  9127. + int code,
  9128. + int outer_code ATTRIBUTE_UNUSED,
  9129. + int opno ATTRIBUTE_UNUSED,
  9130. + int *total)
  9131. +{
  9132. + rtx op0;
  9133. + rtx op1;
  9134. + enum machine_mode mode = GET_MODE (x);
  9135. + /* Scale cost by mode size. */
  9136. + int cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode));
  9137. +
  9138. + switch (code)
  9139. + {
  9140. + case USE:
  9141. + /* Used in combine.c as a marker. */
  9142. + *total = 0;
  9143. + return true;
  9144. +
  9145. + case CONST_INT:
  9146. + /* When not optimizing for size, we care more about the cost
  9147. + of hot code, and hot code is often in a loop. If a constant
  9148. + operand needs to be forced into a register, we will often be
  9149. + able to hoist the constant load out of the loop, so the load
  9150. + should not contribute to the cost. */
  9151. + if (outer_code == SET || outer_code == PLUS)
  9152. + *total = satisfies_constraint_Is20 (x) ? 0 : 4;
  9153. + else if (outer_code == AND || outer_code == IOR || outer_code == XOR
  9154. + || outer_code == MINUS)
  9155. + *total = satisfies_constraint_Iu15 (x) ? 0 : 4;
  9156. + else if (outer_code == ASHIFT || outer_code == ASHIFTRT
  9157. + || outer_code == LSHIFTRT)
  9158. + *total = satisfies_constraint_Iu05 (x) ? 0 : 4;
  9159. + else if (GET_RTX_CLASS (outer_code) == RTX_COMPARE
  9160. + || GET_RTX_CLASS (outer_code) == RTX_COMM_COMPARE)
  9161. + *total = satisfies_constraint_Is16 (x) ? 0 : 4;
  9162. + else
  9163. + *total = COSTS_N_INSNS (1);
  9164. + return true;
  9165. +
  9166. + case CONST:
  9167. + case LO_SUM:
  9168. + case HIGH:
  9169. + case SYMBOL_REF:
  9170. + *total = COSTS_N_INSNS (1);
  9171. + return true;
  9172. +
  9173. + case MEM:
  9174. + *total = COSTS_N_INSNS (1);
  9175. + return true;
  9176. +
  9177. + case SET:
  9178. + op0 = SET_DEST (x);
  9179. + op1 = SET_SRC (x);
  9180. + mode = GET_MODE (op0);
  9181. + /* Scale cost by mode size. */
  9182. + cost = COSTS_N_INSNS (GET_MODE_SIZE (mode) / GET_MODE_SIZE (SImode));
  9183. +
  9184. + switch (GET_CODE (op1))
  9185. + {
  9186. + case REG:
  9187. + case SUBREG:
  9188. + /* Register move and Store instructions. */
  9189. + if ((REG_P (op0) || MEM_P (op0))
  9190. + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode))
  9191. + *total = COSTS_N_INSNS (1);
  9192. + else
  9193. + *total = cost;
  9194. + return true;
  9195. +
  9196. + case MEM:
  9197. + /* Load instructions. */
  9198. + if (REG_P (op0) && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (DImode))
  9199. + *total = COSTS_N_INSNS (1);
  9200. + else
  9201. + *total = cost;
  9202. + return true;
  9203. +
  9204. + case CONST_INT:
  9205. + /* movi instruction. */
  9206. + if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode))
  9207. + {
  9208. + if (satisfies_constraint_Is20 (op1))
  9209. + *total = COSTS_N_INSNS (1) - 1;
  9210. + else
  9211. + *total = COSTS_N_INSNS (2);
  9212. + }
  9213. + else
  9214. + *total = cost;
  9215. + return true;
  9216. +
  9217. + case CONST:
  9218. + case SYMBOL_REF:
  9219. + case LABEL_REF:
  9220. + /* la instruction. */
  9221. + if (REG_P (op0) && GET_MODE_SIZE (mode) < GET_MODE_SIZE (DImode))
  9222. + *total = COSTS_N_INSNS (1) - 1;
  9223. + else
  9224. + *total = cost;
  9225. + return true;
  9226. +
  9227. + default:
  9228. + *total = cost;
  9229. + return true;
  9230. + }
  9231. +
  9232. + case PLUS:
  9233. + op0 = XEXP (x, 0);
  9234. + op1 = XEXP (x, 1);
  9235. +
  9236. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9237. + *total = cost;
  9238. + else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT
  9239. + || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT)
  9240. + /* ALU_SHIFT */
  9241. + *total = COSTS_N_INSNS (2);
  9242. + else if ((GET_CODE (op1) == CONST_INT
  9243. + && satisfies_constraint_Is15 (op1))
  9244. + || REG_P (op1))
  9245. + /* ADD instructions */
  9246. + *total = COSTS_N_INSNS (1);
  9247. + else
  9248. + /* ADD instructions: IMM out of range. */
  9249. + *total = COSTS_N_INSNS (2);
  9250. + return true;
  9251. +
  9252. + case MINUS:
  9253. + op0 = XEXP (x, 0);
  9254. + op1 = XEXP (x, 1);
  9255. +
  9256. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9257. + *total = cost;
  9258. + else if (GET_CODE (op0) == MULT || GET_CODE (op0) == LSHIFTRT
  9259. + || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT)
  9260. + /* ALU_SHIFT */
  9261. + *total = COSTS_N_INSNS (2);
  9262. + else if ((GET_CODE (op0) == CONST_INT
  9263. + && satisfies_constraint_Is15 (op0))
  9264. + || REG_P (op0))
  9265. + /* SUB instructions */
  9266. + *total = COSTS_N_INSNS (1);
  9267. + else
  9268. + /* SUB instructions: IMM out of range. */
  9269. + *total = COSTS_N_INSNS (2);
  9270. + return true;
  9271. +
  9272. + case TRUNCATE:
  9273. + /* TRUNCATE and AND behavior is same. */
  9274. + *total = COSTS_N_INSNS (1);
  9275. + return true;
  9276. +
  9277. + case AND:
  9278. + case IOR:
  9279. + case XOR:
  9280. + op0 = XEXP (x, 0);
  9281. + op1 = XEXP (x, 1);
  9282. +
  9283. + if (NDS32_EXT_DSP_P ())
  9284. + {
  9285. + /* We prefer (and (ior) (ior)) than (ior (and) (and)) for
  9286. + synthetize pk** and insb instruction. */
  9287. + if (code == AND && GET_CODE (op0) == IOR && GET_CODE (op1) == IOR)
  9288. + return COSTS_N_INSNS (1);
  9289. +
  9290. + if (code == IOR && GET_CODE (op0) == AND && GET_CODE (op1) == AND)
  9291. + return COSTS_N_INSNS (10);
  9292. + }
  9293. +
  9294. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9295. + *total = cost;
  9296. + else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFTRT)
  9297. + /* ALU_SHIFT */
  9298. + *total = COSTS_N_INSNS (2);
  9299. + else if ((GET_CODE (op1) == CONST_INT
  9300. + && satisfies_constraint_Iu15 (op1))
  9301. + || REG_P (op1))
  9302. + /* AND, OR, XOR instructions */
  9303. + *total = COSTS_N_INSNS (1);
  9304. + else if (code == AND || GET_CODE (op0) == NOT)
  9305. + /* BITC instruction */
  9306. + *total = COSTS_N_INSNS (1);
  9307. + else
  9308. + /* AND, OR, XOR instructions: IMM out of range. */
  9309. + *total = COSTS_N_INSNS (2);
  9310. + return true;
  9311. +
  9312. + case MULT:
  9313. + if (GET_MODE (x) == DImode
  9314. + || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
  9315. + || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
  9316. + /* MUL instructions */
  9317. + *total = COSTS_N_INSNS (1);
  9318. + else if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9319. + *total = cost;
  9320. + else if (outer_code == PLUS || outer_code == MINUS)
  9321. + /* ALU_SHIFT */
  9322. + *total = COSTS_N_INSNS (2);
  9323. + else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
  9324. + && satisfies_constraint_Iu05 (XEXP (x, 1)))
  9325. + || REG_P (XEXP (x, 1)))
  9326. + /* MUL instructions */
  9327. + *total = COSTS_N_INSNS (1);
  9328. + else
  9329. + /* MUL instructions: IMM out of range. */
  9330. + *total = COSTS_N_INSNS (2);
  9331. +
  9332. + if (TARGET_MUL_SLOW)
  9333. + *total += COSTS_N_INSNS (4);
  9334. +
  9335. + return true;
  9336. +
  9337. + case LSHIFTRT:
  9338. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9339. + *total = cost;
  9340. + else if (outer_code == PLUS || outer_code == MINUS
  9341. + || outer_code == AND || outer_code == IOR
  9342. + || outer_code == XOR)
  9343. + /* ALU_SHIFT */
  9344. + *total = COSTS_N_INSNS (2);
  9345. + else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
  9346. + && satisfies_constraint_Iu05 (XEXP (x, 1)))
  9347. + || REG_P (XEXP (x, 1)))
  9348. + /* SRL instructions */
  9349. + *total = COSTS_N_INSNS (1);
  9350. + else
  9351. + /* SRL instructions: IMM out of range. */
  9352. + *total = COSTS_N_INSNS (2);
  9353. + return true;
  9354. +
  9355. + case ASHIFT:
  9356. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9357. + *total = cost;
  9358. + else if (outer_code == AND || outer_code == IOR
  9359. + || outer_code == XOR)
  9360. + /* ALU_SHIFT */
  9361. + *total += COSTS_N_INSNS (2);
  9362. + else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
  9363. + && satisfies_constraint_Iu05 (XEXP (x, 1)))
  9364. + || REG_P (XEXP (x, 1)))
  9365. + /* SLL instructions */
  9366. + *total = COSTS_N_INSNS (1);
  9367. + else
  9368. + /* SLL instructions: IMM out of range. */
  9369. + *total = COSTS_N_INSNS (2);
  9370. + return true;
  9371. +
  9372. + case ASHIFTRT:
  9373. + case ROTATERT:
  9374. + if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
  9375. + *total = cost;
  9376. + else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
  9377. + && satisfies_constraint_Iu05 (XEXP (x, 1)))
  9378. + || REG_P (XEXP (x, 1)))
  9379. + /* ROTR, SLL instructions */
  9380. + *total = COSTS_N_INSNS (1);
  9381. + else
  9382. + /* ROTR, SLL instructions: IMM out of range. */
  9383. + *total = COSTS_N_INSNS (2);
  9384. + return true;
  9385. +
  9386. + case LT:
  9387. + case LTU:
  9388. + if (outer_code == SET)
  9389. + {
  9390. + if ((GET_CODE (XEXP (x, 1)) == CONST_INT
  9391. + && satisfies_constraint_Iu15 (XEXP (x, 1)))
  9392. + || REG_P (XEXP (x, 1)))
  9393. + /* SLT, SLTI instructions */
  9394. + *total = COSTS_N_INSNS (1);
  9395. + else
  9396. + /* SLT, SLT instructions: IMM out of range. */
  9397. + *total = COSTS_N_INSNS (2);
  9398. + }
  9399. + else
  9400. + /* branch */
  9401. + *total = COSTS_N_INSNS (2);
  9402. + return true;
  9403. +
  9404. + case EQ:
  9405. + case NE:
  9406. + case GE:
  9407. + case LE:
  9408. + case GT:
  9409. + /* branch */
  9410. + *total = COSTS_N_INSNS (2);
  9411. + return true;
  9412. +
  9413. + case IF_THEN_ELSE:
  9414. + if (GET_CODE (XEXP (x, 1)) == LABEL_REF)
  9415. + /* branch */
  9416. + *total = COSTS_N_INSNS (2);
  9417. + else
  9418. + /* cmovz, cmovn instructions */
  9419. + *total = COSTS_N_INSNS (1);
  9420. + return true;
  9421. +
  9422. + case LABEL_REF:
  9423. + if (outer_code == IF_THEN_ELSE)
  9424. + /* branch */
  9425. + *total = COSTS_N_INSNS (2);
  9426. + else
  9427. + *total = COSTS_N_INSNS (1);
  9428. + return true;
  9429. +
  9430. + case ZERO_EXTEND:
  9431. + case SIGN_EXTEND:
  9432. + if (MEM_P (XEXP (x, 0)))
  9433. + /* Using memory access. */
  9434. + *total = COSTS_N_INSNS (1);
  9435. + else
  9436. + /* Zero extend and sign extend instructions. */
  9437. + *total = COSTS_N_INSNS (1);
  9438. + return true;
  9439. +
  9440. + case NEG:
  9441. + case NOT:
  9442. + *total = COSTS_N_INSNS (1);
  9443. + return true;
  9444. +
  9445. + case DIV:
  9446. + case UDIV:
  9447. + case MOD:
  9448. + case UMOD:
  9449. + *total = COSTS_N_INSNS (20);
  9450. + return true;
  9451. +
  9452. + case CALL:
  9453. + *total = COSTS_N_INSNS (2);
  9454. + return true;
  9455. +
  9456. + case CLZ:
  9457. + case SMIN:
  9458. + case SMAX:
  9459. + case ZERO_EXTRACT:
  9460. + if (TARGET_EXT_PERF)
  9461. + *total = COSTS_N_INSNS (1);
  9462. + else
  9463. + *total = COSTS_N_INSNS (3);
  9464. + return true;
  9465. +
  9466. + default:
  9467. + *total = COSTS_N_INSNS (3);
  9468. + return true;
  9469. + }
  9470. +}
  9471. +
  9472. +static bool
  9473. +nds32_rtx_costs_size_prefer (rtx x,
  9474. + int code,
  9475. + int outer_code,
  9476. + int opno ATTRIBUTE_UNUSED,
  9477. + int *total)
  9478. +{
  9479. + /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
  9480. + We treat it as 4-byte cost for each instruction
  9481. + under code size consideration. */
  9482. + switch (code)
  9483. + {
  9484. + case SET:
  9485. + /* For 'SET' rtx, we need to return false
  9486. + so that it can recursively calculate costs. */
  9487. + return false;
  9488. +
  9489. + case USE:
  9490. + /* Used in combine.c as a marker. */
  9491. + *total = 0;
  9492. + break;
  9493. +
  9494. + case CONST_INT:
  9495. + /* All instructions involving constant operation
  9496. + need to be considered for cost evaluation. */
  9497. + if (outer_code == SET)
  9498. + {
  9499. + /* (set X imm5s), use movi55, 2-byte cost.
  9500. + (set X imm20s), use movi, 4-byte cost.
  9501. + (set X BIG_INT), use sethi/ori, 8-byte cost. */
  9502. + if (satisfies_constraint_Is05 (x))
  9503. + *total = insn_size_16bit;
  9504. + else if (satisfies_constraint_Is20 (x))
  9505. + *total = insn_size_32bit;
  9506. + else
  9507. + *total = insn_size_32bit * 2;
  9508. + }
  9509. + else if (outer_code == PLUS || outer_code == MINUS)
  9510. + {
  9511. + /* Possible addi333/subi333 or subi45/addi45, 2-byte cost.
  9512. + General case, cost 1 instruction with 4-byte. */
  9513. + if (satisfies_constraint_Iu05 (x))
  9514. + *total = insn_size_16bit;
  9515. + else
  9516. + *total = insn_size_32bit;
  9517. + }
  9518. + else if (outer_code == ASHIFT)
  9519. + {
  9520. + /* Possible slli333, 2-byte cost.
  9521. + General case, cost 1 instruction with 4-byte. */
  9522. + if (satisfies_constraint_Iu03 (x))
  9523. + *total = insn_size_16bit;
  9524. + else
  9525. + *total = insn_size_32bit;
  9526. + }
  9527. + else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
  9528. + {
  9529. + /* Possible srai45 or srli45, 2-byte cost.
  9530. + General case, cost 1 instruction with 4-byte. */
  9531. + if (satisfies_constraint_Iu05 (x))
  9532. + *total = insn_size_16bit;
  9533. + else
  9534. + *total = insn_size_32bit;
  9535. + }
  9536. + else
  9537. + {
  9538. + /* For other cases, simply set it 4-byte cost. */
  9539. + *total = insn_size_32bit;
  9540. + }
  9541. + break;
  9542. +
  9543. + case CONST_DOUBLE:
  9544. + /* It requires high part and low part processing, set it 8-byte cost. */
  9545. + *total = insn_size_32bit * 2;
  9546. + break;
  9547. +
  9548. + case CONST:
  9549. + case SYMBOL_REF:
  9550. + *total = insn_size_32bit * 2;
  9551. + break;
  9552. +
  9553. + default:
  9554. + /* For other cases, generally we set it 4-byte cost
  9555. + and stop resurively traversing. */
  9556. + *total = insn_size_32bit;
  9557. + break;
  9558. + }
  9559. +
  9560. + return true;
  9561. +}
  9562. +
  9563. +void
  9564. +nds32_init_rtx_costs (void)
  9565. +{
  9566. + rtx_cost_model.speed_prefer = nds32_rtx_costs_speed_prefer;
  9567. + rtx_cost_model.size_prefer = nds32_rtx_costs_size_prefer;
  9568. +
  9569. + if (TARGET_16_BIT)
  9570. + insn_size_16bit = 2;
  9571. + else
  9572. + insn_size_16bit = 4;
  9573. +}
  9574. +
  9575. +/* This target hook describes the relative costs of RTL expressions.
  9576. + Return 'true' when all subexpressions of x have been processed.
  9577. + Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
  9578. + Refer to gcc/rtlanal.c for more information. */
  9579. +bool
  9580. +nds32_rtx_costs_impl (rtx x,
  9581. + int code,
  9582. + int outer_code,
  9583. + int opno,
  9584. + int *total,
  9585. + bool speed)
  9586. +{
  9587. + /* According to 'speed', use suitable cost model section. */
  9588. + if (speed)
  9589. + return rtx_cost_model.speed_prefer(x, code, outer_code, opno, total);
  9590. + else
  9591. + return rtx_cost_model.size_prefer(x, code, outer_code, opno, total);
  9592. +}
  9593. +
  9594. +
  9595. +int nds32_address_cost_speed_prefer (rtx address)
  9596. +{
  9597. + rtx plus0, plus1;
  9598. + enum rtx_code code;
  9599. +
  9600. + code = GET_CODE (address);
  9601. +
  9602. + switch (code)
  9603. + {
  9604. + case POST_MODIFY:
  9605. + case POST_INC:
  9606. + case POST_DEC:
  9607. + /* We encourage that rtx contains
  9608. + POST_MODIFY/POST_INC/POST_DEC behavior. */
  9609. + return COSTS_N_INSNS (1) - 2;
  9610. +
  9611. + case SYMBOL_REF:
  9612. + /* We can have gp-relative load/store for symbol_ref.
  9613. + Have it 4-byte cost. */
  9614. + return COSTS_N_INSNS (2);
  9615. +
  9616. + case CONST:
  9617. + /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
  9618. + Have it 4-byte cost. */
  9619. + return COSTS_N_INSNS (2);
  9620. +
  9621. + case REG:
  9622. + /* Simply return 4-byte costs. */
  9623. + return COSTS_N_INSNS (1) - 2;
  9624. +
  9625. + case PLUS:
  9626. + /* We do not need to check if the address is a legitimate address,
  9627. + because this hook is never called with an invalid address.
  9628. + But we better check the range of
  9629. + const_int value for cost, if it exists. */
  9630. + plus0 = XEXP (address, 0);
  9631. + plus1 = XEXP (address, 1);
  9632. +
  9633. + if (REG_P (plus0) && CONST_INT_P (plus1))
  9634. + return COSTS_N_INSNS (1) - 2;
  9635. + else if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1))
  9636. + return COSTS_N_INSNS (1) - 1;
  9637. + else if (REG_P (plus0) && REG_P (plus1))
  9638. + return COSTS_N_INSNS (1);
  9639. +
  9640. + /* For other 'plus' situation, make it cost 4-byte. */
  9641. + return COSTS_N_INSNS (1);
  9642. +
  9643. + default:
  9644. + break;
  9645. + }
  9646. +
  9647. + return COSTS_N_INSNS (4);
  9648. +
  9649. +}
  9650. +
  9651. +int nds32_address_cost_speed_fwprop (rtx address)
  9652. +{
  9653. + rtx plus0, plus1;
  9654. + enum rtx_code code;
  9655. +
  9656. + code = GET_CODE (address);
  9657. +
  9658. + switch (code)
  9659. + {
  9660. + case POST_MODIFY:
  9661. + case POST_INC:
  9662. + case POST_DEC:
  9663. + /* We encourage that rtx contains
  9664. + POST_MODIFY/POST_INC/POST_DEC behavior. */
  9665. + return 0;
  9666. +
  9667. + case SYMBOL_REF:
  9668. + /* We can have gp-relative load/store for symbol_ref.
  9669. + Have it 4-byte cost. */
  9670. + return COSTS_N_INSNS (2);
  9671. +
  9672. + case CONST:
  9673. + /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
  9674. + Have it 4-byte cost. */
  9675. + return COSTS_N_INSNS (2);
  9676. +
  9677. + case REG:
  9678. + /* Simply return 4-byte costs. */
  9679. + return COSTS_N_INSNS (1);
  9680. +
  9681. + case PLUS:
  9682. + /* We do not need to check if the address is a legitimate address,
  9683. + because this hook is never called with an invalid address.
  9684. + But we better check the range of
  9685. + const_int value for cost, if it exists. */
  9686. + plus0 = XEXP (address, 0);
  9687. + plus1 = XEXP (address, 1);
  9688. +
  9689. + if (REG_P (plus0) && CONST_INT_P (plus1))
  9690. + {
  9691. + /* If it is possible to be lwi333/swi333 form,
  9692. + make it 2-byte cost. */
  9693. + if (satisfies_constraint_Iu03 (plus1))
  9694. + return (COSTS_N_INSNS (1) - 2);
  9695. + else
  9696. + return COSTS_N_INSNS (1);
  9697. + }
  9698. + if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1))
  9699. + return COSTS_N_INSNS (1) - 2;
  9700. + else if (REG_P (plus0) && REG_P (plus1))
  9701. + return COSTS_N_INSNS (1);
  9702. +
  9703. + /* For other 'plus' situation, make it cost 4-byte. */
  9704. + return COSTS_N_INSNS (1);
  9705. +
  9706. + default:
  9707. + break;
  9708. + }
  9709. +
  9710. + return COSTS_N_INSNS (4);
  9711. +}
  9712. +
  9713. +
  9714. +int nds32_address_cost_size_prefer (rtx address)
  9715. +{
  9716. + rtx plus0, plus1;
  9717. + enum rtx_code code;
  9718. +
  9719. + code = GET_CODE (address);
  9720. +
  9721. + switch (code)
  9722. + {
  9723. + case POST_MODIFY:
  9724. + case POST_INC:
  9725. + case POST_DEC:
  9726. + /* We encourage that rtx contains
  9727. + POST_MODIFY/POST_INC/POST_DEC behavior. */
  9728. + return 0;
  9729. +
  9730. + case SYMBOL_REF:
  9731. + /* We can have gp-relative load/store for symbol_ref.
  9732. + Have it 4-byte cost. */
  9733. + return COSTS_N_INSNS (2);
  9734. +
  9735. + case CONST:
  9736. + /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
  9737. + Have it 4-byte cost. */
  9738. + return COSTS_N_INSNS (2);
  9739. +
  9740. + case REG:
  9741. + /* Simply return 4-byte costs. */
  9742. + return COSTS_N_INSNS (1) - 1;
  9743. +
  9744. + case PLUS:
  9745. + /* We do not need to check if the address is a legitimate address,
  9746. + because this hook is never called with an invalid address.
  9747. + But we better check the range of
  9748. + const_int value for cost, if it exists. */
  9749. + plus0 = XEXP (address, 0);
  9750. + plus1 = XEXP (address, 1);
  9751. +
  9752. + if (REG_P (plus0) && CONST_INT_P (plus1))
  9753. + {
  9754. + /* If it is possible to be lwi333/swi333 form,
  9755. + make it 2-byte cost. */
  9756. + if (satisfies_constraint_Iu03 (plus1))
  9757. + return (COSTS_N_INSNS (1) - 2);
  9758. + else
  9759. + return COSTS_N_INSNS (1) - 1;
  9760. + }
  9761. +
  9762. + /* (plus (reg) (mult (reg) (const))) */
  9763. + if (ARITHMETIC_P (plus0) || ARITHMETIC_P (plus1))
  9764. + return (COSTS_N_INSNS (1) - 1);
  9765. +
  9766. + /* For other 'plus' situation, make it cost 4-byte. */
  9767. + return COSTS_N_INSNS (1);
  9768. +
  9769. + default:
  9770. + break;
  9771. + }
  9772. +
  9773. + return COSTS_N_INSNS (4);
  9774. +
  9775. +}
  9776. +
  9777. +int nds32_address_cost_impl (rtx address,
  9778. + enum machine_mode mode ATTRIBUTE_UNUSED,
  9779. + addr_space_t as ATTRIBUTE_UNUSED,
  9780. + bool speed_p)
  9781. +{
  9782. + if (speed_p)
  9783. + {
  9784. + if (current_pass->tv_id == TV_FWPROP)
  9785. + return nds32_address_cost_speed_fwprop (address);
  9786. + else
  9787. + return nds32_address_cost_speed_prefer (address);
  9788. + }
  9789. + else
  9790. + return nds32_address_cost_size_prefer (address);
  9791. +}
  9792. +
  9793. +/* ------------------------------------------------------------------------ */
  9794. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-doubleword.md gcc-4.9.4/gcc/config/nds32/nds32-doubleword.md
  9795. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-doubleword.md 2014-01-02 23:23:26.000000000 +0100
  9796. +++ gcc-4.9.4/gcc/config/nds32/nds32-doubleword.md 2016-08-08 20:37:45.498269782 +0200
  9797. @@ -1,5 +1,5 @@
  9798. ;; DImode/DFmode patterns description of Andes NDS32 cpu for GNU compiler
  9799. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  9800. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  9801. ;; Contributed by Andes Technology Corporation.
  9802. ;;
  9803. ;; This file is part of GCC.
  9804. @@ -23,7 +23,8 @@
  9805. ;; Move DImode/DFmode instructions.
  9806. ;; -------------------------------------------------------------
  9807. -
  9808. +;; Do *NOT* try to split DI/DFmode before reload since LRA seem
  9809. +;; still buggy for such behavior at least at gcc 4.8.2...
  9810. (define_expand "movdi"
  9811. [(set (match_operand:DI 0 "general_operand" "")
  9812. (match_operand:DI 1 "general_operand" ""))]
  9813. @@ -46,144 +47,77 @@
  9814. (define_insn "move_<mode>"
  9815. - [(set (match_operand:DIDF 0 "nonimmediate_operand" "=r, r, r, m")
  9816. - (match_operand:DIDF 1 "general_operand" " r, i, m, r"))]
  9817. - ""
  9818. + [(set (match_operand:DIDF 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f")
  9819. + (match_operand:DIDF 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))]
  9820. + "register_operand(operands[0], <MODE>mode)
  9821. + || register_operand(operands[1], <MODE>mode)"
  9822. {
  9823. - rtx addr;
  9824. - rtx otherops[5];
  9825. -
  9826. switch (which_alternative)
  9827. {
  9828. case 0:
  9829. return "movd44\t%0, %1";
  9830. -
  9831. case 1:
  9832. /* reg <- const_int, we ask gcc to split instruction. */
  9833. return "#";
  9834. -
  9835. case 2:
  9836. - /* Refer to nds32_legitimate_address_p() in nds32.c,
  9837. - we only allow "reg", "symbol_ref", "const", and "reg + const_int"
  9838. - as address rtx for DImode/DFmode memory access. */
  9839. - addr = XEXP (operands[1], 0);
  9840. -
  9841. - otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
  9842. - otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
  9843. - otherops[2] = addr;
  9844. -
  9845. - if (REG_P (addr))
  9846. - {
  9847. - /* (reg) <- (mem (reg)) */
  9848. - output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
  9849. - }
  9850. - else if (GET_CODE (addr) == PLUS)
  9851. - {
  9852. - /* (reg) <- (mem (plus (reg) (const_int))) */
  9853. - rtx op0 = XEXP (addr, 0);
  9854. - rtx op1 = XEXP (addr, 1);
  9855. -
  9856. - if (REG_P (op0))
  9857. - {
  9858. - otherops[2] = op0;
  9859. - otherops[3] = op1;
  9860. - otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
  9861. - }
  9862. - else
  9863. - {
  9864. - otherops[2] = op1;
  9865. - otherops[3] = op0;
  9866. - otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
  9867. - }
  9868. -
  9869. - /* To avoid base overwrite when REGNO(%0) == REGNO(%2). */
  9870. - if (REGNO (otherops[0]) != REGNO (otherops[2]))
  9871. - {
  9872. - output_asm_insn ("lwi\t%0, [%2 + (%3)]", otherops);
  9873. - output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
  9874. - }
  9875. - else
  9876. - {
  9877. - output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
  9878. - output_asm_insn ("lwi\t%0,[ %2 + (%3)]", otherops);
  9879. - }
  9880. - }
  9881. - else
  9882. - {
  9883. - /* (reg) <- (mem (symbol_ref ...))
  9884. - (reg) <- (mem (const ...)) */
  9885. - output_asm_insn ("lwi.gp\t%0, [ + %2]", otherops);
  9886. - output_asm_insn ("lwi.gp\t%1, [ + %2 + 4]", otherops);
  9887. - }
  9888. -
  9889. - /* We have already used output_asm_insn() by ourself,
  9890. - so return an empty string. */
  9891. - return "";
  9892. -
  9893. + /* The memory format is (mem (reg)),
  9894. + we can generate 'lmw.bi' instruction. */
  9895. + return nds32_output_double (operands, true);
  9896. case 3:
  9897. - /* Refer to nds32_legitimate_address_p() in nds32.c,
  9898. - we only allow "reg", "symbol_ref", "const", and "reg + const_int"
  9899. - as address rtx for DImode/DFmode memory access. */
  9900. - addr = XEXP (operands[0], 0);
  9901. -
  9902. - otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
  9903. - otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
  9904. - otherops[2] = addr;
  9905. -
  9906. - if (REG_P (addr))
  9907. - {
  9908. - /* (mem (reg)) <- (reg) */
  9909. - output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
  9910. - }
  9911. - else if (GET_CODE (addr) == PLUS)
  9912. - {
  9913. - /* (mem (plus (reg) (const_int))) <- (reg) */
  9914. - rtx op0 = XEXP (addr, 0);
  9915. - rtx op1 = XEXP (addr, 1);
  9916. -
  9917. - if (REG_P (op0))
  9918. - {
  9919. - otherops[2] = op0;
  9920. - otherops[3] = op1;
  9921. - otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
  9922. - }
  9923. - else
  9924. - {
  9925. - otherops[2] = op1;
  9926. - otherops[3] = op0;
  9927. - otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
  9928. - }
  9929. -
  9930. - /* To avoid base overwrite when REGNO(%0) == REGNO(%2). */
  9931. - if (REGNO (otherops[0]) != REGNO (otherops[2]))
  9932. - {
  9933. - output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
  9934. - output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
  9935. - }
  9936. - else
  9937. - {
  9938. - output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
  9939. - output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
  9940. - }
  9941. - }
  9942. - else
  9943. - {
  9944. - /* (mem (symbol_ref ...)) <- (reg)
  9945. - (mem (const ...)) <- (reg) */
  9946. - output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
  9947. - output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
  9948. - }
  9949. -
  9950. - /* We have already used output_asm_insn() by ourself,
  9951. - so return an empty string. */
  9952. - return "";
  9953. -
  9954. + /* We haven't 64-bit load instruction,
  9955. + we split this pattern to two SImode pattern. */
  9956. + return "#";
  9957. + case 4:
  9958. + /* The memory format is (mem (reg)),
  9959. + we can generate 'smw.bi' instruction. */
  9960. + return nds32_output_double (operands, false);
  9961. + case 5:
  9962. + /* We haven't 64-bit store instruction,
  9963. + we split this pattern to two SImode pattern. */
  9964. + return "#";
  9965. + case 6:
  9966. + return nds32_output_float_load (operands);
  9967. + case 7:
  9968. + return nds32_output_float_store (operands);
  9969. + case 8:
  9970. + return "fcpysd\t%0, %1, %1";
  9971. + case 9:
  9972. + return "fmfdr\t%0, %1";
  9973. + case 10:
  9974. + return "fmtdr\t%1, %0";
  9975. default:
  9976. gcc_unreachable ();
  9977. }
  9978. }
  9979. - [(set_attr "type" "move,move,move,move")
  9980. - (set_attr "length" " 4, 16, 8, 8")])
  9981. + [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown")
  9982. + (set_attr_alternative "length"
  9983. + [
  9984. + ;; Alternative 0
  9985. + (if_then_else (match_test "!TARGET_16_BIT")
  9986. + (const_int 4)
  9987. + (const_int 2))
  9988. + ;; Alternative 1
  9989. + (const_int 16)
  9990. + ;; Alternative 2
  9991. + (const_int 4)
  9992. + ;; Alternative 3
  9993. + (const_int 8)
  9994. + ;; Alternative 4
  9995. + (const_int 4)
  9996. + ;; Alternative 5
  9997. + (const_int 8)
  9998. + ;; Alternative 6
  9999. + (const_int 4)
  10000. + ;; Alternative 7
  10001. + (const_int 4)
  10002. + ;; Alternative 8
  10003. + (const_int 4)
  10004. + ;; Alternative 9
  10005. + (const_int 4)
  10006. + ;; Alternative 10
  10007. + (const_int 4)
  10008. + ])
  10009. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")])
  10010. (define_split
  10011. [(set (match_operand:DIDF 0 "register_operand" "")
  10012. @@ -217,7 +151,9 @@
  10013. [(set (match_operand:DIDF 0 "register_operand" "")
  10014. (match_operand:DIDF 1 "register_operand" ""))]
  10015. "reload_completed
  10016. - && (TARGET_ISA_V2 || !TARGET_16_BIT)"
  10017. + && (TARGET_ISA_V2 || !TARGET_16_BIT)
  10018. + && NDS32_IS_GPR_REGNUM (REGNO (operands[0]))
  10019. + && NDS32_IS_GPR_REGNUM (REGNO (operands[1]))"
  10020. [(set (match_dup 0) (match_dup 1))
  10021. (set (match_dup 2) (match_dup 3))]
  10022. {
  10023. @@ -239,6 +175,28 @@
  10024. }
  10025. })
  10026. +(define_split
  10027. + [(set (match_operand:DIDF 0 "nds32_general_register_operand" "")
  10028. + (match_operand:DIDF 1 "memory_operand" ""))]
  10029. + "reload_completed
  10030. + && !satisfies_constraint_Da (operands[1])"
  10031. + [(set (match_dup 2) (match_dup 3))
  10032. + (set (match_dup 4) (match_dup 5))]
  10033. +{
  10034. + nds32_spilt_doubleword (operands, true);
  10035. +})
  10036. +
  10037. +(define_split
  10038. + [(set (match_operand:DIDF 0 "memory_operand" "")
  10039. + (match_operand:DIDF 1 "nds32_general_register_operand" ""))]
  10040. + "reload_completed
  10041. + && !satisfies_constraint_Da (operands[0])"
  10042. + [(set (match_dup 2) (match_dup 3))
  10043. + (set (match_dup 4) (match_dup 5))]
  10044. +{
  10045. + nds32_spilt_doubleword (operands, false);
  10046. +})
  10047. +
  10048. ;; -------------------------------------------------------------
  10049. ;; Boolean DImode instructions.
  10050. ;; -------------------------------------------------------------
  10051. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-dspext.md gcc-4.9.4/gcc/config/nds32/nds32-dspext.md
  10052. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-dspext.md 1970-01-01 01:00:00.000000000 +0100
  10053. +++ gcc-4.9.4/gcc/config/nds32/nds32-dspext.md 2016-08-08 20:37:45.498269782 +0200
  10054. @@ -0,0 +1,5177 @@
  10055. +;; Machine description of Andes NDS32 cpu for GNU compiler
  10056. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  10057. +;; Contributed by Andes Technology Corporation.
  10058. +;;
  10059. +;; This file is part of GCC.
  10060. +;;
  10061. +;; GCC is free software; you can redistribute it and/or modify it
  10062. +;; under the terms of the GNU General Public License as published
  10063. +;; by the Free Software Foundation; either version 3, or (at your
  10064. +;; option) any later version.
  10065. +;;
  10066. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  10067. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  10068. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  10069. +;; License for more details.
  10070. +;;
  10071. +;; You should have received a copy of the GNU General Public License
  10072. +;; along with GCC; see the file COPYING3. If not see
  10073. +;; <http://www.gnu.org/licenses/>.
  10074. +
  10075. +(define_expand "mov<mode>"
  10076. + [(set (match_operand:VQIHI 0 "general_operand" "")
  10077. + (match_operand:VQIHI 1 "general_operand" ""))]
  10078. + "NDS32_EXT_DSP_P ()"
  10079. +{
  10080. + /* Need to force register if mem <- !reg. */
  10081. + if (MEM_P (operands[0]) && !REG_P (operands[1]))
  10082. + operands[1] = force_reg (<MODE>mode, operands[1]);
  10083. +
  10084. + /* If operands[1] is a large constant and cannot be performed
  10085. + by a single instruction, we need to split it. */
  10086. + if (GET_CODE (operands[1]) == CONST_VECTOR
  10087. + && !satisfies_constraint_CVs2 (operands[1])
  10088. + && !satisfies_constraint_CVhi (operands[1]))
  10089. + {
  10090. + HOST_WIDE_INT ival = const_vector_to_hwint (operands[1]);
  10091. + rtx tmp_rtx;
  10092. +
  10093. + tmp_rtx = can_create_pseudo_p ()
  10094. + ? gen_reg_rtx (SImode)
  10095. + : simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
  10096. +
  10097. + emit_move_insn (tmp_rtx, gen_int_mode (ival, SImode));
  10098. + convert_move (operands[0], tmp_rtx, false);
  10099. + DONE;
  10100. + }
  10101. +
  10102. + if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1]))
  10103. + {
  10104. + if (nds32_tls_referenced_p (operands [1]))
  10105. + {
  10106. + nds32_expand_tls_move (operands);
  10107. + DONE;
  10108. + }
  10109. + else if (flag_pic)
  10110. + {
  10111. + nds32_expand_pic_move (operands);
  10112. + DONE;
  10113. + }
  10114. + }
  10115. +})
  10116. +
  10117. +(define_insn "*mov<mode>"
  10118. + [(set (match_operand:VQIHI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q, A")
  10119. + (match_operand:VQIHI 1 "nds32_vmove_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, CVp5, CVs5, CVs2, CVhi, *f, r, *f, Q, *f, r"))]
  10120. + "NDS32_EXT_DSP_P ()
  10121. + && (register_operand(operands[0], <MODE>mode)
  10122. + || register_operand(operands[1], <MODE>mode))"
  10123. +{
  10124. + switch (which_alternative)
  10125. + {
  10126. + case 0:
  10127. + return "mov55\t%0, %1";
  10128. + case 1:
  10129. + return "ori\t%0, %1, 0";
  10130. + case 2:
  10131. + case 3:
  10132. + case 4:
  10133. + case 5:
  10134. + return nds32_output_16bit_store (operands, <byte>);
  10135. + case 6:
  10136. + return nds32_output_32bit_store (operands, <byte>);
  10137. + case 7:
  10138. + case 8:
  10139. + case 9:
  10140. + case 10:
  10141. + case 11:
  10142. + return nds32_output_16bit_load (operands, <byte>);
  10143. + case 12:
  10144. + return nds32_output_32bit_load (operands, <byte>);
  10145. + case 13:
  10146. + return "movpi45\t%0, %1";
  10147. + case 14:
  10148. + return "movi55\t%0, %1";
  10149. + case 15:
  10150. + return "movi\t%0, %1";
  10151. + case 16:
  10152. + return "sethi\t%0, hi20(%1)";
  10153. + case 17:
  10154. + if (TARGET_FPU_SINGLE)
  10155. + return "fcpyss\t%0, %1, %1";
  10156. + else
  10157. + return "#";
  10158. + case 18:
  10159. + return "fmtsr\t%1, %0";
  10160. + case 19:
  10161. + return "fmfsr\t%0, %1";
  10162. + case 20:
  10163. + return nds32_output_float_load (operands);
  10164. + case 21:
  10165. + return nds32_output_float_store (operands);
  10166. + case 22:
  10167. + return "mtusr\t%1, %0";
  10168. + default:
  10169. + gcc_unreachable ();
  10170. + }
  10171. +}
  10172. + [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,unknown,unknown,unknown,unknown,unknown, alu")
  10173. + (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4, 4")
  10174. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu, v1")])
  10175. +
  10176. +(define_expand "movv2si"
  10177. + [(set (match_operand:V2SI 0 "general_operand" "")
  10178. + (match_operand:V2SI 1 "general_operand" ""))]
  10179. + "NDS32_EXT_DSP_P ()"
  10180. +{
  10181. + /* Need to force register if mem <- !reg. */
  10182. + if (MEM_P (operands[0]) && !REG_P (operands[1]))
  10183. + operands[1] = force_reg (V2SImode, operands[1]);
  10184. +})
  10185. +
  10186. +(define_insn "*movv2si"
  10187. + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f")
  10188. + (match_operand:V2SI 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))]
  10189. + "NDS32_EXT_DSP_P ()
  10190. + && (register_operand(operands[0], V2SImode)
  10191. + || register_operand(operands[1], V2SImode))"
  10192. +{
  10193. + switch (which_alternative)
  10194. + {
  10195. + case 0:
  10196. + return "movd44\t%0, %1";
  10197. + case 1:
  10198. + /* reg <- const_int, we ask gcc to split instruction. */
  10199. + return "#";
  10200. + case 2:
  10201. + /* The memory format is (mem (reg)),
  10202. + we can generate 'lmw.bi' instruction. */
  10203. + return nds32_output_double (operands, true);
  10204. + case 3:
  10205. + /* We haven't 64-bit load instruction,
  10206. + we split this pattern to two SImode pattern. */
  10207. + return "#";
  10208. + case 4:
  10209. + /* The memory format is (mem (reg)),
  10210. + we can generate 'smw.bi' instruction. */
  10211. + return nds32_output_double (operands, false);
  10212. + case 5:
  10213. + /* We haven't 64-bit store instruction,
  10214. + we split this pattern to two SImode pattern. */
  10215. + return "#";
  10216. + case 6:
  10217. + return nds32_output_float_load (operands);
  10218. + case 7:
  10219. + return nds32_output_float_store (operands);
  10220. + case 8:
  10221. + return "fcpysd\t%0, %1, %1";
  10222. + case 9:
  10223. + return "fmfdr\t%0, %1";
  10224. + case 10:
  10225. + return "fmtdr\t%1, %0";
  10226. + default:
  10227. + gcc_unreachable ();
  10228. + }
  10229. +}
  10230. + [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown")
  10231. + (set_attr_alternative "length"
  10232. + [
  10233. + ;; Alternative 0
  10234. + (if_then_else (match_test "!TARGET_16_BIT")
  10235. + (const_int 4)
  10236. + (const_int 2))
  10237. + ;; Alternative 1
  10238. + (const_int 16)
  10239. + ;; Alternative 2
  10240. + (const_int 4)
  10241. + ;; Alternative 3
  10242. + (const_int 8)
  10243. + ;; Alternative 4
  10244. + (const_int 4)
  10245. + ;; Alternative 5
  10246. + (const_int 8)
  10247. + ;; Alternative 6
  10248. + (const_int 4)
  10249. + ;; Alternative 7
  10250. + (const_int 4)
  10251. + ;; Alternative 8
  10252. + (const_int 4)
  10253. + ;; Alternative 9
  10254. + (const_int 4)
  10255. + ;; Alternative 10
  10256. + (const_int 4)
  10257. + ])
  10258. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")])
  10259. +
  10260. +(define_expand "movmisalign<mode>"
  10261. + [(set (match_operand:VQIHI 0 "general_operand" "")
  10262. + (match_operand:VQIHI 1 "general_operand" ""))]
  10263. + "NDS32_EXT_DSP_P ()"
  10264. +{
  10265. + rtx addr;
  10266. + if (MEM_P (operands[0]) && !REG_P (operands[1]))
  10267. + operands[1] = force_reg (<MODE>mode, operands[1]);
  10268. +
  10269. + if (MEM_P (operands[0]))
  10270. + {
  10271. + addr = force_reg (Pmode, XEXP (operands[0], 0));
  10272. + emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
  10273. + }
  10274. + else
  10275. + {
  10276. + addr = force_reg (Pmode, XEXP (operands[1], 0));
  10277. + emit_insn (gen_unaligned_load<mode> (operands[0], addr));
  10278. + }
  10279. + DONE;
  10280. +})
  10281. +
  10282. +(define_expand "unaligned_load<mode>"
  10283. + [(set (match_operand:VQIHI 0 "register_operand" "=r")
  10284. + (unspec:VQIHI [(mem:VQIHI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))]
  10285. + "NDS32_EXT_DSP_P ()"
  10286. +{
  10287. + if (TARGET_ISA_V3M)
  10288. + nds32_expand_unaligned_load (operands, <MODE>mode);
  10289. + else
  10290. + emit_insn (gen_unaligned_load_w<mode> (operands[0], gen_rtx_MEM (<MODE>mode, operands[1])));
  10291. + DONE;
  10292. +})
  10293. +
  10294. +(define_insn "unaligned_load_w<mode>"
  10295. + [(set (match_operand:VQIHI 0 "register_operand" "= r")
  10296. + (unspec:VQIHI [(match_operand:VQIHI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))]
  10297. + "NDS32_EXT_DSP_P ()"
  10298. +{
  10299. + return nds32_output_lmw_single_word (operands);
  10300. +}
  10301. + [(set_attr "type" "load")
  10302. + (set_attr "length" "4")]
  10303. +)
  10304. +
  10305. +(define_expand "unaligned_store<mode>"
  10306. + [(set (mem:VQIHI (match_operand:SI 0 "register_operand" "r"))
  10307. + (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" "r")] UNSPEC_UASTORE_W))]
  10308. + "NDS32_EXT_DSP_P ()"
  10309. +{
  10310. + if (TARGET_ISA_V3M)
  10311. + nds32_expand_unaligned_store (operands, <MODE>mode);
  10312. + else
  10313. + emit_insn (gen_unaligned_store_w<mode> (gen_rtx_MEM (<MODE>mode, operands[0]), operands[1]));
  10314. + DONE;
  10315. +})
  10316. +
  10317. +(define_insn "unaligned_store_w<mode>"
  10318. + [(set (match_operand:VQIHI 0 "nds32_lmw_smw_base_operand" "=Umw")
  10319. + (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" " r")] UNSPEC_UASTORE_W))]
  10320. + "NDS32_EXT_DSP_P ()"
  10321. +{
  10322. + return nds32_output_smw_single_word (operands);
  10323. +}
  10324. + [(set_attr "type" "store")
  10325. + (set_attr "length" "4")]
  10326. +)
  10327. +
  10328. +(define_insn "<uk>add<mode>3"
  10329. + [(set (match_operand:VQIHIDI 0 "register_operand" "=r")
  10330. + (all_plus:VQIHIDI (match_operand:VQIHIDI 1 "register_operand" " r")
  10331. + (match_operand:VQIHIDI 2 "register_operand" " r")))]
  10332. + "NDS32_EXT_DSP_P ()"
  10333. + "<uk>add<bits> %0, %1, %2"
  10334. + [(set_attr "type" "alu")
  10335. + (set_attr "length" "4")
  10336. + (set_attr "feature" "v1")])
  10337. +
  10338. +(define_insn "raddv4qi3"
  10339. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  10340. + (truncate:V4QI
  10341. + (ashiftrt:V4HI
  10342. + (plus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
  10343. + (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
  10344. + (const_int 1))))]
  10345. + "NDS32_EXT_DSP_P ()"
  10346. + "radd8 %0, %1, %2"
  10347. + [(set_attr "type" "alu")
  10348. + (set_attr "length" "4")
  10349. + (set_attr "feature" "v1")])
  10350. +
  10351. +
  10352. +(define_insn "uraddv4qi3"
  10353. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  10354. + (truncate:V4QI
  10355. + (lshiftrt:V4HI
  10356. + (plus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
  10357. + (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
  10358. + (const_int 1))))]
  10359. + "NDS32_EXT_DSP_P ()"
  10360. + "uradd8 %0, %1, %2"
  10361. + [(set_attr "type" "alu")
  10362. + (set_attr "length" "4")
  10363. + (set_attr "feature" "v1")])
  10364. +
  10365. +(define_insn "raddv2hi3"
  10366. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10367. + (truncate:V2HI
  10368. + (ashiftrt:V2SI
  10369. + (plus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
  10370. + (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
  10371. + (const_int 1))))]
  10372. + "NDS32_EXT_DSP_P ()"
  10373. + "radd16 %0, %1, %2"
  10374. + [(set_attr "type" "alu")
  10375. + (set_attr "length" "4")
  10376. + (set_attr "feature" "v1")])
  10377. +
  10378. +(define_insn "uraddv2hi3"
  10379. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10380. + (truncate:V2HI
  10381. + (lshiftrt:V2SI
  10382. + (plus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
  10383. + (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
  10384. + (const_int 1))))]
  10385. + "NDS32_EXT_DSP_P ()"
  10386. + "uradd16 %0, %1, %2"
  10387. + [(set_attr "type" "alu")
  10388. + (set_attr "length" "4")
  10389. + (set_attr "feature" "v1")])
  10390. +
  10391. +(define_insn "radddi3"
  10392. + [(set (match_operand:DI 0 "register_operand" "=r")
  10393. + (truncate:DI
  10394. + (ashiftrt:TI
  10395. + (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
  10396. + (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
  10397. + (const_int 1))))]
  10398. + "NDS32_EXT_DSP_P ()"
  10399. + "radd64 %0, %1, %2"
  10400. + [(set_attr "type" "alu")
  10401. + (set_attr "length" "4")
  10402. + (set_attr "feature" "v1")])
  10403. +
  10404. +
  10405. +(define_insn "uradddi3"
  10406. + [(set (match_operand:DI 0 "register_operand" "=r")
  10407. + (truncate:DI
  10408. + (lshiftrt:TI
  10409. + (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
  10410. + (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
  10411. + (const_int 1))))]
  10412. + "NDS32_EXT_DSP_P ()"
  10413. + "uradd64 %0, %1, %2"
  10414. + [(set_attr "type" "alu")
  10415. + (set_attr "length" "4")
  10416. + (set_attr "feature" "v1")])
  10417. +
  10418. +(define_insn "<uk>sub<mode>3"
  10419. + [(set (match_operand:VQIHIDI 0 "register_operand" "=r")
  10420. + (all_minus:VQIHIDI (match_operand:VQIHIDI 1 "register_operand" " r")
  10421. + (match_operand:VQIHIDI 2 "register_operand" " r")))]
  10422. + "NDS32_EXT_DSP_P ()"
  10423. + "<uk>sub<bits> %0, %1, %2"
  10424. + [(set_attr "type" "alu")
  10425. + (set_attr "length" "4")
  10426. + (set_attr "feature" "v1")])
  10427. +
  10428. +(define_insn "rsubv4qi3"
  10429. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  10430. + (truncate:V4QI
  10431. + (ashiftrt:V4HI
  10432. + (minus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
  10433. + (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
  10434. + (const_int 1))))]
  10435. + "NDS32_EXT_DSP_P ()"
  10436. + "rsub8 %0, %1, %2"
  10437. + [(set_attr "type" "alu")
  10438. + (set_attr "length" "4")])
  10439. +
  10440. +(define_insn "ursubv4qi3"
  10441. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  10442. + (truncate:V4QI
  10443. + (lshiftrt:V4HI
  10444. + (minus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r"))
  10445. + (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r")))
  10446. + (const_int 1))))]
  10447. + "NDS32_EXT_DSP_P ()"
  10448. + "ursub8 %0, %1, %2"
  10449. + [(set_attr "type" "alu")
  10450. + (set_attr "length" "4")])
  10451. +
  10452. +(define_insn "rsubv2hi3"
  10453. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10454. + (truncate:V2HI
  10455. + (ashiftrt:V2SI
  10456. + (minus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
  10457. + (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
  10458. + (const_int 1))))]
  10459. + "NDS32_EXT_DSP_P ()"
  10460. + "rsub16 %0, %1, %2"
  10461. + [(set_attr "type" "alu")
  10462. + (set_attr "length" "4")])
  10463. +
  10464. +(define_insn "ursubv2hi3"
  10465. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10466. + (truncate:V2HI
  10467. + (lshiftrt:V2SI
  10468. + (minus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r"))
  10469. + (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r")))
  10470. + (const_int 1))))]
  10471. + "NDS32_EXT_DSP_P ()"
  10472. + "ursub16 %0, %1, %2"
  10473. + [(set_attr "type" "alu")
  10474. + (set_attr "length" "4")])
  10475. +
  10476. +(define_insn "rsubdi3"
  10477. + [(set (match_operand:DI 0 "register_operand" "=r")
  10478. + (truncate:DI
  10479. + (ashiftrt:TI
  10480. + (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
  10481. + (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
  10482. + (const_int 1))))]
  10483. + "NDS32_EXT_DSP_P ()"
  10484. + "rsub64 %0, %1, %2"
  10485. + [(set_attr "type" "alu")
  10486. + (set_attr "length" "4")])
  10487. +
  10488. +
  10489. +(define_insn "ursubdi3"
  10490. + [(set (match_operand:DI 0 "register_operand" "=r")
  10491. + (truncate:DI
  10492. + (lshiftrt:TI
  10493. + (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
  10494. + (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
  10495. + (const_int 1))))]
  10496. + "NDS32_EXT_DSP_P ()"
  10497. + "ursub64 %0, %1, %2"
  10498. + [(set_attr "type" "alu")
  10499. + (set_attr "length" "4")])
  10500. +
  10501. +(define_expand "cras16_1"
  10502. + [(match_operand:V2HI 0 "register_operand" "")
  10503. + (match_operand:V2HI 1 "register_operand" "")
  10504. + (match_operand:V2HI 2 "register_operand" "")]
  10505. + "NDS32_EXT_DSP_P ()"
  10506. +{
  10507. + if (TARGET_BIG_ENDIAN)
  10508. + emit_insn (gen_cras16_1_be (operands[0], operands[1], operands[2]));
  10509. + else
  10510. + emit_insn (gen_cras16_1_le (operands[0], operands[1], operands[2]));
  10511. + DONE;
  10512. +})
  10513. +
  10514. +(define_insn "cras16_1_le"
  10515. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10516. + (vec_merge:V2HI
  10517. + (vec_duplicate:V2HI
  10518. + (minus:HI
  10519. + (vec_select:HI
  10520. + (match_operand:V2HI 1 "register_operand" " r")
  10521. + (parallel [(const_int 0)]))
  10522. + (vec_select:HI
  10523. + (match_operand:V2HI 2 "register_operand" " r")
  10524. + (parallel [(const_int 1)]))))
  10525. + (vec_duplicate:V2HI
  10526. + (plus:HI
  10527. + (vec_select:HI
  10528. + (match_dup 2)
  10529. + (parallel [(const_int 0)]))
  10530. + (vec_select:HI
  10531. + (match_dup 1)
  10532. + (parallel [(const_int 1)]))))
  10533. + (const_int 1)))]
  10534. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10535. + "cras16\t%0, %1, %2"
  10536. +)
  10537. +
  10538. +(define_insn "cras16_1_be"
  10539. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10540. + (vec_merge:V2HI
  10541. + (vec_duplicate:V2HI
  10542. + (minus:HI
  10543. + (vec_select:HI
  10544. + (match_operand:V2HI 1 "register_operand" " r")
  10545. + (parallel [(const_int 1)]))
  10546. + (vec_select:HI
  10547. + (match_operand:V2HI 2 "register_operand" " r")
  10548. + (parallel [(const_int 0)]))))
  10549. + (vec_duplicate:V2HI
  10550. + (plus:HI
  10551. + (vec_select:HI
  10552. + (match_dup 2)
  10553. + (parallel [(const_int 1)]))
  10554. + (vec_select:HI
  10555. + (match_dup 1)
  10556. + (parallel [(const_int 0)]))))
  10557. + (const_int 2)))]
  10558. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10559. + "cras16\t%0, %1, %2"
  10560. +)
  10561. +
  10562. +(define_expand "kcras16_1"
  10563. + [(match_operand:V2HI 0 "register_operand" "")
  10564. + (match_operand:V2HI 1 "register_operand" "")
  10565. + (match_operand:V2HI 2 "register_operand" "")]
  10566. + "NDS32_EXT_DSP_P ()"
  10567. +{
  10568. + if (TARGET_BIG_ENDIAN)
  10569. + emit_insn (gen_kcras16_1_be (operands[0], operands[1], operands[2]));
  10570. + else
  10571. + emit_insn (gen_kcras16_1_le (operands[0], operands[1], operands[2]));
  10572. + DONE;
  10573. +})
  10574. +
  10575. +(define_insn "kcras16_1_le"
  10576. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10577. + (vec_merge:V2HI
  10578. + (vec_duplicate:V2HI
  10579. + (ss_minus:HI
  10580. + (vec_select:HI
  10581. + (match_operand:V2HI 1 "register_operand" " r")
  10582. + (parallel [(const_int 0)]))
  10583. + (vec_select:HI
  10584. + (match_operand:V2HI 2 "register_operand" " r")
  10585. + (parallel [(const_int 1)]))))
  10586. + (vec_duplicate:V2HI
  10587. + (ss_plus:HI
  10588. + (vec_select:HI
  10589. + (match_dup 2)
  10590. + (parallel [(const_int 0)]))
  10591. + (vec_select:HI
  10592. + (match_dup 1)
  10593. + (parallel [(const_int 1)]))))
  10594. + (const_int 1)))]
  10595. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10596. + "kcras16\t%0, %1, %2"
  10597. +)
  10598. +
  10599. +(define_insn "kcras16_1_be"
  10600. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10601. + (vec_merge:V2HI
  10602. + (vec_duplicate:V2HI
  10603. + (ss_minus:HI
  10604. + (vec_select:HI
  10605. + (match_operand:V2HI 1 "register_operand" " r")
  10606. + (parallel [(const_int 1)]))
  10607. + (vec_select:HI
  10608. + (match_operand:V2HI 2 "register_operand" " r")
  10609. + (parallel [(const_int 0)]))))
  10610. + (vec_duplicate:V2HI
  10611. + (ss_plus:HI
  10612. + (vec_select:HI
  10613. + (match_dup 2)
  10614. + (parallel [(const_int 1)]))
  10615. + (vec_select:HI
  10616. + (match_dup 1)
  10617. + (parallel [(const_int 0)]))))
  10618. + (const_int 2)))]
  10619. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10620. + "kcras16\t%0, %1, %2"
  10621. +)
  10622. +
  10623. +(define_expand "ukcras16_1"
  10624. + [(match_operand:V2HI 0 "register_operand" "")
  10625. + (match_operand:V2HI 1 "register_operand" "")
  10626. + (match_operand:V2HI 2 "register_operand" "")]
  10627. + "NDS32_EXT_DSP_P ()"
  10628. +{
  10629. + if (TARGET_BIG_ENDIAN)
  10630. + emit_insn (gen_ukcras16_1_be (operands[0], operands[1], operands[2]));
  10631. + else
  10632. + emit_insn (gen_ukcras16_1_le (operands[0], operands[1], operands[2]));
  10633. + DONE;
  10634. +})
  10635. +
  10636. +(define_insn "ukcras16_1_le"
  10637. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10638. + (vec_merge:V2HI
  10639. + (vec_duplicate:V2HI
  10640. + (us_minus:HI
  10641. + (vec_select:HI
  10642. + (match_operand:V2HI 1 "register_operand" " r")
  10643. + (parallel [(const_int 0)]))
  10644. + (vec_select:HI
  10645. + (match_operand:V2HI 2 "register_operand" " r")
  10646. + (parallel [(const_int 1)]))))
  10647. + (vec_duplicate:V2HI
  10648. + (us_plus:HI
  10649. + (vec_select:HI
  10650. + (match_dup 2)
  10651. + (parallel [(const_int 0)]))
  10652. + (vec_select:HI
  10653. + (match_dup 1)
  10654. + (parallel [(const_int 1)]))))
  10655. + (const_int 1)))]
  10656. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10657. + "ukcras16\t%0, %1, %2"
  10658. +)
  10659. +
  10660. +(define_insn "ukcras16_1_be"
  10661. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10662. + (vec_merge:V2HI
  10663. + (vec_duplicate:V2HI
  10664. + (us_minus:HI
  10665. + (vec_select:HI
  10666. + (match_operand:V2HI 1 "register_operand" " r")
  10667. + (parallel [(const_int 1)]))
  10668. + (vec_select:HI
  10669. + (match_operand:V2HI 2 "register_operand" " r")
  10670. + (parallel [(const_int 0)]))))
  10671. + (vec_duplicate:V2HI
  10672. + (us_plus:HI
  10673. + (vec_select:HI
  10674. + (match_dup 2)
  10675. + (parallel [(const_int 1)]))
  10676. + (vec_select:HI
  10677. + (match_dup 1)
  10678. + (parallel [(const_int 0)]))))
  10679. + (const_int 2)))]
  10680. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10681. + "ukcras16\t%0, %1, %2"
  10682. +)
  10683. +
  10684. +(define_expand "crsa16_1"
  10685. + [(match_operand:V2HI 0 "register_operand" "")
  10686. + (match_operand:V2HI 1 "register_operand" "")
  10687. + (match_operand:V2HI 2 "register_operand" "")]
  10688. + "NDS32_EXT_DSP_P ()"
  10689. +{
  10690. + if (TARGET_BIG_ENDIAN)
  10691. + emit_insn (gen_crsa16_1_be (operands[0], operands[1], operands[2]));
  10692. + else
  10693. + emit_insn (gen_crsa16_1_le (operands[0], operands[1], operands[2]));
  10694. + DONE;
  10695. +})
  10696. +
  10697. +(define_insn "crsa16_1_le"
  10698. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10699. + (vec_merge:V2HI
  10700. + (vec_duplicate:V2HI
  10701. + (minus:HI
  10702. + (vec_select:HI
  10703. + (match_operand:V2HI 1 "register_operand" " r")
  10704. + (parallel [(const_int 1)]))
  10705. + (vec_select:HI
  10706. + (match_operand:V2HI 2 "register_operand" " r")
  10707. + (parallel [(const_int 0)]))))
  10708. + (vec_duplicate:V2HI
  10709. + (plus:HI
  10710. + (vec_select:HI
  10711. + (match_dup 1)
  10712. + (parallel [(const_int 0)]))
  10713. + (vec_select:HI
  10714. + (match_dup 2)
  10715. + (parallel [(const_int 1)]))))
  10716. + (const_int 2)))]
  10717. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10718. + "crsa16\t%0, %1, %2"
  10719. +)
  10720. +
  10721. +(define_insn "crsa16_1_be"
  10722. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10723. + (vec_merge:V2HI
  10724. + (vec_duplicate:V2HI
  10725. + (minus:HI
  10726. + (vec_select:HI
  10727. + (match_operand:V2HI 1 "register_operand" " r")
  10728. + (parallel [(const_int 0)]))
  10729. + (vec_select:HI
  10730. + (match_operand:V2HI 2 "register_operand" " r")
  10731. + (parallel [(const_int 1)]))))
  10732. + (vec_duplicate:V2HI
  10733. + (plus:HI
  10734. + (vec_select:HI
  10735. + (match_dup 1)
  10736. + (parallel [(const_int 1)]))
  10737. + (vec_select:HI
  10738. + (match_dup 2)
  10739. + (parallel [(const_int 0)]))))
  10740. + (const_int 1)))]
  10741. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10742. + "crsa16\t%0, %1, %2"
  10743. +)
  10744. +
  10745. +(define_expand "kcrsa16_1"
  10746. + [(match_operand:V2HI 0 "register_operand" "")
  10747. + (match_operand:V2HI 1 "register_operand" "")
  10748. + (match_operand:V2HI 2 "register_operand" "")]
  10749. + "NDS32_EXT_DSP_P ()"
  10750. +{
  10751. + if (TARGET_BIG_ENDIAN)
  10752. + emit_insn (gen_kcrsa16_1_be (operands[0], operands[1], operands[2]));
  10753. + else
  10754. + emit_insn (gen_kcrsa16_1_le (operands[0], operands[1], operands[2]));
  10755. + DONE;
  10756. +})
  10757. +
  10758. +(define_insn "kcrsa16_1_le"
  10759. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10760. + (vec_merge:V2HI
  10761. + (vec_duplicate:V2HI
  10762. + (ss_minus:HI
  10763. + (vec_select:HI
  10764. + (match_operand:V2HI 1 "register_operand" " r")
  10765. + (parallel [(const_int 1)]))
  10766. + (vec_select:HI
  10767. + (match_operand:V2HI 2 "register_operand" " r")
  10768. + (parallel [(const_int 0)]))))
  10769. + (vec_duplicate:V2HI
  10770. + (ss_plus:HI
  10771. + (vec_select:HI
  10772. + (match_dup 1)
  10773. + (parallel [(const_int 0)]))
  10774. + (vec_select:HI
  10775. + (match_dup 2)
  10776. + (parallel [(const_int 1)]))))
  10777. + (const_int 2)))]
  10778. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10779. + "kcrsa16\t%0, %1, %2"
  10780. +)
  10781. +
  10782. +(define_insn "kcrsa16_1_be"
  10783. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10784. + (vec_merge:V2HI
  10785. + (vec_duplicate:V2HI
  10786. + (ss_minus:HI
  10787. + (vec_select:HI
  10788. + (match_operand:V2HI 1 "register_operand" " r")
  10789. + (parallel [(const_int 0)]))
  10790. + (vec_select:HI
  10791. + (match_operand:V2HI 2 "register_operand" " r")
  10792. + (parallel [(const_int 1)]))))
  10793. + (vec_duplicate:V2HI
  10794. + (ss_plus:HI
  10795. + (vec_select:HI
  10796. + (match_dup 1)
  10797. + (parallel [(const_int 1)]))
  10798. + (vec_select:HI
  10799. + (match_dup 2)
  10800. + (parallel [(const_int 0)]))))
  10801. + (const_int 1)))]
  10802. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10803. + "kcrsa16\t%0, %1, %2"
  10804. +)
  10805. +
  10806. +(define_expand "ukcrsa16_1"
  10807. + [(match_operand:V2HI 0 "register_operand" "")
  10808. + (match_operand:V2HI 1 "register_operand" "")
  10809. + (match_operand:V2HI 2 "register_operand" "")]
  10810. + "NDS32_EXT_DSP_P ()"
  10811. +{
  10812. + if (TARGET_BIG_ENDIAN)
  10813. + emit_insn (gen_ukcrsa16_1_be (operands[0], operands[1], operands[2]));
  10814. + else
  10815. + emit_insn (gen_ukcrsa16_1_le (operands[0], operands[1], operands[2]));
  10816. + DONE;
  10817. +})
  10818. +
  10819. +(define_insn "ukcrsa16_1_le"
  10820. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10821. + (vec_merge:V2HI
  10822. + (vec_duplicate:V2HI
  10823. + (us_minus:HI
  10824. + (vec_select:HI
  10825. + (match_operand:V2HI 1 "register_operand" " r")
  10826. + (parallel [(const_int 1)]))
  10827. + (vec_select:HI
  10828. + (match_operand:V2HI 2 "register_operand" " r")
  10829. + (parallel [(const_int 0)]))))
  10830. + (vec_duplicate:V2HI
  10831. + (us_plus:HI
  10832. + (vec_select:HI
  10833. + (match_dup 1)
  10834. + (parallel [(const_int 0)]))
  10835. + (vec_select:HI
  10836. + (match_dup 2)
  10837. + (parallel [(const_int 1)]))))
  10838. + (const_int 2)))]
  10839. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10840. + "ukcrsa16\t%0, %1, %2"
  10841. +)
  10842. +
  10843. +(define_insn "ukcrsa16_1_be"
  10844. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10845. + (vec_merge:V2HI
  10846. + (vec_duplicate:V2HI
  10847. + (us_minus:HI
  10848. + (vec_select:HI
  10849. + (match_operand:V2HI 1 "register_operand" " r")
  10850. + (parallel [(const_int 0)]))
  10851. + (vec_select:HI
  10852. + (match_operand:V2HI 2 "register_operand" " r")
  10853. + (parallel [(const_int 1)]))))
  10854. + (vec_duplicate:V2HI
  10855. + (us_plus:HI
  10856. + (vec_select:HI
  10857. + (match_dup 1)
  10858. + (parallel [(const_int 1)]))
  10859. + (vec_select:HI
  10860. + (match_dup 2)
  10861. + (parallel [(const_int 0)]))))
  10862. + (const_int 1)))]
  10863. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10864. + "ukcrsa16\t%0, %1, %2"
  10865. +)
  10866. +
  10867. +(define_expand "rcras16_1"
  10868. + [(match_operand:V2HI 0 "register_operand" "")
  10869. + (match_operand:V2HI 1 "register_operand" "")
  10870. + (match_operand:V2HI 2 "register_operand" "")]
  10871. + "NDS32_EXT_DSP_P ()"
  10872. +{
  10873. + if (TARGET_BIG_ENDIAN)
  10874. + emit_insn (gen_rcras16_1_be (operands[0], operands[1], operands[2]));
  10875. + else
  10876. + emit_insn (gen_rcras16_1_le (operands[0], operands[1], operands[2]));
  10877. + DONE;
  10878. +})
  10879. +
  10880. +(define_insn "rcras16_1_le"
  10881. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10882. + (vec_merge:V2HI
  10883. + (vec_duplicate:V2HI
  10884. + (truncate:HI
  10885. + (ashiftrt:SI
  10886. + (minus:SI
  10887. + (sign_extend:SI
  10888. + (vec_select:HI
  10889. + (match_operand:V2HI 1 "register_operand" " r")
  10890. + (parallel [(const_int 0)])))
  10891. + (sign_extend:SI
  10892. + (vec_select:HI
  10893. + (match_operand:V2HI 2 "register_operand" " r")
  10894. + (parallel [(const_int 1)]))))
  10895. + (const_int 1))))
  10896. + (vec_duplicate:V2HI
  10897. + (truncate:HI
  10898. + (ashiftrt:SI
  10899. + (plus:SI
  10900. + (sign_extend:SI
  10901. + (vec_select:HI
  10902. + (match_dup 2)
  10903. + (parallel [(const_int 0)])))
  10904. + (sign_extend:SI
  10905. + (vec_select:HI
  10906. + (match_dup 1)
  10907. + (parallel [(const_int 1)]))))
  10908. + (const_int 1))))
  10909. + (const_int 1)))]
  10910. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10911. + "rcras16\t%0, %1, %2"
  10912. +)
  10913. +
  10914. +(define_insn "rcras16_1_be"
  10915. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10916. + (vec_merge:V2HI
  10917. + (vec_duplicate:V2HI
  10918. + (truncate:HI
  10919. + (ashiftrt:SI
  10920. + (minus:SI
  10921. + (sign_extend:SI
  10922. + (vec_select:HI
  10923. + (match_operand:V2HI 1 "register_operand" " r")
  10924. + (parallel [(const_int 1)])))
  10925. + (sign_extend:SI
  10926. + (vec_select:HI
  10927. + (match_operand:V2HI 2 "register_operand" " r")
  10928. + (parallel [(const_int 0)]))))
  10929. + (const_int 1))))
  10930. + (vec_duplicate:V2HI
  10931. + (truncate:HI
  10932. + (ashiftrt:SI
  10933. + (plus:SI
  10934. + (sign_extend:SI
  10935. + (vec_select:HI
  10936. + (match_dup 2)
  10937. + (parallel [(const_int 1)])))
  10938. + (sign_extend:SI
  10939. + (vec_select:HI
  10940. + (match_dup 1)
  10941. + (parallel [(const_int 0)]))))
  10942. + (const_int 1))))
  10943. + (const_int 2)))]
  10944. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  10945. + "rcras16\t%0, %1, %2"
  10946. +)
  10947. +
  10948. +(define_expand "urcras16_1"
  10949. + [(match_operand:V2HI 0 "register_operand" "")
  10950. + (match_operand:V2HI 1 "register_operand" "")
  10951. + (match_operand:V2HI 2 "register_operand" "")]
  10952. + "NDS32_EXT_DSP_P ()"
  10953. +{
  10954. + if (TARGET_BIG_ENDIAN)
  10955. + emit_insn (gen_urcras16_1_be (operands[0], operands[1], operands[2]));
  10956. + else
  10957. + emit_insn (gen_urcras16_1_le (operands[0], operands[1], operands[2]));
  10958. + DONE;
  10959. +})
  10960. +
  10961. +(define_insn "urcras16_1_le"
  10962. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10963. + (vec_merge:V2HI
  10964. + (vec_duplicate:V2HI
  10965. + (truncate:HI
  10966. + (lshiftrt:SI
  10967. + (minus:SI
  10968. + (zero_extend:SI
  10969. + (vec_select:HI
  10970. + (match_operand:V2HI 1 "register_operand" " r")
  10971. + (parallel [(const_int 0)])))
  10972. + (zero_extend:SI
  10973. + (vec_select:HI
  10974. + (match_operand:V2HI 2 "register_operand" " r")
  10975. + (parallel [(const_int 1)]))))
  10976. + (const_int 1))))
  10977. + (vec_duplicate:V2HI
  10978. + (truncate:HI
  10979. + (lshiftrt:SI
  10980. + (plus:SI
  10981. + (zero_extend:SI
  10982. + (vec_select:HI
  10983. + (match_dup 2)
  10984. + (parallel [(const_int 0)])))
  10985. + (zero_extend:SI
  10986. + (vec_select:HI
  10987. + (match_dup 1)
  10988. + (parallel [(const_int 1)]))))
  10989. + (const_int 1))))
  10990. + (const_int 1)))]
  10991. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  10992. + "urcras16\t%0, %1, %2"
  10993. +)
  10994. +
  10995. +(define_insn "urcras16_1_be"
  10996. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  10997. + (vec_merge:V2HI
  10998. + (vec_duplicate:V2HI
  10999. + (truncate:HI
  11000. + (lshiftrt:SI
  11001. + (minus:SI
  11002. + (zero_extend:SI
  11003. + (vec_select:HI
  11004. + (match_operand:V2HI 1 "register_operand" " r")
  11005. + (parallel [(const_int 1)])))
  11006. + (zero_extend:SI
  11007. + (vec_select:HI
  11008. + (match_operand:V2HI 2 "register_operand" " r")
  11009. + (parallel [(const_int 0)]))))
  11010. + (const_int 1))))
  11011. + (vec_duplicate:V2HI
  11012. + (truncate:HI
  11013. + (lshiftrt:SI
  11014. + (plus:SI
  11015. + (zero_extend:SI
  11016. + (vec_select:HI
  11017. + (match_dup 2)
  11018. + (parallel [(const_int 1)])))
  11019. + (zero_extend:SI
  11020. + (vec_select:HI
  11021. + (match_dup 1)
  11022. + (parallel [(const_int 0)]))))
  11023. + (const_int 1))))
  11024. + (const_int 2)))]
  11025. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  11026. + "urcras16\t%0, %1, %2"
  11027. +)
  11028. +
  11029. +(define_expand "rcrsa16_1"
  11030. + [(match_operand:V2HI 0 "register_operand" "")
  11031. + (match_operand:V2HI 1 "register_operand" "")
  11032. + (match_operand:V2HI 2 "register_operand" "")]
  11033. + "NDS32_EXT_DSP_P ()"
  11034. +{
  11035. + if (TARGET_BIG_ENDIAN)
  11036. + emit_insn (gen_rcrsa16_1_be (operands[0], operands[1], operands[2]));
  11037. + else
  11038. + emit_insn (gen_rcrsa16_1_le (operands[0], operands[1], operands[2]));
  11039. + DONE;
  11040. +})
  11041. +
  11042. +(define_insn "rcrsa16_1_le"
  11043. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11044. + (vec_merge:V2HI
  11045. + (vec_duplicate:V2HI
  11046. + (truncate:HI
  11047. + (ashiftrt:SI
  11048. + (minus:SI
  11049. + (sign_extend:SI
  11050. + (vec_select:HI
  11051. + (match_operand:V2HI 1 "register_operand" " r")
  11052. + (parallel [(const_int 1)])))
  11053. + (sign_extend:SI
  11054. + (vec_select:HI
  11055. + (match_operand:V2HI 2 "register_operand" " r")
  11056. + (parallel [(const_int 0)]))))
  11057. + (const_int 1))))
  11058. + (vec_duplicate:V2HI
  11059. + (truncate:HI
  11060. + (ashiftrt:SI
  11061. + (plus:SI
  11062. + (sign_extend:SI
  11063. + (vec_select:HI
  11064. + (match_dup 1)
  11065. + (parallel [(const_int 0)])))
  11066. + (sign_extend:SI
  11067. + (vec_select:HI
  11068. + (match_dup 2)
  11069. + (parallel [(const_int 1)]))))
  11070. + (const_int 1))))
  11071. + (const_int 2)))]
  11072. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11073. + "rcrsa16\t%0, %1, %2"
  11074. +)
  11075. +
  11076. +(define_insn "rcrsa16_1_be"
  11077. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11078. + (vec_merge:V2HI
  11079. + (vec_duplicate:V2HI
  11080. + (truncate:HI
  11081. + (ashiftrt:SI
  11082. + (minus:SI
  11083. + (sign_extend:SI
  11084. + (vec_select:HI
  11085. + (match_operand:V2HI 1 "register_operand" " r")
  11086. + (parallel [(const_int 0)])))
  11087. + (sign_extend:SI
  11088. + (vec_select:HI
  11089. + (match_operand:V2HI 2 "register_operand" " r")
  11090. + (parallel [(const_int 1)]))))
  11091. + (const_int 1))))
  11092. + (vec_duplicate:V2HI
  11093. + (truncate:HI
  11094. + (ashiftrt:SI
  11095. + (plus:SI
  11096. + (sign_extend:SI
  11097. + (vec_select:HI
  11098. + (match_dup 1)
  11099. + (parallel [(const_int 1)])))
  11100. + (sign_extend:SI
  11101. + (vec_select:HI
  11102. + (match_dup 2)
  11103. + (parallel [(const_int 0)]))))
  11104. + (const_int 1))))
  11105. + (const_int 1)))]
  11106. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  11107. + "rcrsa16\t%0, %1, %2"
  11108. +)
  11109. +
  11110. +(define_expand "urcrsa16_1"
  11111. + [(match_operand:V2HI 0 "register_operand" "")
  11112. + (match_operand:V2HI 1 "register_operand" "")
  11113. + (match_operand:V2HI 2 "register_operand" "")]
  11114. + "NDS32_EXT_DSP_P ()"
  11115. +{
  11116. + if (TARGET_BIG_ENDIAN)
  11117. + emit_insn (gen_urcrsa16_1_be (operands[0], operands[1], operands[2]));
  11118. + else
  11119. + emit_insn (gen_urcrsa16_1_le (operands[0], operands[1], operands[2]));
  11120. + DONE;
  11121. +})
  11122. +
  11123. +(define_insn "urcrsa16_1_le"
  11124. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11125. + (vec_merge:V2HI
  11126. + (vec_duplicate:V2HI
  11127. + (truncate:HI
  11128. + (lshiftrt:SI
  11129. + (minus:SI
  11130. + (zero_extend:SI
  11131. + (vec_select:HI
  11132. + (match_operand:V2HI 1 "register_operand" " r")
  11133. + (parallel [(const_int 1)])))
  11134. + (zero_extend:SI
  11135. + (vec_select:HI
  11136. + (match_operand:V2HI 2 "register_operand" " r")
  11137. + (parallel [(const_int 0)]))))
  11138. + (const_int 1))))
  11139. + (vec_duplicate:V2HI
  11140. + (truncate:HI
  11141. + (lshiftrt:SI
  11142. + (plus:SI
  11143. + (zero_extend:SI
  11144. + (vec_select:HI
  11145. + (match_dup 1)
  11146. + (parallel [(const_int 0)])))
  11147. + (zero_extend:SI
  11148. + (vec_select:HI
  11149. + (match_dup 2)
  11150. + (parallel [(const_int 1)]))))
  11151. + (const_int 1))))
  11152. + (const_int 2)))]
  11153. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11154. + "urcrsa16\t%0, %1, %2"
  11155. +)
  11156. +
  11157. +(define_insn "urcrsa16_1_be"
  11158. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11159. + (vec_merge:V2HI
  11160. + (vec_duplicate:V2HI
  11161. + (truncate:HI
  11162. + (lshiftrt:SI
  11163. + (minus:SI
  11164. + (zero_extend:SI
  11165. + (vec_select:HI
  11166. + (match_operand:V2HI 1 "register_operand" " r")
  11167. + (parallel [(const_int 0)])))
  11168. + (zero_extend:SI
  11169. + (vec_select:HI
  11170. + (match_operand:V2HI 2 "register_operand" " r")
  11171. + (parallel [(const_int 1)]))))
  11172. + (const_int 1))))
  11173. + (vec_duplicate:V2HI
  11174. + (truncate:HI
  11175. + (lshiftrt:SI
  11176. + (plus:SI
  11177. + (zero_extend:SI
  11178. + (vec_select:HI
  11179. + (match_dup 1)
  11180. + (parallel [(const_int 1)])))
  11181. + (zero_extend:SI
  11182. + (vec_select:HI
  11183. + (match_dup 2)
  11184. + (parallel [(const_int 0)]))))
  11185. + (const_int 1))))
  11186. + (const_int 1)))]
  11187. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  11188. + "urcrsa16\t%0, %1, %2"
  11189. +)
  11190. +
  11191. +(define_expand "<shift>v2hi3"
  11192. + [(set (match_operand:V2HI 0 "register_operand" "")
  11193. + (shifts:V2HI (match_operand:V2HI 1 "register_operand" "")
  11194. + (match_operand:SI 2 "nds32_rimm4u_operand" "")))]
  11195. + "NDS32_EXT_DSP_P ()"
  11196. +{
  11197. + if (operands[2] == const0_rtx)
  11198. + {
  11199. + emit_move_insn (operands[0], operands[1]);
  11200. + DONE;
  11201. + }
  11202. +})
  11203. +
  11204. +(define_insn "*ashlv2hi3"
  11205. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11206. + (ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11207. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
  11208. + "NDS32_EXT_DSP_P ()"
  11209. + "@
  11210. + slli16\t%0, %1, %2
  11211. + sll16\t%0, %1, %2"
  11212. + [(set_attr "type" "alu,alu")
  11213. + (set_attr "length" " 4, 4")])
  11214. +
  11215. +(define_insn "kslli16"
  11216. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11217. + (ss_ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11218. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
  11219. + "NDS32_EXT_DSP_P ()"
  11220. + "@
  11221. + kslli16\t%0, %1, %2
  11222. + ksll16\t%0, %1, %2"
  11223. + [(set_attr "type" "alu,alu")
  11224. + (set_attr "length" " 4, 4")])
  11225. +
  11226. +(define_insn "*ashrv2hi3"
  11227. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11228. + (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11229. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
  11230. + "NDS32_EXT_DSP_P ()"
  11231. + "@
  11232. + srai16\t%0, %1, %2
  11233. + sra16\t%0, %1, %2"
  11234. + [(set_attr "type" "alu,alu")
  11235. + (set_attr "length" " 4, 4")])
  11236. +
  11237. +(define_insn "sra16_round"
  11238. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11239. + (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11240. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))]
  11241. + UNSPEC_ROUND))]
  11242. + "NDS32_EXT_DSP_P ()"
  11243. + "@
  11244. + srai16.u\t%0, %1, %2
  11245. + sra16.u\t%0, %1, %2"
  11246. + [(set_attr "type" "alu,alu")
  11247. + (set_attr "length" " 4, 4")])
  11248. +
  11249. +(define_insn "*lshrv2hi3"
  11250. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11251. + (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11252. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))]
  11253. + "NDS32_EXT_DSP_P ()"
  11254. + "@
  11255. + srli16\t%0, %1, %2
  11256. + srl16\t%0, %1, %2"
  11257. + [(set_attr "type" "alu,alu")
  11258. + (set_attr "length" " 4, 4")])
  11259. +
  11260. +(define_insn "srl16_round"
  11261. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11262. + (unspec:V2HI [(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r")
  11263. + (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))]
  11264. + UNSPEC_ROUND))]
  11265. + "NDS32_EXT_DSP_P ()"
  11266. + "@
  11267. + srli16.u\t%0, %1, %2
  11268. + srl16.u\t%0, %1, %2"
  11269. + [(set_attr "type" "alu,alu")
  11270. + (set_attr "length" " 4, 4")])
  11271. +
  11272. +(define_insn "kslra16"
  11273. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11274. + (if_then_else:V2HI
  11275. + (lt:SI (match_operand:SI 2 "register_operand" " r")
  11276. + (const_int 0))
  11277. + (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r")
  11278. + (neg:SI (match_dup 2)))
  11279. + (ashift:V2HI (match_dup 1)
  11280. + (match_dup 2))))]
  11281. + "NDS32_EXT_DSP_P ()"
  11282. + "kslra16\t%0, %1, %2"
  11283. + [(set_attr "type" "alu")
  11284. + (set_attr "length" "4")])
  11285. +
  11286. +(define_insn "kslra16_round"
  11287. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11288. + (if_then_else:V2HI
  11289. + (lt:SI (match_operand:SI 2 "register_operand" " r")
  11290. + (const_int 0))
  11291. + (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r")
  11292. + (neg:SI (match_dup 2)))]
  11293. + UNSPEC_ROUND)
  11294. + (ashift:V2HI (match_dup 1)
  11295. + (match_dup 2))))]
  11296. + "NDS32_EXT_DSP_P ()"
  11297. + "kslra16.u\t%0, %1, %2"
  11298. + [(set_attr "type" "alu")
  11299. + (set_attr "length" "4")])
  11300. +
  11301. +(define_insn "cmpeq<bits>"
  11302. + [(set (match_operand:SI 0 "register_operand" "=r")
  11303. + (unspec:SI [(eq:SI (match_operand:VQIHI 1 "register_operand" " r")
  11304. + (match_operand:VQIHI 2 "register_operand" " r"))]
  11305. + UNSPEC_VEC_COMPARE))]
  11306. + "NDS32_EXT_DSP_P ()"
  11307. + "cmpeq<bits>\t%0, %1, %2"
  11308. + [(set_attr "type" "alu")
  11309. + (set_attr "length" "4")])
  11310. +
  11311. +(define_insn "scmplt<bits>"
  11312. + [(set (match_operand:SI 0 "register_operand" "=r")
  11313. + (unspec:SI [(lt:SI (match_operand:VQIHI 1 "register_operand" " r")
  11314. + (match_operand:VQIHI 2 "register_operand" " r"))]
  11315. + UNSPEC_VEC_COMPARE))]
  11316. + "NDS32_EXT_DSP_P ()"
  11317. + "scmplt<bits>\t%0, %1, %2"
  11318. + [(set_attr "type" "alu")
  11319. + (set_attr "length" "4")])
  11320. +
  11321. +(define_insn "scmple<bits>"
  11322. + [(set (match_operand:SI 0 "register_operand" "=r")
  11323. + (unspec:SI [(le:SI (match_operand:VQIHI 1 "register_operand" " r")
  11324. + (match_operand:VQIHI 2 "register_operand" " r"))]
  11325. + UNSPEC_VEC_COMPARE))]
  11326. + "NDS32_EXT_DSP_P ()"
  11327. + "scmple<bits>\t%0, %1, %2"
  11328. + [(set_attr "type" "alu")
  11329. + (set_attr "length" "4")])
  11330. +
  11331. +(define_insn "ucmplt<bits>"
  11332. + [(set (match_operand:SI 0 "register_operand" "=r")
  11333. + (unspec:SI [(ltu:SI (match_operand:VQIHI 1 "register_operand" " r")
  11334. + (match_operand:VQIHI 2 "register_operand" " r"))]
  11335. + UNSPEC_VEC_COMPARE))]
  11336. + "NDS32_EXT_DSP_P ()"
  11337. + "ucmplt<bits>\t%0, %1, %2"
  11338. + [(set_attr "type" "alu")
  11339. + (set_attr "length" "4")])
  11340. +
  11341. +(define_insn "ucmple<bits>"
  11342. + [(set (match_operand:SI 0 "register_operand" "=r")
  11343. + (unspec:SI [(leu:SI (match_operand:VQIHI 1 "register_operand" " r")
  11344. + (match_operand:VQIHI 2 "register_operand" " r"))]
  11345. + UNSPEC_VEC_COMPARE))]
  11346. + "NDS32_EXT_DSP_P ()"
  11347. + "ucmple<bits>\t%0, %1, %2"
  11348. + [(set_attr "type" "alu")
  11349. + (set_attr "length" "4")])
  11350. +
  11351. +(define_insn "sclip16"
  11352. + [(set (match_operand:V2HI 0 "register_operand" "= r")
  11353. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
  11354. + (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")]
  11355. + UNSPEC_CLIPS))]
  11356. + "NDS32_EXT_DSP_P ()"
  11357. + "sclip16\t%0, %1, %2"
  11358. + [(set_attr "type" "alu")
  11359. + (set_attr "length" "4")])
  11360. +
  11361. +(define_insn "uclip16"
  11362. + [(set (match_operand:V2HI 0 "register_operand" "= r")
  11363. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
  11364. + (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")]
  11365. + UNSPEC_CLIP))]
  11366. + "NDS32_EXT_DSP_P ()"
  11367. + "uclip16\t%0, %1, %2"
  11368. + [(set_attr "type" "alu")
  11369. + (set_attr "length" "4")])
  11370. +
  11371. +(define_insn "khm16"
  11372. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11373. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
  11374. + (match_operand:V2HI 2 "register_operand" " r")]
  11375. + UNSPEC_KHM))]
  11376. + "NDS32_EXT_DSP_P ()"
  11377. + "khm16\t%0, %1, %2"
  11378. + [(set_attr "type" "alu")
  11379. + (set_attr "length" "4")])
  11380. +
  11381. +(define_insn "khmx16"
  11382. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  11383. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r")
  11384. + (match_operand:V2HI 2 "register_operand" " r")]
  11385. + UNSPEC_KHMX))]
  11386. + "NDS32_EXT_DSP_P ()"
  11387. + "khmx16\t%0, %1, %2"
  11388. + [(set_attr "type" "alu")
  11389. + (set_attr "length" "4")])
  11390. +
  11391. +(define_expand "vec_setv4qi"
  11392. + [(match_operand:V4QI 0 "register_operand" "")
  11393. + (match_operand:QI 1 "register_operand" "")
  11394. + (match_operand:SI 2 "immediate_operand" "")]
  11395. + "NDS32_EXT_DSP_P ()"
  11396. +{
  11397. + HOST_WIDE_INT pos = INTVAL (operands[2]);
  11398. + if (pos > 4)
  11399. + gcc_unreachable ();
  11400. + HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos;
  11401. + emit_insn (gen_vec_setv4qi_internal (operands[0], operands[1],
  11402. + operands[0], GEN_INT (elem)));
  11403. + DONE;
  11404. +})
  11405. +
  11406. +(define_expand "insb"
  11407. + [(match_operand:V4QI 0 "register_operand" "")
  11408. + (match_operand:V4QI 1 "register_operand" "")
  11409. + (match_operand:SI 2 "register_operand" "")
  11410. + (match_operand:SI 3 "const_int_operand" "")]
  11411. + "NDS32_EXT_DSP_P ()"
  11412. +{
  11413. + if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0)
  11414. + gcc_unreachable ();
  11415. +
  11416. + rtx src = gen_reg_rtx (QImode);
  11417. +
  11418. + convert_move (src, operands[2], false);
  11419. +
  11420. + HOST_WIDE_INT selector_index;
  11421. + /* Big endian need reverse index. */
  11422. + if (TARGET_BIG_ENDIAN)
  11423. + selector_index = 4 - INTVAL (operands[3]) - 1;
  11424. + else
  11425. + selector_index = INTVAL (operands[3]);
  11426. + rtx selector = gen_int_mode (1 << selector_index, SImode);
  11427. + emit_insn (gen_vec_setv4qi_internal (operands[0], src,
  11428. + operands[1], selector));
  11429. + DONE;
  11430. +})
  11431. +
  11432. +(define_expand "insvsi"
  11433. + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
  11434. + (match_operand:SI 1 "const_int_operand" "")
  11435. + (match_operand:SI 2 "nds32_insv_operand" ""))
  11436. + (match_operand:SI 3 "register_operand" ""))]
  11437. + "NDS32_EXT_DSP_P ()"
  11438. +{
  11439. + if (INTVAL (operands[1]) != 8)
  11440. + FAIL;
  11441. +}
  11442. + [(set_attr "type" "alu")
  11443. + (set_attr "length" "4")])
  11444. +
  11445. +
  11446. +(define_insn "insvsi_internal"
  11447. + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
  11448. + (const_int 8)
  11449. + (match_operand:SI 1 "nds32_insv_operand" "i"))
  11450. + (match_operand:SI 2 "register_operand" "r"))]
  11451. + "NDS32_EXT_DSP_P ()"
  11452. + "insb\t%0, %2, %v1"
  11453. + [(set_attr "type" "alu")
  11454. + (set_attr "length" "4")])
  11455. +
  11456. +(define_insn "insvsiqi_internal"
  11457. + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
  11458. + (const_int 8)
  11459. + (match_operand:SI 1 "nds32_insv_operand" "i"))
  11460. + (zero_extend:SI (match_operand:QI 2 "register_operand" "r")))]
  11461. + "NDS32_EXT_DSP_P ()"
  11462. + "insb\t%0, %2, %v1"
  11463. + [(set_attr "type" "alu")
  11464. + (set_attr "length" "4")])
  11465. +
  11466. +;; Intermedium pattern for synthetize insvsiqi_internal
  11467. +;; v0 = ((v1 & 0xff) << 8)
  11468. +(define_insn_and_split "and0xff_s8"
  11469. + [(set (match_operand:SI 0 "register_operand" "=r")
  11470. + (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
  11471. + (const_int 8))
  11472. + (const_int 65280)))]
  11473. + "NDS32_EXT_DSP_P () && !reload_completed"
  11474. + "#"
  11475. + "NDS32_EXT_DSP_P () && !reload_completed"
  11476. + [(const_int 1)]
  11477. +{
  11478. + rtx tmp = gen_reg_rtx (SImode);
  11479. + emit_insn (gen_ashlsi3 (tmp, operands[1], gen_int_mode (8, SImode)));
  11480. + emit_insn (gen_andsi3 (operands[0], tmp, gen_int_mode (0xffff, SImode)));
  11481. + DONE;
  11482. +})
  11483. +
  11484. +;; v0 = (v1 & 0xff00ffff) | ((v2 << 16) | 0xff0000)
  11485. +(define_insn_and_split "insbsi2"
  11486. + [(set (match_operand:SI 0 "register_operand" "=r")
  11487. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
  11488. + (const_int -16711681))
  11489. + (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
  11490. + (const_int 16))
  11491. + (const_int 16711680))))]
  11492. + "NDS32_EXT_DSP_P () && !reload_completed"
  11493. + "#"
  11494. + "NDS32_EXT_DSP_P () && !reload_completed"
  11495. + [(const_int 1)]
  11496. +{
  11497. + rtx tmp = gen_reg_rtx (SImode);
  11498. + emit_move_insn (tmp, operands[1]);
  11499. + emit_insn (gen_insvsi_internal (tmp, gen_int_mode(16, SImode), operands[2]));
  11500. + emit_move_insn (operands[0], tmp);
  11501. + DONE;
  11502. +})
  11503. +
  11504. +;; v0 = (v1 & 0xff00ffff) | v2
  11505. +(define_insn_and_split "ior_and0xff00ffff_reg"
  11506. + [(set (match_operand:SI 0 "register_operand" "=r")
  11507. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
  11508. + (const_int -16711681))
  11509. + (match_operand:SI 2 "register_operand" "r")))]
  11510. + "NDS32_EXT_DSP_P () && !reload_completed"
  11511. + "#"
  11512. + "NDS32_EXT_DSP_P () && !reload_completed"
  11513. + [(const_int 1)]
  11514. +{
  11515. + rtx tmp = gen_reg_rtx (SImode);
  11516. + emit_insn (gen_andsi3 (tmp, operands[1], gen_int_mode (0xff00ffff, SImode)));
  11517. + emit_insn (gen_iorsi3 (operands[0], tmp, operands[2]));
  11518. + DONE;
  11519. +})
  11520. +
  11521. +(define_insn "vec_setv4qi_internal"
  11522. + [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r")
  11523. + (vec_merge:V4QI
  11524. + (vec_duplicate:V4QI
  11525. + (match_operand:QI 1 "register_operand" " r, r, r, r"))
  11526. + (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0")
  11527. + (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))]
  11528. + "NDS32_EXT_DSP_P ()"
  11529. +{
  11530. + if (TARGET_BIG_ENDIAN)
  11531. + {
  11532. + const char *pats[] = { "insb\t%0, %1, 3",
  11533. + "insb\t%0, %1, 2",
  11534. + "insb\t%0, %1, 1",
  11535. + "insb\t%0, %1, 0" };
  11536. + return pats[which_alternative];
  11537. + }
  11538. + else
  11539. + {
  11540. + const char *pats[] = { "insb\t%0, %1, 0",
  11541. + "insb\t%0, %1, 1",
  11542. + "insb\t%0, %1, 2",
  11543. + "insb\t%0, %1, 3" };
  11544. + return pats[which_alternative];
  11545. + }
  11546. +}
  11547. + [(set_attr "type" "alu")
  11548. + (set_attr "length" "4")])
  11549. +
  11550. +(define_insn "vec_setv4qi_internal_vec"
  11551. + [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r")
  11552. + (vec_merge:V4QI
  11553. + (vec_duplicate:V4QI
  11554. + (vec_select:QI
  11555. + (match_operand:V4QI 1 "register_operand" " r, r, r, r")
  11556. + (parallel [(const_int 0)])))
  11557. + (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0")
  11558. + (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))]
  11559. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11560. + "@
  11561. + insb\t%0, %1, 0
  11562. + insb\t%0, %1, 1
  11563. + insb\t%0, %1, 2
  11564. + insb\t%0, %1, 3"
  11565. + [(set_attr "type" "alu")
  11566. + (set_attr "length" "4")])
  11567. +
  11568. +(define_insn "vec_mergev4qi_and_cv0_1"
  11569. + [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
  11570. + (vec_merge:V4QI
  11571. + (vec_duplicate:V4QI
  11572. + (vec_select:QI
  11573. + (match_operand:V4QI 1 "register_operand" " l,r")
  11574. + (parallel [(const_int 0)])))
  11575. + (const_vector:V4QI [
  11576. + (const_int 0)
  11577. + (const_int 0)
  11578. + (const_int 0)
  11579. + (const_int 0)])
  11580. + (const_int 1)))]
  11581. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11582. + "@
  11583. + zeb33\t%0, %1
  11584. + zeb\t%0, %1"
  11585. + [(set_attr "type" "alu,alu")
  11586. + (set_attr "length" " 2, 4")])
  11587. +
  11588. +(define_insn "vec_mergev4qi_and_cv0_2"
  11589. + [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
  11590. + (vec_merge:V4QI
  11591. + (const_vector:V4QI [
  11592. + (const_int 0)
  11593. + (const_int 0)
  11594. + (const_int 0)
  11595. + (const_int 0)])
  11596. + (vec_duplicate:V4QI
  11597. + (vec_select:QI
  11598. + (match_operand:V4QI 1 "register_operand" " l,r")
  11599. + (parallel [(const_int 0)])))
  11600. + (const_int 2)))]
  11601. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11602. + "@
  11603. + zeb33\t%0, %1
  11604. + zeb\t%0, %1"
  11605. + [(set_attr "type" "alu,alu")
  11606. + (set_attr "length" " 2, 4")])
  11607. +
  11608. +(define_insn "vec_mergeqi_and_cv0_1"
  11609. + [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
  11610. + (vec_merge:V4QI
  11611. + (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r"))
  11612. + (const_vector:V4QI [
  11613. + (const_int 0)
  11614. + (const_int 0)
  11615. + (const_int 0)
  11616. + (const_int 0)])
  11617. + (const_int 1)))]
  11618. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11619. + "@
  11620. + zeb33\t%0, %1
  11621. + zeb\t%0, %1"
  11622. + [(set_attr "type" "alu,alu")
  11623. + (set_attr "length" " 2, 4")])
  11624. +
  11625. +(define_insn "vec_mergeqi_and_cv0_2"
  11626. + [(set (match_operand:V4QI 0 "register_operand" "=$l,r")
  11627. + (vec_merge:V4QI
  11628. + (const_vector:V4QI [
  11629. + (const_int 0)
  11630. + (const_int 0)
  11631. + (const_int 0)
  11632. + (const_int 0)])
  11633. + (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r"))
  11634. + (const_int 2)))]
  11635. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11636. + "@
  11637. + zeb33\t%0, %1
  11638. + zeb\t%0, %1"
  11639. + [(set_attr "type" "alu,alu")
  11640. + (set_attr "length" " 2, 4")])
  11641. +
  11642. +(define_expand "vec_setv2hi"
  11643. + [(match_operand:V2HI 0 "register_operand" "")
  11644. + (match_operand:HI 1 "register_operand" "")
  11645. + (match_operand:SI 2 "immediate_operand" "")]
  11646. + "NDS32_EXT_DSP_P ()"
  11647. +{
  11648. + HOST_WIDE_INT pos = INTVAL (operands[2]);
  11649. + if (pos > 2)
  11650. + gcc_unreachable ();
  11651. + HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos;
  11652. + emit_insn (gen_vec_setv2hi_internal (operands[0], operands[1],
  11653. + operands[0], GEN_INT (elem)));
  11654. + DONE;
  11655. +})
  11656. +
  11657. +(define_insn "vec_setv2hi_internal"
  11658. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11659. + (vec_merge:V2HI
  11660. + (vec_duplicate:V2HI
  11661. + (match_operand:HI 1 "register_operand" " r, r"))
  11662. + (match_operand:V2HI 2 "register_operand" " r, r")
  11663. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
  11664. + "NDS32_EXT_DSP_P ()"
  11665. +{
  11666. + if (TARGET_BIG_ENDIAN)
  11667. + {
  11668. + const char *pats[] = { "pkbb16\t%0, %1, %2",
  11669. + "pktb16\t%0, %2, %1" };
  11670. + return pats[which_alternative];
  11671. + }
  11672. + else
  11673. + {
  11674. + const char *pats[] = { "pktb16\t%0, %2, %1",
  11675. + "pkbb16\t%0, %1, %2" };
  11676. + return pats[which_alternative];
  11677. + }
  11678. +}
  11679. + [(set_attr "type" "alu")
  11680. + (set_attr "length" "4")])
  11681. +
  11682. +(define_insn "vec_mergev2hi_and_cv0_1"
  11683. + [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
  11684. + (vec_merge:V2HI
  11685. + (vec_duplicate:V2HI
  11686. + (vec_select:HI
  11687. + (match_operand:V2HI 1 "register_operand" " l,r")
  11688. + (parallel [(const_int 0)])))
  11689. + (const_vector:V2HI [
  11690. + (const_int 0)
  11691. + (const_int 0)])
  11692. + (const_int 1)))]
  11693. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11694. + "@
  11695. + zeh33\t%0, %1
  11696. + zeh\t%0, %1"
  11697. + [(set_attr "type" "alu,alu")
  11698. + (set_attr "length" " 2, 4")])
  11699. +
  11700. +(define_insn "vec_mergev2hi_and_cv0_2"
  11701. + [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
  11702. + (vec_merge:V2HI
  11703. + (const_vector:V2HI [
  11704. + (const_int 0)
  11705. + (const_int 0)])
  11706. + (vec_duplicate:V2HI
  11707. + (vec_select:HI
  11708. + (match_operand:V2HI 1 "register_operand" " l,r")
  11709. + (parallel [(const_int 0)])))
  11710. + (const_int 2)))]
  11711. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11712. + "@
  11713. + zeh33\t%0, %1
  11714. + zeh\t%0, %1"
  11715. + [(set_attr "type" "alu,alu")
  11716. + (set_attr "length" " 2, 4")])
  11717. +
  11718. +(define_insn "vec_mergehi_and_cv0_1"
  11719. + [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
  11720. + (vec_merge:V2HI
  11721. + (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r"))
  11722. + (const_vector:V2HI [
  11723. + (const_int 0)
  11724. + (const_int 0)])
  11725. + (const_int 1)))]
  11726. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11727. + "@
  11728. + zeh33\t%0, %1
  11729. + zeh\t%0, %1"
  11730. + [(set_attr "type" "alu,alu")
  11731. + (set_attr "length" " 2, 4")])
  11732. +
  11733. +(define_insn "vec_mergehi_and_cv0_2"
  11734. + [(set (match_operand:V2HI 0 "register_operand" "=$l,r")
  11735. + (vec_merge:V2HI
  11736. + (const_vector:V2HI [
  11737. + (const_int 0)
  11738. + (const_int 0)])
  11739. + (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r"))
  11740. + (const_int 2)))]
  11741. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11742. + "@
  11743. + zeh33\t%0, %1
  11744. + zeh\t%0, %1"
  11745. + [(set_attr "type" "alu,alu")
  11746. + (set_attr "length" " 2, 4")])
  11747. +
  11748. +(define_expand "pkbb"
  11749. + [(match_operand:V2HI 0 "register_operand")
  11750. + (match_operand:V2HI 1 "register_operand")
  11751. + (match_operand:V2HI 2 "register_operand")]
  11752. + "NDS32_EXT_DSP_P ()"
  11753. +{
  11754. + if (TARGET_BIG_ENDIAN)
  11755. + {
  11756. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11757. + GEN_INT (1), GEN_INT (1), GEN_INT (1)));
  11758. + }
  11759. + else
  11760. + {
  11761. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11762. + GEN_INT (2), GEN_INT (0), GEN_INT (0)));
  11763. + }
  11764. + DONE;
  11765. +})
  11766. +
  11767. +(define_insn "pkbbsi_1"
  11768. + [(set (match_operand:SI 0 "register_operand" "=r")
  11769. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
  11770. + (const_int 65535))
  11771. + (ashift:SI (match_operand:SI 2 "register_operand" "r")
  11772. + (const_int 16))))]
  11773. + "NDS32_EXT_DSP_P ()"
  11774. + "pkbb16\t%0, %2, %1"
  11775. + [(set_attr "type" "alu")
  11776. + (set_attr "length" "4")])
  11777. +
  11778. +(define_insn "pkbbsi_2"
  11779. + [(set (match_operand:SI 0 "register_operand" "=r")
  11780. + (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
  11781. + (const_int 16))
  11782. + (and:SI (match_operand:SI 1 "register_operand" "r")
  11783. + (const_int 65535))))]
  11784. + "NDS32_EXT_DSP_P ()"
  11785. + "pkbb16\t%0, %2, %1"
  11786. + [(set_attr "type" "alu")
  11787. + (set_attr "length" "4")])
  11788. +
  11789. +(define_insn "pkbbsi_3"
  11790. + [(set (match_operand:SI 0 "register_operand" "=r")
  11791. + (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
  11792. + (ashift:SI (match_operand:SI 2 "register_operand" "r")
  11793. + (const_int 16))))]
  11794. + "NDS32_EXT_DSP_P ()"
  11795. + "pkbb16\t%0, %2, %1"
  11796. + [(set_attr "type" "alu")
  11797. + (set_attr "length" "4")])
  11798. +
  11799. +(define_insn "pkbbsi_4"
  11800. + [(set (match_operand:SI 0 "register_operand" "=r")
  11801. + (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
  11802. + (const_int 16))
  11803. + (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))))]
  11804. + "NDS32_EXT_DSP_P ()"
  11805. + "pkbb16\t%0, %2, %1"
  11806. + [(set_attr "type" "alu")
  11807. + (set_attr "length" "4")])
  11808. +
  11809. +;; v0 = (v1 & 0xffff0000) | (v2 & 0xffff)
  11810. +(define_insn "pktbsi_1"
  11811. + [(set (match_operand:SI 0 "register_operand" "=r")
  11812. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
  11813. + (const_int -65536))
  11814. + (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  11815. + "NDS32_EXT_DSP_P ()"
  11816. + "pktb16\t%0, %1, %2"
  11817. + [(set_attr "type" "alu")
  11818. + (set_attr "length" "4")])
  11819. +
  11820. +(define_insn "pktbsi_2"
  11821. + [(set (match_operand:SI 0 "register_operand" "=r")
  11822. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r")
  11823. + (const_int -65536))
  11824. + (and:SI (match_operand:SI 2 "register_operand" "r")
  11825. + (const_int 65535))))]
  11826. + "NDS32_EXT_DSP_P ()"
  11827. + "pktb16\t%0, %1, %2"
  11828. + [(set_attr "type" "alu")
  11829. + (set_attr "length" "4")])
  11830. +
  11831. +(define_insn "pktbsi_3"
  11832. + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
  11833. + (const_int 16 )
  11834. + (const_int 0))
  11835. + (match_operand:SI 1 "register_operand" " r"))]
  11836. + "NDS32_EXT_DSP_P ()"
  11837. + "pktb16\t%0, %0, %1"
  11838. + [(set_attr "type" "alu")
  11839. + (set_attr "length" "4")])
  11840. +
  11841. +(define_insn "pktbsi_4"
  11842. + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
  11843. + (const_int 16 )
  11844. + (const_int 0))
  11845. + (zero_extend:SI (match_operand:HI 1 "register_operand" " r")))]
  11846. + "NDS32_EXT_DSP_P ()"
  11847. + "pktb16\t%0, %0, %1"
  11848. + [(set_attr "type" "alu")
  11849. + (set_attr "length" "4")])
  11850. +
  11851. +(define_insn "pkttsi"
  11852. + [(set (match_operand:SI 0 "register_operand" "=r")
  11853. + (ior:SI (and:SI (match_operand:SI 1 "register_operand" " r")
  11854. + (const_int -65536))
  11855. + (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
  11856. + (const_int 16))))]
  11857. + "NDS32_EXT_DSP_P ()"
  11858. + "pktt16\t%0, %1, %2"
  11859. + [(set_attr "type" "alu")
  11860. + (set_attr "length" "4")])
  11861. +
  11862. +(define_expand "pkbt"
  11863. + [(match_operand:V2HI 0 "register_operand")
  11864. + (match_operand:V2HI 1 "register_operand")
  11865. + (match_operand:V2HI 2 "register_operand")]
  11866. + "NDS32_EXT_DSP_P ()"
  11867. +{
  11868. + if (TARGET_BIG_ENDIAN)
  11869. + {
  11870. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11871. + GEN_INT (1), GEN_INT (1), GEN_INT (0)));
  11872. + }
  11873. + else
  11874. + {
  11875. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11876. + GEN_INT (2), GEN_INT (0), GEN_INT (1)));
  11877. + }
  11878. + DONE;
  11879. +})
  11880. +
  11881. +(define_expand "pktt"
  11882. + [(match_operand:V2HI 0 "register_operand")
  11883. + (match_operand:V2HI 1 "register_operand")
  11884. + (match_operand:V2HI 2 "register_operand")]
  11885. + "NDS32_EXT_DSP_P ()"
  11886. +{
  11887. + if (TARGET_BIG_ENDIAN)
  11888. + {
  11889. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11890. + GEN_INT (1), GEN_INT (0), GEN_INT (0)));
  11891. + }
  11892. + else
  11893. + {
  11894. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11895. + GEN_INT (2), GEN_INT (1), GEN_INT (1)));
  11896. + }
  11897. + DONE;
  11898. +})
  11899. +
  11900. +(define_expand "pktb"
  11901. + [(match_operand:V2HI 0 "register_operand")
  11902. + (match_operand:V2HI 1 "register_operand")
  11903. + (match_operand:V2HI 2 "register_operand")]
  11904. + "NDS32_EXT_DSP_P ()"
  11905. +{
  11906. + if (TARGET_BIG_ENDIAN)
  11907. + {
  11908. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11909. + GEN_INT (1), GEN_INT (0), GEN_INT (1)));
  11910. + }
  11911. + else
  11912. + {
  11913. + emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2],
  11914. + GEN_INT (2), GEN_INT (1), GEN_INT (0)));
  11915. + }
  11916. + DONE;
  11917. +})
  11918. +
  11919. +(define_insn "vec_mergerr"
  11920. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11921. + (vec_merge:V2HI
  11922. + (vec_duplicate:V2HI
  11923. + (match_operand:HI 1 "register_operand" " r, r"))
  11924. + (vec_duplicate:V2HI
  11925. + (match_operand:HI 2 "register_operand" " r, r"))
  11926. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
  11927. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11928. + "@
  11929. + pkbb16\t%0, %2, %1
  11930. + pkbb16\t%0, %1, %2"
  11931. + [(set_attr "type" "alu")
  11932. + (set_attr "length" "4")])
  11933. +
  11934. +
  11935. +(define_insn "vec_merge"
  11936. + [(set (match_operand:V2HI 0 "register_operand" "= r, r")
  11937. + (vec_merge:V2HI
  11938. + (match_operand:V2HI 1 "register_operand" " r, r")
  11939. + (match_operand:V2HI 2 "register_operand" " r, r")
  11940. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))]
  11941. + "NDS32_EXT_DSP_P ()"
  11942. +{
  11943. + if (TARGET_BIG_ENDIAN)
  11944. + {
  11945. + const char *pats[] = { "pktb16\t%0, %1, %2",
  11946. + "pktb16\t%0, %2, %1" };
  11947. + return pats[which_alternative];
  11948. + }
  11949. + else
  11950. + {
  11951. + const char *pats[] = { "pktb16\t%0, %2, %1",
  11952. + "pktb16\t%0, %1, %2" };
  11953. + return pats[which_alternative];
  11954. + }
  11955. +}
  11956. + [(set_attr "type" "alu")
  11957. + (set_attr "length" "4")])
  11958. +
  11959. +(define_insn "vec_mergerv"
  11960. + [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r")
  11961. + (vec_merge:V2HI
  11962. + (vec_duplicate:V2HI
  11963. + (match_operand:HI 1 "register_operand" " r, r, r, r"))
  11964. + (vec_duplicate:V2HI
  11965. + (vec_select:HI
  11966. + (match_operand:V2HI 2 "register_operand" " r, r, r, r")
  11967. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")])))
  11968. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))]
  11969. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11970. + "@
  11971. + pkbb16\t%0, %2, %1
  11972. + pktb16\t%0, %2, %1
  11973. + pkbb16\t%0, %1, %2
  11974. + pkbt16\t%0, %1, %2"
  11975. + [(set_attr "type" "alu")
  11976. + (set_attr "length" "4")])
  11977. +
  11978. +(define_insn "vec_mergevr"
  11979. + [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r")
  11980. + (vec_merge:V2HI
  11981. + (vec_duplicate:V2HI
  11982. + (vec_select:HI
  11983. + (match_operand:V2HI 1 "register_operand" " r, r, r, r")
  11984. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")])))
  11985. + (vec_duplicate:V2HI
  11986. + (match_operand:HI 2 "register_operand" " r, r, r, r"))
  11987. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))]
  11988. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  11989. + "@
  11990. + pkbb16\t%0, %2, %1
  11991. + pkbt16\t%0, %2, %1
  11992. + pkbb16\t%0, %1, %2
  11993. + pktb16\t%0, %1, %2"
  11994. + [(set_attr "type" "alu")
  11995. + (set_attr "length" "4")])
  11996. +
  11997. +(define_insn "vec_mergevv"
  11998. + [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r, r, r, r, r")
  11999. + (vec_merge:V2HI
  12000. + (vec_duplicate:V2HI
  12001. + (vec_select:HI
  12002. + (match_operand:V2HI 1 "register_operand" " r, r, r, r, r, r, r, r")
  12003. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01")])))
  12004. + (vec_duplicate:V2HI
  12005. + (vec_select:HI
  12006. + (match_operand:V2HI 2 "register_operand" " r, r, r, r, r, r, r, r")
  12007. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01, Iv00")])))
  12008. + (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv01, Iv01, Iv02, Iv02, Iv02, Iv02")))]
  12009. + "NDS32_EXT_DSP_P ()"
  12010. +{
  12011. + if (TARGET_BIG_ENDIAN)
  12012. + {
  12013. + const char *pats[] = { "pktt16\t%0, %1, %2",
  12014. + "pktb16\t%0, %1, %2",
  12015. + "pkbb16\t%0, %1, %2",
  12016. + "pkbt16\t%0, %1, %2",
  12017. + "pktt16\t%0, %2, %1",
  12018. + "pkbt16\t%0, %2, %1",
  12019. + "pkbb16\t%0, %2, %1",
  12020. + "pktb16\t%0, %2, %1" };
  12021. + return pats[which_alternative];
  12022. + }
  12023. + else
  12024. + {
  12025. + const char *pats[] = { "pkbb16\t%0, %2, %1",
  12026. + "pktb16\t%0, %2, %1",
  12027. + "pktt16\t%0, %2, %1",
  12028. + "pkbt16\t%0, %2, %1",
  12029. + "pkbb16\t%0, %1, %2",
  12030. + "pkbt16\t%0, %1, %2",
  12031. + "pktt16\t%0, %1, %2",
  12032. + "pktb16\t%0, %1, %2" };
  12033. + return pats[which_alternative];
  12034. + }
  12035. +}
  12036. + [(set_attr "type" "alu")
  12037. + (set_attr "length" "4")])
  12038. +
  12039. +(define_expand "vec_extractv4qi"
  12040. + [(set (match_operand:QI 0 "register_operand" "")
  12041. + (vec_select:QI
  12042. + (match_operand:V4QI 1 "nonimmediate_operand" "")
  12043. + (parallel [(match_operand:SI 2 "const_int_operand" "")])))]
  12044. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12045. +{
  12046. + if (INTVAL (operands[2]) != 0
  12047. + && INTVAL (operands[2]) != 1
  12048. + && INTVAL (operands[2]) != 2
  12049. + && INTVAL (operands[2]) != 3)
  12050. + gcc_unreachable ();
  12051. +
  12052. + if (INTVAL (operands[2]) != 0 && MEM_P (operands[0]))
  12053. + FAIL;
  12054. +})
  12055. +
  12056. +(define_insn "vec_extractv4qi0"
  12057. + [(set (match_operand:QI 0 "register_operand" "=l,r,r")
  12058. + (vec_select:QI
  12059. + (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
  12060. + (parallel [(const_int 0)])))]
  12061. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12062. +{
  12063. + switch (which_alternative)
  12064. + {
  12065. + case 0:
  12066. + return "zeb33\t%0, %1";
  12067. + case 1:
  12068. + return "zeb\t%0, %1";
  12069. + case 2:
  12070. + return nds32_output_32bit_load (operands, 1);
  12071. + default:
  12072. + gcc_unreachable ();
  12073. + }
  12074. +}
  12075. + [(set_attr "type" "alu")
  12076. + (set_attr "length" "4")])
  12077. +
  12078. +(define_insn "vec_extractv4qi0_ze"
  12079. + [(set (match_operand:SI 0 "register_operand" "=l,r,r")
  12080. + (zero_extend:SI
  12081. + (vec_select:QI
  12082. + (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
  12083. + (parallel [(const_int 0)]))))]
  12084. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12085. +{
  12086. + switch (which_alternative)
  12087. + {
  12088. + case 0:
  12089. + return "zeb33\t%0, %1";
  12090. + case 1:
  12091. + return "zeb\t%0, %1";
  12092. + case 2:
  12093. + return nds32_output_32bit_load (operands, 1);
  12094. + default:
  12095. + gcc_unreachable ();
  12096. + }
  12097. +}
  12098. + [(set_attr "type" "alu")
  12099. + (set_attr "length" "4")])
  12100. +
  12101. +(define_insn "vec_extractv4qi0_se"
  12102. + [(set (match_operand:SI 0 "register_operand" "=l,r,r")
  12103. + (sign_extend:SI
  12104. + (vec_select:QI
  12105. + (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m")
  12106. + (parallel [(const_int 0)]))))]
  12107. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12108. +{
  12109. + switch (which_alternative)
  12110. + {
  12111. + case 0:
  12112. + return "seb33\t%0, %1";
  12113. + case 1:
  12114. + return "seb\t%0, %1";
  12115. + case 2:
  12116. + return nds32_output_32bit_load_se (operands, 1);
  12117. + default:
  12118. + gcc_unreachable ();
  12119. + }
  12120. +}
  12121. + [(set_attr "type" "alu")
  12122. + (set_attr "length" "4")])
  12123. +
  12124. +(define_insn_and_split "vec_extractv4qi1"
  12125. + [(set (match_operand:QI 0 "register_operand" "=r")
  12126. + (vec_select:QI
  12127. + (match_operand:V4QI 1 "register_operand" " r")
  12128. + (parallel [(const_int 1)])))]
  12129. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12130. + "#"
  12131. + "NDS32_EXT_DSP_P () && !reload_completed"
  12132. + [(const_int 1)]
  12133. +{
  12134. + rtx tmp = gen_reg_rtx (V4QImode);
  12135. + emit_insn (gen_rotrv4qi_1 (tmp, operands[1]));
  12136. + emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
  12137. + DONE;
  12138. +}
  12139. + [(set_attr "type" "alu")
  12140. + (set_attr "length" "4")])
  12141. +
  12142. +(define_insn_and_split "vec_extractv4qi2"
  12143. + [(set (match_operand:QI 0 "register_operand" "=r")
  12144. + (vec_select:QI
  12145. + (match_operand:V4QI 1 "register_operand" " r")
  12146. + (parallel [(const_int 2)])))]
  12147. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12148. + "#"
  12149. + "NDS32_EXT_DSP_P () && !reload_completed"
  12150. + [(const_int 1)]
  12151. +{
  12152. + rtx tmp = gen_reg_rtx (V4QImode);
  12153. + emit_insn (gen_rotrv4qi_2 (tmp, operands[1]));
  12154. + emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
  12155. + DONE;
  12156. +}
  12157. + [(set_attr "type" "alu")
  12158. + (set_attr "length" "4")])
  12159. +
  12160. +(define_insn_and_split "vec_extractv4qi3"
  12161. + [(set (match_operand:QI 0 "register_operand" "=r")
  12162. + (vec_select:QI
  12163. + (match_operand:V4QI 1 "register_operand" " r")
  12164. + (parallel [(const_int 3)])))]
  12165. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12166. + "#"
  12167. + "NDS32_EXT_DSP_P () && !reload_completed"
  12168. + [(const_int 1)]
  12169. +{
  12170. + rtx tmp = gen_reg_rtx (V4QImode);
  12171. + emit_insn (gen_rotrv4qi_3 (tmp, operands[1]));
  12172. + emit_insn (gen_vec_extractv4qi0 (operands[0], tmp));
  12173. + DONE;
  12174. +}
  12175. + [(set_attr "type" "alu")
  12176. + (set_attr "length" "4")])
  12177. +
  12178. +(define_insn "vec_extractv4qi3_se"
  12179. + [(set (match_operand:SI 0 "register_operand" "=$d,r")
  12180. + (sign_extend:SI
  12181. + (vec_select:QI
  12182. + (match_operand:V4QI 1 "register_operand" " 0,r")
  12183. + (parallel [(const_int 3)]))))]
  12184. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12185. + "@
  12186. + srai45\t%0, 24
  12187. + srai\t%0, %1, 24"
  12188. + [(set_attr "type" "alu,alu")
  12189. + (set_attr "length" " 2, 4")])
  12190. +
  12191. +(define_insn "vec_extractv4qi3_ze"
  12192. + [(set (match_operand:SI 0 "register_operand" "=$d,r")
  12193. + (zero_extend:SI
  12194. + (vec_select:QI
  12195. + (match_operand:V4QI 1 "register_operand" " 0,r")
  12196. + (parallel [(const_int 3)]))))]
  12197. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12198. + "@
  12199. + srli45\t%0, 24
  12200. + srli\t%0, %1, 24"
  12201. + [(set_attr "type" "alu,alu")
  12202. + (set_attr "length" " 2, 4")])
  12203. +
  12204. +(define_insn_and_split "vec_extractv4qihi0"
  12205. + [(set (match_operand:HI 0 "register_operand" "=r")
  12206. + (sign_extend:HI
  12207. + (vec_select:QI
  12208. + (match_operand:V4QI 1 "register_operand" " r")
  12209. + (parallel [(const_int 0)]))))]
  12210. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12211. + "#"
  12212. + "NDS32_EXT_DSP_P () && !reload_completed"
  12213. + [(const_int 1)]
  12214. +{
  12215. + rtx tmp = gen_reg_rtx (QImode);
  12216. + emit_insn (gen_vec_extractv4qi0 (tmp, operands[1]));
  12217. + emit_insn (gen_extendqihi2 (operands[0], tmp));
  12218. + DONE;
  12219. +}
  12220. + [(set_attr "type" "alu")
  12221. + (set_attr "length" "4")])
  12222. +
  12223. +(define_insn_and_split "vec_extractv4qihi1"
  12224. + [(set (match_operand:HI 0 "register_operand" "=r")
  12225. + (sign_extend:HI
  12226. + (vec_select:QI
  12227. + (match_operand:V4QI 1 "register_operand" " r")
  12228. + (parallel [(const_int 1)]))))]
  12229. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12230. + "#"
  12231. + "NDS32_EXT_DSP_P () && !reload_completed"
  12232. + [(const_int 1)]
  12233. +{
  12234. + rtx tmp = gen_reg_rtx (QImode);
  12235. + emit_insn (gen_vec_extractv4qi1 (tmp, operands[1]));
  12236. + emit_insn (gen_extendqihi2 (operands[0], tmp));
  12237. + DONE;
  12238. +}
  12239. + [(set_attr "type" "alu")
  12240. + (set_attr "length" "4")])
  12241. +
  12242. +(define_insn_and_split "vec_extractv4qihi2"
  12243. + [(set (match_operand:HI 0 "register_operand" "=r")
  12244. + (sign_extend:HI
  12245. + (vec_select:QI
  12246. + (match_operand:V4QI 1 "register_operand" " r")
  12247. + (parallel [(const_int 2)]))))]
  12248. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12249. + "#"
  12250. + "NDS32_EXT_DSP_P () && !reload_completed"
  12251. + [(const_int 1)]
  12252. +{
  12253. + rtx tmp = gen_reg_rtx (QImode);
  12254. + emit_insn (gen_vec_extractv4qi2 (tmp, operands[1]));
  12255. + emit_insn (gen_extendqihi2 (operands[0], tmp));
  12256. + DONE;
  12257. +}
  12258. + [(set_attr "type" "alu")
  12259. + (set_attr "length" "4")])
  12260. +
  12261. +(define_insn_and_split "vec_extractv4qihi3"
  12262. + [(set (match_operand:HI 0 "register_operand" "=r")
  12263. + (sign_extend:HI
  12264. + (vec_select:QI
  12265. + (match_operand:V4QI 1 "register_operand" " r")
  12266. + (parallel [(const_int 3)]))))]
  12267. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  12268. + "#"
  12269. + "NDS32_EXT_DSP_P () && !reload_completed"
  12270. + [(const_int 1)]
  12271. +{
  12272. + rtx tmp = gen_reg_rtx (QImode);
  12273. + emit_insn (gen_vec_extractv4qi3 (tmp, operands[1]));
  12274. + emit_insn (gen_extendqihi2 (operands[0], tmp));
  12275. + DONE;
  12276. +}
  12277. + [(set_attr "type" "alu")
  12278. + (set_attr "length" "4")])
  12279. +
  12280. +(define_expand "vec_extractv2hi"
  12281. + [(set (match_operand:HI 0 "register_operand" "")
  12282. + (vec_select:HI
  12283. + (match_operand:V2HI 1 "nonimmediate_operand" "")
  12284. + (parallel [(match_operand:SI 2 "const_int_operand" "")])))]
  12285. + "NDS32_EXT_DSP_P ()"
  12286. +{
  12287. + if (INTVAL (operands[2]) != 0
  12288. + && INTVAL (operands[2]) != 1)
  12289. + gcc_unreachable ();
  12290. +
  12291. + if (INTVAL (operands[2]) != 0 && MEM_P (operands[0]))
  12292. + FAIL;
  12293. +})
  12294. +
  12295. +(define_insn "vec_extractv2hi0"
  12296. + [(set (match_operand:HI 0 "register_operand" "=$l,r,r")
  12297. + (vec_select:HI
  12298. + (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m")
  12299. + (parallel [(const_int 0)])))]
  12300. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12301. +{
  12302. + switch (which_alternative)
  12303. + {
  12304. + case 0:
  12305. + return "seh33\t%0, %1";
  12306. + case 1:
  12307. + return "seh\t%0, %1";
  12308. + case 2:
  12309. + return nds32_output_32bit_load_se (operands, 2);
  12310. +
  12311. + default:
  12312. + gcc_unreachable ();
  12313. + }
  12314. +}
  12315. + [(set_attr "type" "alu,alu,load")
  12316. + (set_attr "length" " 2, 4, 4")])
  12317. +
  12318. +(define_insn "vec_extractv2hi0_be"
  12319. + [(set (match_operand:HI 0 "register_operand" "=$d,r")
  12320. + (vec_select:HI
  12321. + (match_operand:V2HI 1 "register_operand" " 0,r")
  12322. + (parallel [(const_int 0)])))]
  12323. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12324. + "@
  12325. + srai45\t%0, 16
  12326. + srai\t%0, %1, 16"
  12327. + [(set_attr "type" "alu,alu")
  12328. + (set_attr "length" " 2, 4")])
  12329. +
  12330. +(define_insn "vec_extractv2hi1"
  12331. + [(set (match_operand:HI 0 "register_operand" "=$d,r")
  12332. + (vec_select:HI
  12333. + (match_operand:V2HI 1 "register_operand" " 0,r")
  12334. + (parallel [(const_int 1)])))]
  12335. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12336. + "@
  12337. + srai45\t%0, 16
  12338. + srai\t%0, %1, 16"
  12339. + [(set_attr "type" "alu,alu")
  12340. + (set_attr "length" " 2, 4")])
  12341. +
  12342. +(define_insn "vec_extractv2hi1_be"
  12343. + [(set (match_operand:HI 0 "register_operand" "=$l,r,r")
  12344. + (vec_select:HI
  12345. + (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m")
  12346. + (parallel [(const_int 1)])))]
  12347. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12348. +{
  12349. + switch (which_alternative)
  12350. + {
  12351. + case 0:
  12352. + return "seh33\t%0, %1";
  12353. + case 1:
  12354. + return "seh\t%0, %1";
  12355. + case 2:
  12356. + return nds32_output_32bit_load_se (operands, 2);
  12357. +
  12358. + default:
  12359. + gcc_unreachable ();
  12360. + }
  12361. +}
  12362. + [(set_attr "type" "alu,alu,load")
  12363. + (set_attr "length" " 2, 4, 4")])
  12364. +
  12365. +(define_insn "<su>mul16"
  12366. + [(set (match_operand:V2SI 0 "register_operand" "=r")
  12367. + (mult:V2SI (extend:V2SI (match_operand:V2HI 1 "register_operand" "%r"))
  12368. + (extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))]
  12369. + "NDS32_EXT_DSP_P ()"
  12370. + "<su>mul16\t%0, %1, %2"
  12371. + [(set_attr "type" "mul")
  12372. + (set_attr "length" "4")])
  12373. +
  12374. +(define_insn "<su>mulx16"
  12375. + [(set (match_operand:V2SI 0 "register_operand" "=r")
  12376. + (vec_merge:V2SI
  12377. + (vec_duplicate:V2SI
  12378. + (mult:SI
  12379. + (extend:SI
  12380. + (vec_select:HI
  12381. + (match_operand:V2HI 1 "register_operand" " r")
  12382. + (parallel [(const_int 0)])))
  12383. + (extend:SI
  12384. + (vec_select:HI
  12385. + (match_operand:V2HI 2 "register_operand" " r")
  12386. + (parallel [(const_int 1)])))))
  12387. + (vec_duplicate:V2SI
  12388. + (mult:SI
  12389. + (extend:SI
  12390. + (vec_select:HI
  12391. + (match_dup 1)
  12392. + (parallel [(const_int 1)])))
  12393. + (extend:SI
  12394. + (vec_select:HI
  12395. + (match_dup 2)
  12396. + (parallel [(const_int 0)])))))
  12397. + (const_int 1)))]
  12398. + "NDS32_EXT_DSP_P ()"
  12399. + "<su>mulx16\t%0, %1, %2"
  12400. + [(set_attr "type" "mul")
  12401. + (set_attr "length" "4")])
  12402. +
  12403. +(define_insn "rotrv2hi_1"
  12404. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12405. + (vec_select:V2HI
  12406. + (match_operand:V2HI 1 "register_operand" " r")
  12407. + (parallel [(const_int 1) (const_int 0)])))]
  12408. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12409. + "rotri\t%0, %1, 16"
  12410. + [(set_attr "type" "alu")
  12411. + (set_attr "length" "4")])
  12412. +
  12413. +(define_insn "rotrv2hi_1_be"
  12414. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12415. + (vec_select:V2HI
  12416. + (match_operand:V2HI 1 "register_operand" " r")
  12417. + (parallel [(const_int 0) (const_int 1)])))]
  12418. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12419. + "rotri\t%0, %1, 16"
  12420. + [(set_attr "type" "alu")
  12421. + (set_attr "length" "4")])
  12422. +
  12423. +(define_insn "rotrv4qi_1"
  12424. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12425. + (vec_select:V4QI
  12426. + (match_operand:V4QI 1 "register_operand" " r")
  12427. + (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 0)])))]
  12428. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12429. + "rotri\t%0, %1, 8"
  12430. + [(set_attr "type" "alu")
  12431. + (set_attr "length" "4")])
  12432. +
  12433. +(define_insn "rotrv4qi_1_be"
  12434. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12435. + (vec_select:V4QI
  12436. + (match_operand:V4QI 1 "register_operand" " r")
  12437. + (parallel [(const_int 2) (const_int 1) (const_int 0) (const_int 3)])))]
  12438. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12439. + "rotri\t%0, %1, 8"
  12440. + [(set_attr "type" "alu")
  12441. + (set_attr "length" "4")])
  12442. +
  12443. +(define_insn "rotrv4qi_2"
  12444. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12445. + (vec_select:V4QI
  12446. + (match_operand:V4QI 1 "register_operand" " r")
  12447. + (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))]
  12448. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12449. + "rotri\t%0, %1, 16"
  12450. + [(set_attr "type" "alu")
  12451. + (set_attr "length" "4")])
  12452. +
  12453. +(define_insn "rotrv4qi_2_be"
  12454. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12455. + (vec_select:V4QI
  12456. + (match_operand:V4QI 1 "register_operand" " r")
  12457. + (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))]
  12458. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12459. + "rotri\t%0, %1, 16"
  12460. + [(set_attr "type" "alu")
  12461. + (set_attr "length" "4")])
  12462. +
  12463. +(define_insn "rotrv4qi_3"
  12464. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12465. + (vec_select:V4QI
  12466. + (match_operand:V4QI 1 "register_operand" " r")
  12467. + (parallel [(const_int 3) (const_int 0) (const_int 1) (const_int 2)])))]
  12468. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12469. + "rotri\t%0, %1, 24"
  12470. + [(set_attr "type" "alu")
  12471. + (set_attr "length" "4")])
  12472. +
  12473. +(define_insn "rotrv4qi_3_be"
  12474. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12475. + (vec_select:V4QI
  12476. + (match_operand:V4QI 1 "register_operand" " r")
  12477. + (parallel [(const_int 0) (const_int 3) (const_int 2) (const_int 1)])))]
  12478. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12479. + "rotri\t%0, %1, 24"
  12480. + [(set_attr "type" "alu")
  12481. + (set_attr "length" "4")])
  12482. +
  12483. +(define_insn "v4qi_dup_10"
  12484. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12485. + (vec_select:V4QI
  12486. + (match_operand:V4QI 1 "register_operand" " r")
  12487. + (parallel [(const_int 0) (const_int 1) (const_int 0) (const_int 1)])))]
  12488. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12489. + "pkbb\t%0, %1, %1"
  12490. + [(set_attr "type" "alu")
  12491. + (set_attr "length" "4")])
  12492. +
  12493. +(define_insn "v4qi_dup_32"
  12494. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  12495. + (vec_select:V4QI
  12496. + (match_operand:V4QI 1 "register_operand" " r")
  12497. + (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)])))]
  12498. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12499. + "pktt\t%0, %1, %1"
  12500. + [(set_attr "type" "alu")
  12501. + (set_attr "length" "4")])
  12502. +
  12503. +(define_expand "vec_unpacks_lo_v4qi"
  12504. + [(match_operand:V2HI 0 "register_operand" "=r")
  12505. + (match_operand:V4QI 1 "register_operand" " r")]
  12506. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12507. +{
  12508. + emit_insn (gen_sunpkd810 (operands[0], operands[1]));
  12509. + DONE;
  12510. +})
  12511. +
  12512. +(define_expand "sunpkd810"
  12513. + [(match_operand:V2HI 0 "register_operand")
  12514. + (match_operand:V4QI 1 "register_operand")]
  12515. + "NDS32_EXT_DSP_P ()"
  12516. +{
  12517. + if (TARGET_BIG_ENDIAN)
  12518. + emit_insn (gen_sunpkd810_imp_be (operands[0], operands[1]));
  12519. + else
  12520. + emit_insn (gen_sunpkd810_imp (operands[0], operands[1]));
  12521. + DONE;
  12522. +})
  12523. +
  12524. +(define_insn "<zs>unpkd810_imp"
  12525. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12526. + (vec_merge:V2HI
  12527. + (vec_duplicate:V2HI
  12528. + (extend:HI
  12529. + (vec_select:QI
  12530. + (match_operand:V4QI 1 "register_operand" " r")
  12531. + (parallel [(const_int 1)]))))
  12532. + (vec_duplicate:V2HI
  12533. + (extend:HI
  12534. + (vec_select:QI
  12535. + (match_dup 1)
  12536. + (parallel [(const_int 0)]))))
  12537. + (const_int 2)))]
  12538. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12539. + "<zs>unpkd810\t%0, %1"
  12540. + [(set_attr "type" "alu")
  12541. + (set_attr "length" "4")])
  12542. +
  12543. +(define_insn "<zs>unpkd810_imp_inv"
  12544. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12545. + (vec_merge:V2HI
  12546. + (vec_duplicate:V2HI
  12547. + (extend:HI
  12548. + (vec_select:QI
  12549. + (match_operand:V4QI 1 "register_operand" " r")
  12550. + (parallel [(const_int 0)]))))
  12551. + (vec_duplicate:V2HI
  12552. + (extend:HI
  12553. + (vec_select:QI
  12554. + (match_dup 1)
  12555. + (parallel [(const_int 1)]))))
  12556. + (const_int 1)))]
  12557. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12558. + "<zs>unpkd810\t%0, %1"
  12559. + [(set_attr "type" "alu")
  12560. + (set_attr "length" "4")])
  12561. +
  12562. +(define_insn "<zs>unpkd810_imp_be"
  12563. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12564. + (vec_merge:V2HI
  12565. + (vec_duplicate:V2HI
  12566. + (extend:HI
  12567. + (vec_select:QI
  12568. + (match_operand:V4QI 1 "register_operand" " r")
  12569. + (parallel [(const_int 2)]))))
  12570. + (vec_duplicate:V2HI
  12571. + (extend:HI
  12572. + (vec_select:QI
  12573. + (match_dup 1)
  12574. + (parallel [(const_int 3)]))))
  12575. + (const_int 1)))]
  12576. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12577. + "<zs>unpkd810\t%0, %1"
  12578. + [(set_attr "type" "alu")
  12579. + (set_attr "length" "4")])
  12580. +
  12581. +(define_insn "<zs>unpkd810_imp_inv_be"
  12582. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12583. + (vec_merge:V2HI
  12584. + (vec_duplicate:V2HI
  12585. + (extend:HI
  12586. + (vec_select:QI
  12587. + (match_operand:V4QI 1 "register_operand" " r")
  12588. + (parallel [(const_int 3)]))))
  12589. + (vec_duplicate:V2HI
  12590. + (extend:HI
  12591. + (vec_select:QI
  12592. + (match_dup 1)
  12593. + (parallel [(const_int 2)]))))
  12594. + (const_int 2)))]
  12595. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12596. + "<zs>unpkd810\t%0, %1"
  12597. + [(set_attr "type" "alu")
  12598. + (set_attr "length" "4")])
  12599. +
  12600. +(define_expand "sunpkd820"
  12601. + [(match_operand:V2HI 0 "register_operand")
  12602. + (match_operand:V4QI 1 "register_operand")]
  12603. + "NDS32_EXT_DSP_P ()"
  12604. +{
  12605. + if (TARGET_BIG_ENDIAN)
  12606. + emit_insn (gen_sunpkd820_imp_be (operands[0], operands[1]));
  12607. + else
  12608. + emit_insn (gen_sunpkd820_imp (operands[0], operands[1]));
  12609. + DONE;
  12610. +})
  12611. +
  12612. +(define_insn "<zs>unpkd820_imp"
  12613. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12614. + (vec_merge:V2HI
  12615. + (vec_duplicate:V2HI
  12616. + (extend:HI
  12617. + (vec_select:QI
  12618. + (match_operand:V4QI 1 "register_operand" " r")
  12619. + (parallel [(const_int 2)]))))
  12620. + (vec_duplicate:V2HI
  12621. + (extend:HI
  12622. + (vec_select:QI
  12623. + (match_dup 1)
  12624. + (parallel [(const_int 0)]))))
  12625. + (const_int 2)))]
  12626. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12627. + "<zs>unpkd820\t%0, %1"
  12628. + [(set_attr "type" "alu")
  12629. + (set_attr "length" "4")])
  12630. +
  12631. +(define_insn "<zs>unpkd820_imp_inv"
  12632. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12633. + (vec_merge:V2HI
  12634. + (vec_duplicate:V2HI
  12635. + (extend:HI
  12636. + (vec_select:QI
  12637. + (match_operand:V4QI 1 "register_operand" " r")
  12638. + (parallel [(const_int 0)]))))
  12639. + (vec_duplicate:V2HI
  12640. + (extend:HI
  12641. + (vec_select:QI
  12642. + (match_dup 1)
  12643. + (parallel [(const_int 2)]))))
  12644. + (const_int 1)))]
  12645. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12646. + "<zs>unpkd820\t%0, %1"
  12647. + [(set_attr "type" "alu")
  12648. + (set_attr "length" "4")])
  12649. +
  12650. +(define_insn "<zs>unpkd820_imp_be"
  12651. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12652. + (vec_merge:V2HI
  12653. + (vec_duplicate:V2HI
  12654. + (extend:HI
  12655. + (vec_select:QI
  12656. + (match_operand:V4QI 1 "register_operand" " r")
  12657. + (parallel [(const_int 1)]))))
  12658. + (vec_duplicate:V2HI
  12659. + (extend:HI
  12660. + (vec_select:QI
  12661. + (match_dup 1)
  12662. + (parallel [(const_int 3)]))))
  12663. + (const_int 1)))]
  12664. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12665. + "<zs>unpkd820\t%0, %1"
  12666. + [(set_attr "type" "alu")
  12667. + (set_attr "length" "4")])
  12668. +
  12669. +(define_insn "<zs>unpkd820_imp_inv_be"
  12670. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12671. + (vec_merge:V2HI
  12672. + (vec_duplicate:V2HI
  12673. + (extend:HI
  12674. + (vec_select:QI
  12675. + (match_operand:V4QI 1 "register_operand" " r")
  12676. + (parallel [(const_int 3)]))))
  12677. + (vec_duplicate:V2HI
  12678. + (extend:HI
  12679. + (vec_select:QI
  12680. + (match_dup 1)
  12681. + (parallel [(const_int 1)]))))
  12682. + (const_int 2)))]
  12683. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12684. + "<zs>unpkd820\t%0, %1"
  12685. + [(set_attr "type" "alu")
  12686. + (set_attr "length" "4")])
  12687. +
  12688. +(define_expand "sunpkd830"
  12689. + [(match_operand:V2HI 0 "register_operand")
  12690. + (match_operand:V4QI 1 "register_operand")]
  12691. + "NDS32_EXT_DSP_P ()"
  12692. +{
  12693. + if (TARGET_BIG_ENDIAN)
  12694. + emit_insn (gen_sunpkd830_imp_be (operands[0], operands[1]));
  12695. + else
  12696. + emit_insn (gen_sunpkd830_imp (operands[0], operands[1]));
  12697. + DONE;
  12698. +})
  12699. +
  12700. +(define_insn "<zs>unpkd830_imp"
  12701. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12702. + (vec_merge:V2HI
  12703. + (vec_duplicate:V2HI
  12704. + (extend:HI
  12705. + (vec_select:QI
  12706. + (match_operand:V4QI 1 "register_operand" " r")
  12707. + (parallel [(const_int 3)]))))
  12708. + (vec_duplicate:V2HI
  12709. + (extend:HI
  12710. + (vec_select:QI
  12711. + (match_dup 1)
  12712. + (parallel [(const_int 0)]))))
  12713. + (const_int 2)))]
  12714. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12715. + "<zs>unpkd830\t%0, %1"
  12716. + [(set_attr "type" "alu")
  12717. + (set_attr "length" "4")])
  12718. +
  12719. +(define_insn "<zs>unpkd830_imp_inv"
  12720. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12721. + (vec_merge:V2HI
  12722. + (vec_duplicate:V2HI
  12723. + (extend:HI
  12724. + (vec_select:QI
  12725. + (match_operand:V4QI 1 "register_operand" " r")
  12726. + (parallel [(const_int 0)]))))
  12727. + (vec_duplicate:V2HI
  12728. + (extend:HI
  12729. + (vec_select:QI
  12730. + (match_dup 1)
  12731. + (parallel [(const_int 3)]))))
  12732. + (const_int 1)))]
  12733. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12734. + "<zs>unpkd830\t%0, %1"
  12735. + [(set_attr "type" "alu")
  12736. + (set_attr "length" "4")])
  12737. +
  12738. +(define_insn "<zs>unpkd830_imp_be"
  12739. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12740. + (vec_merge:V2HI
  12741. + (vec_duplicate:V2HI
  12742. + (extend:HI
  12743. + (vec_select:QI
  12744. + (match_operand:V4QI 1 "register_operand" " r")
  12745. + (parallel [(const_int 0)]))))
  12746. + (vec_duplicate:V2HI
  12747. + (extend:HI
  12748. + (vec_select:QI
  12749. + (match_dup 1)
  12750. + (parallel [(const_int 3)]))))
  12751. + (const_int 1)))]
  12752. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12753. + "<zs>unpkd830\t%0, %1"
  12754. + [(set_attr "type" "alu")
  12755. + (set_attr "length" "4")])
  12756. +
  12757. +(define_insn "<zs>unpkd830_imp_inv_be"
  12758. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12759. + (vec_merge:V2HI
  12760. + (vec_duplicate:V2HI
  12761. + (extend:HI
  12762. + (vec_select:QI
  12763. + (match_operand:V4QI 1 "register_operand" " r")
  12764. + (parallel [(const_int 3)]))))
  12765. + (vec_duplicate:V2HI
  12766. + (extend:HI
  12767. + (vec_select:QI
  12768. + (match_dup 1)
  12769. + (parallel [(const_int 0)]))))
  12770. + (const_int 2)))]
  12771. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12772. + "<zs>unpkd830\t%0, %1"
  12773. + [(set_attr "type" "alu")
  12774. + (set_attr "length" "4")])
  12775. +
  12776. +(define_expand "sunpkd831"
  12777. + [(match_operand:V2HI 0 "register_operand")
  12778. + (match_operand:V4QI 1 "register_operand")]
  12779. + "NDS32_EXT_DSP_P ()"
  12780. +{
  12781. + if (TARGET_BIG_ENDIAN)
  12782. + emit_insn (gen_sunpkd831_imp_be (operands[0], operands[1]));
  12783. + else
  12784. + emit_insn (gen_sunpkd831_imp (operands[0], operands[1]));
  12785. + DONE;
  12786. +})
  12787. +
  12788. +(define_insn "<zs>unpkd831_imp"
  12789. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12790. + (vec_merge:V2HI
  12791. + (vec_duplicate:V2HI
  12792. + (extend:HI
  12793. + (vec_select:QI
  12794. + (match_operand:V4QI 1 "register_operand" " r")
  12795. + (parallel [(const_int 3)]))))
  12796. + (vec_duplicate:V2HI
  12797. + (extend:HI
  12798. + (vec_select:QI
  12799. + (match_dup 1)
  12800. + (parallel [(const_int 1)]))))
  12801. + (const_int 2)))]
  12802. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12803. + "<zs>unpkd831\t%0, %1"
  12804. + [(set_attr "type" "alu")
  12805. + (set_attr "length" "4")])
  12806. +
  12807. +(define_insn "<zs>unpkd831_imp_inv"
  12808. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12809. + (vec_merge:V2HI
  12810. + (vec_duplicate:V2HI
  12811. + (extend:HI
  12812. + (vec_select:QI
  12813. + (match_operand:V4QI 1 "register_operand" " r")
  12814. + (parallel [(const_int 1)]))))
  12815. + (vec_duplicate:V2HI
  12816. + (extend:HI
  12817. + (vec_select:QI
  12818. + (match_dup 1)
  12819. + (parallel [(const_int 3)]))))
  12820. + (const_int 1)))]
  12821. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  12822. + "<zs>unpkd831\t%0, %1"
  12823. + [(set_attr "type" "alu")
  12824. + (set_attr "length" "4")])
  12825. +
  12826. +(define_insn "<zs>unpkd831_imp_be"
  12827. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12828. + (vec_merge:V2HI
  12829. + (vec_duplicate:V2HI
  12830. + (extend:HI
  12831. + (vec_select:QI
  12832. + (match_operand:V4QI 1 "register_operand" " r")
  12833. + (parallel [(const_int 0)]))))
  12834. + (vec_duplicate:V2HI
  12835. + (extend:HI
  12836. + (vec_select:QI
  12837. + (match_dup 1)
  12838. + (parallel [(const_int 2)]))))
  12839. + (const_int 1)))]
  12840. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12841. + "<zs>unpkd831\t%0, %1"
  12842. + [(set_attr "type" "alu")
  12843. + (set_attr "length" "4")])
  12844. +
  12845. +(define_insn "<zs>unpkd831_imp_inv_be"
  12846. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  12847. + (vec_merge:V2HI
  12848. + (vec_duplicate:V2HI
  12849. + (extend:HI
  12850. + (vec_select:QI
  12851. + (match_operand:V4QI 1 "register_operand" " r")
  12852. + (parallel [(const_int 2)]))))
  12853. + (vec_duplicate:V2HI
  12854. + (extend:HI
  12855. + (vec_select:QI
  12856. + (match_dup 1)
  12857. + (parallel [(const_int 0)]))))
  12858. + (const_int 2)))]
  12859. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  12860. + "<zs>unpkd831\t%0, %1"
  12861. + [(set_attr "type" "alu")
  12862. + (set_attr "length" "4")])
  12863. +
  12864. +(define_expand "zunpkd810"
  12865. + [(match_operand:V2HI 0 "register_operand")
  12866. + (match_operand:V4QI 1 "register_operand")]
  12867. + "NDS32_EXT_DSP_P ()"
  12868. +{
  12869. + if (TARGET_BIG_ENDIAN)
  12870. + emit_insn (gen_zunpkd810_imp_be (operands[0], operands[1]));
  12871. + else
  12872. + emit_insn (gen_zunpkd810_imp (operands[0], operands[1]));
  12873. + DONE;
  12874. +})
  12875. +
  12876. +(define_expand "zunpkd820"
  12877. + [(match_operand:V2HI 0 "register_operand")
  12878. + (match_operand:V4QI 1 "register_operand")]
  12879. + "NDS32_EXT_DSP_P ()"
  12880. +{
  12881. + if (TARGET_BIG_ENDIAN)
  12882. + emit_insn (gen_zunpkd820_imp_be (operands[0], operands[1]));
  12883. + else
  12884. + emit_insn (gen_zunpkd820_imp (operands[0], operands[1]));
  12885. + DONE;
  12886. +})
  12887. +
  12888. +(define_expand "zunpkd830"
  12889. + [(match_operand:V2HI 0 "register_operand")
  12890. + (match_operand:V4QI 1 "register_operand")]
  12891. + "NDS32_EXT_DSP_P ()"
  12892. +{
  12893. + if (TARGET_BIG_ENDIAN)
  12894. + emit_insn (gen_zunpkd830_imp_be (operands[0], operands[1]));
  12895. + else
  12896. + emit_insn (gen_zunpkd830_imp (operands[0], operands[1]));
  12897. + DONE;
  12898. +})
  12899. +
  12900. +(define_expand "zunpkd831"
  12901. + [(match_operand:V2HI 0 "register_operand")
  12902. + (match_operand:V4QI 1 "register_operand")]
  12903. + "NDS32_EXT_DSP_P ()"
  12904. +{
  12905. + if (TARGET_BIG_ENDIAN)
  12906. + emit_insn (gen_zunpkd831_imp_be (operands[0], operands[1]));
  12907. + else
  12908. + emit_insn (gen_zunpkd831_imp (operands[0], operands[1]));
  12909. + DONE;
  12910. +})
  12911. +
  12912. +(define_expand "smbb"
  12913. + [(match_operand:SI 0 "register_operand" "")
  12914. + (match_operand:V2HI 1 "register_operand" "")
  12915. + (match_operand:V2HI 2 "register_operand" "")]
  12916. + "NDS32_EXT_DSP_P ()"
  12917. +{
  12918. + if (TARGET_BIG_ENDIAN)
  12919. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12920. + GEN_INT (1), GEN_INT (1)));
  12921. + else
  12922. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12923. + GEN_INT (0), GEN_INT (0)));
  12924. + DONE;
  12925. +})
  12926. +
  12927. +(define_expand "smbt"
  12928. + [(match_operand:SI 0 "register_operand" "")
  12929. + (match_operand:V2HI 1 "register_operand" "")
  12930. + (match_operand:V2HI 2 "register_operand" "")]
  12931. + "NDS32_EXT_DSP_P ()"
  12932. +{
  12933. + if (TARGET_BIG_ENDIAN)
  12934. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12935. + GEN_INT (1), GEN_INT (0)));
  12936. + else
  12937. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12938. + GEN_INT (0), GEN_INT (1)));
  12939. + DONE;
  12940. +})
  12941. +
  12942. +(define_expand "smtt"
  12943. + [(match_operand:SI 0 "register_operand" "")
  12944. + (match_operand:V2HI 1 "register_operand" "")
  12945. + (match_operand:V2HI 2 "register_operand" "")]
  12946. + "NDS32_EXT_DSP_P ()"
  12947. +{
  12948. + if (TARGET_BIG_ENDIAN)
  12949. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12950. + GEN_INT (0), GEN_INT (0)));
  12951. + else
  12952. + emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
  12953. + GEN_INT (1), GEN_INT (1)));
  12954. + DONE;
  12955. +})
  12956. +
  12957. +(define_insn "mulhisi3v"
  12958. + [(set (match_operand:SI 0 "register_operand" "= r, r, r, r")
  12959. + (mult:SI
  12960. + (sign_extend:SI
  12961. + (vec_select:HI
  12962. + (match_operand:V2HI 1 "register_operand" " r, r, r, r")
  12963. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
  12964. + (sign_extend:SI (vec_select:HI
  12965. + (match_operand:V2HI 2 "register_operand" " r, r, r, r")
  12966. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))))]
  12967. + "NDS32_EXT_DSP_P ()"
  12968. +{
  12969. + if (TARGET_BIG_ENDIAN)
  12970. + {
  12971. + const char *pats[] = { "smtt\t%0, %1, %2",
  12972. + "smbt\t%0, %2, %1",
  12973. + "smbb\t%0, %1, %2",
  12974. + "smbt\t%0, %1, %2" };
  12975. + return pats[which_alternative];
  12976. + }
  12977. + else
  12978. + {
  12979. + const char *pats[] = { "smbb\t%0, %1, %2",
  12980. + "smbt\t%0, %1, %2",
  12981. + "smtt\t%0, %1, %2",
  12982. + "smbt\t%0, %2, %1" };
  12983. + return pats[which_alternative];
  12984. + }
  12985. +}
  12986. + [(set_attr "type" "mul")
  12987. + (set_attr "length" "4")])
  12988. +
  12989. +(define_expand "kmabb"
  12990. + [(match_operand:SI 0 "register_operand" "")
  12991. + (match_operand:SI 1 "register_operand" "")
  12992. + (match_operand:V2HI 2 "register_operand" "")
  12993. + (match_operand:V2HI 3 "register_operand" "")]
  12994. + "NDS32_EXT_DSP_P ()"
  12995. +{
  12996. + if (TARGET_BIG_ENDIAN)
  12997. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  12998. + GEN_INT (1), GEN_INT (1),
  12999. + operands[1]));
  13000. + else
  13001. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  13002. + GEN_INT (0), GEN_INT (0),
  13003. + operands[1]));
  13004. + DONE;
  13005. +})
  13006. +
  13007. +(define_expand "kmabt"
  13008. + [(match_operand:SI 0 "register_operand" "")
  13009. + (match_operand:SI 1 "register_operand" "")
  13010. + (match_operand:V2HI 2 "register_operand" "")
  13011. + (match_operand:V2HI 3 "register_operand" "")]
  13012. + "NDS32_EXT_DSP_P ()"
  13013. +{
  13014. + if (TARGET_BIG_ENDIAN)
  13015. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  13016. + GEN_INT (1), GEN_INT (0),
  13017. + operands[1]));
  13018. + else
  13019. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  13020. + GEN_INT (0), GEN_INT (1),
  13021. + operands[1]));
  13022. + DONE;
  13023. +})
  13024. +
  13025. +(define_expand "kmatt"
  13026. + [(match_operand:SI 0 "register_operand" "")
  13027. + (match_operand:SI 1 "register_operand" "")
  13028. + (match_operand:V2HI 2 "register_operand" "")
  13029. + (match_operand:V2HI 3 "register_operand" "")]
  13030. + "NDS32_EXT_DSP_P ()"
  13031. +{
  13032. + if (TARGET_BIG_ENDIAN)
  13033. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  13034. + GEN_INT (0), GEN_INT (0),
  13035. + operands[1]));
  13036. + else
  13037. + emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
  13038. + GEN_INT (1), GEN_INT (1),
  13039. + operands[1]));
  13040. + DONE;
  13041. +})
  13042. +
  13043. +(define_insn "kma_internal"
  13044. + [(set (match_operand:SI 0 "register_operand" "= r, r, r, r")
  13045. + (ss_plus:SI
  13046. + (match_operand:SI 5 "register_operand" " 0, 0, 0, 0")
  13047. + (mult:SI
  13048. + (sign_extend:SI
  13049. + (vec_select:HI
  13050. + (match_operand:V2HI 1 "register_operand" " r, r, r, r")
  13051. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
  13052. + (sign_extend:SI
  13053. + (vec_select:HI
  13054. + (match_operand:V2HI 2 "register_operand" " r, r, r, r")
  13055. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))]
  13056. + "NDS32_EXT_DSP_P ()"
  13057. +{
  13058. + if (TARGET_BIG_ENDIAN)
  13059. + {
  13060. + const char *pats[] = { "kmatt\t%0, %1, %2",
  13061. + "kmabt\t%0, %2, %1",
  13062. + "kmabb\t%0, %1, %2",
  13063. + "kmabt\t%0, %1, %2" };
  13064. + return pats[which_alternative];
  13065. + }
  13066. + else
  13067. + {
  13068. + const char *pats[] = { "kmabb\t%0, %1, %2",
  13069. + "kmabt\t%0, %1, %2",
  13070. + "kmatt\t%0, %1, %2",
  13071. + "kmabt\t%0, %2, %1" };
  13072. + return pats[which_alternative];
  13073. + }
  13074. +}
  13075. + [(set_attr "type" "mac")
  13076. + (set_attr "length" "4")])
  13077. +
  13078. +(define_expand "smds"
  13079. + [(match_operand:SI 0 "register_operand" "")
  13080. + (match_operand:V2HI 1 "register_operand" "")
  13081. + (match_operand:V2HI 2 "register_operand" "")]
  13082. + "NDS32_EXT_DSP_P ()"
  13083. +{
  13084. + if (TARGET_BIG_ENDIAN)
  13085. + emit_insn (gen_smds_be (operands[0], operands[1], operands[2]));
  13086. + else
  13087. + emit_insn (gen_smds_le (operands[0], operands[1], operands[2]));
  13088. + DONE;
  13089. +})
  13090. +
  13091. +(define_expand "smds_le"
  13092. + [(set (match_operand:SI 0 "register_operand" "=r")
  13093. + (minus:SI
  13094. + (mult:SI
  13095. + (sign_extend:SI (vec_select:HI
  13096. + (match_operand:V2HI 1 "register_operand" " r")
  13097. + (parallel [(const_int 1)])))
  13098. + (sign_extend:SI (vec_select:HI
  13099. + (match_operand:V2HI 2 "register_operand" " r")
  13100. + (parallel [(const_int 1)]))))
  13101. + (mult:SI
  13102. + (sign_extend:SI (vec_select:HI
  13103. + (match_dup 1)
  13104. + (parallel [(const_int 0)])))
  13105. + (sign_extend:SI (vec_select:HI
  13106. + (match_dup 2)
  13107. + (parallel [(const_int 0)]))))))]
  13108. + "NDS32_EXT_DSP_P ()"
  13109. +{
  13110. +})
  13111. +
  13112. +(define_expand "smds_be"
  13113. + [(set (match_operand:SI 0 "register_operand" "=r")
  13114. + (minus:SI
  13115. + (mult:SI
  13116. + (sign_extend:SI (vec_select:HI
  13117. + (match_operand:V2HI 1 "register_operand" " r")
  13118. + (parallel [(const_int 0)])))
  13119. + (sign_extend:SI (vec_select:HI
  13120. + (match_operand:V2HI 2 "register_operand" " r")
  13121. + (parallel [(const_int 0)]))))
  13122. + (mult:SI
  13123. + (sign_extend:SI (vec_select:HI
  13124. + (match_dup 1)
  13125. + (parallel [(const_int 1)])))
  13126. + (sign_extend:SI (vec_select:HI
  13127. + (match_dup 2)
  13128. + (parallel [(const_int 1)]))))))]
  13129. + "NDS32_EXT_DSP_P ()"
  13130. +{
  13131. +})
  13132. +
  13133. +(define_expand "smdrs"
  13134. + [(match_operand:SI 0 "register_operand" "")
  13135. + (match_operand:V2HI 1 "register_operand" "")
  13136. + (match_operand:V2HI 2 "register_operand" "")]
  13137. + "NDS32_EXT_DSP_P ()"
  13138. +{
  13139. + if (TARGET_BIG_ENDIAN)
  13140. + emit_insn (gen_smdrs_be (operands[0], operands[1], operands[2]));
  13141. + else
  13142. + emit_insn (gen_smdrs_le (operands[0], operands[1], operands[2]));
  13143. + DONE;
  13144. +})
  13145. +
  13146. +(define_expand "smdrs_le"
  13147. + [(set (match_operand:SI 0 "register_operand" "=r")
  13148. + (minus:SI
  13149. + (mult:SI
  13150. + (sign_extend:SI (vec_select:HI
  13151. + (match_operand:V2HI 1 "register_operand" " r")
  13152. + (parallel [(const_int 0)])))
  13153. + (sign_extend:SI (vec_select:HI
  13154. + (match_operand:V2HI 2 "register_operand" " r")
  13155. + (parallel [(const_int 0)]))))
  13156. + (mult:SI
  13157. + (sign_extend:SI (vec_select:HI
  13158. + (match_dup 1)
  13159. + (parallel [(const_int 1)])))
  13160. + (sign_extend:SI (vec_select:HI
  13161. + (match_dup 2)
  13162. + (parallel [(const_int 1)]))))))]
  13163. + "NDS32_EXT_DSP_P ()"
  13164. +{
  13165. +})
  13166. +
  13167. +(define_expand "smdrs_be"
  13168. + [(set (match_operand:SI 0 "register_operand" "=r")
  13169. + (minus:SI
  13170. + (mult:SI
  13171. + (sign_extend:SI (vec_select:HI
  13172. + (match_operand:V2HI 1 "register_operand" " r")
  13173. + (parallel [(const_int 1)])))
  13174. + (sign_extend:SI (vec_select:HI
  13175. + (match_operand:V2HI 2 "register_operand" " r")
  13176. + (parallel [(const_int 1)]))))
  13177. + (mult:SI
  13178. + (sign_extend:SI (vec_select:HI
  13179. + (match_dup 1)
  13180. + (parallel [(const_int 0)])))
  13181. + (sign_extend:SI (vec_select:HI
  13182. + (match_dup 2)
  13183. + (parallel [(const_int 0)]))))))]
  13184. + "NDS32_EXT_DSP_P ()"
  13185. +{
  13186. +})
  13187. +
  13188. +(define_expand "smxdsv"
  13189. + [(match_operand:SI 0 "register_operand" "")
  13190. + (match_operand:V2HI 1 "register_operand" "")
  13191. + (match_operand:V2HI 2 "register_operand" "")]
  13192. + "NDS32_EXT_DSP_P ()"
  13193. +{
  13194. + if (TARGET_BIG_ENDIAN)
  13195. + emit_insn (gen_smxdsv_be (operands[0], operands[1], operands[2]));
  13196. + else
  13197. + emit_insn (gen_smxdsv_le (operands[0], operands[1], operands[2]));
  13198. + DONE;
  13199. +})
  13200. +
  13201. +
  13202. +(define_expand "smxdsv_le"
  13203. + [(set (match_operand:SI 0 "register_operand" "=r")
  13204. + (minus:SI
  13205. + (mult:SI
  13206. + (sign_extend:SI (vec_select:HI
  13207. + (match_operand:V2HI 1 "register_operand" " r")
  13208. + (parallel [(const_int 1)])))
  13209. + (sign_extend:SI (vec_select:HI
  13210. + (match_operand:V2HI 2 "register_operand" " r")
  13211. + (parallel [(const_int 0)]))))
  13212. + (mult:SI
  13213. + (sign_extend:SI (vec_select:HI
  13214. + (match_dup 1)
  13215. + (parallel [(const_int 0)])))
  13216. + (sign_extend:SI (vec_select:HI
  13217. + (match_dup 2)
  13218. + (parallel [(const_int 1)]))))))]
  13219. + "NDS32_EXT_DSP_P ()"
  13220. +{
  13221. +})
  13222. +
  13223. +(define_expand "smxdsv_be"
  13224. + [(set (match_operand:SI 0 "register_operand" "=r")
  13225. + (minus:SI
  13226. + (mult:SI
  13227. + (sign_extend:SI (vec_select:HI
  13228. + (match_operand:V2HI 1 "register_operand" " r")
  13229. + (parallel [(const_int 0)])))
  13230. + (sign_extend:SI (vec_select:HI
  13231. + (match_operand:V2HI 2 "register_operand" " r")
  13232. + (parallel [(const_int 1)]))))
  13233. + (mult:SI
  13234. + (sign_extend:SI (vec_select:HI
  13235. + (match_dup 1)
  13236. + (parallel [(const_int 1)])))
  13237. + (sign_extend:SI (vec_select:HI
  13238. + (match_dup 2)
  13239. + (parallel [(const_int 0)]))))))]
  13240. + "NDS32_EXT_DSP_P ()"
  13241. +{
  13242. +})
  13243. +
  13244. +(define_insn "smal1"
  13245. + [(set (match_operand:DI 0 "register_operand" "=r")
  13246. + (plus:DI (match_operand:DI 1 "register_operand" " r")
  13247. + (sign_extend:DI
  13248. + (mult:SI
  13249. + (sign_extend:SI
  13250. + (vec_select:HI
  13251. + (match_operand:V2HI 2 "register_operand" " r")
  13252. + (parallel [(const_int 0)])))
  13253. + (sign_extend:SI
  13254. + (vec_select:HI
  13255. + (match_dup 2)
  13256. + (parallel [(const_int 1)])))))))]
  13257. + "NDS32_EXT_DSP_P ()"
  13258. + "smal\t%0, %1, %2"
  13259. + [(set_attr "type" "mac")
  13260. + (set_attr "length" "4")])
  13261. +
  13262. +(define_insn "smal2"
  13263. + [(set (match_operand:DI 0 "register_operand" "=r")
  13264. + (plus:DI (match_operand:DI 1 "register_operand" " r")
  13265. + (mult:DI
  13266. + (sign_extend:DI
  13267. + (vec_select:HI
  13268. + (match_operand:V2HI 2 "register_operand" " r")
  13269. + (parallel [(const_int 0)])))
  13270. + (sign_extend:DI
  13271. + (vec_select:HI
  13272. + (match_dup 2)
  13273. + (parallel [(const_int 1)]))))))]
  13274. + "NDS32_EXT_DSP_P ()"
  13275. + "smal\t%0, %1, %2"
  13276. + [(set_attr "type" "mac")
  13277. + (set_attr "length" "4")])
  13278. +
  13279. +(define_insn "smal3"
  13280. + [(set (match_operand:DI 0 "register_operand" "=r")
  13281. + (plus:DI (match_operand:DI 1 "register_operand" " r")
  13282. + (sign_extend:DI
  13283. + (mult:SI
  13284. + (sign_extend:SI
  13285. + (vec_select:HI
  13286. + (match_operand:V2HI 2 "register_operand" " r")
  13287. + (parallel [(const_int 1)])))
  13288. + (sign_extend:SI
  13289. + (vec_select:HI
  13290. + (match_dup 2)
  13291. + (parallel [(const_int 0)])))))))]
  13292. + "NDS32_EXT_DSP_P ()"
  13293. + "smal\t%0, %1, %2"
  13294. + [(set_attr "type" "mac")
  13295. + (set_attr "length" "4")])
  13296. +
  13297. +(define_insn "smal4"
  13298. + [(set (match_operand:DI 0 "register_operand" "=r")
  13299. + (plus:DI (match_operand:DI 1 "register_operand" " r")
  13300. + (mult:DI
  13301. + (sign_extend:DI
  13302. + (vec_select:HI
  13303. + (match_operand:V2HI 2 "register_operand" " r")
  13304. + (parallel [(const_int 1)])))
  13305. + (sign_extend:DI
  13306. + (vec_select:HI
  13307. + (match_dup 2)
  13308. + (parallel [(const_int 0)]))))))]
  13309. + "NDS32_EXT_DSP_P ()"
  13310. + "smal\t%0, %1, %2"
  13311. + [(set_attr "type" "mac")
  13312. + (set_attr "length" "4")])
  13313. +
  13314. +(define_insn "smal5"
  13315. + [(set (match_operand:DI 0 "register_operand" "=r")
  13316. + (plus:DI
  13317. + (sign_extend:DI
  13318. + (mult:SI
  13319. + (sign_extend:SI
  13320. + (vec_select:HI
  13321. + (match_operand:V2HI 2 "register_operand" " r")
  13322. + (parallel [(const_int 0)])))
  13323. + (sign_extend:SI
  13324. + (vec_select:HI
  13325. + (match_dup 2)
  13326. + (parallel [(const_int 1)])))))
  13327. + (match_operand:DI 1 "register_operand" " r")))]
  13328. + "NDS32_EXT_DSP_P ()"
  13329. + "smal\t%0, %1, %2"
  13330. + [(set_attr "type" "mac")
  13331. + (set_attr "length" "4")])
  13332. +
  13333. +(define_insn "smal6"
  13334. + [(set (match_operand:DI 0 "register_operand" "=r")
  13335. + (plus:DI
  13336. + (mult:DI
  13337. + (sign_extend:DI
  13338. + (vec_select:HI
  13339. + (match_operand:V2HI 2 "register_operand" " r")
  13340. + (parallel [(const_int 0)])))
  13341. + (sign_extend:DI
  13342. + (vec_select:HI
  13343. + (match_dup 2)
  13344. + (parallel [(const_int 1)]))))
  13345. + (match_operand:DI 1 "register_operand" " r")))]
  13346. + "NDS32_EXT_DSP_P ()"
  13347. + "smal\t%0, %1, %2"
  13348. + [(set_attr "type" "mac")
  13349. + (set_attr "length" "4")])
  13350. +
  13351. +(define_insn "smal7"
  13352. + [(set (match_operand:DI 0 "register_operand" "=r")
  13353. + (plus:DI
  13354. + (sign_extend:DI
  13355. + (mult:SI
  13356. + (sign_extend:SI
  13357. + (vec_select:HI
  13358. + (match_operand:V2HI 2 "register_operand" " r")
  13359. + (parallel [(const_int 1)])))
  13360. + (sign_extend:SI
  13361. + (vec_select:HI
  13362. + (match_dup 2)
  13363. + (parallel [(const_int 0)])))))
  13364. + (match_operand:DI 1 "register_operand" " r")))]
  13365. + "NDS32_EXT_DSP_P ()"
  13366. + "smal\t%0, %1, %2"
  13367. + [(set_attr "type" "mac")
  13368. + (set_attr "length" "4")])
  13369. +
  13370. +(define_insn "smal8"
  13371. + [(set (match_operand:DI 0 "register_operand" "=r")
  13372. + (plus:DI
  13373. + (mult:DI
  13374. + (sign_extend:DI
  13375. + (vec_select:HI
  13376. + (match_operand:V2HI 2 "register_operand" " r")
  13377. + (parallel [(const_int 1)])))
  13378. + (sign_extend:DI
  13379. + (vec_select:HI
  13380. + (match_dup 2)
  13381. + (parallel [(const_int 0)]))))
  13382. + (match_operand:DI 1 "register_operand" " r")))]
  13383. + "NDS32_EXT_DSP_P ()"
  13384. + "smal\t%0, %1, %2"
  13385. + [(set_attr "type" "mac")
  13386. + (set_attr "length" "4")])
  13387. +
  13388. +;; We need this dummy pattern for smal
  13389. +(define_insn_and_split "extendsidi2"
  13390. + [(set (match_operand:DI 0 "register_operand" "")
  13391. + (sign_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))]
  13392. + "NDS32_EXT_DSP_P ()"
  13393. + "#"
  13394. + "NDS32_EXT_DSP_P ()"
  13395. + [(const_int 0)]
  13396. +{
  13397. + rtx high_part_dst, low_part_dst;
  13398. +
  13399. + low_part_dst = nds32_di_low_part_subreg (operands[0]);
  13400. + high_part_dst = nds32_di_high_part_subreg (operands[0]);
  13401. +
  13402. + emit_move_insn (low_part_dst, operands[1]);
  13403. + emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31)));
  13404. + DONE;
  13405. +}
  13406. + [(set_attr "type" "alu")
  13407. + (set_attr "length" "4")])
  13408. +
  13409. +;; We need this dummy pattern for usmar64/usmsr64
  13410. +(define_insn_and_split "zero_extendsidi2"
  13411. + [(set (match_operand:DI 0 "register_operand" "")
  13412. + (zero_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))]
  13413. + "NDS32_EXT_DSP_P ()"
  13414. + "#"
  13415. + "NDS32_EXT_DSP_P ()"
  13416. + [(const_int 0)]
  13417. +{
  13418. + rtx high_part_dst, low_part_dst;
  13419. +
  13420. + low_part_dst = nds32_di_low_part_subreg (operands[0]);
  13421. + high_part_dst = nds32_di_high_part_subreg (operands[0]);
  13422. +
  13423. + emit_move_insn (low_part_dst, operands[1]);
  13424. + emit_move_insn (high_part_dst, const0_rtx);
  13425. + DONE;
  13426. +}
  13427. + [(set_attr "type" "alu")
  13428. + (set_attr "length" "4")])
  13429. +
  13430. +(define_insn_and_split "extendhidi2"
  13431. + [(set (match_operand:DI 0 "register_operand" "")
  13432. + (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
  13433. + "NDS32_EXT_DSP_P ()"
  13434. + "#"
  13435. + "NDS32_EXT_DSP_P ()"
  13436. + [(const_int 0)]
  13437. +{
  13438. + rtx high_part_dst, low_part_dst;
  13439. +
  13440. + low_part_dst = nds32_di_low_part_subreg (operands[0]);
  13441. + high_part_dst = nds32_di_high_part_subreg (operands[0]);
  13442. +
  13443. +
  13444. + emit_insn (gen_extendhisi2 (low_part_dst, operands[1]));
  13445. + emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31)));
  13446. + DONE;
  13447. +}
  13448. + [(set_attr "type" "alu")
  13449. + (set_attr "length" "4")])
  13450. +
  13451. +(define_insn "extendqihi2"
  13452. + [(set (match_operand:HI 0 "register_operand" "=r")
  13453. + (sign_extend:HI (match_operand:QI 1 "register_operand" " r")))]
  13454. + "NDS32_EXT_DSP_P ()"
  13455. + "sunpkd820\t%0, %1"
  13456. + [(set_attr "type" "alu")
  13457. + (set_attr "length" "4")])
  13458. +
  13459. +(define_insn "smulsi3_highpart"
  13460. + [(set (match_operand:SI 0 "register_operand" "=r")
  13461. + (truncate:SI
  13462. + (lshiftrt:DI
  13463. + (mult:DI
  13464. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
  13465. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
  13466. + (const_int 32))))]
  13467. + "NDS32_EXT_DSP_P ()"
  13468. + "smmul\t%0, %1, %2"
  13469. + [(set_attr "type" "mul")
  13470. + (set_attr "length" "4")])
  13471. +
  13472. +(define_insn "smmul_round"
  13473. + [(set (match_operand:SI 0 "register_operand" "=r")
  13474. + (truncate:SI
  13475. + (lshiftrt:DI
  13476. + (unspec:DI [(mult:DI
  13477. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
  13478. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))]
  13479. + UNSPEC_ROUND)
  13480. + (const_int 32))))]
  13481. + "NDS32_EXT_DSP_P ()"
  13482. + "smmul.u\t%0, %1, %2"
  13483. + [(set_attr "type" "mul")
  13484. + (set_attr "length" "4")])
  13485. +
  13486. +(define_insn "kmmac"
  13487. + [(set (match_operand:SI 0 "register_operand" "=r")
  13488. + (ss_plus:SI (match_operand:SI 1 "register_operand" " 0")
  13489. + (truncate:SI
  13490. + (lshiftrt:DI
  13491. + (mult:DI
  13492. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
  13493. + (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
  13494. + (const_int 32)))))]
  13495. + "NDS32_EXT_DSP_P ()"
  13496. + "kmmac\t%0, %2, %3"
  13497. + [(set_attr "type" "mac")
  13498. + (set_attr "length" "4")])
  13499. +
  13500. +(define_insn "kmmac_round"
  13501. + [(set (match_operand:SI 0 "register_operand" "=r")
  13502. + (ss_plus:SI (match_operand:SI 1 "register_operand" " 0")
  13503. + (truncate:SI
  13504. + (lshiftrt:DI
  13505. + (unspec:DI [(mult:DI
  13506. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
  13507. + (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
  13508. + UNSPEC_ROUND)
  13509. + (const_int 32)))))]
  13510. + "NDS32_EXT_DSP_P ()"
  13511. + "kmmac.u\t%0, %2, %3"
  13512. + [(set_attr "type" "mac")
  13513. + (set_attr "length" "4")])
  13514. +
  13515. +(define_insn "kmmsb"
  13516. + [(set (match_operand:SI 0 "register_operand" "=r")
  13517. + (ss_minus:SI (match_operand:SI 1 "register_operand" " 0")
  13518. + (truncate:SI
  13519. + (lshiftrt:DI
  13520. + (mult:DI
  13521. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
  13522. + (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
  13523. + (const_int 32)))))]
  13524. + "NDS32_EXT_DSP_P ()"
  13525. + "kmmsb\t%0, %2, %3"
  13526. + [(set_attr "type" "mac")
  13527. + (set_attr "length" "4")])
  13528. +
  13529. +(define_insn "kmmsb_round"
  13530. + [(set (match_operand:SI 0 "register_operand" "=r")
  13531. + (ss_minus:SI (match_operand:SI 1 "register_operand" " 0")
  13532. + (truncate:SI
  13533. + (lshiftrt:DI
  13534. + (unspec:DI [(mult:DI
  13535. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
  13536. + (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
  13537. + UNSPEC_ROUND)
  13538. + (const_int 32)))))]
  13539. + "NDS32_EXT_DSP_P ()"
  13540. + "kmmsb.u\t%0, %2, %3"
  13541. + [(set_attr "type" "mac")
  13542. + (set_attr "length" "4")])
  13543. +
  13544. +(define_insn "kwmmul"
  13545. + [(set (match_operand:SI 0 "register_operand" "=r")
  13546. + (truncate:SI
  13547. + (lshiftrt:DI
  13548. + (ss_mult:DI
  13549. + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
  13550. + (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))
  13551. + (const_int 32))))]
  13552. + "NDS32_EXT_DSP_P ()"
  13553. + "kwmmul\t%0, %1, %2"
  13554. + [(set_attr "type" "mul")
  13555. + (set_attr "length" "4")])
  13556. +
  13557. +(define_insn "kwmmul_round"
  13558. + [(set (match_operand:SI 0 "register_operand" "=r")
  13559. + (truncate:SI
  13560. + (lshiftrt:DI
  13561. + (unspec:DI [
  13562. + (ss_mult:DI
  13563. + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
  13564. + (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))]
  13565. + UNSPEC_ROUND)
  13566. + (const_int 32))))]
  13567. + "NDS32_EXT_DSP_P ()"
  13568. + "kwmmul.u\t%0, %1, %2"
  13569. + [(set_attr "type" "mul")
  13570. + (set_attr "length" "4")])
  13571. +
  13572. +(define_expand "smmwb"
  13573. + [(match_operand:SI 0 "register_operand" "")
  13574. + (match_operand:SI 1 "register_operand" "")
  13575. + (match_operand:V2HI 2 "register_operand" "")]
  13576. + "NDS32_EXT_DSP_P ()"
  13577. +{
  13578. + if (TARGET_BIG_ENDIAN)
  13579. + emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1)));
  13580. + else
  13581. + emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0)));
  13582. + DONE;
  13583. +}
  13584. + [(set_attr "type" "alu")
  13585. + (set_attr "length" "4")])
  13586. +
  13587. +(define_expand "smmwt"
  13588. + [(match_operand:SI 0 "register_operand" "")
  13589. + (match_operand:SI 1 "register_operand" "")
  13590. + (match_operand:V2HI 2 "register_operand" "")]
  13591. + "NDS32_EXT_DSP_P ()"
  13592. +{
  13593. + if (TARGET_BIG_ENDIAN)
  13594. + emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0)));
  13595. + else
  13596. + emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1)));
  13597. + DONE;
  13598. +}
  13599. + [(set_attr "type" "alu")
  13600. + (set_attr "length" "4")])
  13601. +
  13602. +
  13603. +(define_insn "smulhisi3_highpart_1"
  13604. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  13605. + (truncate:SI
  13606. + (lshiftrt:DI
  13607. + (mult:DI
  13608. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
  13609. + (sign_extend:DI
  13610. + (vec_select:HI
  13611. + (match_operand:V2HI 2 "register_operand" " r, r")
  13612. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))
  13613. + (const_int 16))))]
  13614. + "NDS32_EXT_DSP_P ()"
  13615. +{
  13616. + if (TARGET_BIG_ENDIAN)
  13617. + {
  13618. + const char *pats[] = { "smmwt\t%0, %1, %2",
  13619. + "smmwb\t%0, %1, %2" };
  13620. + return pats[which_alternative];
  13621. + }
  13622. + else
  13623. + {
  13624. + const char *pats[] = { "smmwb\t%0, %1, %2",
  13625. + "smmwt\t%0, %1, %2" };
  13626. + return pats[which_alternative];
  13627. + }
  13628. +}
  13629. + [(set_attr "type" "mul")
  13630. + (set_attr "length" "4")])
  13631. +
  13632. +(define_insn "smulhisi3_highpart_2"
  13633. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  13634. + (truncate:SI
  13635. + (lshiftrt:DI
  13636. + (mult:DI
  13637. + (sign_extend:DI
  13638. + (vec_select:HI
  13639. + (match_operand:V2HI 1 "register_operand" " r, r")
  13640. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))
  13641. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r, r")))
  13642. + (const_int 16))))]
  13643. + "NDS32_EXT_DSP_P ()"
  13644. +{
  13645. + if (TARGET_BIG_ENDIAN)
  13646. + {
  13647. + const char *pats[] = { "smmwt\t%0, %1, %2",
  13648. + "smmwb\t%0, %1, %2" };
  13649. + return pats[which_alternative];
  13650. + }
  13651. + else
  13652. + {
  13653. + const char *pats[] = { "smmwb\t%0, %1, %2",
  13654. + "smmwt\t%0, %1, %2" };
  13655. + return pats[which_alternative];
  13656. + }
  13657. +}
  13658. + [(set_attr "type" "mul")
  13659. + (set_attr "length" "4")])
  13660. +
  13661. +(define_expand "smmwb_round"
  13662. + [(match_operand:SI 0 "register_operand" "")
  13663. + (match_operand:SI 1 "register_operand" "")
  13664. + (match_operand:V2HI 2 "register_operand" "")]
  13665. + "NDS32_EXT_DSP_P ()"
  13666. +{
  13667. + if (TARGET_BIG_ENDIAN)
  13668. + emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
  13669. + else
  13670. + emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
  13671. + DONE;
  13672. +}
  13673. + [(set_attr "type" "mul")
  13674. + (set_attr "length" "4")])
  13675. +
  13676. +(define_expand "smmwt_round"
  13677. + [(match_operand:SI 0 "register_operand" "")
  13678. + (match_operand:SI 1 "register_operand" "")
  13679. + (match_operand:V2HI 2 "register_operand" "")]
  13680. + "NDS32_EXT_DSP_P ()"
  13681. +{
  13682. + if (TARGET_BIG_ENDIAN)
  13683. + emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
  13684. + else
  13685. + emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
  13686. + DONE;
  13687. +}
  13688. + [(set_attr "type" "alu")
  13689. + (set_attr "length" "4")])
  13690. +
  13691. +(define_insn "smmw_round_internal"
  13692. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  13693. + (truncate:SI
  13694. + (lshiftrt:DI
  13695. + (unspec:DI
  13696. + [(mult:DI
  13697. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
  13698. + (sign_extend:DI
  13699. + (vec_select:HI
  13700. + (match_operand:V2HI 2 "register_operand" " r, r")
  13701. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))]
  13702. + UNSPEC_ROUND)
  13703. + (const_int 16))))]
  13704. + "NDS32_EXT_DSP_P ()"
  13705. +{
  13706. + if (TARGET_BIG_ENDIAN)
  13707. + {
  13708. + const char *pats[] = { "smmwt.u\t%0, %1, %2",
  13709. + "smmwb.u\t%0, %1, %2" };
  13710. + return pats[which_alternative];
  13711. + }
  13712. + else
  13713. + {
  13714. + const char *pats[] = { "smmwb.u\t%0, %1, %2",
  13715. + "smmwt.u\t%0, %1, %2" };
  13716. + return pats[which_alternative];
  13717. + }
  13718. +}
  13719. + [(set_attr "type" "mul")
  13720. + (set_attr "length" "4")])
  13721. +
  13722. +(define_expand "kmmawb"
  13723. + [(match_operand:SI 0 "register_operand" "")
  13724. + (match_operand:SI 1 "register_operand" "")
  13725. + (match_operand:SI 2 "register_operand" "")
  13726. + (match_operand:V2HI 3 "register_operand" "")]
  13727. + "NDS32_EXT_DSP_P ()"
  13728. +{
  13729. + if (TARGET_BIG_ENDIAN)
  13730. + emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
  13731. + else
  13732. + emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
  13733. + DONE;
  13734. +}
  13735. + [(set_attr "type" "alu")
  13736. + (set_attr "length" "4")])
  13737. +
  13738. +(define_expand "kmmawt"
  13739. + [(match_operand:SI 0 "register_operand" "")
  13740. + (match_operand:SI 1 "register_operand" "")
  13741. + (match_operand:SI 2 "register_operand" "")
  13742. + (match_operand:V2HI 3 "register_operand" "")]
  13743. + "NDS32_EXT_DSP_P ()"
  13744. +{
  13745. + if (TARGET_BIG_ENDIAN)
  13746. + emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
  13747. + else
  13748. + emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
  13749. + DONE;
  13750. +}
  13751. + [(set_attr "type" "alu")
  13752. + (set_attr "length" "4")])
  13753. +
  13754. +(define_insn "kmmaw_internal"
  13755. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  13756. + (ss_plus:SI
  13757. + (match_operand:SI 4 "register_operand" " 0, 0")
  13758. + (truncate:SI
  13759. + (lshiftrt:DI
  13760. + (mult:DI
  13761. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
  13762. + (sign_extend:DI
  13763. + (vec_select:HI
  13764. + (match_operand:V2HI 2 "register_operand" " r, r")
  13765. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))
  13766. + (const_int 16)))))]
  13767. + "NDS32_EXT_DSP_P ()"
  13768. +{
  13769. + if (TARGET_BIG_ENDIAN)
  13770. + {
  13771. + const char *pats[] = { "kmmawt\t%0, %1, %2",
  13772. + "kmmawb\t%0, %1, %2" };
  13773. + return pats[which_alternative];
  13774. + }
  13775. + else
  13776. + {
  13777. + const char *pats[] = { "kmmawb\t%0, %1, %2",
  13778. + "kmmawt\t%0, %1, %2" };
  13779. + return pats[which_alternative];
  13780. + }
  13781. +}
  13782. + [(set_attr "type" "mac")
  13783. + (set_attr "length" "4")])
  13784. +
  13785. +(define_expand "kmmawb_round"
  13786. + [(match_operand:SI 0 "register_operand" "")
  13787. + (match_operand:SI 1 "register_operand" "")
  13788. + (match_operand:SI 2 "register_operand" "")
  13789. + (match_operand:V2HI 3 "register_operand" "")]
  13790. + "NDS32_EXT_DSP_P ()"
  13791. +{
  13792. + if (TARGET_BIG_ENDIAN)
  13793. + emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
  13794. + else
  13795. + emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
  13796. + DONE;
  13797. +}
  13798. + [(set_attr "type" "alu")
  13799. + (set_attr "length" "4")])
  13800. +
  13801. +(define_expand "kmmawt_round"
  13802. + [(match_operand:SI 0 "register_operand" "")
  13803. + (match_operand:SI 1 "register_operand" "")
  13804. + (match_operand:SI 2 "register_operand" "")
  13805. + (match_operand:V2HI 3 "register_operand" "")]
  13806. + "NDS32_EXT_DSP_P ()"
  13807. +{
  13808. + if (TARGET_BIG_ENDIAN)
  13809. + emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1]));
  13810. + else
  13811. + emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1]));
  13812. + DONE;
  13813. +}
  13814. + [(set_attr "type" "alu")
  13815. + (set_attr "length" "4")])
  13816. +
  13817. +
  13818. +(define_insn "kmmaw_round_internal"
  13819. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  13820. + (ss_plus:SI
  13821. + (match_operand:SI 4 "register_operand" " 0, 0")
  13822. + (truncate:SI
  13823. + (lshiftrt:DI
  13824. + (unspec:DI
  13825. + [(mult:DI
  13826. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r"))
  13827. + (sign_extend:DI
  13828. + (vec_select:HI
  13829. + (match_operand:V2HI 2 "register_operand" " r, r")
  13830. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))]
  13831. + UNSPEC_ROUND)
  13832. + (const_int 16)))))]
  13833. + "NDS32_EXT_DSP_P ()"
  13834. +{
  13835. + if (TARGET_BIG_ENDIAN)
  13836. + {
  13837. + const char *pats[] = { "kmmawt.u\t%0, %1, %2",
  13838. + "kmmawb.u\t%0, %1, %2" };
  13839. + return pats[which_alternative];
  13840. + }
  13841. + else
  13842. + {
  13843. + const char *pats[] = { "kmmawb.u\t%0, %1, %2",
  13844. + "kmmawt.u\t%0, %1, %2" };
  13845. + return pats[which_alternative];
  13846. + }
  13847. +}
  13848. + [(set_attr "type" "mac")
  13849. + (set_attr "length" "4")])
  13850. +
  13851. +(define_expand "smalbb"
  13852. + [(match_operand:DI 0 "register_operand" "")
  13853. + (match_operand:DI 1 "register_operand" "")
  13854. + (match_operand:V2HI 2 "register_operand" "")
  13855. + (match_operand:V2HI 3 "register_operand" "")]
  13856. + "NDS32_EXT_DSP_P ()"
  13857. +{
  13858. + if (TARGET_BIG_ENDIAN)
  13859. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13860. + operands[3], operands[1],
  13861. + GEN_INT (1), GEN_INT (1)));
  13862. + else
  13863. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13864. + operands[3], operands[1],
  13865. + GEN_INT (0), GEN_INT (0)));
  13866. + DONE;
  13867. +})
  13868. +
  13869. +(define_expand "smalbt"
  13870. + [(match_operand:DI 0 "register_operand" "")
  13871. + (match_operand:DI 1 "register_operand" "")
  13872. + (match_operand:V2HI 2 "register_operand" "")
  13873. + (match_operand:V2HI 3 "register_operand" "")]
  13874. + "NDS32_EXT_DSP_P ()"
  13875. +{
  13876. + if (TARGET_BIG_ENDIAN)
  13877. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13878. + operands[3], operands[1],
  13879. + GEN_INT (1), GEN_INT (0)));
  13880. + else
  13881. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13882. + operands[3], operands[1],
  13883. + GEN_INT (0), GEN_INT (1)));
  13884. + DONE;
  13885. +})
  13886. +
  13887. +(define_expand "smaltt"
  13888. + [(match_operand:DI 0 "register_operand" "")
  13889. + (match_operand:DI 1 "register_operand" "")
  13890. + (match_operand:V2HI 2 "register_operand" "")
  13891. + (match_operand:V2HI 3 "register_operand" "")]
  13892. + "NDS32_EXT_DSP_P ()"
  13893. +{
  13894. + if (TARGET_BIG_ENDIAN)
  13895. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13896. + operands[3], operands[1],
  13897. + GEN_INT (0), GEN_INT (0)));
  13898. + else
  13899. + emit_insn (gen_smaddhidi (operands[0], operands[2],
  13900. + operands[3], operands[1],
  13901. + GEN_INT (1), GEN_INT (1)));
  13902. + DONE;
  13903. +})
  13904. +
  13905. +(define_insn "smaddhidi"
  13906. + [(set (match_operand:DI 0 "register_operand" "= r, r, r, r")
  13907. + (plus:DI
  13908. + (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")
  13909. + (mult:DI
  13910. + (sign_extend:DI
  13911. + (vec_select:HI
  13912. + (match_operand:V2HI 1 "register_operand" " r, r, r, r")
  13913. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
  13914. + (sign_extend:DI
  13915. + (vec_select:HI
  13916. + (match_operand:V2HI 2 "register_operand" " r, r, r, r")
  13917. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))]
  13918. + "NDS32_EXT_DSP_P ()"
  13919. +{
  13920. + if (TARGET_BIG_ENDIAN)
  13921. + {
  13922. + const char *pats[] = { "smaltt\t%0, %1, %2",
  13923. + "smalbt\t%0, %2, %1",
  13924. + "smalbb\t%0, %1, %2",
  13925. + "smalbt\t%0, %1, %2" };
  13926. + return pats[which_alternative];
  13927. + }
  13928. + else
  13929. + {
  13930. + const char *pats[] = { "smalbb\t%0, %1, %2",
  13931. + "smalbt\t%0, %1, %2",
  13932. + "smaltt\t%0, %1, %2",
  13933. + "smalbt\t%0, %2, %1" };
  13934. + return pats[which_alternative];
  13935. + }
  13936. +}
  13937. + [(set_attr "type" "mac")
  13938. + (set_attr "length" "4")])
  13939. +
  13940. +(define_insn "smaddhidi2"
  13941. + [(set (match_operand:DI 0 "register_operand" "= r, r, r, r")
  13942. + (plus:DI
  13943. + (mult:DI
  13944. + (sign_extend:DI
  13945. + (vec_select:HI
  13946. + (match_operand:V2HI 1 "register_operand" " r, r, r, r")
  13947. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")])))
  13948. + (sign_extend:DI
  13949. + (vec_select:HI
  13950. + (match_operand:V2HI 2 "register_operand" " r, r, r, r")
  13951. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))
  13952. + (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")))]
  13953. + "NDS32_EXT_DSP_P ()"
  13954. +{
  13955. + if (TARGET_BIG_ENDIAN)
  13956. + {
  13957. + const char *pats[] = { "smaltt\t%0, %1, %2",
  13958. + "smalbt\t%0, %2, %1",
  13959. + "smalbb\t%0, %1, %2",
  13960. + "smalbt\t%0, %1, %2" };
  13961. + return pats[which_alternative];
  13962. + }
  13963. + else
  13964. + {
  13965. + const char *pats[] = { "smalbb\t%0, %1, %2",
  13966. + "smalbt\t%0, %1, %2",
  13967. + "smaltt\t%0, %1, %2",
  13968. + "smalbt\t%0, %2, %1" };
  13969. + return pats[which_alternative];
  13970. + }
  13971. +}
  13972. + [(set_attr "type" "mac")
  13973. + (set_attr "length" "4")])
  13974. +
  13975. +(define_expand "smalda1"
  13976. + [(match_operand:DI 0 "register_operand" "")
  13977. + (match_operand:DI 1 "register_operand" "")
  13978. + (match_operand:V2HI 2 "register_operand" " r")
  13979. + (match_operand:V2HI 3 "register_operand" " r")]
  13980. + "NDS32_EXT_DSP_P ()"
  13981. +{
  13982. + if (TARGET_BIG_ENDIAN)
  13983. + emit_insn (gen_smalda1_be (operands[0], operands[1], operands[2], operands[3]));
  13984. + else
  13985. + emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3]));
  13986. + DONE;
  13987. +})
  13988. +
  13989. +(define_expand "smalds1"
  13990. + [(match_operand:DI 0 "register_operand" "")
  13991. + (match_operand:DI 1 "register_operand" "")
  13992. + (match_operand:V2HI 2 "register_operand" " r")
  13993. + (match_operand:V2HI 3 "register_operand" " r")]
  13994. + "NDS32_EXT_DSP_P ()"
  13995. +{
  13996. + if (TARGET_BIG_ENDIAN)
  13997. + emit_insn (gen_smalds1_be (operands[0], operands[1], operands[2], operands[3]));
  13998. + else
  13999. + emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3]));
  14000. + DONE;
  14001. +})
  14002. +
  14003. +(define_insn "smalda1_le"
  14004. + [(set (match_operand:DI 0 "register_operand" "=r")
  14005. + (plus:DI
  14006. + (match_operand:DI 1 "register_operand" " 0")
  14007. + (sign_extend:DI
  14008. + (plus:SI
  14009. + (mult:SI
  14010. + (sign_extend:SI (vec_select:HI
  14011. + (match_operand:V2HI 2 "register_operand" " r")
  14012. + (parallel [(const_int 1)])))
  14013. + (sign_extend:SI (vec_select:HI
  14014. + (match_operand:V2HI 3 "register_operand" " r")
  14015. + (parallel [(const_int 1)]))))
  14016. + (mult:SI
  14017. + (sign_extend:SI (vec_select:HI
  14018. + (match_dup 2)
  14019. + (parallel [(const_int 0)])))
  14020. + (sign_extend:SI (vec_select:HI
  14021. + (match_dup 3)
  14022. + (parallel [(const_int 0)]))))))))]
  14023. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14024. + "smalda\t%0, %2, %3"
  14025. + [(set_attr "type" "mac")
  14026. + (set_attr "length" "4")])
  14027. +
  14028. +(define_insn "smalds1_le"
  14029. + [(set (match_operand:DI 0 "register_operand" "=r")
  14030. + (plus:DI
  14031. + (match_operand:DI 1 "register_operand" " 0")
  14032. + (sign_extend:DI
  14033. + (minus:SI
  14034. + (mult:SI
  14035. + (sign_extend:SI (vec_select:HI
  14036. + (match_operand:V2HI 2 "register_operand" " r")
  14037. + (parallel [(const_int 1)])))
  14038. + (sign_extend:SI (vec_select:HI
  14039. + (match_operand:V2HI 3 "register_operand" " r")
  14040. + (parallel [(const_int 1)]))))
  14041. + (mult:SI
  14042. + (sign_extend:SI (vec_select:HI
  14043. + (match_dup 2)
  14044. + (parallel [(const_int 0)])))
  14045. + (sign_extend:SI (vec_select:HI
  14046. + (match_dup 3)
  14047. + (parallel [(const_int 0)]))))))))]
  14048. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14049. + "smalds\t%0, %2, %3"
  14050. + [(set_attr "type" "mac")
  14051. + (set_attr "length" "4")])
  14052. +
  14053. +(define_insn "smalda1_be"
  14054. + [(set (match_operand:DI 0 "register_operand" "=r")
  14055. + (plus:DI
  14056. + (match_operand:DI 1 "register_operand" " 0")
  14057. + (sign_extend:DI
  14058. + (plus:SI
  14059. + (mult:SI
  14060. + (sign_extend:SI (vec_select:HI
  14061. + (match_operand:V2HI 2 "register_operand" " r")
  14062. + (parallel [(const_int 0)])))
  14063. + (sign_extend:SI (vec_select:HI
  14064. + (match_operand:V2HI 3 "register_operand" " r")
  14065. + (parallel [(const_int 0)]))))
  14066. + (mult:SI
  14067. + (sign_extend:SI (vec_select:HI
  14068. + (match_dup 2)
  14069. + (parallel [(const_int 1)])))
  14070. + (sign_extend:SI (vec_select:HI
  14071. + (match_dup 3)
  14072. + (parallel [(const_int 1)]))))))))]
  14073. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  14074. + "smalda\t%0, %2, %3"
  14075. + [(set_attr "type" "mac")
  14076. + (set_attr "length" "4")])
  14077. +
  14078. +(define_insn "smalds1_be"
  14079. + [(set (match_operand:DI 0 "register_operand" "=r")
  14080. + (plus:DI
  14081. + (match_operand:DI 1 "register_operand" " 0")
  14082. + (sign_extend:DI
  14083. + (minus:SI
  14084. + (mult:SI
  14085. + (sign_extend:SI (vec_select:HI
  14086. + (match_operand:V2HI 2 "register_operand" " r")
  14087. + (parallel [(const_int 0)])))
  14088. + (sign_extend:SI (vec_select:HI
  14089. + (match_operand:V2HI 3 "register_operand" " r")
  14090. + (parallel [(const_int 0)]))))
  14091. + (mult:SI
  14092. + (sign_extend:SI (vec_select:HI
  14093. + (match_dup 2)
  14094. + (parallel [(const_int 1)])))
  14095. + (sign_extend:SI (vec_select:HI
  14096. + (match_dup 3)
  14097. + (parallel [(const_int 1)]))))))))]
  14098. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  14099. + "smalds\t%0, %2, %3"
  14100. + [(set_attr "type" "mac")
  14101. + (set_attr "length" "4")])
  14102. +
  14103. +(define_expand "smaldrs3"
  14104. + [(match_operand:DI 0 "register_operand" "")
  14105. + (match_operand:DI 1 "register_operand" "")
  14106. + (match_operand:V2HI 2 "register_operand" " r")
  14107. + (match_operand:V2HI 3 "register_operand" " r")]
  14108. + "NDS32_EXT_DSP_P ()"
  14109. +{
  14110. + if (TARGET_BIG_ENDIAN)
  14111. + emit_insn (gen_smaldrs3_be (operands[0], operands[1], operands[2], operands[3]));
  14112. + else
  14113. + emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3]));
  14114. + DONE;
  14115. +})
  14116. +
  14117. +(define_insn "smaldrs3_le"
  14118. + [(set (match_operand:DI 0 "register_operand" "=r")
  14119. + (plus:DI
  14120. + (match_operand:DI 1 "register_operand" " 0")
  14121. + (sign_extend:DI
  14122. + (minus:SI
  14123. + (mult:SI
  14124. + (sign_extend:SI (vec_select:HI
  14125. + (match_operand:V2HI 2 "register_operand" " r")
  14126. + (parallel [(const_int 0)])))
  14127. + (sign_extend:SI (vec_select:HI
  14128. + (match_operand:V2HI 3 "register_operand" " r")
  14129. + (parallel [(const_int 0)]))))
  14130. + (mult:SI
  14131. + (sign_extend:SI (vec_select:HI
  14132. + (match_dup 2)
  14133. + (parallel [(const_int 1)])))
  14134. + (sign_extend:SI (vec_select:HI
  14135. + (match_dup 3)
  14136. + (parallel [(const_int 1)]))))))))]
  14137. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14138. + "smaldrs\t%0, %2, %3"
  14139. + [(set_attr "type" "mac")
  14140. + (set_attr "length" "4")])
  14141. +
  14142. +(define_insn "smaldrs3_be"
  14143. + [(set (match_operand:DI 0 "register_operand" "=r")
  14144. + (plus:DI
  14145. + (match_operand:DI 1 "register_operand" " 0")
  14146. + (sign_extend:DI
  14147. + (minus:SI
  14148. + (mult:SI
  14149. + (sign_extend:SI (vec_select:HI
  14150. + (match_operand:V2HI 2 "register_operand" " r")
  14151. + (parallel [(const_int 1)])))
  14152. + (sign_extend:SI (vec_select:HI
  14153. + (match_operand:V2HI 3 "register_operand" " r")
  14154. + (parallel [(const_int 1)]))))
  14155. + (mult:SI
  14156. + (sign_extend:SI (vec_select:HI
  14157. + (match_dup 2)
  14158. + (parallel [(const_int 0)])))
  14159. + (sign_extend:SI (vec_select:HI
  14160. + (match_dup 3)
  14161. + (parallel [(const_int 0)]))))))))]
  14162. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  14163. + "smaldrs\t%0, %2, %3"
  14164. + [(set_attr "type" "mac")
  14165. + (set_attr "length" "4")])
  14166. +
  14167. +(define_expand "smalxda1"
  14168. + [(match_operand:DI 0 "register_operand" "")
  14169. + (match_operand:DI 1 "register_operand" "")
  14170. + (match_operand:V2HI 2 "register_operand" " r")
  14171. + (match_operand:V2HI 3 "register_operand" " r")]
  14172. + "NDS32_EXT_DSP_P ()"
  14173. +{
  14174. + if (TARGET_BIG_ENDIAN)
  14175. + emit_insn (gen_smalxda1_be (operands[0], operands[1], operands[2], operands[3]));
  14176. + else
  14177. + emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3]));
  14178. + DONE;
  14179. +})
  14180. +
  14181. +(define_expand "smalxds1"
  14182. + [(match_operand:DI 0 "register_operand" "")
  14183. + (match_operand:DI 1 "register_operand" "")
  14184. + (match_operand:V2HI 2 "register_operand" " r")
  14185. + (match_operand:V2HI 3 "register_operand" " r")]
  14186. + "NDS32_EXT_DSP_P ()"
  14187. +{
  14188. + if (TARGET_BIG_ENDIAN)
  14189. + emit_insn (gen_smalxds1_be (operands[0], operands[1], operands[2], operands[3]));
  14190. + else
  14191. + emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3]));
  14192. + DONE;
  14193. +})
  14194. +
  14195. +(define_insn "smalxd<add_sub>1_le"
  14196. + [(set (match_operand:DI 0 "register_operand" "=r")
  14197. + (plus:DI
  14198. + (match_operand:DI 1 "register_operand" " 0")
  14199. + (sign_extend:DI
  14200. + (plus_minus:SI
  14201. + (mult:SI
  14202. + (sign_extend:SI (vec_select:HI
  14203. + (match_operand:V2HI 2 "register_operand" " r")
  14204. + (parallel [(const_int 1)])))
  14205. + (sign_extend:SI (vec_select:HI
  14206. + (match_operand:V2HI 3 "register_operand" " r")
  14207. + (parallel [(const_int 0)]))))
  14208. + (mult:SI
  14209. + (sign_extend:SI (vec_select:HI
  14210. + (match_dup 2)
  14211. + (parallel [(const_int 0)])))
  14212. + (sign_extend:SI (vec_select:HI
  14213. + (match_dup 3)
  14214. + (parallel [(const_int 1)]))))))))]
  14215. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14216. + "smalxd<add_sub>\t%0, %2, %3"
  14217. + [(set_attr "type" "mac")
  14218. + (set_attr "length" "4")])
  14219. +
  14220. +
  14221. +(define_insn "smalxd<add_sub>1_be"
  14222. + [(set (match_operand:DI 0 "register_operand" "=r")
  14223. + (plus:DI
  14224. + (match_operand:DI 1 "register_operand" " 0")
  14225. + (sign_extend:DI
  14226. + (plus_minus:SI
  14227. + (mult:SI
  14228. + (sign_extend:SI (vec_select:HI
  14229. + (match_operand:V2HI 2 "register_operand" " r")
  14230. + (parallel [(const_int 0)])))
  14231. + (sign_extend:SI (vec_select:HI
  14232. + (match_operand:V2HI 3 "register_operand" " r")
  14233. + (parallel [(const_int 1)]))))
  14234. + (mult:SI
  14235. + (sign_extend:SI (vec_select:HI
  14236. + (match_dup 2)
  14237. + (parallel [(const_int 1)])))
  14238. + (sign_extend:SI (vec_select:HI
  14239. + (match_dup 3)
  14240. + (parallel [(const_int 0)]))))))))]
  14241. + "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN"
  14242. + "smalxd<add_sub>\t%0, %2, %3"
  14243. + [(set_attr "type" "mac")
  14244. + (set_attr "length" "4")])
  14245. +
  14246. +(define_insn "smslda1"
  14247. + [(set (match_operand:DI 0 "register_operand" "=r")
  14248. + (minus:DI
  14249. + (minus:DI
  14250. + (match_operand:DI 1 "register_operand" " 0")
  14251. + (sign_extend:DI
  14252. + (mult:SI
  14253. + (sign_extend:SI (vec_select:HI
  14254. + (match_operand:V2HI 2 "register_operand" " r")
  14255. + (parallel [(const_int 1)])))
  14256. + (sign_extend:SI (vec_select:HI
  14257. + (match_operand:V2HI 3 "register_operand" " r")
  14258. + (parallel [(const_int 1)]))))))
  14259. + (sign_extend:DI
  14260. + (mult:SI
  14261. + (sign_extend:SI (vec_select:HI
  14262. + (match_dup 2)
  14263. + (parallel [(const_int 0)])))
  14264. + (sign_extend:SI (vec_select:HI
  14265. + (match_dup 3)
  14266. + (parallel [(const_int 0)])))))))]
  14267. + "NDS32_EXT_DSP_P ()"
  14268. + "smslda\t%0, %2, %3"
  14269. + [(set_attr "type" "mac")
  14270. + (set_attr "length" "4")])
  14271. +
  14272. +(define_insn "smslxda1"
  14273. + [(set (match_operand:DI 0 "register_operand" "=r")
  14274. + (minus:DI
  14275. + (minus:DI
  14276. + (match_operand:DI 1 "register_operand" " 0")
  14277. + (sign_extend:DI
  14278. + (mult:SI
  14279. + (sign_extend:SI (vec_select:HI
  14280. + (match_operand:V2HI 2 "register_operand" " r")
  14281. + (parallel [(const_int 1)])))
  14282. + (sign_extend:SI (vec_select:HI
  14283. + (match_operand:V2HI 3 "register_operand" " r")
  14284. + (parallel [(const_int 0)]))))))
  14285. + (sign_extend:DI
  14286. + (mult:SI
  14287. + (sign_extend:SI (vec_select:HI
  14288. + (match_dup 2)
  14289. + (parallel [(const_int 0)])))
  14290. + (sign_extend:SI (vec_select:HI
  14291. + (match_dup 3)
  14292. + (parallel [(const_int 1)])))))))]
  14293. + "NDS32_EXT_DSP_P ()"
  14294. + "smslxda\t%0, %2, %3"
  14295. + [(set_attr "type" "mac")
  14296. + (set_attr "length" "4")])
  14297. +
  14298. +;; mada for synthetize smalda
  14299. +(define_insn_and_split "mada1"
  14300. + [(set (match_operand:SI 0 "register_operand" "=r")
  14301. + (plus:SI
  14302. + (mult:SI
  14303. + (sign_extend:SI (vec_select:HI
  14304. + (match_operand:V2HI 1 "register_operand" "r")
  14305. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
  14306. + (sign_extend:SI (vec_select:HI
  14307. + (match_operand:V2HI 2 "register_operand" "r")
  14308. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
  14309. + (mult:SI
  14310. + (sign_extend:SI (vec_select:HI
  14311. + (match_dup 1)
  14312. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
  14313. + (sign_extend:SI (vec_select:HI
  14314. + (match_dup 2)
  14315. + (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
  14316. + "NDS32_EXT_DSP_P () && !reload_completed"
  14317. + "#"
  14318. + "NDS32_EXT_DSP_P () && !reload_completed"
  14319. + [(const_int 1)]
  14320. +{
  14321. + rtx result0 = gen_reg_rtx (SImode);
  14322. + rtx result1 = gen_reg_rtx (SImode);
  14323. + emit_insn (gen_mulhisi3v (result0, operands[1], operands[2],
  14324. + operands[3], operands[4]));
  14325. + emit_insn (gen_mulhisi3v (result1, operands[1], operands[2],
  14326. + operands[5], operands[6]));
  14327. + emit_insn (gen_addsi3 (operands[0], result0, result1));
  14328. + DONE;
  14329. +})
  14330. +
  14331. +(define_insn_and_split "mada2"
  14332. + [(set (match_operand:SI 0 "register_operand" "=r")
  14333. + (plus:SI
  14334. + (mult:SI
  14335. + (sign_extend:SI (vec_select:HI
  14336. + (match_operand:V2HI 1 "register_operand" "r")
  14337. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
  14338. + (sign_extend:SI (vec_select:HI
  14339. + (match_operand:V2HI 2 "register_operand" "r")
  14340. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
  14341. + (mult:SI
  14342. + (sign_extend:SI (vec_select:HI
  14343. + (match_dup 2)
  14344. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
  14345. + (sign_extend:SI (vec_select:HI
  14346. + (match_dup 1)
  14347. + (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
  14348. + "NDS32_EXT_DSP_P () && !reload_completed"
  14349. + "#"
  14350. + "NDS32_EXT_DSP_P () && !reload_completed"
  14351. + [(const_int 1)]
  14352. +{
  14353. + rtx result0 = gen_reg_rtx (SImode);
  14354. + rtx result1 = gen_reg_rtx (SImode);
  14355. + emit_insn (gen_mulhisi3v (result0, operands[1], operands[2],
  14356. + operands[3], operands[4]));
  14357. + emit_insn (gen_mulhisi3v (result1, operands[1], operands[2],
  14358. + operands[6], operands[5]));
  14359. + emit_insn (gen_addsi3 (operands[0], result0, result1));
  14360. + DONE;
  14361. +})
  14362. +
  14363. +;; sms for synthetize smalds
  14364. +(define_insn_and_split "sms1"
  14365. + [(set (match_operand:SI 0 "register_operand" "= r")
  14366. + (minus:SI
  14367. + (mult:SI
  14368. + (sign_extend:SI (vec_select:HI
  14369. + (match_operand:V2HI 1 "register_operand" " r")
  14370. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
  14371. + (sign_extend:SI (vec_select:HI
  14372. + (match_operand:V2HI 2 "register_operand" " r")
  14373. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
  14374. + (mult:SI
  14375. + (sign_extend:SI (vec_select:HI
  14376. + (match_dup 1)
  14377. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
  14378. + (sign_extend:SI (vec_select:HI
  14379. + (match_dup 2)
  14380. + (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
  14381. + "NDS32_EXT_DSP_P ()
  14382. + && (!reload_completed
  14383. + || !nds32_need_split_sms_p (operands[3], operands[4],
  14384. + operands[5], operands[6]))"
  14385. +
  14386. +{
  14387. + return nds32_output_sms (operands[3], operands[4],
  14388. + operands[5], operands[6]);
  14389. +}
  14390. + "NDS32_EXT_DSP_P ()
  14391. + && !reload_completed
  14392. + && nds32_need_split_sms_p (operands[3], operands[4],
  14393. + operands[5], operands[6])"
  14394. + [(const_int 1)]
  14395. +{
  14396. + nds32_split_sms (operands[0], operands[1], operands[2],
  14397. + operands[3], operands[4],
  14398. + operands[5], operands[6]);
  14399. + DONE;
  14400. +}
  14401. + [(set_attr "type" "mac")
  14402. + (set_attr "length" "4")])
  14403. +
  14404. +(define_insn_and_split "sms2"
  14405. + [(set (match_operand:SI 0 "register_operand" "= r")
  14406. + (minus:SI
  14407. + (mult:SI
  14408. + (sign_extend:SI (vec_select:HI
  14409. + (match_operand:V2HI 1 "register_operand" " r")
  14410. + (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")])))
  14411. + (sign_extend:SI (vec_select:HI
  14412. + (match_operand:V2HI 2 "register_operand" " r")
  14413. + (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")]))))
  14414. + (mult:SI
  14415. + (sign_extend:SI (vec_select:HI
  14416. + (match_dup 2)
  14417. + (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")])))
  14418. + (sign_extend:SI (vec_select:HI
  14419. + (match_dup 1)
  14420. + (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))]
  14421. + "NDS32_EXT_DSP_P ()
  14422. + && (!reload_completed
  14423. + || !nds32_need_split_sms_p (operands[3], operands[4],
  14424. + operands[6], operands[5]))"
  14425. +{
  14426. + return nds32_output_sms (operands[3], operands[4],
  14427. + operands[6], operands[5]);
  14428. +}
  14429. + "NDS32_EXT_DSP_P ()
  14430. + && !reload_completed
  14431. + && nds32_need_split_sms_p (operands[3], operands[4],
  14432. + operands[6], operands[5])"
  14433. + [(const_int 1)]
  14434. +{
  14435. + nds32_split_sms (operands[0], operands[1], operands[2],
  14436. + operands[3], operands[4],
  14437. + operands[6], operands[5]);
  14438. + DONE;
  14439. +}
  14440. + [(set_attr "type" "mac")
  14441. + (set_attr "length" "4")])
  14442. +
  14443. +(define_insn "kmda"
  14444. + [(set (match_operand:SI 0 "register_operand" "=r")
  14445. + (ss_plus:SI
  14446. + (mult:SI
  14447. + (sign_extend:SI (vec_select:HI
  14448. + (match_operand:V2HI 1 "register_operand" "r")
  14449. + (parallel [(const_int 1)])))
  14450. + (sign_extend:SI (vec_select:HI
  14451. + (match_operand:V2HI 2 "register_operand" "r")
  14452. + (parallel [(const_int 1)]))))
  14453. + (mult:SI
  14454. + (sign_extend:SI (vec_select:HI
  14455. + (match_dup 1)
  14456. + (parallel [(const_int 0)])))
  14457. + (sign_extend:SI (vec_select:HI
  14458. + (match_dup 2)
  14459. + (parallel [(const_int 0)]))))))]
  14460. + "NDS32_EXT_DSP_P ()"
  14461. + "kmda\t%0, %1, %2"
  14462. + [(set_attr "type" "mac")
  14463. + (set_attr "length" "4")])
  14464. +
  14465. +(define_insn "kmxda"
  14466. + [(set (match_operand:SI 0 "register_operand" "=r")
  14467. + (ss_plus:SI
  14468. + (mult:SI
  14469. + (sign_extend:SI (vec_select:HI
  14470. + (match_operand:V2HI 1 "register_operand" "r")
  14471. + (parallel [(const_int 1)])))
  14472. + (sign_extend:SI (vec_select:HI
  14473. + (match_operand:V2HI 2 "register_operand" "r")
  14474. + (parallel [(const_int 0)]))))
  14475. + (mult:SI
  14476. + (sign_extend:SI (vec_select:HI
  14477. + (match_dup 1)
  14478. + (parallel [(const_int 0)])))
  14479. + (sign_extend:SI (vec_select:HI
  14480. + (match_dup 2)
  14481. + (parallel [(const_int 1)]))))))]
  14482. + "NDS32_EXT_DSP_P ()"
  14483. + "kmxda\t%0, %1, %2"
  14484. + [(set_attr "type" "mac")
  14485. + (set_attr "length" "4")])
  14486. +
  14487. +(define_insn "kmada"
  14488. + [(set (match_operand:SI 0 "register_operand" "=r")
  14489. + (ss_plus:SI
  14490. + (match_operand:SI 1 "register_operand" " 0")
  14491. + (ss_plus:SI
  14492. + (mult:SI
  14493. + (sign_extend:SI (vec_select:HI
  14494. + (match_operand:V2HI 2 "register_operand" " r")
  14495. + (parallel [(const_int 1)])))
  14496. + (sign_extend:SI (vec_select:HI
  14497. + (match_operand:V2HI 3 "register_operand" " r")
  14498. + (parallel [(const_int 1)]))))
  14499. + (mult:SI
  14500. + (sign_extend:SI (vec_select:HI
  14501. + (match_dup 2)
  14502. + (parallel [(const_int 0)])))
  14503. + (sign_extend:SI (vec_select:HI
  14504. + (match_dup 3)
  14505. + (parallel [(const_int 0)])))))))]
  14506. + "NDS32_EXT_DSP_P ()"
  14507. + "kmada\t%0, %2, %3"
  14508. + [(set_attr "type" "mac")
  14509. + (set_attr "length" "4")])
  14510. +
  14511. +(define_insn "kmada2"
  14512. + [(set (match_operand:SI 0 "register_operand" "=r")
  14513. + (ss_plus:SI
  14514. + (match_operand:SI 1 "register_operand" " 0")
  14515. + (ss_plus:SI
  14516. + (mult:SI
  14517. + (sign_extend:SI (vec_select:HI
  14518. + (match_operand:V2HI 2 "register_operand" " r")
  14519. + (parallel [(const_int 0)])))
  14520. + (sign_extend:SI (vec_select:HI
  14521. + (match_operand:V2HI 3 "register_operand" " r")
  14522. + (parallel [(const_int 0)]))))
  14523. + (mult:SI
  14524. + (sign_extend:SI (vec_select:HI
  14525. + (match_dup 2)
  14526. + (parallel [(const_int 1)])))
  14527. + (sign_extend:SI (vec_select:HI
  14528. + (match_dup 3)
  14529. + (parallel [(const_int 1)])))))))]
  14530. + "NDS32_EXT_DSP_P ()"
  14531. + "kmada\t%0, %2, %3"
  14532. + [(set_attr "type" "mac")
  14533. + (set_attr "length" "4")])
  14534. +
  14535. +(define_insn "kmaxda"
  14536. + [(set (match_operand:SI 0 "register_operand" "=r")
  14537. + (ss_plus:SI
  14538. + (match_operand:SI 1 "register_operand" " 0")
  14539. + (ss_plus:SI
  14540. + (mult:SI
  14541. + (sign_extend:SI (vec_select:HI
  14542. + (match_operand:V2HI 2 "register_operand" " r")
  14543. + (parallel [(const_int 1)])))
  14544. + (sign_extend:SI (vec_select:HI
  14545. + (match_operand:V2HI 3 "register_operand" " r")
  14546. + (parallel [(const_int 0)]))))
  14547. + (mult:SI
  14548. + (sign_extend:SI (vec_select:HI
  14549. + (match_dup 2)
  14550. + (parallel [(const_int 0)])))
  14551. + (sign_extend:SI (vec_select:HI
  14552. + (match_dup 3)
  14553. + (parallel [(const_int 1)])))))))]
  14554. + "NDS32_EXT_DSP_P ()"
  14555. + "kmaxda\t%0, %2, %3"
  14556. + [(set_attr "type" "mac")
  14557. + (set_attr "length" "4")])
  14558. +
  14559. +(define_insn "kmads"
  14560. + [(set (match_operand:SI 0 "register_operand" "=r")
  14561. + (ss_plus:SI
  14562. + (match_operand:SI 1 "register_operand" " 0")
  14563. + (ss_minus:SI
  14564. + (mult:SI
  14565. + (sign_extend:SI (vec_select:HI
  14566. + (match_operand:V2HI 2 "register_operand" " r")
  14567. + (parallel [(const_int 1)])))
  14568. + (sign_extend:SI (vec_select:HI
  14569. + (match_operand:V2HI 3 "register_operand" " r")
  14570. + (parallel [(const_int 1)]))))
  14571. + (mult:SI
  14572. + (sign_extend:SI (vec_select:HI
  14573. + (match_dup 2)
  14574. + (parallel [(const_int 0)])))
  14575. + (sign_extend:SI (vec_select:HI
  14576. + (match_dup 3)
  14577. + (parallel [(const_int 0)])))))))]
  14578. + "NDS32_EXT_DSP_P ()"
  14579. + "kmads\t%0, %2, %3"
  14580. + [(set_attr "type" "mac")
  14581. + (set_attr "length" "4")])
  14582. +
  14583. +(define_insn "kmadrs"
  14584. + [(set (match_operand:SI 0 "register_operand" "=r")
  14585. + (ss_plus:SI
  14586. + (match_operand:SI 1 "register_operand" " 0")
  14587. + (ss_minus:SI
  14588. + (mult:SI
  14589. + (sign_extend:SI (vec_select:HI
  14590. + (match_operand:V2HI 2 "register_operand" " r")
  14591. + (parallel [(const_int 0)])))
  14592. + (sign_extend:SI (vec_select:HI
  14593. + (match_operand:V2HI 3 "register_operand" " r")
  14594. + (parallel [(const_int 0)]))))
  14595. + (mult:SI
  14596. + (sign_extend:SI (vec_select:HI
  14597. + (match_dup 2)
  14598. + (parallel [(const_int 1)])))
  14599. + (sign_extend:SI (vec_select:HI
  14600. + (match_dup 3)
  14601. + (parallel [(const_int 1)])))))))]
  14602. + "NDS32_EXT_DSP_P ()"
  14603. + "kmadrs\t%0, %2, %3"
  14604. + [(set_attr "type" "mac")
  14605. + (set_attr "length" "4")])
  14606. +
  14607. +(define_insn "kmaxds"
  14608. + [(set (match_operand:SI 0 "register_operand" "=r")
  14609. + (ss_plus:SI
  14610. + (match_operand:SI 1 "register_operand" " 0")
  14611. + (ss_minus:SI
  14612. + (mult:SI
  14613. + (sign_extend:SI (vec_select:HI
  14614. + (match_operand:V2HI 2 "register_operand" " r")
  14615. + (parallel [(const_int 1)])))
  14616. + (sign_extend:SI (vec_select:HI
  14617. + (match_operand:V2HI 3 "register_operand" " r")
  14618. + (parallel [(const_int 0)]))))
  14619. + (mult:SI
  14620. + (sign_extend:SI (vec_select:HI
  14621. + (match_dup 2)
  14622. + (parallel [(const_int 0)])))
  14623. + (sign_extend:SI (vec_select:HI
  14624. + (match_dup 3)
  14625. + (parallel [(const_int 1)])))))))]
  14626. + "NDS32_EXT_DSP_P ()"
  14627. + "kmaxds\t%0, %2, %3"
  14628. + [(set_attr "type" "mac")
  14629. + (set_attr "length" "4")])
  14630. +
  14631. +(define_insn "kmsda"
  14632. + [(set (match_operand:SI 0 "register_operand" "=r")
  14633. + (ss_minus:SI
  14634. + (match_operand:SI 1 "register_operand" " 0")
  14635. + (ss_minus:SI
  14636. + (mult:SI
  14637. + (sign_extend:SI (vec_select:HI
  14638. + (match_operand:V2HI 2 "register_operand" " r")
  14639. + (parallel [(const_int 1)])))
  14640. + (sign_extend:SI (vec_select:HI
  14641. + (match_operand:V2HI 3 "register_operand" " r")
  14642. + (parallel [(const_int 1)]))))
  14643. + (mult:SI
  14644. + (sign_extend:SI (vec_select:HI
  14645. + (match_dup 2)
  14646. + (parallel [(const_int 0)])))
  14647. + (sign_extend:SI (vec_select:HI
  14648. + (match_dup 3)
  14649. + (parallel [(const_int 0)])))))))]
  14650. + "NDS32_EXT_DSP_P ()"
  14651. + "kmsda\t%0, %2, %3"
  14652. + [(set_attr "type" "mac")
  14653. + (set_attr "length" "4")])
  14654. +
  14655. +(define_insn "kmsxda"
  14656. + [(set (match_operand:SI 0 "register_operand" "=r")
  14657. + (ss_minus:SI
  14658. + (match_operand:SI 1 "register_operand" " 0")
  14659. + (ss_minus:SI
  14660. + (mult:SI
  14661. + (sign_extend:SI (vec_select:HI
  14662. + (match_operand:V2HI 2 "register_operand" " r")
  14663. + (parallel [(const_int 1)])))
  14664. + (sign_extend:SI (vec_select:HI
  14665. + (match_operand:V2HI 3 "register_operand" " r")
  14666. + (parallel [(const_int 0)]))))
  14667. + (mult:SI
  14668. + (sign_extend:SI (vec_select:HI
  14669. + (match_dup 2)
  14670. + (parallel [(const_int 0)])))
  14671. + (sign_extend:SI (vec_select:HI
  14672. + (match_dup 3)
  14673. + (parallel [(const_int 1)])))))))]
  14674. + "NDS32_EXT_DSP_P ()"
  14675. + "kmsxda\t%0, %2, %3"
  14676. + [(set_attr "type" "mac")
  14677. + (set_attr "length" "4")])
  14678. +
  14679. +;; smax[8|16] and umax[8|16]
  14680. +(define_insn "<opcode><mode>3"
  14681. + [(set (match_operand:VQIHI 0 "register_operand" "=r")
  14682. + (sumax:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
  14683. + (match_operand:VQIHI 2 "register_operand" " r")))]
  14684. + "NDS32_EXT_DSP_P ()"
  14685. + "<opcode><bits>\t%0, %1, %2"
  14686. + [(set_attr "type" "alu")
  14687. + (set_attr "length" "4")])
  14688. +
  14689. +;; smin[8|16] and umin[8|16]
  14690. +(define_insn "<opcode><mode>3"
  14691. + [(set (match_operand:VQIHI 0 "register_operand" "=r")
  14692. + (sumin:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
  14693. + (match_operand:VQIHI 2 "register_operand" " r")))]
  14694. + "NDS32_EXT_DSP_P ()"
  14695. + "<opcode><bits>\t%0, %1, %2"
  14696. + [(set_attr "type" "alu")
  14697. + (set_attr "length" "4")])
  14698. +
  14699. +(define_insn "<opcode><mode>3_bb"
  14700. + [(set (match_operand:<VELT> 0 "register_operand" "=r")
  14701. + (sumin_max:<VELT> (vec_select:<VELT>
  14702. + (match_operand:VQIHI 1 "register_operand" " r")
  14703. + (parallel [(const_int 0)]))
  14704. + (vec_select:<VELT>
  14705. + (match_operand:VQIHI 2 "register_operand" " r")
  14706. + (parallel [(const_int 0)]))))]
  14707. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14708. + "<opcode><bits>\t%0, %1, %2"
  14709. + [(set_attr "type" "alu")
  14710. + (set_attr "length" "4")])
  14711. +
  14712. +(define_insn_and_split "<opcode><mode>3_tt"
  14713. + [(set (match_operand:<VELT> 0 "register_operand" "=r")
  14714. + (sumin_max:<VELT> (vec_select:<VELT>
  14715. + (match_operand:VQIHI 1 "register_operand" " r")
  14716. + (parallel [(const_int 1)]))
  14717. + (vec_select:<VELT>
  14718. + (match_operand:VQIHI 2 "register_operand" " r")
  14719. + (parallel [(const_int 1)]))))]
  14720. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  14721. + "#"
  14722. + "NDS32_EXT_DSP_P () && !reload_completed"
  14723. + [(const_int 0)]
  14724. +{
  14725. + rtx tmp = gen_reg_rtx (<MODE>mode);
  14726. + emit_insn (gen_<opcode><mode>3 (tmp, operands[1], operands[2]));
  14727. + emit_insn (gen_rotr<mode>_1 (tmp, tmp));
  14728. + emit_move_insn (operands[0], simplify_gen_subreg (<VELT>mode, tmp, <MODE>mode, 0));
  14729. + DONE;
  14730. +}
  14731. + [(set_attr "type" "alu")
  14732. + (set_attr "length" "4")])
  14733. +
  14734. +(define_insn_and_split "<opcode>v4qi3_22"
  14735. + [(set (match_operand:QI 0 "register_operand" "=r")
  14736. + (sumin_max:QI (vec_select:QI
  14737. + (match_operand:V4QI 1 "register_operand" " r")
  14738. + (parallel [(const_int 2)]))
  14739. + (vec_select:QI
  14740. + (match_operand:V4QI 2 "register_operand" " r")
  14741. + (parallel [(const_int 2)]))))]
  14742. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  14743. + "#"
  14744. + "NDS32_EXT_DSP_P () && !reload_completed"
  14745. + [(const_int 0)]
  14746. +{
  14747. + rtx tmp = gen_reg_rtx (V4QImode);
  14748. + emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2]));
  14749. + emit_insn (gen_rotrv4qi_2 (tmp, tmp));
  14750. + emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0));
  14751. + DONE;
  14752. +}
  14753. + [(set_attr "type" "alu")
  14754. + (set_attr "length" "4")])
  14755. +
  14756. +(define_insn_and_split "<opcode>v4qi3_33"
  14757. + [(set (match_operand:QI 0 "register_operand" "=r")
  14758. + (sumin_max:QI (vec_select:QI
  14759. + (match_operand:V4QI 1 "register_operand" " r")
  14760. + (parallel [(const_int 3)]))
  14761. + (vec_select:QI
  14762. + (match_operand:V4QI 2 "register_operand" " r")
  14763. + (parallel [(const_int 3)]))))]
  14764. + "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN"
  14765. + "#"
  14766. + "NDS32_EXT_DSP_P () && !reload_completed"
  14767. + [(const_int 0)]
  14768. +{
  14769. + rtx tmp = gen_reg_rtx (V4QImode);
  14770. + emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2]));
  14771. + emit_insn (gen_rotrv4qi_3 (tmp, tmp));
  14772. + emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0));
  14773. + DONE;
  14774. +}
  14775. + [(set_attr "type" "alu")
  14776. + (set_attr "length" "4")])
  14777. +
  14778. +(define_insn_and_split "<opcode>v2hi3_bbtt"
  14779. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  14780. + (vec_merge:V2HI
  14781. + (vec_duplicate:V2HI
  14782. + (sumin_max:HI (vec_select:HI
  14783. + (match_operand:V2HI 1 "register_operand" " r")
  14784. + (parallel [(const_int 1)]))
  14785. + (vec_select:HI
  14786. + (match_operand:V2HI 2 "register_operand" " r")
  14787. + (parallel [(const_int 1)]))))
  14788. + (vec_duplicate:V2HI
  14789. + (sumin_max:HI (vec_select:HI
  14790. + (match_dup:V2HI 1)
  14791. + (parallel [(const_int 0)]))
  14792. + (vec_select:HI
  14793. + (match_dup:HI 2)
  14794. + (parallel [(const_int 0)]))))
  14795. + (const_int 2)))]
  14796. + "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN"
  14797. + "#"
  14798. + "NDS32_EXT_DSP_P ()"
  14799. + [(const_int 0)]
  14800. +{
  14801. + emit_insn (gen_<opcode>v2hi3 (operands[0], operands[1], operands[2]));
  14802. + DONE;
  14803. +}
  14804. + [(set_attr "type" "alu")
  14805. + (set_attr "length" "4")])
  14806. +
  14807. +(define_expand "abs<mode>2"
  14808. + [(set (match_operand:VQIHI 0 "register_operand" "=r")
  14809. + (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))]
  14810. + "NDS32_EXT_DSP_P () && TARGET_HW_ABS && !flag_wrapv"
  14811. +{
  14812. +})
  14813. +
  14814. +(define_insn "kabs<mode>2"
  14815. + [(set (match_operand:VQIHI 0 "register_operand" "=r")
  14816. + (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))]
  14817. + "NDS32_EXT_DSP_P ()"
  14818. + "kabs<bits>\t%0, %1"
  14819. + [(set_attr "type" "alu")
  14820. + (set_attr "length" "4")])
  14821. +
  14822. +(define_insn "<su>mar64_1"
  14823. + [(set (match_operand:DI 0 "register_operand" "=r")
  14824. + (plus:DI
  14825. + (match_operand:DI 1 "register_operand" " 0")
  14826. + (mult:DI
  14827. + (extend:DI
  14828. + (match_operand:SI 2 "register_operand" " r"))
  14829. + (extend:DI
  14830. + (match_operand:SI 3 "register_operand" " r")))))]
  14831. + "NDS32_EXT_DSP_P ()"
  14832. + "<su>mar64\t%0, %2, %3"
  14833. + [(set_attr "type" "mac")
  14834. + (set_attr "length" "4")])
  14835. +
  14836. +(define_insn "<su>mar64_2"
  14837. + [(set (match_operand:DI 0 "register_operand" "=r")
  14838. + (plus:DI
  14839. + (mult:DI
  14840. + (extend:DI
  14841. + (match_operand:SI 2 "register_operand" " r"))
  14842. + (extend:DI
  14843. + (match_operand:SI 3 "register_operand" " r")))
  14844. + (match_operand:DI 1 "register_operand" " 0")))]
  14845. + "NDS32_EXT_DSP_P ()"
  14846. + "<su>mar64\t%0, %2, %3"
  14847. + [(set_attr "type" "mac")
  14848. + (set_attr "length" "4")])
  14849. +
  14850. +(define_insn "<su>mar64_3"
  14851. + [(set (match_operand:DI 0 "register_operand" "=r")
  14852. + (plus:DI
  14853. + (match_operand:DI 1 "register_operand" " 0")
  14854. + (extend:DI
  14855. + (mult:SI
  14856. + (match_operand:SI 2 "register_operand" " r")
  14857. + (match_operand:SI 3 "register_operand" " r")))))]
  14858. + "NDS32_EXT_DSP_P ()"
  14859. + "<su>mar64\t%0, %2, %3"
  14860. + [(set_attr "type" "mac")
  14861. + (set_attr "length" "4")])
  14862. +
  14863. +(define_insn "<su>mar64_4"
  14864. + [(set (match_operand:DI 0 "register_operand" "=r")
  14865. + (plus:DI
  14866. + (extend:DI
  14867. + (mult:SI
  14868. + (match_operand:SI 2 "register_operand" " r")
  14869. + (match_operand:SI 3 "register_operand" " r")))
  14870. + (match_operand:DI 1 "register_operand" " 0")))]
  14871. + "NDS32_EXT_DSP_P ()"
  14872. + "<su>mar64\t%0, %2, %3"
  14873. + [(set_attr "type" "mac")
  14874. + (set_attr "length" "4")])
  14875. +
  14876. +(define_insn "<su>msr64"
  14877. + [(set (match_operand:DI 0 "register_operand" "=r")
  14878. + (minus:DI
  14879. + (match_operand:DI 1 "register_operand" " 0")
  14880. + (mult:DI
  14881. + (extend:DI
  14882. + (match_operand:SI 2 "register_operand" " r"))
  14883. + (extend:DI
  14884. + (match_operand:SI 3 "register_operand" " r")))))]
  14885. + "NDS32_EXT_DSP_P ()"
  14886. + "<su>msr64\t%0, %2, %3"
  14887. + [(set_attr "type" "mul")
  14888. + (set_attr "length" "4")])
  14889. +
  14890. +(define_insn "<su>msr64_2"
  14891. + [(set (match_operand:DI 0 "register_operand" "=r")
  14892. + (minus:DI
  14893. + (match_operand:DI 1 "register_operand" " 0")
  14894. + (extend:DI
  14895. + (mult:SI
  14896. + (match_operand:SI 2 "register_operand" " r")
  14897. + (match_operand:SI 3 "register_operand" " r")))))]
  14898. + "NDS32_EXT_DSP_P ()"
  14899. + "<su>msr64\t%0, %2, %3"
  14900. + [(set_attr "type" "mac")
  14901. + (set_attr "length" "4")])
  14902. +
  14903. +;; kmar64, kmsr64, ukmar64 and ukmsr64
  14904. +(define_insn "kmar64_1"
  14905. + [(set (match_operand:DI 0 "register_operand" "=r")
  14906. + (ss_plus:DI
  14907. + (match_operand:DI 1 "register_operand" " 0")
  14908. + (mult:DI
  14909. + (sign_extend:DI
  14910. + (match_operand:SI 2 "register_operand" " r"))
  14911. + (sign_extend:DI
  14912. + (match_operand:SI 3 "register_operand" " r")))))]
  14913. + "NDS32_EXT_DSP_P ()"
  14914. + "kmar64\t%0, %2, %3"
  14915. + [(set_attr "type" "mac")
  14916. + (set_attr "length" "4")])
  14917. +
  14918. +(define_insn "kmar64_2"
  14919. + [(set (match_operand:DI 0 "register_operand" "=r")
  14920. + (ss_plus:DI
  14921. + (mult:DI
  14922. + (sign_extend:DI
  14923. + (match_operand:SI 2 "register_operand" " r"))
  14924. + (sign_extend:DI
  14925. + (match_operand:SI 3 "register_operand" " r")))
  14926. + (match_operand:DI 1 "register_operand" " 0")))]
  14927. + "NDS32_EXT_DSP_P ()"
  14928. + "kmar64\t%0, %2, %3"
  14929. + [(set_attr "type" "mac")
  14930. + (set_attr "length" "4")])
  14931. +
  14932. +(define_insn "kmsr64"
  14933. + [(set (match_operand:DI 0 "register_operand" "=r")
  14934. + (ss_minus:DI
  14935. + (match_operand:DI 1 "register_operand" " 0")
  14936. + (mult:DI
  14937. + (sign_extend:DI
  14938. + (match_operand:SI 2 "register_operand" " r"))
  14939. + (sign_extend:DI
  14940. + (match_operand:SI 3 "register_operand" " r")))))]
  14941. + "NDS32_EXT_DSP_P ()"
  14942. + "kmsr64\t%0, %2, %3"
  14943. + [(set_attr "type" "mac")
  14944. + (set_attr "length" "4")])
  14945. +
  14946. +(define_insn "ukmar64_1"
  14947. + [(set (match_operand:DI 0 "register_operand" "=r")
  14948. + (us_plus:DI
  14949. + (match_operand:DI 1 "register_operand" " 0")
  14950. + (mult:DI
  14951. + (zero_extend:DI
  14952. + (match_operand:SI 2 "register_operand" " r"))
  14953. + (zero_extend:DI
  14954. + (match_operand:SI 3 "register_operand" " r")))))]
  14955. + "NDS32_EXT_DSP_P ()"
  14956. + "ukmar64\t%0, %2, %3"
  14957. + [(set_attr "type" "mac")
  14958. + (set_attr "length" "4")])
  14959. +
  14960. +(define_insn "ukmar64_2"
  14961. + [(set (match_operand:DI 0 "register_operand" "=r")
  14962. + (us_plus:DI
  14963. + (mult:DI
  14964. + (zero_extend:DI
  14965. + (match_operand:SI 2 "register_operand" " r"))
  14966. + (zero_extend:DI
  14967. + (match_operand:SI 3 "register_operand" " r")))
  14968. + (match_operand:DI 1 "register_operand" " 0")))]
  14969. + "NDS32_EXT_DSP_P ()"
  14970. + "ukmar64\t%0, %2, %3"
  14971. + [(set_attr "type" "mac")
  14972. + (set_attr "length" "4")])
  14973. +
  14974. +(define_insn "ukmsr64"
  14975. + [(set (match_operand:DI 0 "register_operand" "=r")
  14976. + (us_minus:DI
  14977. + (match_operand:DI 1 "register_operand" " 0")
  14978. + (mult:DI
  14979. + (zero_extend:DI
  14980. + (match_operand:SI 2 "register_operand" " r"))
  14981. + (zero_extend:DI
  14982. + (match_operand:SI 3 "register_operand" " r")))))]
  14983. + "NDS32_EXT_DSP_P ()"
  14984. + "ukmsr64\t%0, %2, %3"
  14985. + [(set_attr "type" "mac")
  14986. + (set_attr "length" "4")])
  14987. +
  14988. +(define_insn "bpick1"
  14989. + [(set (match_operand:SI 0 "register_operand" "=r")
  14990. + (ior:SI
  14991. + (and:SI
  14992. + (match_operand:SI 1 "register_operand" " r")
  14993. + (match_operand:SI 3 "register_operand" " r"))
  14994. + (and:SI
  14995. + (match_operand:SI 2 "register_operand" " r")
  14996. + (not:SI (match_dup 3)))))]
  14997. + "NDS32_EXT_DSP_P ()"
  14998. + "bpick\t%0, %1, %2, %3"
  14999. + [(set_attr "type" "alu")
  15000. + (set_attr "length" "4")])
  15001. +
  15002. +(define_insn "bpick2"
  15003. + [(set (match_operand:SI 0 "register_operand" "=r")
  15004. + (ior:SI
  15005. + (and:SI
  15006. + (match_operand:SI 1 "register_operand" " r")
  15007. + (match_operand:SI 2 "register_operand" " r"))
  15008. + (and:SI
  15009. + (not:SI (match_dup 2))
  15010. + (match_operand:SI 3 "register_operand" " r"))))]
  15011. + "NDS32_EXT_DSP_P ()"
  15012. + "bpick\t%0, %1, %3, %2"
  15013. + [(set_attr "type" "alu")
  15014. + (set_attr "length" "4")])
  15015. +
  15016. +(define_insn "bpick3"
  15017. + [(set (match_operand:SI 0 "register_operand" "=r")
  15018. + (ior:SI
  15019. + (and:SI
  15020. + (match_operand:SI 1 "register_operand" " r")
  15021. + (match_operand:SI 2 "register_operand" " r"))
  15022. + (and:SI
  15023. + (match_operand:SI 3 "register_operand" " r")
  15024. + (not:SI (match_dup 1)))))]
  15025. + "NDS32_EXT_DSP_P ()"
  15026. + "bpick\t%0, %2, %3, %1"
  15027. + [(set_attr "type" "alu")
  15028. + (set_attr "length" "4")])
  15029. +
  15030. +(define_insn "bpick4"
  15031. + [(set (match_operand:SI 0 "register_operand" "=r")
  15032. + (ior:SI
  15033. + (and:SI
  15034. + (match_operand:SI 1 "register_operand" " r")
  15035. + (match_operand:SI 2 "register_operand" " r"))
  15036. + (and:SI
  15037. + (not:SI (match_dup 1))
  15038. + (match_operand:SI 3 "register_operand" " r"))))]
  15039. + "NDS32_EXT_DSP_P ()"
  15040. + "bpick\t%0, %2, %3, %1"
  15041. + [(set_attr "type" "alu")
  15042. + (set_attr "length" "4")])
  15043. +
  15044. +(define_insn "bpick5"
  15045. + [(set (match_operand:SI 0 "register_operand" "=r")
  15046. + (ior:SI
  15047. + (and:SI
  15048. + (match_operand:SI 1 "register_operand" " r")
  15049. + (not:SI (match_operand:SI 2 "register_operand" " r")))
  15050. + (and:SI
  15051. + (match_operand:SI 3 "register_operand" " r")
  15052. + (match_dup 2))))]
  15053. + "NDS32_EXT_DSP_P ()"
  15054. + "bpick\t%0, %3, %1, %2"
  15055. + [(set_attr "type" "alu")
  15056. + (set_attr "length" "4")])
  15057. +
  15058. +(define_insn "bpick6"
  15059. + [(set (match_operand:SI 0 "register_operand" "=r")
  15060. + (ior:SI
  15061. + (and:SI
  15062. + (not:SI (match_operand:SI 1 "register_operand" " r"))
  15063. + (match_operand:SI 2 "register_operand" " r"))
  15064. + (and:SI
  15065. + (match_operand:SI 3 "register_operand" " r")
  15066. + (match_dup 1))))]
  15067. + "NDS32_EXT_DSP_P ()"
  15068. + "bpick\t%0, %3, %2, %1"
  15069. + [(set_attr "type" "alu")
  15070. + (set_attr "length" "4")])
  15071. +
  15072. +(define_insn "bpick7"
  15073. + [(set (match_operand:SI 0 "register_operand" "=r")
  15074. + (ior:SI
  15075. + (and:SI
  15076. + (match_operand:SI 1 "register_operand" " r")
  15077. + (not:SI (match_operand:SI 2 "register_operand" " r")))
  15078. + (and:SI
  15079. + (match_dup 2)
  15080. + (match_operand:SI 3 "register_operand" " r"))))]
  15081. + "NDS32_EXT_DSP_P ()"
  15082. + "bpick\t%0, %3, %1, %2"
  15083. + [(set_attr "type" "alu")
  15084. + (set_attr "length" "4")])
  15085. +
  15086. +(define_insn "bpick8"
  15087. + [(set (match_operand:SI 0 "register_operand" "=r")
  15088. + (ior:SI
  15089. + (and:SI
  15090. + (not:SI (match_operand:SI 1 "register_operand" " r"))
  15091. + (match_operand:SI 2 "register_operand" " r"))
  15092. + (and:SI
  15093. + (match_dup 1)
  15094. + (match_operand:SI 3 "register_operand" " r"))))]
  15095. + "NDS32_EXT_DSP_P ()"
  15096. + "bpick\t%0, %3, %2, %1"
  15097. + [(set_attr "type" "alu")
  15098. + (set_attr "length" "4")])
  15099. +
  15100. +(define_insn "sraiu"
  15101. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  15102. + (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r, r")
  15103. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r"))]
  15104. + UNSPEC_ROUND))]
  15105. + "NDS32_EXT_DSP_P ()"
  15106. + "@
  15107. + srai.u\t%0, %1, %2
  15108. + sra.u\t%0, %1, %2"
  15109. + [(set_attr "type" "alu")
  15110. + (set_attr "length" "4")])
  15111. +
  15112. +(define_insn "kssl"
  15113. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  15114. + (ss_ashift:SI (match_operand:SI 1 "register_operand" " r, r")
  15115. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))]
  15116. + "NDS32_EXT_DSP_P ()"
  15117. + "@
  15118. + kslli\t%0, %1, %2
  15119. + ksll\t%0, %1, %2"
  15120. + [(set_attr "type" "alu")
  15121. + (set_attr "length" "4")])
  15122. +
  15123. +(define_insn "kslraw_round"
  15124. + [(set (match_operand:SI 0 "register_operand" "=r")
  15125. + (if_then_else:SI
  15126. + (lt:SI (match_operand:SI 2 "register_operand" " r")
  15127. + (const_int 0))
  15128. + (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r")
  15129. + (neg:SI (match_dup 2)))]
  15130. + UNSPEC_ROUND)
  15131. + (ss_ashift:SI (match_dup 1)
  15132. + (match_dup 2))))]
  15133. + "NDS32_EXT_DSP_P ()"
  15134. + "kslraw.u\t%0, %1, %2"
  15135. + [(set_attr "type" "alu")
  15136. + (set_attr "length" "4")])
  15137. +
  15138. +(define_insn_and_split "<shift>di3"
  15139. + [(set (match_operand:DI 0 "register_operand" "")
  15140. + (shift_rotate:DI (match_operand:DI 1 "register_operand" "")
  15141. + (match_operand:SI 2 "nds32_rimm6u_operand" "")))]
  15142. + "NDS32_EXT_DSP_P () && !reload_completed"
  15143. + "#"
  15144. + "NDS32_EXT_DSP_P () && !reload_completed"
  15145. + [(const_int 0)]
  15146. +{
  15147. + if (REGNO (operands[0]) == REGNO (operands[1]))
  15148. + {
  15149. + rtx tmp = gen_reg_rtx (DImode);
  15150. + nds32_split_<code>di3 (tmp, operands[1], operands[2]);
  15151. + emit_move_insn (operands[0], tmp);
  15152. + }
  15153. + else
  15154. + nds32_split_<code>di3 (operands[0], operands[1], operands[2]);
  15155. + DONE;
  15156. +})
  15157. +
  15158. +(define_insn "sclip32"
  15159. + [(set (match_operand:SI 0 "register_operand" "=r")
  15160. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  15161. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))]
  15162. + "NDS32_EXT_DSP_P ()"
  15163. + "sclip32\t%0, %1, %2"
  15164. + [(set_attr "type" "alu")
  15165. + (set_attr "length" "4")]
  15166. +)
  15167. +
  15168. +(define_insn "uclip32"
  15169. + [(set (match_operand:SI 0 "register_operand" "=r")
  15170. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  15171. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP_OV))]
  15172. + "NDS32_EXT_DSP_P ()"
  15173. + "uclip32\t%0, %1, %2"
  15174. + [(set_attr "type" "alu")
  15175. + (set_attr "length" "4")]
  15176. +)
  15177. +
  15178. +(define_insn "bitrev"
  15179. + [(set (match_operand:SI 0 "register_operand" "=r, r")
  15180. + (unspec:SI [(match_operand:SI 1 "register_operand" " r, r")
  15181. + (match_operand:SI 2 "nds32_rimm5u_operand" " r, Iu05")]
  15182. + UNSPEC_BITREV))]
  15183. + ""
  15184. + "@
  15185. + bitrev\t%0, %1, %2
  15186. + bitrevi\t%0, %1, %2"
  15187. + [(set_attr "type" "alu")
  15188. + (set_attr "length" "4")]
  15189. +)
  15190. +
  15191. +;; wext, wexti
  15192. +(define_insn "<su>wext"
  15193. + [(set (match_operand:SI 0 "register_operand" "=r, r")
  15194. + (truncate:SI
  15195. + (shiftrt:DI
  15196. + (match_operand:DI 1 "register_operand" " r, r")
  15197. + (match_operand:SI 2 "nds32_rimm5u_operand" " r,Iu05"))))]
  15198. + "NDS32_EXT_DSP_P ()"
  15199. + "@
  15200. + wext\t%0, %1, %2
  15201. + wexti\t%0, %1, %2"
  15202. + [(set_attr "type" "alu")
  15203. + (set_attr "length" "4")])
  15204. +
  15205. +;; 32-bit add/sub instruction: raddw and rsubw.
  15206. +(define_insn "r<opcode>si3"
  15207. + [(set (match_operand:SI 0 "register_operand" "=r")
  15208. + (truncate:SI
  15209. + (ashiftrt:DI
  15210. + (plus_minus:DI
  15211. + (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
  15212. + (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
  15213. + (const_int 1))))]
  15214. + "NDS32_EXT_DSP_P ()"
  15215. + "r<opcode>w\t%0, %1, %2"
  15216. + [(set_attr "type" "alu")
  15217. + (set_attr "length" "4")])
  15218. +
  15219. +;; 32-bit add/sub instruction: uraddw and ursubw.
  15220. +(define_insn "ur<opcode>si3"
  15221. + [(set (match_operand:SI 0 "register_operand" "=r")
  15222. + (truncate:SI
  15223. + (lshiftrt:DI
  15224. + (plus_minus:DI
  15225. + (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
  15226. + (zero_extend:DI (match_operand:SI 2 "register_operand" " r")))
  15227. + (const_int 1))))]
  15228. + "NDS32_EXT_DSP_P ()"
  15229. + "ur<opcode>w\t%0, %1, %2"
  15230. + [(set_attr "type" "alu")
  15231. + (set_attr "length" "4")])
  15232. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-e8.md gcc-4.9.4/gcc/config/nds32/nds32-e8.md
  15233. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-e8.md 1970-01-01 01:00:00.000000000 +0100
  15234. +++ gcc-4.9.4/gcc/config/nds32/nds32-e8.md 2016-08-08 20:37:45.498269782 +0200
  15235. @@ -0,0 +1,284 @@
  15236. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  15237. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  15238. +;; Contributed by Andes Technology Corporation.
  15239. +;;
  15240. +;; This file is part of GCC.
  15241. +;;
  15242. +;; GCC is free software; you can redistribute it and/or modify it
  15243. +;; under the terms of the GNU General Public License as published
  15244. +;; by the Free Software Foundation; either version 3, or (at your
  15245. +;; option) any later version.
  15246. +;;
  15247. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  15248. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15249. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  15250. +;; License for more details.
  15251. +;;
  15252. +;; You should have received a copy of the GNU General Public License
  15253. +;; along with GCC; see the file COPYING3. If not see
  15254. +;; <http://www.gnu.org/licenses/>.
  15255. +
  15256. +
  15257. +;; ------------------------------------------------------------------------
  15258. +;; Define E8 pipeline settings.
  15259. +;; ------------------------------------------------------------------------
  15260. +
  15261. +(define_automaton "nds32_e8_machine")
  15262. +
  15263. +(define_cpu_unit "e8_ii" "nds32_e8_machine")
  15264. +(define_cpu_unit "e8_ex" "nds32_e8_machine")
  15265. +
  15266. +(define_insn_reservation "nds_e8_unknown" 1
  15267. + (and (eq_attr "type" "unknown")
  15268. + (eq_attr "pipeline_model" "e8"))
  15269. + "e8_ii, e8_ex")
  15270. +
  15271. +(define_insn_reservation "nds_e8_misc" 1
  15272. + (and (eq_attr "type" "misc")
  15273. + (eq_attr "pipeline_model" "e8"))
  15274. + "e8_ii, e8_ex")
  15275. +
  15276. +(define_insn_reservation "nds_e8_alu" 1
  15277. + (and (eq_attr "type" "alu")
  15278. + (eq_attr "pipeline_model" "e8"))
  15279. + "e8_ii, e8_ex")
  15280. +
  15281. +(define_insn_reservation "nds_e8_load" 1
  15282. + (and (match_test "nds32_load_single_p (insn)")
  15283. + (eq_attr "pipeline_model" "e8"))
  15284. + "e8_ii, e8_ex")
  15285. +
  15286. +(define_insn_reservation "nds_e8_store" 1
  15287. + (and (match_test "nds32_store_single_p (insn)")
  15288. + (eq_attr "pipeline_model" "e8"))
  15289. + "e8_ii, e8_ex")
  15290. +
  15291. +(define_insn_reservation "nds_e8_load_multiple_1" 1
  15292. + (and (and (eq_attr "type" "load_multiple")
  15293. + (eq_attr "combo" "1"))
  15294. + (eq_attr "pipeline_model" "e8"))
  15295. + "e8_ii, e8_ex")
  15296. +
  15297. +(define_insn_reservation "nds_e8_load_multiple_2" 1
  15298. + (and (ior (and (eq_attr "type" "load_multiple")
  15299. + (eq_attr "combo" "2"))
  15300. + (match_test "nds32_load_double_p (insn)"))
  15301. + (eq_attr "pipeline_model" "e8"))
  15302. + "e8_ii, e8_ii+e8_ex, e8_ex")
  15303. +
  15304. +(define_insn_reservation "nds_e8_load_multiple_3" 1
  15305. + (and (and (eq_attr "type" "load_multiple")
  15306. + (eq_attr "combo" "3"))
  15307. + (eq_attr "pipeline_model" "e8"))
  15308. + "e8_ii, (e8_ii+e8_ex)*2, e8_ex")
  15309. +
  15310. +(define_insn_reservation "nds_e8_load_multiple_4" 1
  15311. + (and (and (eq_attr "type" "load_multiple")
  15312. + (eq_attr "combo" "4"))
  15313. + (eq_attr "pipeline_model" "e8"))
  15314. + "e8_ii, (e8_ii+e8_ex)*3, e8_ex")
  15315. +
  15316. +(define_insn_reservation "nds_e8_load_multiple_5" 1
  15317. + (and (and (eq_attr "type" "load_multiple")
  15318. + (eq_attr "combo" "5"))
  15319. + (eq_attr "pipeline_model" "e8"))
  15320. + "e8_ii, (e8_ii+e8_ex)*4, e8_ex")
  15321. +
  15322. +(define_insn_reservation "nds_e8_load_multiple_6" 1
  15323. + (and (and (eq_attr "type" "load_multiple")
  15324. + (eq_attr "combo" "6"))
  15325. + (eq_attr "pipeline_model" "e8"))
  15326. + "e8_ii, (e8_ii+e8_ex)*5, e8_ex")
  15327. +
  15328. +(define_insn_reservation "nds_e8_load_multiple_7" 1
  15329. + (and (and (eq_attr "type" "load_multiple")
  15330. + (eq_attr "combo" "7"))
  15331. + (eq_attr "pipeline_model" "e8"))
  15332. + "e8_ii, (e8_ii+e8_ex)*6, e8_ex")
  15333. +
  15334. +(define_insn_reservation "nds_e8_load_multiple_8" 1
  15335. + (and (and (eq_attr "type" "load_multiple")
  15336. + (eq_attr "combo" "8"))
  15337. + (eq_attr "pipeline_model" "e8"))
  15338. + "e8_ii, (e8_ii+e8_ex)*7, e8_ex")
  15339. +
  15340. +(define_insn_reservation "nds_e8_load_multiple_12" 1
  15341. + (and (and (eq_attr "type" "load_multiple")
  15342. + (eq_attr "combo" "12"))
  15343. + (eq_attr "pipeline_model" "e8"))
  15344. + "e8_ii, (e8_ii+e8_ex)*11, e8_ex")
  15345. +
  15346. +(define_insn_reservation "nds_e8_store_multiple_1" 1
  15347. + (and (and (eq_attr "type" "store_multiple")
  15348. + (eq_attr "combo" "1"))
  15349. + (eq_attr "pipeline_model" "e8"))
  15350. + "e8_ii, e8_ex")
  15351. +
  15352. +(define_insn_reservation "nds_e8_store_multiple_2" 1
  15353. + (and (ior (and (eq_attr "type" "store_multiple")
  15354. + (eq_attr "combo" "2"))
  15355. + (match_test "nds32_store_double_p (insn)"))
  15356. + (eq_attr "pipeline_model" "e8"))
  15357. + "e8_ii, e8_ii+e8_ex, e8_ex")
  15358. +
  15359. +(define_insn_reservation "nds_e8_store_multiple_3" 1
  15360. + (and (and (eq_attr "type" "store_multiple")
  15361. + (eq_attr "combo" "3"))
  15362. + (eq_attr "pipeline_model" "e8"))
  15363. + "e8_ii, (e8_ii+e8_ex)*2, e8_ex")
  15364. +
  15365. +(define_insn_reservation "nds_e8_store_multiple_4" 1
  15366. + (and (and (eq_attr "type" "store_multiple")
  15367. + (eq_attr "combo" "4"))
  15368. + (eq_attr "pipeline_model" "e8"))
  15369. + "e8_ii, (e8_ii+e8_ex)*3, e8_ex")
  15370. +
  15371. +(define_insn_reservation "nds_e8_store_multiple_5" 1
  15372. + (and (and (eq_attr "type" "store_multiple")
  15373. + (eq_attr "combo" "5"))
  15374. + (eq_attr "pipeline_model" "e8"))
  15375. + "e8_ii, (e8_ii+e8_ex)*4, e8_ex")
  15376. +
  15377. +(define_insn_reservation "nds_e8_store_multiple_6" 1
  15378. + (and (and (eq_attr "type" "store_multiple")
  15379. + (eq_attr "combo" "6"))
  15380. + (eq_attr "pipeline_model" "e8"))
  15381. + "e8_ii, (e8_ii+e8_ex)*5, e8_ex")
  15382. +
  15383. +(define_insn_reservation "nds_e8_store_multiple_7" 1
  15384. + (and (and (eq_attr "type" "store_multiple")
  15385. + (eq_attr "combo" "7"))
  15386. + (eq_attr "pipeline_model" "e8"))
  15387. + "e8_ii, (e8_ii+e8_ex)*6, e8_ex")
  15388. +
  15389. +(define_insn_reservation "nds_e8_store_multiple_8" 1
  15390. + (and (and (eq_attr "type" "store_multiple")
  15391. + (eq_attr "combo" "8"))
  15392. + (eq_attr "pipeline_model" "e8"))
  15393. + "e8_ii, (e8_ii+e8_ex)*7, e8_ex")
  15394. +
  15395. +(define_insn_reservation "nds_e8_store_multiple_12" 1
  15396. + (and (and (eq_attr "type" "store_multiple")
  15397. + (eq_attr "combo" "12"))
  15398. + (eq_attr "pipeline_model" "e8"))
  15399. + "e8_ii, (e8_ii+e8_ex)*11, e8_ex")
  15400. +
  15401. +(define_insn_reservation "nds_e8_mul_fast" 1
  15402. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  15403. + (and (eq_attr "type" "mul")
  15404. + (eq_attr "pipeline_model" "e8")))
  15405. + "e8_ii, e8_ex")
  15406. +
  15407. +(define_insn_reservation "nds_e8_mul_slow" 1
  15408. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  15409. + (and (eq_attr "type" "mul")
  15410. + (eq_attr "pipeline_model" "e8")))
  15411. + "e8_ii, e8_ex*16")
  15412. +
  15413. +(define_insn_reservation "nds_e8_mac_fast" 1
  15414. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  15415. + (and (eq_attr "type" "mac")
  15416. + (eq_attr "pipeline_model" "e8")))
  15417. + "e8_ii, e8_ii+e8_ex, e8_ex")
  15418. +
  15419. +(define_insn_reservation "nds_e8_mac_slow" 1
  15420. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  15421. + (and (eq_attr "type" "mac")
  15422. + (eq_attr "pipeline_model" "e8")))
  15423. + "e8_ii, (e8_ii+e8_ex)*16, e8_ex")
  15424. +
  15425. +(define_insn_reservation "nds_e8_div" 1
  15426. + (and (eq_attr "type" "div")
  15427. + (eq_attr "pipeline_model" "e8"))
  15428. + "e8_ii, (e8_ii+e8_ex)*36, e8_ex")
  15429. +
  15430. +(define_insn_reservation "nds_e8_branch" 1
  15431. + (and (eq_attr "type" "branch")
  15432. + (eq_attr "pipeline_model" "e8"))
  15433. + "e8_ii, e8_ex")
  15434. +
  15435. +;; LD -> ADDR_IN_MOP(1)
  15436. +(define_bypass 2
  15437. + "nds_e8_load"
  15438. + "nds_e8_branch,\
  15439. + nds_e8_load, nds_e8_store,\
  15440. + nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15441. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15442. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
  15443. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15444. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15445. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15446. + "nds32_e8_load_to_ii_p"
  15447. +)
  15448. +
  15449. +;; LD -> ALU, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
  15450. +(define_bypass 2
  15451. + "nds_e8_load"
  15452. + "nds_e8_alu,
  15453. + nds_e8_mul_fast, nds_e8_mul_slow,\
  15454. + nds_e8_mac_fast, nds_e8_mac_slow,\
  15455. + nds_e8_div,\
  15456. + nds_e8_branch,\
  15457. + nds_e8_store,\
  15458. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15459. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15460. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15461. + "nds32_e8_load_to_ex_p"
  15462. +)
  15463. +
  15464. +;; ALU, MOVD44, MUL, MAC, DIV_Rs, LD_bi, ADDR_OUT -> ADDR_IN_MOP(1)
  15465. +(define_bypass 2
  15466. + "nds_e8_alu,
  15467. + nds_e8_mul_fast, nds_e8_mul_slow,\
  15468. + nds_e8_mac_fast, nds_e8_mac_slow,\
  15469. + nds_e8_div,\
  15470. + nds_e8_load, nds_e8_store,\
  15471. + nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15472. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15473. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
  15474. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15475. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15476. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15477. + "nds_e8_branch,\
  15478. + nds_e8_load, nds_e8_store,\
  15479. + nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15480. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15481. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
  15482. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15483. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15484. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15485. + "nds32_e8_ex_to_ii_p"
  15486. +)
  15487. +
  15488. +;; LMW(N, N) -> ADDR_IN_MOP(1)
  15489. +(define_bypass 2
  15490. + "nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15491. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15492. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12"
  15493. + "nds_e8_branch,\
  15494. + nds_e8_load, nds_e8_store,\
  15495. + nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15496. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15497. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
  15498. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15499. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15500. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15501. + "nds32_e8_last_load_to_ii_p"
  15502. +)
  15503. +
  15504. +;; LMW(N, N) -> ALU, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
  15505. +(define_bypass 2
  15506. + "nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
  15507. + nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
  15508. + nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12"
  15509. + "nds_e8_alu,
  15510. + nds_e8_mul_fast, nds_e8_mul_slow,\
  15511. + nds_e8_mac_fast, nds_e8_mac_slow,\
  15512. + nds_e8_div,\
  15513. + nds_e8_branch,\
  15514. + nds_e8_store,\
  15515. + nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
  15516. + nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
  15517. + nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
  15518. + "nds32_e8_last_load_to_ex_p"
  15519. +)
  15520. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-elf.opt gcc-4.9.4/gcc/config/nds32/nds32-elf.opt
  15521. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-elf.opt 1970-01-01 01:00:00.000000000 +0100
  15522. +++ gcc-4.9.4/gcc/config/nds32/nds32-elf.opt 2016-08-08 20:37:45.498269782 +0200
  15523. @@ -0,0 +1,16 @@
  15524. +mcmodel=
  15525. +Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_MEDIUM)
  15526. +Specify the address generation strategy for code model.
  15527. +
  15528. +Enum
  15529. +Name(nds32_cmodel_type) Type(enum nds32_cmodel_type)
  15530. +Known cmodel types (for use with the -mcmodel= option):
  15531. +
  15532. +EnumValue
  15533. +Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL)
  15534. +
  15535. +EnumValue
  15536. +Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM)
  15537. +
  15538. +EnumValue
  15539. +Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE)
  15540. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-fp-as-gp.c gcc-4.9.4/gcc/config/nds32/nds32-fp-as-gp.c
  15541. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-fp-as-gp.c 1970-01-01 01:00:00.000000000 +0100
  15542. +++ gcc-4.9.4/gcc/config/nds32/nds32-fp-as-gp.c 2016-08-08 20:37:45.502269936 +0200
  15543. @@ -0,0 +1,287 @@
  15544. +/* fp-as-gp pass of Andes NDS32 cpu for GNU compiler
  15545. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  15546. + Contributed by Andes Technology Corporation.
  15547. +
  15548. + This file is part of GCC.
  15549. +
  15550. + GCC is free software; you can redistribute it and/or modify it
  15551. + under the terms of the GNU General Public License as published
  15552. + by the Free Software Foundation; either version 3, or (at your
  15553. + option) any later version.
  15554. +
  15555. + GCC is distributed in the hope that it will be useful, but WITHOUT
  15556. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15557. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  15558. + License for more details.
  15559. +
  15560. + You should have received a copy of the GNU General Public License
  15561. + along with GCC; see the file COPYING3. If not see
  15562. + <http://www.gnu.org/licenses/>. */
  15563. +
  15564. +/* ------------------------------------------------------------------------ */
  15565. +
  15566. +#include "config.h"
  15567. +#include "system.h"
  15568. +#include "coretypes.h"
  15569. +#include "tm.h"
  15570. +#include "tree.h"
  15571. +#include "rtl.h"
  15572. +#include "regs.h"
  15573. +#include "hard-reg-set.h"
  15574. +#include "insn-config.h" /* Required by recog.h. */
  15575. +#include "conditions.h"
  15576. +#include "output.h"
  15577. +#include "insn-attr.h" /* For DFA state_t. */
  15578. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  15579. +#include "reload.h" /* For push_reload(). */
  15580. +#include "flags.h"
  15581. +#include "function.h"
  15582. +#include "expr.h"
  15583. +#include "recog.h"
  15584. +#include "diagnostic-core.h"
  15585. +#include "df.h"
  15586. +#include "tm_p.h"
  15587. +#include "tm-constrs.h"
  15588. +#include "target.h"
  15589. +#include "target-def.h"
  15590. +#include "langhooks.h" /* For add_builtin_function(). */
  15591. +#include "ggc.h"
  15592. +#include "tree-pass.h"
  15593. +#include "target-globals.h"
  15594. +#include "ira-int.h"
  15595. +
  15596. +/* ------------------------------------------------------------------------ */
  15597. +
  15598. +/* A helper function to check if this function should contain prologue. */
  15599. +static bool
  15600. +nds32_have_prologue_p (void)
  15601. +{
  15602. + int i;
  15603. +
  15604. + for (i = 0; i < 28; i++)
  15605. + if (NDS32_REQUIRED_CALLEE_SAVED_P (i))
  15606. + return true;
  15607. +
  15608. + return (flag_pic
  15609. + || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
  15610. + || NDS32_REQUIRED_CALLEE_SAVED_P (LP_REGNUM));
  15611. +}
  15612. +
  15613. +static int
  15614. +nds32_get_symbol_count (void)
  15615. +{
  15616. + int symbol_count = 0;
  15617. + rtx insn;
  15618. + basic_block bb;
  15619. +
  15620. + FOR_EACH_BB_FN (bb, cfun)
  15621. + {
  15622. + FOR_BB_INSNS (bb, insn)
  15623. + {
  15624. + /* Counting the insn number which the addressing mode is symbol. */
  15625. + if (single_set (insn) && nds32_symbol_load_store_p (insn))
  15626. + {
  15627. + rtx pattern = PATTERN (insn);
  15628. + rtx mem;
  15629. + gcc_assert (GET_CODE (pattern) == SET);
  15630. + if (GET_CODE (SET_SRC (pattern)) == REG )
  15631. + mem = SET_DEST (pattern);
  15632. + else
  15633. + mem = SET_SRC (pattern);
  15634. +
  15635. + /* We have only lwi37 and swi37 for fp-as-gp optimization,
  15636. + so don't count any other than SImode.
  15637. + MEM for QImode and HImode will wrap by ZERO_EXTEND
  15638. + or SIGN_EXTEND */
  15639. + if (GET_CODE (mem) == MEM)
  15640. + symbol_count++;
  15641. + }
  15642. + }
  15643. + }
  15644. +
  15645. + return symbol_count;
  15646. +}
  15647. +
  15648. +/* Function to determine whether it is worth to do fp_as_gp optimization.
  15649. + Return false: It is NOT worth to do fp_as_gp optimization.
  15650. + Return true: It is APPROXIMATELY worth to do fp_as_gp optimization.
  15651. + Note that if it is worth to do fp_as_gp optimization,
  15652. + we MUST set FP_REGNUM ever live in this function. */
  15653. +static bool
  15654. +nds32_fp_as_gp_check_available (void)
  15655. +{
  15656. + basic_block bb;
  15657. + basic_block exit_bb;
  15658. + edge_iterator ei;
  15659. + edge e;
  15660. + bool first_exit_blocks_p;
  15661. +
  15662. + /* If there exists ANY of following conditions,
  15663. + we DO NOT perform fp_as_gp optimization:
  15664. + 1. TARGET_FORBID_FP_AS_GP is set
  15665. + regardless of the TARGET_FORCE_FP_AS_GP.
  15666. + 2. User explicitly uses 'naked'/'no_prologue' attribute.
  15667. + We use nds32_naked_function_p() to help such checking.
  15668. + 3. Not optimize for size.
  15669. + 4. Need frame pointer.
  15670. + 5. If $fp is already required to be saved,
  15671. + it means $fp is already choosen by register allocator.
  15672. + Thus we better not to use it for fp_as_gp optimization.
  15673. + 6. This function is a vararg function.
  15674. + DO NOT apply fp_as_gp optimization on this function
  15675. + because it may change and break stack frame.
  15676. + 7. The epilogue is empty.
  15677. + This happens when the function uses exit()
  15678. + or its attribute is no_return.
  15679. + In that case, compiler will not expand epilogue
  15680. + so that we have no chance to output .omit_fp_end directive. */
  15681. + if (TARGET_FORBID_FP_AS_GP
  15682. + || nds32_naked_function_p (current_function_decl)
  15683. + || !optimize_size
  15684. + || frame_pointer_needed
  15685. + || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
  15686. + || (cfun->stdarg == 1)
  15687. + || (find_fallthru_edge (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == NULL))
  15688. + return false;
  15689. +
  15690. + /* Disable fp_as_gp if there is any infinite loop since the fp may
  15691. + reuse in infinite loops by register rename.
  15692. + For check infinite loops we should make sure exit_bb is post dominate
  15693. + all other basic blocks if there is no infinite loops. */
  15694. + first_exit_blocks_p = true;
  15695. + exit_bb = NULL;
  15696. +
  15697. + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds)
  15698. + {
  15699. + /* More than one exit block also do not perform fp_as_gp optimization. */
  15700. + if (!first_exit_blocks_p)
  15701. + return false;
  15702. +
  15703. + exit_bb = e->src;
  15704. + first_exit_blocks_p = false;
  15705. + }
  15706. +
  15707. + /* Not found exit_bb? just abort fp_as_gp! */
  15708. + if (!exit_bb)
  15709. + return false;
  15710. +
  15711. + /* Each bb should post dominate by exit_bb if there is no infinite loop! */
  15712. + FOR_EACH_BB_FN (bb, cfun)
  15713. + {
  15714. + if (!dominated_by_p (CDI_POST_DOMINATORS,
  15715. + bb,
  15716. + exit_bb))
  15717. + return false;
  15718. + }
  15719. +
  15720. + /* Now we can check the possibility of using fp_as_gp optimization. */
  15721. + if (TARGET_FORCE_FP_AS_GP)
  15722. + {
  15723. + /* User explicitly issues -mforce-fp-as-gp option. */
  15724. + return true;
  15725. + }
  15726. + else
  15727. + {
  15728. + /* In the following we are going to evaluate whether
  15729. + it is worth to do fp_as_gp optimization. */
  15730. + bool good_gain = false;
  15731. + int symbol_count;
  15732. +
  15733. + int threshold;
  15734. +
  15735. + /* We check if there already requires prologue.
  15736. + Note that $gp will be saved in prologue for PIC code generation.
  15737. + After that, we can set threshold by the existence of prologue.
  15738. + Each fp-implied instruction will gain 2-byte code size
  15739. + from gp-aware instruction, so we have following heuristics. */
  15740. + if (flag_pic
  15741. + || nds32_have_prologue_p ())
  15742. + {
  15743. + /* Have-prologue:
  15744. + Compiler already intends to generate prologue content,
  15745. + so the fp_as_gp optimization will only insert
  15746. + 'la $fp,_FP_BASE_' instruction, which will be
  15747. + converted into 4-byte instruction at link time.
  15748. + The threshold is "3" symbol accesses, 2 + 2 + 2 > 4. */
  15749. + threshold = 3;
  15750. + }
  15751. + else
  15752. + {
  15753. + /* None-prologue:
  15754. + Compiler originally does not generate prologue content,
  15755. + so the fp_as_gp optimization will NOT ONLY insert
  15756. + 'la $fp,_FP_BASE' instruction, but also causes
  15757. + push/pop instructions.
  15758. + If we are using v3push (push25/pop25),
  15759. + the threshold is "5" symbol accesses, 5*2 > 4 + 2 + 2;
  15760. + If we are using normal push (smw/lmw),
  15761. + the threshold is "5+2" symbol accesses 7*2 > 4 + 4 + 4. */
  15762. + threshold = 5 + (TARGET_V3PUSH ? 0 : 2);
  15763. + }
  15764. +
  15765. + symbol_count = nds32_get_symbol_count ();
  15766. +
  15767. + if (symbol_count >= threshold)
  15768. + good_gain = true;
  15769. +
  15770. + /* Enable fp_as_gp optimization when potential gain is good enough. */
  15771. + return good_gain;
  15772. + }
  15773. +}
  15774. +
  15775. +static unsigned int
  15776. +nds32_fp_as_gp (void)
  15777. +{
  15778. + bool fp_as_gp_p;
  15779. + calculate_dominance_info (CDI_POST_DOMINATORS);
  15780. + fp_as_gp_p = nds32_fp_as_gp_check_available ();
  15781. +
  15782. + /* Here is a hack to IRA for enable/disable a hard register per function.
  15783. + We *MUST* review this way after migrate gcc 4.9! */
  15784. + if (fp_as_gp_p) {
  15785. + SET_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM);
  15786. + df_set_regs_ever_live (FP_REGNUM, 1);
  15787. + } else {
  15788. + CLEAR_HARD_REG_BIT(this_target_ira_int->x_no_unit_alloc_regs, FP_REGNUM);
  15789. + }
  15790. +
  15791. + cfun->machine->fp_as_gp_p = fp_as_gp_p;
  15792. +
  15793. + free_dominance_info (CDI_POST_DOMINATORS);
  15794. + return 1;
  15795. +}
  15796. +
  15797. +const pass_data pass_data_nds32_fp_as_gp =
  15798. +{
  15799. + RTL_PASS, /* type */
  15800. + "fp_as_gp", /* name */
  15801. + OPTGROUP_NONE, /* optinfo_flags */
  15802. + true, /* has_gate */
  15803. + true, /* has_execute */
  15804. + TV_MACH_DEP, /* tv_id */
  15805. + 0, /* properties_required */
  15806. + 0, /* properties_provided */
  15807. + 0, /* properties_destroyed */
  15808. + 0, /* todo_flags_start */
  15809. + TODO_verify_rtl_sharing, /* todo_flags_finish */
  15810. +};
  15811. +
  15812. +class pass_nds32_fp_as_gp : public rtl_opt_pass
  15813. +{
  15814. +public:
  15815. + pass_nds32_fp_as_gp (gcc::context *ctxt)
  15816. + : rtl_opt_pass (pass_data_nds32_fp_as_gp, ctxt)
  15817. + {}
  15818. +
  15819. + /* opt_pass methods: */
  15820. + bool gate () { return !TARGET_LINUX_ABI && TARGET_16_BIT && optimize_size; }
  15821. + unsigned int execute () { return nds32_fp_as_gp (); }
  15822. +};
  15823. +
  15824. +rtl_opt_pass *
  15825. +make_pass_nds32_fp_as_gp (gcc::context *ctxt)
  15826. +{
  15827. + return new pass_nds32_fp_as_gp (ctxt);
  15828. +}
  15829. +
  15830. +/* ------------------------------------------------------------------------ */
  15831. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-fpu.md gcc-4.9.4/gcc/config/nds32/nds32-fpu.md
  15832. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-fpu.md 1970-01-01 01:00:00.000000000 +0100
  15833. +++ gcc-4.9.4/gcc/config/nds32/nds32-fpu.md 2016-08-08 20:37:45.502269936 +0200
  15834. @@ -0,0 +1,475 @@
  15835. +;; Machine description of Andes NDS32 cpu for GNU compiler
  15836. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  15837. +;; Contributed by Andes Technology Corporation.
  15838. +;;
  15839. +;; This file is part of GCC.
  15840. +;;
  15841. +;; GCC is free software; you can redistribute it and/or modify it
  15842. +;; under the terms of the GNU General Public License as published
  15843. +;; by the Free Software Foundation; either version 3, or (at your
  15844. +;; option) any later version.
  15845. +;;
  15846. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  15847. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15848. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  15849. +;; License for more details.
  15850. +;;
  15851. +;; You should have received a copy of the GNU General Public License
  15852. +;; along with GCC; see the file COPYING3. If not see
  15853. +;; <http://www.gnu.org/licenses/>.
  15854. +
  15855. +;;SFmode moves
  15856. +
  15857. +(define_expand "movsf"
  15858. + [(set (match_operand:SF 0 "general_operand" "")
  15859. + (match_operand:SF 1 "general_operand" ""))]
  15860. + ""
  15861. +{
  15862. + /* Need to force register if mem <- !reg. */
  15863. + if (MEM_P (operands[0]) && !REG_P (operands[1]))
  15864. + operands[1] = force_reg (SFmode, operands[1]);
  15865. + if (CONST_DOUBLE_P (operands[1])
  15866. + && !satisfies_constraint_Cs20 (operands[1]))
  15867. + {
  15868. + REAL_VALUE_TYPE r;
  15869. + unsigned long l;
  15870. +
  15871. + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
  15872. + REAL_VALUE_TO_TARGET_SINGLE (r, l);
  15873. +
  15874. + emit_move_insn (operands[0], gen_rtx_HIGH (SFmode, operands[1]));
  15875. +
  15876. + if ((l & 0xFFF) != 0)
  15877. + emit_insn (gen_movsf_lo (operands[0], operands[0], operands[1]));
  15878. + DONE;
  15879. + }
  15880. +})
  15881. +
  15882. +(define_insn "movsf_lo"
  15883. + [(set (match_operand:SF 0 "register_operand" "=r")
  15884. + (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
  15885. + (match_operand:SF 2 "immediate_operand" "i")))]
  15886. + ""
  15887. + "ori\t%0, %1, lo12(%2)"
  15888. + [(set_attr "type" "alu")
  15889. + (set_attr "length" "4")]
  15890. +)
  15891. +
  15892. +(define_insn "*movsf"
  15893. + [(set (match_operand:SF 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m, l, l, l, d, r, f, f, r, f, Q, r, r, r")
  15894. + (match_operand:SF 1 "general_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45, m, f, r, f, Q, f,Cs05,Cs20, Chig"))]
  15895. + "(register_operand(operands[0], SFmode)
  15896. + || register_operand(operands[1], SFmode))"
  15897. +{
  15898. + switch (which_alternative)
  15899. + {
  15900. + case 0:
  15901. + return "mov55\t%0, %1";
  15902. + case 1:
  15903. + return "ori\t%0, %1, 0";
  15904. + case 2:
  15905. + case 3:
  15906. + case 4:
  15907. + case 5:
  15908. + return nds32_output_16bit_store (operands, 4);
  15909. + case 6:
  15910. + return nds32_output_32bit_store (operands, 4);
  15911. + case 7:
  15912. + case 8:
  15913. + case 9:
  15914. + case 10:
  15915. + return nds32_output_16bit_load (operands, 4);
  15916. + case 11:
  15917. + return nds32_output_32bit_load (operands, 4);
  15918. + case 12:
  15919. + if (TARGET_FPU_SINGLE)
  15920. + return "fcpyss\t%0, %1, %1";
  15921. + else
  15922. + return "#";
  15923. + case 13:
  15924. + return "fmtsr\t%1, %0";
  15925. + case 14:
  15926. + return "fmfsr\t%0, %1";
  15927. + case 15:
  15928. + return nds32_output_float_load (operands);
  15929. + case 16:
  15930. + return nds32_output_float_store (operands);
  15931. + case 17:
  15932. + return "movi55\t%0, %1";
  15933. + case 18:
  15934. + return "movi\t%0, %1";
  15935. + case 19:
  15936. + return "sethi\t%0, %1";
  15937. + default:
  15938. + gcc_unreachable ();
  15939. + }
  15940. +}
  15941. + [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,unknown,unknown,unknown,unknown,unknown,alu,alu,alu")
  15942. + (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 4, 4, 4, 4, 4, 4, 2, 4, 4")
  15943. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu, v1, v1, v1")])
  15944. +
  15945. +;; Conditional Move Instructions
  15946. +
  15947. +(define_expand "mov<mode>cc"
  15948. + [(set (match_operand:ANYF 0 "register_operand" "")
  15949. + (if_then_else:ANYF (match_operand 1 "nds32_float_comparison_operator" "")
  15950. + (match_operand:ANYF 2 "register_operand" "")
  15951. + (match_operand:ANYF 3 "register_operand" "")))]
  15952. + ""
  15953. +{
  15954. + if (nds32_cond_move_p (operands[1]))
  15955. + {
  15956. + /* Operands[1] condition code is UNORDERED or ORDERED, and
  15957. + sub-operands[1] MODE isn't SFmode or SFmode, return FAIL
  15958. + for gcc, because we don't using slt compare instruction
  15959. + to generate UNORDERED and ORDERED condition. */
  15960. + FAIL;
  15961. + }
  15962. + else
  15963. + nds32_expand_float_movcc (operands);
  15964. +})
  15965. +
  15966. +(define_insn "fcmov<mode>_eq"
  15967. + [(set (match_operand:ANYF 0 "register_operand" "=f, f")
  15968. + (if_then_else:ANYF (eq (match_operand:SI 1 "register_operand" "f, f")
  15969. + (const_int 0))
  15970. + (match_operand:ANYF 2 "register_operand" "f, 0")
  15971. + (match_operand:ANYF 3 "register_operand" "0, f")))]
  15972. + ""
  15973. + "@
  15974. + fcmovz<size>\t%0,%2,%1
  15975. + fcmovn<size>\t%0,%3,%1"
  15976. + [(set_attr "length" "4, 4")]
  15977. +)
  15978. +
  15979. +(define_insn "fcmov<mode>_ne"
  15980. + [(set (match_operand:ANYF 0 "register_operand" "=f, f")
  15981. + (if_then_else:ANYF (ne (match_operand:SI 1 "register_operand" "f, f")
  15982. + (const_int 0))
  15983. + (match_operand:ANYF 2 "register_operand" "f, 0")
  15984. + (match_operand:ANYF 3 "register_operand" "0, f")))]
  15985. + ""
  15986. + "@
  15987. + fcmovn<size>\t%0,%2,%1
  15988. + fcmovz<size>\t%0,%3,%1"
  15989. + [(set_attr "length" "4, 4")]
  15990. +)
  15991. +
  15992. +;; Arithmetic instructions.
  15993. +
  15994. +(define_insn "add<mode>3"
  15995. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  15996. + (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
  15997. + (match_operand:ANYF 2 "register_operand" "f")))]
  15998. + ""
  15999. + "fadd<size>\t %0, %1, %2"
  16000. + [(set_attr "length" "4")]
  16001. +)
  16002. +
  16003. +(define_insn "sub<mode>3"
  16004. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16005. + (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
  16006. + (match_operand:ANYF 2 "register_operand" "f")))]
  16007. + ""
  16008. + "fsub<size>\t %0, %1, %2"
  16009. + [(set_attr "length" "4")]
  16010. +)
  16011. +
  16012. +;; Multiplication insns.
  16013. +
  16014. +(define_insn "mul<mode>3"
  16015. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16016. + (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
  16017. + (match_operand:ANYF 2 "register_operand" "f")))]
  16018. + ""
  16019. + "fmul<size>\t %0, %1, %2"
  16020. + [(set_attr "length" "4")]
  16021. +)
  16022. +
  16023. +(define_insn "fma<mode>4"
  16024. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16025. + (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
  16026. + (match_operand:ANYF 2 "register_operand" "f")
  16027. + (match_operand:ANYF 3 "register_operand" "0")))]
  16028. + "TARGET_EXT_FPU_FMA"
  16029. + "fmadd<size>\t%0, %1, %2"
  16030. + [(set_attr "length" "4")]
  16031. +)
  16032. +
  16033. +(define_insn "fnma<mode>4"
  16034. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16035. + (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
  16036. + (match_operand:ANYF 2 "register_operand" "f")
  16037. + (match_operand:ANYF 3 "register_operand" "0")))]
  16038. + "TARGET_EXT_FPU_FMA"
  16039. + "fmsub<size>\t%0, %1, %2"
  16040. + [(set_attr "length" "4")]
  16041. +)
  16042. +
  16043. +(define_insn "fms<mode>4"
  16044. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16045. + (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
  16046. + (match_operand:ANYF 2 "register_operand" "f")
  16047. + (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
  16048. + "TARGET_EXT_FPU_FMA"
  16049. + "fnmsub<size>\t%0, %1, %2"
  16050. + [(set_attr "length" "4")]
  16051. +)
  16052. +
  16053. +(define_insn "fnms<mode>4"
  16054. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16055. + (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
  16056. + (match_operand:ANYF 2 "register_operand" "f")
  16057. + (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
  16058. + "TARGET_EXT_FPU_FMA"
  16059. + "fnmadd<size>\t%0, %1, %2"
  16060. + [(set_attr "length" "4")]
  16061. +)
  16062. +
  16063. +;; Div Instructions.
  16064. +
  16065. +(define_insn "div<mode>3"
  16066. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16067. + (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
  16068. + (match_operand:ANYF 2 "register_operand" "f")))]
  16069. + ""
  16070. + "fdiv<size>\t %0, %1, %2"
  16071. + [(set_attr "length" "4")]
  16072. +)
  16073. +
  16074. +(define_insn "sqrt<mode>2"
  16075. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16076. + (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
  16077. + ""
  16078. + "fsqrt<size>\t %0, %1"
  16079. + [(set_attr "length" "4")]
  16080. +)
  16081. +
  16082. +;; Conditional Branch patterns
  16083. +
  16084. +(define_expand "cstore<mode>4"
  16085. + [(set (match_operand:SI 0 "register_operand" "")
  16086. + (match_operator:SI 1 "nds32_float_comparison_operator"
  16087. + [(match_operand:ANYF 2 "register_operand" "")
  16088. + (match_operand:ANYF 3 "register_operand" "")]))]
  16089. + ""
  16090. +{
  16091. + nds32_expand_float_cstore (operands);
  16092. + DONE;
  16093. +})
  16094. +
  16095. +(define_expand "cbranch<mode>4"
  16096. + [(set (pc)
  16097. + (if_then_else (match_operator 0 "nds32_float_comparison_operator"
  16098. + [(match_operand:ANYF 1 "register_operand" "")
  16099. + (match_operand:ANYF 2 "register_operand" "")])
  16100. + (label_ref (match_operand 3 "" ""))
  16101. + (pc)))]
  16102. + ""
  16103. +{
  16104. + nds32_expand_float_cbranch (operands);
  16105. + DONE;
  16106. +})
  16107. +
  16108. +;; Copysign Instructions.
  16109. +
  16110. +(define_insn "copysignsf3"
  16111. + [(set (match_operand:SF 0 "register_operand" "=f")
  16112. + (unspec:SF [(match_operand:SF 1 "register_operand" "f")
  16113. + (match_operand:SF 2 "register_operand" "f")]
  16114. + UNSPEC_COPYSIGN))]
  16115. + "TARGET_FPU_SINGLE"
  16116. + "fcpyss\t%0,%1,%2"
  16117. + [(set_attr "length" "4")]
  16118. +)
  16119. +
  16120. +(define_insn "copysigndf3"
  16121. + [(set (match_operand:DF 0 "register_operand" "=f")
  16122. + (unspec:DF [(match_operand:DF 1 "register_operand" "f")
  16123. + (match_operand:DF 2 "register_operand" "f")]
  16124. + UNSPEC_COPYSIGN))]
  16125. + "TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE"
  16126. + "fcpysd\t%0,%1,%2"
  16127. + [(set_attr "length" "4")]
  16128. +)
  16129. +
  16130. +(define_insn "*ncopysign<mode>3"
  16131. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16132. + (neg:ANYF (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
  16133. + (match_operand:ANYF 2 "register_operand" "f")]
  16134. + UNSPEC_COPYSIGN)))]
  16135. + ""
  16136. + "fcpyns<size>\t%0,%1,%2"
  16137. + [(set_attr "length" "4")]
  16138. +)
  16139. +
  16140. +;; Absolute Instructions
  16141. +
  16142. +(define_insn "abssf2"
  16143. + [(set (match_operand:SF 0 "register_operand" "=f, r")
  16144. + (abs:SF (match_operand:SF 1 "register_operand" "f, r")))]
  16145. + "TARGET_FPU_SINGLE || TARGET_EXT_PERF"
  16146. + "@
  16147. + fabss\t%0, %1
  16148. + bclr\t%0, %1, 31"
  16149. + [(set_attr "length" "4")
  16150. + (set_attr "feature" "fpu,pe1")]
  16151. +)
  16152. +
  16153. +(define_insn "absdf2"
  16154. + [(set (match_operand:DF 0 "register_operand" "=f")
  16155. + (abs:DF (match_operand:DF 1 "register_operand" "f")))]
  16156. + "TARGET_FPU_DOUBLE"
  16157. + "fabsd\t%0, %1"
  16158. + [(set_attr "length" "4")]
  16159. +)
  16160. +
  16161. +;; Negation Instructions
  16162. +
  16163. +(define_insn "*negsf2"
  16164. + [(set (match_operand:SF 0 "register_operand" "=f, r")
  16165. + (neg:SF (match_operand:SF 1 "register_operand" "f, r")))]
  16166. + "TARGET_FPU_SINGLE || TARGET_EXT_PERF"
  16167. + "@
  16168. + fcpynss\t%0, %1, %1
  16169. + btgl\t%0, %1, 31"
  16170. + [(set_attr "length" "4")
  16171. + (set_attr "feature" "fpu,pe1")]
  16172. +)
  16173. +
  16174. +(define_insn "*negdf2"
  16175. + [(set (match_operand:DF 0 "register_operand" "=f")
  16176. + (neg:DF (match_operand:DF 1 "register_operand" "f")))]
  16177. + "TARGET_FPU_DOUBLE"
  16178. + "fcpynsd\t%0, %1, %1"
  16179. + [(set_attr "length" "4")]
  16180. +)
  16181. +
  16182. +;; Data Format Conversion Instructions
  16183. +
  16184. +(define_insn "floatunssi<mode>2"
  16185. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16186. + (unsigned_float:ANYF (match_operand:SI 1 "register_operand" "f")))]
  16187. + ""
  16188. + "fui2<size>\t %0, %1"
  16189. + [(set_attr "length" "4")]
  16190. +)
  16191. +
  16192. +(define_insn "floatsi<mode>2"
  16193. + [(set (match_operand:ANYF 0 "register_operand" "=f")
  16194. + (float:ANYF (match_operand:SI 1 "register_operand" "f")))]
  16195. + ""
  16196. + "fsi2<size>\t %0, %1"
  16197. + [(set_attr "length" "4")]
  16198. +)
  16199. +
  16200. +(define_insn "fixuns_trunc<mode>si2"
  16201. + [(set (match_operand:SI 0 "register_operand" "=f")
  16202. + (unsigned_fix:SI (fix:ANYF (match_operand:ANYF 1 "register_operand" "f"))))]
  16203. + ""
  16204. + "f<size>2ui.z\t %0, %1"
  16205. + [(set_attr "length" "4")]
  16206. +)
  16207. +
  16208. +(define_insn "fix_trunc<mode>si2"
  16209. + [(set (match_operand:SI 0 "register_operand" "=f")
  16210. + (fix:SI (fix:ANYF (match_operand:ANYF 1 "register_operand" "f"))))]
  16211. + ""
  16212. + "f<size>2si.z\t %0, %1"
  16213. + [(set_attr "length" "4")]
  16214. +)
  16215. +
  16216. +(define_insn "extendsfdf2"
  16217. + [(set (match_operand:DF 0 "register_operand" "=f")
  16218. + (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
  16219. + "TARGET_FPU_SINGLE && TARGET_FPU_DOUBLE"
  16220. + "fs2d\t%0, %1"
  16221. + [(set_attr "length" "4")]
  16222. +)
  16223. +
  16224. +(define_insn "truncdfsf2"
  16225. + [(set (match_operand:SF 0 "register_operand" "=f")
  16226. + (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
  16227. + "TARGET_FPU_SINGLE && TARGET_FPU_DOUBLE"
  16228. + "fd2s\t%0, %1"
  16229. + [(set_attr "length" "4")]
  16230. +)
  16231. +
  16232. +;; Compare Instructions
  16233. +
  16234. +(define_insn "cmp<mode>_eq"
  16235. + [(set (match_operand:SI 0 "register_operand" "=f")
  16236. + (eq:SI (match_operand:ANYF 1 "register_operand" "f")
  16237. + (match_operand:ANYF 2 "register_operand" "f")))]
  16238. + ""
  16239. + {
  16240. + if (NDS32_EXT_FPU_DOT_E)
  16241. + return "fcmpeq<size>.e %0, %1, %2";
  16242. + else
  16243. + return "fcmpeq<size>\t%0, %1, %2";
  16244. + }
  16245. + [(set_attr "length" "4")]
  16246. +)
  16247. +
  16248. +(define_insn "cmp<mode>_lt"
  16249. + [(set (match_operand:SI 0 "register_operand" "=f")
  16250. + (lt:SI (match_operand:ANYF 1 "register_operand" "f")
  16251. + (match_operand:ANYF 2 "register_operand" "f")))]
  16252. + ""
  16253. +{
  16254. + if (NDS32_EXT_FPU_DOT_E)
  16255. + return "fcmplt<size>.e %0, %1, %2";
  16256. + else
  16257. + return "fcmplt<size>\t%0, %1, %2";
  16258. +}
  16259. + [(set_attr "length" "4")]
  16260. +)
  16261. +
  16262. +(define_insn "cmp<mode>_le"
  16263. + [(set (match_operand:SI 0 "register_operand" "=f")
  16264. + (le:SI (match_operand:ANYF 1 "register_operand" "f")
  16265. + (match_operand:ANYF 2 "register_operand" "f")))]
  16266. + ""
  16267. +{
  16268. + if (NDS32_EXT_FPU_DOT_E)
  16269. + return "fcmple<size>.e %0, %1, %2";
  16270. + else
  16271. + return "fcmple<size>\t%0, %1, %2";
  16272. +}
  16273. + [(set_attr "length" "4")]
  16274. +)
  16275. +
  16276. +(define_insn "cmp<mode>_un"
  16277. + [(set (match_operand:SI 0 "register_operand" "=f")
  16278. + (unordered:SI (match_operand:ANYF 1 "register_operand" "f")
  16279. + (match_operand:ANYF 2 "register_operand" "f")))]
  16280. + ""
  16281. +{
  16282. + if (NDS32_EXT_FPU_DOT_E)
  16283. + return "fcmpun<size>.e %0, %1, %2";
  16284. + else
  16285. + return "fcmpun<size>\t%0, %1, %2";
  16286. +}
  16287. + [(set_attr "length" "4")]
  16288. +)
  16289. +
  16290. +(define_split
  16291. + [(set (match_operand:SF 0 "register_operand" "")
  16292. + (match_operand:SF 1 "register_operand" ""))]
  16293. + "!TARGET_FPU_SINGLE
  16294. + && NDS32_IS_FPR_REGNUM (REGNO (operands[0]))
  16295. + && NDS32_IS_FPR_REGNUM (REGNO (operands[1]))"
  16296. + [(set (match_dup 2) (match_dup 1))
  16297. + (set (match_dup 0) (match_dup 2))]
  16298. +{
  16299. + operands[2] = gen_rtx_REG (SFmode, TA_REGNUM);
  16300. +})
  16301. +
  16302. +(define_split
  16303. + [(set (match_operand:SF 0 "register_operand" "")
  16304. + (match_operand:SF 1 "const_double_operand" ""))]
  16305. + "!satisfies_constraint_Cs20 (operands[1])
  16306. + && !satisfies_constraint_Chig (operands[1])"
  16307. + [(set (match_dup 0) (high:SF (match_dup 1)))
  16308. + (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
  16309. +;; ----------------------------------------------------------------------------
  16310. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-gcse.c gcc-4.9.4/gcc/config/nds32/nds32-gcse.c
  16311. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-gcse.c 1970-01-01 01:00:00.000000000 +0100
  16312. +++ gcc-4.9.4/gcc/config/nds32/nds32-gcse.c 2016-08-08 20:37:45.502269936 +0200
  16313. @@ -0,0 +1,650 @@
  16314. +/* Global CSE pass of Andes NDS32 cpu for GNU compiler
  16315. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  16316. + Contributed by Andes Technology Corporation.
  16317. +
  16318. + This file is part of GCC.
  16319. +
  16320. + GCC is free software; you can redistribute it and/or modify it
  16321. + under the terms of the GNU General Public License as published
  16322. + by the Free Software Foundation; either version 3, or (at your
  16323. + option) any later version.
  16324. +
  16325. + GCC is distributed in the hope that it will be useful, but WITHOUT
  16326. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16327. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  16328. + License for more details.
  16329. +
  16330. + You should have received a copy of the GNU General Public License
  16331. + along with GCC; see the file COPYING3. If not see
  16332. + <http://www.gnu.org/licenses/>. */
  16333. +
  16334. +/* ------------------------------------------------------------------------ */
  16335. +
  16336. +#include "config.h"
  16337. +#include "system.h"
  16338. +#include "coretypes.h"
  16339. +#include "tm.h"
  16340. +#include "diagnostic-core.h"
  16341. +
  16342. +#include "hash-table.h"
  16343. +#include "rtl.h"
  16344. +#include "tree.h"
  16345. +#include "tm_p.h"
  16346. +#include "regs.h"
  16347. +#include "hard-reg-set.h"
  16348. +#include "flags.h"
  16349. +#include "insn-config.h"
  16350. +#include "recog.h"
  16351. +#include "basic-block.h"
  16352. +#include "function.h"
  16353. +#include "expr.h"
  16354. +#include "except.h"
  16355. +#include "intl.h"
  16356. +#include "obstack.h"
  16357. +#include "hashtab.h"
  16358. +#include "params.h"
  16359. +#include "target.h"
  16360. +#include "tree-pass.h"
  16361. +#include "dbgcnt.h"
  16362. +#include "df.h"
  16363. +
  16364. +/* ------------------------------------------------------------------------ */
  16365. +
  16366. +struct expr
  16367. +{
  16368. + /* The expression. */
  16369. + rtx expr;
  16370. +
  16371. + /* The same hash for this entry. */
  16372. + hashval_t hash;
  16373. +
  16374. + struct occr *antic_occr;
  16375. + /* The number of antic_occr. */
  16376. + unsigned int count;
  16377. +};
  16378. +
  16379. +struct occr
  16380. +{
  16381. + /* Next occurrence of this expression. */
  16382. + struct occr *next;
  16383. + /* The insn that computes the expression. */
  16384. + rtx insn;
  16385. + /* Nonzero if this [anticipatable] occurrence has been deleted. */
  16386. + char deleted_p;
  16387. +};
  16388. +
  16389. +struct reg_avail_info
  16390. +{
  16391. + basic_block last_bb;
  16392. + int first_set;
  16393. + int first_use;
  16394. +};
  16395. +
  16396. +/* Hashtable helpers. */
  16397. +
  16398. +struct expr_hasher : typed_noop_remove <expr>
  16399. +{
  16400. + typedef expr value_type;
  16401. + typedef expr compare_type;
  16402. + static inline hashval_t hash (const value_type *);
  16403. + static inline bool equal (const value_type *, const compare_type *);
  16404. +};
  16405. +
  16406. +/* Callback for hashtab.
  16407. + Return the hash value for expression EXP. We don't actually hash
  16408. + here, we just return the cached hash value. */
  16409. +
  16410. +inline hashval_t
  16411. +expr_hasher::hash (const value_type *exp)
  16412. +{
  16413. + return exp->hash;
  16414. +}
  16415. +
  16416. +/* Callback for hashtab.
  16417. + Return nonzero if exp1 is equivalent to exp2. */
  16418. +
  16419. +inline bool
  16420. +expr_hasher::equal (const value_type *exp1, const compare_type *exp2)
  16421. +{
  16422. + int equiv_p = exp_equiv_p (exp1->expr, exp2->expr, 0, true);
  16423. +
  16424. + gcc_assert (!equiv_p || exp1->hash == exp2->hash);
  16425. + return equiv_p;
  16426. +}
  16427. +
  16428. +static hashval_t
  16429. +hash_expr (rtx x, int *do_not_record_p)
  16430. +{
  16431. + *do_not_record_p = 0;
  16432. + return hash_rtx (x, GET_MODE (x), do_not_record_p,
  16433. + NULL, /*have_reg_qty=*/false);
  16434. +}
  16435. +
  16436. +
  16437. +/* Helpers for memory allocation/freeing. */
  16438. +static void alloc_mem (void);
  16439. +static void free_mem (void);
  16440. +static void compute_hash_table (void);
  16441. +/* Scan the pattern of INSN and add an entry to the hash TABLE.
  16442. + After reload we are interested in loads/stores only. */
  16443. +static void hash_scan_set (rtx);
  16444. +static void insert_expr_in_table (rtx, rtx);
  16445. +static void dump_hash_table (FILE *);
  16446. +
  16447. +static struct obstack expr_obstack;
  16448. +/* The table itself. */
  16449. +static hash_table <expr_hasher> expr_table;
  16450. +static struct reg_avail_info *reg_avail_info;
  16451. +static sbitmap *hoist_vbein;
  16452. +static sbitmap *hoist_vbeout;
  16453. +
  16454. +/* Allocate memory for the CUID mapping array and register/memory
  16455. + tracking tables. */
  16456. +
  16457. +static void
  16458. +alloc_mem (void)
  16459. +{
  16460. + /* Allocate the available expressions hash table. We don't want to
  16461. + make the hash table too small, but unnecessarily making it too large
  16462. + also doesn't help. The i/4 is a gcse.c relic, and seems like a
  16463. + reasonable choice. */
  16464. + expr_table.create (MAX (get_max_insn_count () / 4, 13));
  16465. +
  16466. + /* We allocate everything on obstacks because we often can roll back
  16467. + the whole obstack to some point. Freeing obstacks is very fast. */
  16468. + gcc_obstack_init (&expr_obstack);
  16469. +}
  16470. +
  16471. +/* Free memory allocated by alloc_mem. */
  16472. +
  16473. +static void
  16474. +free_mem (void)
  16475. +{
  16476. + expr_table.dispose ();
  16477. +
  16478. + obstack_free (&expr_obstack, NULL);
  16479. +}
  16480. +
  16481. +
  16482. +/* Dump all expressions and occurrences that are currently in the
  16483. + expression hash table to FILE. */
  16484. +
  16485. +/* This helper is called via htab_traverse. */
  16486. +int
  16487. +nds32_dump_expr_hash_table_entry (expr **slot, FILE *file)
  16488. +{
  16489. + struct expr *exprs = *slot;
  16490. + struct occr *occr;
  16491. +
  16492. + fprintf (file, "expr: ");
  16493. + print_rtl (file, exprs->expr);
  16494. + fprintf (file,"\nhashcode: %u\n", exprs->hash);
  16495. + fprintf (file,"list of occurrences:\n");
  16496. + occr = exprs->antic_occr;
  16497. + while (occr)
  16498. + {
  16499. + rtx insn = occr->insn;
  16500. + print_rtl_single (file, insn);
  16501. + fprintf (file, "\n");
  16502. + occr = occr->next;
  16503. + }
  16504. + fprintf (file, "\n");
  16505. + return 1;
  16506. +}
  16507. +
  16508. +static void
  16509. +dump_hash_table (FILE *file)
  16510. +{
  16511. + fprintf (file, "\n\nexpression hash table\n");
  16512. + fprintf (file, "size %ld, %ld elements, %f collision/search ratio\n",
  16513. + (long) expr_table.size (),
  16514. + (long) expr_table.elements (),
  16515. + expr_table.collisions ());
  16516. + if (expr_table.elements () > 0)
  16517. + {
  16518. + fprintf (file, "\n\ntable entries:\n");
  16519. + expr_table.traverse <FILE *, nds32_dump_expr_hash_table_entry> (file);
  16520. + }
  16521. + fprintf (file, "\n");
  16522. +}
  16523. +
  16524. +/* Insert expression X in INSN in the hash TABLE.
  16525. + If it is already present, record it as the last occurrence in INSN's
  16526. + basic block. */
  16527. +
  16528. +static void
  16529. +insert_expr_in_table (rtx x, rtx insn)
  16530. +{
  16531. + int do_not_record_p;
  16532. + hashval_t hash;
  16533. + struct expr *cur_expr, **slot;
  16534. + struct occr *antic_occr, *last_occr = NULL;
  16535. +
  16536. + hash = hash_expr (x, &do_not_record_p);
  16537. +
  16538. + /* Do not insert expression in the table if it contains volatile operands,
  16539. + or if hash_expr determines the expression is something we don't want
  16540. + to or can't handle. */
  16541. + if (do_not_record_p)
  16542. + return;
  16543. +
  16544. + /* We anticipate that redundant expressions are rare, so for convenience
  16545. + allocate a new hash table element here already and set its fields.
  16546. + If we don't do this, we need a hack with a static struct expr. Anyway,
  16547. + obstack_free is really fast and one more obstack_alloc doesn't hurt if
  16548. + we're going to see more expressions later on. */
  16549. + cur_expr = (struct expr *) obstack_alloc (&expr_obstack,
  16550. + sizeof (struct expr));
  16551. + cur_expr->expr = x;
  16552. + cur_expr->hash = hash;
  16553. + cur_expr->antic_occr = NULL;
  16554. +
  16555. + slot = expr_table.find_slot_with_hash (cur_expr, hash, INSERT);
  16556. +
  16557. + if (! (*slot))
  16558. + /* The expression isn't found, so insert it. */
  16559. + *slot = cur_expr;
  16560. + else
  16561. + {
  16562. + /* The expression is already in the table, so roll back the
  16563. + obstack and use the existing table entry. */
  16564. + obstack_free (&expr_obstack, cur_expr);
  16565. + cur_expr = *slot;
  16566. + }
  16567. +
  16568. + /* Search for another occurrence in the same basic block. */
  16569. + antic_occr = cur_expr->antic_occr;
  16570. + cur_expr->count++;
  16571. + while (antic_occr
  16572. + && BLOCK_FOR_INSN (antic_occr->insn) != BLOCK_FOR_INSN (insn))
  16573. + {
  16574. + /* If an occurrence isn't found, save a pointer to the end of
  16575. + the list. */
  16576. + last_occr = antic_occr;
  16577. + antic_occr = antic_occr->next;
  16578. + }
  16579. +
  16580. + if (antic_occr)
  16581. + /* Found another instance of the expression in the same basic block.
  16582. + Prefer this occurrence to the currently recorded one. We want
  16583. + the last one in the block and the block is scanned from start
  16584. + to end. */
  16585. + antic_occr->insn = insn;
  16586. + else
  16587. + {
  16588. + /* First occurrence of this expression in this basic block. */
  16589. + antic_occr = (struct occr *) obstack_alloc (&expr_obstack,
  16590. + sizeof (struct occr));
  16591. +
  16592. + /* First occurrence of this expression in any block? */
  16593. + if (cur_expr->antic_occr == NULL)
  16594. + cur_expr->antic_occr = antic_occr;
  16595. + else
  16596. + last_occr->next = antic_occr;
  16597. +
  16598. + antic_occr->insn = insn;
  16599. + antic_occr->next = NULL;
  16600. + antic_occr->deleted_p = 0;
  16601. + }
  16602. +}
  16603. +
  16604. +/* Check whether this instruction is supported format. */
  16605. +
  16606. +static void
  16607. +hash_scan_set (rtx insn)
  16608. +{
  16609. + rtx pat = PATTERN (insn);
  16610. + rtx src = SET_SRC (pat);
  16611. + rtx dest = SET_DEST (pat);
  16612. + int regno;
  16613. + struct reg_avail_info *info;
  16614. +
  16615. + /* Don't mess with jumps and nops. */
  16616. + if (JUMP_P (insn) || set_noop_p (pat))
  16617. + return;
  16618. +
  16619. + /* TODO: support more format. */
  16620. +
  16621. + /* Only consider locally anticipatable intructions currently. */
  16622. + if (REG_P (dest) && REGNO (dest) <= SP_REGNUM)
  16623. + {
  16624. + regno = REGNO (dest);
  16625. + info = &reg_avail_info[regno];
  16626. +
  16627. + if (BLOCK_FOR_INSN (insn) == info->last_bb
  16628. + && info->first_set == DF_INSN_LUID (insn)
  16629. + && info->first_use >= info->first_set)
  16630. + {
  16631. + /* Only support immediate input currently because
  16632. + this is bugzilla case. */
  16633. + if (CONST_INT_P (src) || CONST_DOUBLE_P (src))
  16634. + insert_expr_in_table (PATTERN (insn), insn);
  16635. + }
  16636. + }
  16637. +}
  16638. +
  16639. +/* Record register first use information for REGNO in INSN.
  16640. +
  16641. + first_use records the first place in the block where the register
  16642. + is used and is used to compute "anticipatability".
  16643. +
  16644. + last_bb records the block for which first_use is valid,
  16645. + as a quick test to invalidate them. */
  16646. +
  16647. +static void
  16648. +record_first_reg_use_info (rtx insn, int regno)
  16649. +{
  16650. + struct reg_avail_info *info = &reg_avail_info[regno];
  16651. + int luid = DF_INSN_LUID (insn);
  16652. +
  16653. + if (info->last_bb != BLOCK_FOR_INSN (insn))
  16654. + {
  16655. + info->last_bb = BLOCK_FOR_INSN (insn);
  16656. + info->first_use = luid;
  16657. + /* Set the value to record the using is former than setting. */
  16658. + info->first_set = luid + 1;
  16659. + }
  16660. +}
  16661. +
  16662. +/* Called from compute_hash_table via note_stores to handle one
  16663. + SET or CLOBBER in an insn. DATA is really the instruction in which
  16664. + the SET is taking place. */
  16665. +
  16666. +static void
  16667. +record_first_use_info (rtx *dest, void *data)
  16668. +{
  16669. + rtx last_set_insn = (rtx) data;
  16670. + int i, j;
  16671. + enum rtx_code code;
  16672. + const char *fmt;
  16673. + rtx x = *dest;
  16674. +
  16675. + if (x == 0)
  16676. + return;
  16677. +
  16678. + code = GET_CODE (x);
  16679. + if (REG_P (x) && REGNO (x) <= SP_REGNUM)
  16680. + {
  16681. + record_first_reg_use_info (last_set_insn, REGNO (x));
  16682. + /* DF and DI mode may use two registers. */
  16683. + if (GET_MODE_SIZE (GET_MODE (x)) == 8)
  16684. + record_first_reg_use_info (last_set_insn, REGNO (x) + 1);
  16685. + }
  16686. +
  16687. + for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
  16688. + {
  16689. + if (fmt[i] == 'e')
  16690. + record_first_use_info (&XEXP (x, i), data);
  16691. + else if (fmt[i] == 'E')
  16692. + for (j = 0; j < XVECLEN (x, i); j++)
  16693. + record_first_use_info (&XVECEXP (x, i, j), data);
  16694. + }
  16695. +}
  16696. +
  16697. +/* Record register first/block set information for REGNO in INSN.
  16698. +
  16699. + first_set records the first place in the block where the register
  16700. + is set and is used to compute "anticipatability".
  16701. +
  16702. + last_bb records the block for which first_set is valid,
  16703. + as a quick test to invalidate them. */
  16704. +
  16705. +static void
  16706. +record_first_reg_set_info (rtx insn, int regno)
  16707. +{
  16708. + struct reg_avail_info *info = &reg_avail_info[regno];
  16709. + int luid = DF_INSN_LUID (insn);
  16710. +
  16711. + if (info->last_bb != BLOCK_FOR_INSN (insn))
  16712. + {
  16713. + info->last_bb = BLOCK_FOR_INSN (insn);
  16714. + info->first_set = luid;
  16715. + /* Set the value to record the using is later than setting. */
  16716. + info->first_use = luid + 1;
  16717. + }
  16718. +}
  16719. +
  16720. +/* Called from compute_hash_table via note_stores to handle one
  16721. + SET or CLOBBER in an insn. DATA is really the instruction in which
  16722. + the SET is taking place. */
  16723. +
  16724. +static void
  16725. +record_first_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
  16726. +{
  16727. + rtx last_set_insn = (rtx) data;
  16728. +
  16729. + if (GET_CODE (dest) == SUBREG)
  16730. + dest = SUBREG_REG (dest);
  16731. +
  16732. + if (REG_P (dest) && REGNO (dest) <= SP_REGNUM)
  16733. + {
  16734. + record_first_reg_set_info (last_set_insn, REGNO (dest));
  16735. + if (GET_MODE_SIZE (GET_MODE (dest)) == 8)
  16736. + record_first_reg_set_info (last_set_insn, REGNO (dest) + 1);
  16737. + }
  16738. +}
  16739. +
  16740. +/* Build hash table for supported format instructions.
  16741. + Only consider if the instruction is anticipatable in the basic block here.
  16742. + We postpone the def-use check until hoisting. */
  16743. +
  16744. +static void
  16745. +compute_hash_table (void)
  16746. +{
  16747. + basic_block bb;
  16748. + int i;
  16749. +
  16750. + /* We only take care hard registers. */
  16751. + reg_avail_info =
  16752. + (struct reg_avail_info *) xmalloc (sizeof (struct reg_avail_info) *
  16753. + (SP_REGNUM + 1));
  16754. +
  16755. + for (i = 0; i < 32; i++)
  16756. + reg_avail_info[i].last_bb = NULL;
  16757. +
  16758. + FOR_EACH_BB_FN (bb, cfun)
  16759. + {
  16760. + rtx insn;
  16761. +
  16762. + /* Do not hoist instrucion from block which has more
  16763. + than one predecessor. */
  16764. + if (EDGE_COUNT (bb->preds) > 1)
  16765. + continue;
  16766. +
  16767. + FOR_BB_INSNS (bb, insn)
  16768. + {
  16769. + if (!NONDEBUG_INSN_P (insn))
  16770. + continue;
  16771. +
  16772. + /* Construct a caller save register barrier. We cannot hoist the
  16773. + instruction over a function call which sets caller save
  16774. + registers. */
  16775. + if (CALL_P (insn))
  16776. + {
  16777. + for (i = 0; i <= SP_REGNUM; i++)
  16778. + if (call_used_regs[i])
  16779. + record_first_reg_use_info (insn, i);
  16780. + continue;
  16781. + }
  16782. +
  16783. + note_uses (&PATTERN (insn), record_first_use_info, insn);
  16784. + note_stores (PATTERN (insn), record_first_set_info, insn);
  16785. + }
  16786. +
  16787. + /* Build the hash table. */
  16788. + FOR_BB_INSNS (bb, insn)
  16789. + if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SET)
  16790. + hash_scan_set (insn);
  16791. + }
  16792. +}
  16793. +
  16794. +/* Hoist instructions in this slot if possible. */
  16795. +int
  16796. +nds32_find_gcse_expr_table (expr **slot, void *data ATTRIBUTE_UNUSED)
  16797. +{
  16798. + struct expr *exprs = *slot;
  16799. + struct occr *occr;
  16800. + rtx insn;
  16801. + rtx last_insn;
  16802. + basic_block bb;
  16803. + edge e;
  16804. + unsigned ix;
  16805. + unsigned emit_done;
  16806. + unsigned cover;
  16807. + df_ref *use_rec;
  16808. +
  16809. + if (exprs->count < 2)
  16810. + return 1;
  16811. +
  16812. + bitmap_vector_clear (hoist_vbeout, last_basic_block_for_fn (cfun));
  16813. + bitmap_vector_clear (hoist_vbein, last_basic_block_for_fn (cfun));
  16814. +
  16815. + /* Set the bit for this slot. */
  16816. + occr = exprs->antic_occr;
  16817. + while (occr)
  16818. + {
  16819. + insn = occr->insn;
  16820. + bb = BLOCK_FOR_INSN (insn);
  16821. + if (!occr->deleted_p)
  16822. + bitmap_set_bit (hoist_vbein[bb->index], 0);
  16823. + occr = occr->next;
  16824. + }
  16825. +
  16826. + /* Try to hoist code for each basic block. */
  16827. + FOR_EACH_BB_REVERSE_FN (bb, cfun)
  16828. + {
  16829. + if (bb->next_bb != EXIT_BLOCK_PTR_FOR_FN (cfun))
  16830. + bitmap_intersection_of_succs (hoist_vbeout[bb->index], hoist_vbein, bb);
  16831. +
  16832. + if (bitmap_bit_p (hoist_vbeout[bb->index], 0)
  16833. + && EDGE_COUNT (bb->succs) > 1)
  16834. + {
  16835. + emit_done = 0;
  16836. + cover = FALSE;
  16837. + for (e = NULL, ix = 0; ix < EDGE_COUNT (bb->succs); ix++)
  16838. + {
  16839. + e = EDGE_SUCC (bb, ix);
  16840. + if (e->dest == EXIT_BLOCK_PTR_FOR_FN (cfun))
  16841. + continue;
  16842. + occr = exprs->antic_occr;
  16843. + while (occr)
  16844. + {
  16845. + insn = occr->insn;
  16846. + if (!occr->deleted_p && e->dest == BLOCK_FOR_INSN (insn))
  16847. + break;
  16848. + occr = occr->next;
  16849. + }
  16850. +
  16851. + if (!emit_done)
  16852. + {
  16853. + last_insn = BB_END (bb);
  16854. + /* Check the defined register is not used by the last
  16855. + instruction of the previos block.*/
  16856. + for (use_rec = DF_INSN_USES (last_insn); *use_rec; use_rec++)
  16857. + {
  16858. + if (DF_REF_REGNO (*use_rec)
  16859. + == REGNO (SET_DEST (PATTERN (insn))))
  16860. + {
  16861. + cover = TRUE;
  16862. + break;
  16863. + }
  16864. + }
  16865. +
  16866. + /* TODO: support more format. */
  16867. + if (cover)
  16868. + break;
  16869. + else if (JUMP_P (last_insn))
  16870. + {
  16871. + emit_insn_before_noloc (PATTERN (insn), last_insn, bb);
  16872. + emit_done = TRUE;
  16873. + }
  16874. + else
  16875. + break;
  16876. + }
  16877. +
  16878. + if (emit_done)
  16879. + {
  16880. + delete_insn (insn);
  16881. + occr->deleted_p = TRUE;
  16882. + }
  16883. + }
  16884. + }
  16885. + }
  16886. + return 1;
  16887. +}
  16888. +
  16889. +static int
  16890. +hoist_code (void)
  16891. +{
  16892. + hoist_vbein = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), 1);
  16893. + hoist_vbeout = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), 1);
  16894. +
  16895. + expr_table.traverse <void *, nds32_find_gcse_expr_table> (NULL);
  16896. +
  16897. + sbitmap_vector_free (hoist_vbein);
  16898. + sbitmap_vector_free (hoist_vbeout);
  16899. +
  16900. + return 0;
  16901. +}
  16902. +
  16903. +
  16904. +static unsigned int
  16905. +nds32_gcse_opt (void)
  16906. +{
  16907. +
  16908. + if (n_basic_blocks_for_fn (cfun) <= NUM_FIXED_BLOCKS + 1)
  16909. + return 0;
  16910. + /* Allocate memory for this pass.
  16911. + Also computes and initializes the insns' CUIDs. */
  16912. + alloc_mem ();
  16913. +
  16914. + df_chain_add_problem (DF_DU_CHAIN);
  16915. + df_insn_rescan_all ();
  16916. + df_analyze ();
  16917. +
  16918. + compute_hash_table ();
  16919. +
  16920. + if (dump_file)
  16921. + dump_hash_table (dump_file);
  16922. +
  16923. + hoist_code ();
  16924. +
  16925. + df_insn_rescan_all ();
  16926. + free_mem ();
  16927. + return 0;
  16928. +}
  16929. +
  16930. +const pass_data pass_data_nds32_gcse_opt =
  16931. +{
  16932. + RTL_PASS, /* type */
  16933. + "gcse_opt", /* name */
  16934. + OPTGROUP_NONE, /* optinfo_flags */
  16935. + true, /* has_gate */
  16936. + true, /* has_execute */
  16937. + TV_MACH_DEP, /* tv_id */
  16938. + 0, /* properties_required */
  16939. + 0, /* properties_provided */
  16940. + 0, /* properties_destroyed */
  16941. + 0, /* todo_flags_start */
  16942. + (TODO_df_finish | TODO_verify_rtl_sharing), /* todo_flags_finish */
  16943. +};
  16944. +
  16945. +class pass_nds32_gcse_opt : public rtl_opt_pass
  16946. +{
  16947. +public:
  16948. + pass_nds32_gcse_opt (gcc::context *ctxt)
  16949. + : rtl_opt_pass (pass_data_nds32_gcse_opt, ctxt)
  16950. + {}
  16951. +
  16952. + /* opt_pass methods: */
  16953. + bool gate () { return TARGET_GCSE_OPT; }
  16954. + unsigned int execute () { return nds32_gcse_opt (); }
  16955. +};
  16956. +
  16957. +rtl_opt_pass *
  16958. +make_pass_nds32_gcse_opt (gcc::context *ctxt)
  16959. +{
  16960. + return new pass_nds32_gcse_opt (ctxt);
  16961. +}
  16962. +
  16963. +/* ------------------------------------------------------------------------ */
  16964. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32.h gcc-4.9.4/gcc/config/nds32/nds32.h
  16965. --- gcc-4.9.4.orig/gcc/config/nds32/nds32.h 2014-01-02 23:23:26.000000000 +0100
  16966. +++ gcc-4.9.4/gcc/config/nds32/nds32.h 2016-08-08 20:37:45.590273343 +0200
  16967. @@ -1,5 +1,5 @@
  16968. /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
  16969. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  16970. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  16971. Contributed by Andes Technology Corporation.
  16972. This file is part of GCC.
  16973. @@ -24,69 +24,35 @@
  16974. /* The following are auxiliary macros or structure declarations
  16975. that are used all over the nds32.c and nds32.h. */
  16976. -
  16977. -/* Computing the Length of an Insn. */
  16978. #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  16979. (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  16980. -/* Check instruction LS-37-FP-implied form.
  16981. - Note: actually its immediate range is imm9u
  16982. - since it is used for lwi37/swi37 instructions. */
  16983. -#define NDS32_LS_37_FP_P(rt, ra, imm) \
  16984. - (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  16985. - && REGNO (ra) == FP_REGNUM \
  16986. - && satisfies_constraint_Iu09 (imm))
  16987. -
  16988. -/* Check instruction LS-37-SP-implied form.
  16989. - Note: actually its immediate range is imm9u
  16990. - since it is used for lwi37/swi37 instructions. */
  16991. -#define NDS32_LS_37_SP_P(rt, ra, imm) \
  16992. - (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  16993. - && REGNO (ra) == SP_REGNUM \
  16994. - && satisfies_constraint_Iu09 (imm))
  16995. -
  16996. -
  16997. -/* Check load/store instruction form : Rt3, Ra3, imm3u. */
  16998. -#define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  16999. -
  17000. -/* Check load/store instruction form : Rt4, Ra5, const_int_0.
  17001. - Note: no need to check ra because Ra5 means it covers all registers. */
  17002. -#define NDS32_LS_450_P(rt, ra, imm) \
  17003. - ((imm == const0_rtx) \
  17004. - && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17005. - || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  17006. -
  17007. -/* Check instruction RRI-333-form. */
  17008. -#define NDS32_RRI_333_P(rt, ra, imm) \
  17009. - (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17010. - && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  17011. - && satisfies_constraint_Iu03 (imm))
  17012. -
  17013. -/* Check instruction RI-45-form. */
  17014. -#define NDS32_RI_45_P(rt, ra, imm) \
  17015. - (REGNO (rt) == REGNO (ra) \
  17016. - && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17017. - || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  17018. - && satisfies_constraint_Iu05 (imm))
  17019. -
  17020. -
  17021. -/* Check instruction RR-33-form. */
  17022. -#define NDS32_RR_33_P(rt, ra) \
  17023. - (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17024. - && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  17025. -
  17026. -/* Check instruction RRR-333-form. */
  17027. -#define NDS32_RRR_333_P(rt, ra, rb) \
  17028. - (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17029. - && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  17030. - && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  17031. -
  17032. -/* Check instruction RR-45-form.
  17033. - Note: no need to check rb because Rb5 means it covers all registers. */
  17034. -#define NDS32_RR_45_P(rt, ra, rb) \
  17035. - (REGNO (rt) == REGNO (ra) \
  17036. - && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  17037. - || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  17038. +/* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  17039. + It is used in nds32_encode_section_info() to store flag in symbol_ref
  17040. + in case the symbol should be placed in .rodata section.
  17041. + So that we can check it in nds32_legitimate_address_p(). */
  17042. +#define NDS32_SYMBOL_FLAG_RODATA \
  17043. + (SYMBOL_FLAG_MACH_DEP << 0)
  17044. +#define NDS32_SYMBOL_REF_RODATA_P(x) \
  17045. + ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  17046. +
  17047. +enum nds32_relax_insn_type
  17048. +{
  17049. + RELAX_ORI,
  17050. + RELAX_PLT_ADD,
  17051. + RELAX_TLS_ADD_or_LW,
  17052. + RELAX_TLS_ADD_LW,
  17053. + RELAX_TLS_LW_JRAL,
  17054. + RELAX_DONE
  17055. +};
  17056. +
  17057. +/* Classifies expand result for expand helper function. */
  17058. +enum nds32_expand_result_type
  17059. +{
  17060. + EXPAND_DONE,
  17061. + EXPAND_FAIL,
  17062. + EXPAND_CREATE_TEMPLATE
  17063. +};
  17064. /* Classifies address type to distinguish 16-bit/32-bit format. */
  17065. enum nds32_16bit_address_type
  17066. @@ -97,6 +63,10 @@
  17067. ADDRESS_LO_REG_IMM3U,
  17068. /* post_inc [lo_reg + imm3u]: 333 format address. */
  17069. ADDRESS_POST_INC_LO_REG_IMM3U,
  17070. + /* post_modify [lo_reg + imm3u]: 333 format address. */
  17071. + ADDRESS_POST_MODIFY_LO_REG_IMM3U,
  17072. + /* [$r8 + imm7u]: r8 imply address. */
  17073. + ADDRESS_R8_IMM7U,
  17074. /* [$fp + imm7u]: fp imply address. */
  17075. ADDRESS_FP_IMM7U,
  17076. /* [$sp + imm7u]: sp imply address. */
  17077. @@ -105,18 +75,66 @@
  17078. ADDRESS_NOT_16BIT_FORMAT
  17079. };
  17080. -
  17081. /* ------------------------------------------------------------------------ */
  17082. /* Define maximum numbers of registers for passing arguments. */
  17083. -#define NDS32_MAX_REGS_FOR_ARGS 6
  17084. +#define NDS32_MAX_GPR_REGS_FOR_ARGS 6
  17085. +#define NDS32_MAX_FPR_REGS_FOR_ARGS 6
  17086. /* Define the register number for first argument. */
  17087. #define NDS32_GPR_ARG_FIRST_REGNUM 0
  17088. +#define NDS32_FPR_ARG_FIRST_REGNUM 34
  17089. /* Define the register number for return value. */
  17090. #define NDS32_GPR_RET_FIRST_REGNUM 0
  17091. +#define NDS32_FPR_RET_FIRST_REGNUM 34
  17092. +
  17093. +/* Define the first integer register number. */
  17094. +#define NDS32_FIRST_GPR_REGNUM 0
  17095. +/* Define the last integer register number. */
  17096. +#define NDS32_LAST_GPR_REGNUM 31
  17097. +
  17098. +#define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
  17099. +#define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
  17100. + (TARGET_REDUCED_REGS ? 10 : 14)
  17101. +
  17102. +/* Define the floating-point number of registers. */
  17103. +#define NDS32_FLOAT_REGISTER_NUMBER \
  17104. + (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \
  17105. + || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \
  17106. + : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \
  17107. + || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \
  17108. + : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \
  17109. + || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \
  17110. + : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \
  17111. + || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \
  17112. + : 32)
  17113. +
  17114. +#define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
  17115. +
  17116. +/* Define the first floating-point register number. */
  17117. +#define NDS32_FIRST_FPR_REGNUM 34
  17118. +/* Define the last floating-point register number. */
  17119. +#define NDS32_LAST_FPR_REGNUM \
  17120. + (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
  17121. +
  17122. +
  17123. +#define NDS32_IS_EXT_FPR_REGNUM(regno) \
  17124. + (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
  17125. + && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
  17126. +
  17127. +#define NDS32_IS_FPR_REGNUM(regno) \
  17128. + (((regno) >= NDS32_FIRST_FPR_REGNUM) \
  17129. + && ((regno) <= NDS32_LAST_FPR_REGNUM))
  17130. +#define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
  17131. + ((regno) <= NDS32_LAST_FPR_REGNUM)
  17132. +
  17133. +#define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
  17134. + ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
  17135. +
  17136. +#define NDS32_IS_GPR_REGNUM(regno) \
  17137. + (((regno) <= NDS32_LAST_GPR_REGNUM))
  17138. /* Define double word alignment bits. */
  17139. #define NDS32_DOUBLE_WORD_ALIGNMENT 64
  17140. @@ -126,6 +144,16 @@
  17141. #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
  17142. #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
  17143. +/* Determine whether we would like to have code generation strictly aligned.
  17144. + We set it strictly aligned when -malways-align is enabled.
  17145. + Check gcc/common/config/nds32/nds32-common.c for the optimizations that
  17146. + apply -malways-align. */
  17147. +#define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
  17148. +
  17149. +#define NDS32_HW_LOOP_P() (TARGET_HWLOOP && !TARGET_FORCE_NO_HWLOOP)
  17150. +
  17151. +#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP)
  17152. +
  17153. /* Get alignment according to mode or type information.
  17154. When 'type' is nonnull, there is no need to look at 'mode'. */
  17155. #define NDS32_MODE_TYPE_ALIGN(mode, type) \
  17156. @@ -147,26 +175,51 @@
  17157. /* This macro is used to return the register number for passing argument.
  17158. We need to obey the following rules:
  17159. 1. If it is required MORE THAN one register,
  17160. - we need to further check if it really needs to be
  17161. - aligned on double words.
  17162. - a) If double word alignment is necessary,
  17163. - the register number must be even value.
  17164. - b) Otherwise, the register number can be odd or even value.
  17165. + we need to further check if it really needs to be
  17166. + aligned on double words.
  17167. + a) If double word alignment is necessary,
  17168. + the register number must be even value.
  17169. + b) Otherwise, the register number can be odd or even value.
  17170. 2. If it is required ONLY one register,
  17171. - the register number can be odd or even value. */
  17172. -#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
  17173. - ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
  17174. - ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
  17175. - ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
  17176. - : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
  17177. + the register number can be odd or even value. */
  17178. +#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
  17179. + ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
  17180. + ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
  17181. + ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
  17182. + : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
  17183. : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
  17184. -/* This macro is to check if there are still available registers
  17185. - for passing argument. */
  17186. -#define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type) \
  17187. - (((reg_offset) < NDS32_MAX_REGS_FOR_ARGS) \
  17188. - && ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
  17189. - <= NDS32_MAX_REGS_FOR_ARGS))
  17190. +#define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
  17191. + ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
  17192. + ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
  17193. + ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
  17194. + : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
  17195. + : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
  17196. +
  17197. +/* These two macros are to check if there are still available registers
  17198. + for passing argument, which must be entirely in registers. */
  17199. +#define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
  17200. + ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
  17201. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
  17202. + <= (NDS32_GPR_ARG_FIRST_REGNUM \
  17203. + + NDS32_MAX_GPR_REGS_FOR_ARGS))
  17204. +
  17205. +#define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \
  17206. + ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
  17207. + + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
  17208. + <= (NDS32_FPR_ARG_FIRST_REGNUM \
  17209. + + NDS32_MAX_FPR_REGS_FOR_ARGS))
  17210. +
  17211. +/* These two macros are to check if there are still available registers
  17212. + for passing argument, either entirely in registers or partially
  17213. + in registers. */
  17214. +#define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
  17215. + (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
  17216. + < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
  17217. +
  17218. +#define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
  17219. + (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
  17220. + < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
  17221. /* This macro is to check if the register is required to be saved on stack.
  17222. If call_used_regs[regno] == 0, regno is the callee-saved register.
  17223. @@ -176,6 +229,19 @@
  17224. #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
  17225. ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
  17226. +/* This macro is to check if the push25/pop25 are available to be used
  17227. + for code generation. Because pop25 also performs return behavior,
  17228. + the instructions may not be available for some cases.
  17229. + If we want to use push25/pop25, all the following conditions must
  17230. + be satisfied:
  17231. + 1. TARGET_V3PUSH is set.
  17232. + 2. Current function is not an ISR function.
  17233. + 3. Current function is not a variadic function.*/
  17234. +#define NDS32_V3PUSH_AVAILABLE_P \
  17235. + (TARGET_V3PUSH \
  17236. + && !nds32_isr_function_p (current_function_decl) \
  17237. + && (cfun->machine->va_args_size == 0))
  17238. +
  17239. /* ------------------------------------------------------------------------ */
  17240. /* A C structure for machine-specific, per-function data.
  17241. @@ -198,22 +264,44 @@
  17242. /* Number of bytes on the stack for saving $lp. */
  17243. int lp_size;
  17244. - /* Number of bytes on the stack for saving callee-saved registers. */
  17245. - int callee_saved_regs_size;
  17246. + /* Number of bytes on the stack for saving general purpose
  17247. + callee-saved registers. */
  17248. + int callee_saved_gpr_regs_size;
  17249. +
  17250. + /* Number of bytes on the stack for saving floating-point
  17251. + callee-saved registers. */
  17252. + int callee_saved_fpr_regs_size;
  17253. +
  17254. /* The padding bytes in callee-saved area may be required. */
  17255. - int callee_saved_area_padding_bytes;
  17256. + int callee_saved_area_gpr_padding_bytes;
  17257. - /* The first required register that should be saved on stack
  17258. - for va_args (one named argument + nameless arguments). */
  17259. + /* The first required general purpose callee-saved register. */
  17260. + int callee_saved_first_gpr_regno;
  17261. + /* The last required general purpose callee-saved register. */
  17262. + int callee_saved_last_gpr_regno;
  17263. +
  17264. + /* The first required floating-point callee-saved register. */
  17265. + int callee_saved_first_fpr_regno;
  17266. + /* The last required floating-point callee-saved register. */
  17267. + int callee_saved_last_fpr_regno;
  17268. +
  17269. + /* The padding bytes in varargs area may be required. */
  17270. + int va_args_area_padding_bytes;
  17271. + /* The first required register that should be saved on stack for va_args. */
  17272. int va_args_first_regno;
  17273. - /* The last required register that should be saved on stack
  17274. - for va_args (one named argument + nameless arguments). */
  17275. + /* The last required register that should be saved on stack for va_args. */
  17276. int va_args_last_regno;
  17277. - /* The first required callee-saved register. */
  17278. - int callee_saved_regs_first_regno;
  17279. - /* The last required callee-saved register. */
  17280. - int callee_saved_regs_last_regno;
  17281. + /* Number of bytes on the stack for saving exception handling registers. */
  17282. + int eh_return_data_regs_size;
  17283. + /* The first register of passing exception handling information. */
  17284. + int eh_return_data_first_regno;
  17285. + /* The last register of passing exception handling information. */
  17286. + int eh_return_data_last_regno;
  17287. +
  17288. + /* Indicate that whether this function
  17289. + calls __builtin_eh_return. */
  17290. + int use_eh_return_p;
  17291. /* Indicate that whether this function needs
  17292. prologue/epilogue code generation. */
  17293. @@ -221,12 +309,27 @@
  17294. /* Indicate that whether this function
  17295. uses fp_as_gp optimization. */
  17296. int fp_as_gp_p;
  17297. + /* Indicate that whether this function is under strictly aligned
  17298. + situation for legitimate address checking. This flag informs
  17299. + nds32_legitimate_address_p() how to treat offset alignment:
  17300. + 1. The IVOPT phase needs to detect available range for memory access,
  17301. + such as checking [base + 32767] ~ [base + (-32768)].
  17302. + For this case we do not want address to be strictly aligned.
  17303. + 2. The rtl lowering and optimization are close to target code.
  17304. + For this case we need address to be strictly aligned. */
  17305. + int strict_aligned_p;
  17306. +
  17307. + /* Record two similar attributes status. */
  17308. + int attr_naked_p;
  17309. + int attr_no_prologue_p;
  17310. +
  17311. };
  17312. /* A C structure that contains the arguments information. */
  17313. typedef struct
  17314. {
  17315. - unsigned int reg_offset;
  17316. + unsigned int gpr_offset;
  17317. + unsigned int fpr_offset;
  17318. } nds32_cumulative_args;
  17319. /* ------------------------------------------------------------------------ */
  17320. @@ -265,7 +368,8 @@
  17321. {
  17322. NDS32_NESTED,
  17323. NDS32_NOT_NESTED,
  17324. - NDS32_NESTED_READY
  17325. + NDS32_NESTED_READY,
  17326. + NDS32_CRITICAL
  17327. };
  17328. /* Define structure to record isr information.
  17329. @@ -317,106 +421,615 @@
  17330. {
  17331. NDS32_BUILTIN_ISYNC,
  17332. NDS32_BUILTIN_ISB,
  17333. + NDS32_BUILTIN_DSB,
  17334. + NDS32_BUILTIN_MSYNC_ALL,
  17335. + NDS32_BUILTIN_MSYNC_STORE,
  17336. NDS32_BUILTIN_MFSR,
  17337. NDS32_BUILTIN_MFUSR,
  17338. NDS32_BUILTIN_MTSR,
  17339. + NDS32_BUILTIN_MTSR_ISB,
  17340. + NDS32_BUILTIN_MTSR_DSB,
  17341. NDS32_BUILTIN_MTUSR,
  17342. NDS32_BUILTIN_SETGIE_EN,
  17343. - NDS32_BUILTIN_SETGIE_DIS
  17344. + NDS32_BUILTIN_SETGIE_DIS,
  17345. + NDS32_BUILTIN_FMFCFG,
  17346. + NDS32_BUILTIN_FMFCSR,
  17347. + NDS32_BUILTIN_FMTCSR,
  17348. + NDS32_BUILTIN_FCPYNSS,
  17349. + NDS32_BUILTIN_FCPYSS,
  17350. + NDS32_BUILTIN_FCPYNSD,
  17351. + NDS32_BUILTIN_FCPYSD,
  17352. + NDS32_BUILTIN_FABSS,
  17353. + NDS32_BUILTIN_FABSD,
  17354. + NDS32_BUILTIN_FSQRTS,
  17355. + NDS32_BUILTIN_FSQRTD,
  17356. + NDS32_BUILTIN_ABS,
  17357. + NDS32_BUILTIN_AVE,
  17358. + NDS32_BUILTIN_BCLR,
  17359. + NDS32_BUILTIN_BSET,
  17360. + NDS32_BUILTIN_BTGL,
  17361. + NDS32_BUILTIN_BTST,
  17362. + NDS32_BUILTIN_CLIP,
  17363. + NDS32_BUILTIN_CLIPS,
  17364. + NDS32_BUILTIN_CLZ,
  17365. + NDS32_BUILTIN_CLO,
  17366. + NDS32_BUILTIN_MAX,
  17367. + NDS32_BUILTIN_MIN,
  17368. + NDS32_BUILTIN_PBSAD,
  17369. + NDS32_BUILTIN_PBSADA,
  17370. + NDS32_BUILTIN_BSE,
  17371. + NDS32_BUILTIN_BSP,
  17372. + NDS32_BUILTIN_FFB,
  17373. + NDS32_BUILTIN_FFMISM,
  17374. + NDS32_BUILTIN_FLMISM,
  17375. + NDS32_BUILTIN_KADDW,
  17376. + NDS32_BUILTIN_KSUBW,
  17377. + NDS32_BUILTIN_KADDH,
  17378. + NDS32_BUILTIN_KSUBH,
  17379. + NDS32_BUILTIN_KDMBB,
  17380. + NDS32_BUILTIN_V_KDMBB,
  17381. + NDS32_BUILTIN_KDMBT,
  17382. + NDS32_BUILTIN_V_KDMBT,
  17383. + NDS32_BUILTIN_KDMTB,
  17384. + NDS32_BUILTIN_V_KDMTB,
  17385. + NDS32_BUILTIN_KDMTT,
  17386. + NDS32_BUILTIN_V_KDMTT,
  17387. + NDS32_BUILTIN_KHMBB,
  17388. + NDS32_BUILTIN_V_KHMBB,
  17389. + NDS32_BUILTIN_KHMBT,
  17390. + NDS32_BUILTIN_V_KHMBT,
  17391. + NDS32_BUILTIN_KHMTB,
  17392. + NDS32_BUILTIN_V_KHMTB,
  17393. + NDS32_BUILTIN_KHMTT,
  17394. + NDS32_BUILTIN_V_KHMTT,
  17395. + NDS32_BUILTIN_KSLRAW,
  17396. + NDS32_BUILTIN_KSLRAW_U,
  17397. + NDS32_BUILTIN_RDOV,
  17398. + NDS32_BUILTIN_CLROV,
  17399. + NDS32_BUILTIN_ROTR,
  17400. + NDS32_BUILTIN_SVA,
  17401. + NDS32_BUILTIN_SVS,
  17402. + NDS32_BUILTIN_WSBH,
  17403. + NDS32_BUILTIN_JR_ITOFF,
  17404. + NDS32_BUILTIN_JR_TOFF,
  17405. + NDS32_BUILTIN_JRAL_ITON,
  17406. + NDS32_BUILTIN_JRAL_TON,
  17407. + NDS32_BUILTIN_RET_ITOFF,
  17408. + NDS32_BUILTIN_RET_TOFF,
  17409. + NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
  17410. + NDS32_BUILTIN_STANDBY_WAKE_GRANT,
  17411. + NDS32_BUILTIN_STANDBY_WAKE_DONE,
  17412. + NDS32_BUILTIN_TEQZ,
  17413. + NDS32_BUILTIN_TNEZ,
  17414. + NDS32_BUILTIN_TRAP,
  17415. + NDS32_BUILTIN_SETEND_BIG,
  17416. + NDS32_BUILTIN_SETEND_LITTLE,
  17417. + NDS32_BUILTIN_SYSCALL,
  17418. + NDS32_BUILTIN_BREAK,
  17419. + NDS32_BUILTIN_NOP,
  17420. + NDS32_BUILTIN_SCHE_BARRIER,
  17421. + NDS32_BUILTIN_GET_CURRENT_SP,
  17422. + NDS32_BUILTIN_SET_CURRENT_SP,
  17423. + NDS32_BUILTIN_RETURN_ADDRESS,
  17424. + NDS32_BUILTIN_LLW,
  17425. + NDS32_BUILTIN_LWUP,
  17426. + NDS32_BUILTIN_LBUP,
  17427. + NDS32_BUILTIN_SCW,
  17428. + NDS32_BUILTIN_SWUP,
  17429. + NDS32_BUILTIN_SBUP,
  17430. + NDS32_BUILTIN_CCTL_VA_LCK,
  17431. + NDS32_BUILTIN_CCTL_IDX_WBINVAL,
  17432. + NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
  17433. + NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
  17434. + NDS32_BUILTIN_CCTL_IDX_READ,
  17435. + NDS32_BUILTIN_CCTL_IDX_WRITE,
  17436. + NDS32_BUILTIN_CCTL_L1D_INVALALL,
  17437. + NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
  17438. + NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
  17439. + NDS32_BUILTIN_DPREF_QW,
  17440. + NDS32_BUILTIN_DPREF_HW,
  17441. + NDS32_BUILTIN_DPREF_W,
  17442. + NDS32_BUILTIN_DPREF_DW,
  17443. + NDS32_BUILTIN_TLBOP_TRD,
  17444. + NDS32_BUILTIN_TLBOP_TWR,
  17445. + NDS32_BUILTIN_TLBOP_RWR,
  17446. + NDS32_BUILTIN_TLBOP_RWLK,
  17447. + NDS32_BUILTIN_TLBOP_UNLK,
  17448. + NDS32_BUILTIN_TLBOP_PB,
  17449. + NDS32_BUILTIN_TLBOP_INV,
  17450. + NDS32_BUILTIN_TLBOP_FLUA,
  17451. + NDS32_BUILTIN_UALOAD_HW,
  17452. + NDS32_BUILTIN_UALOAD_W,
  17453. + NDS32_BUILTIN_UALOAD_DW,
  17454. + NDS32_BUILTIN_UASTORE_HW,
  17455. + NDS32_BUILTIN_UASTORE_W,
  17456. + NDS32_BUILTIN_UASTORE_DW,
  17457. + NDS32_BUILTIN_GIE_DIS,
  17458. + NDS32_BUILTIN_GIE_EN,
  17459. + NDS32_BUILTIN_ENABLE_INT,
  17460. + NDS32_BUILTIN_DISABLE_INT,
  17461. + NDS32_BUILTIN_SET_PENDING_SWINT,
  17462. + NDS32_BUILTIN_CLR_PENDING_SWINT,
  17463. + NDS32_BUILTIN_CLR_PENDING_HWINT,
  17464. + NDS32_BUILTIN_GET_ALL_PENDING_INT,
  17465. + NDS32_BUILTIN_GET_PENDING_INT,
  17466. + NDS32_BUILTIN_SET_INT_PRIORITY,
  17467. + NDS32_BUILTIN_GET_INT_PRIORITY,
  17468. + NDS32_BUILTIN_SET_TRIG_LEVEL,
  17469. + NDS32_BUILTIN_SET_TRIG_EDGE,
  17470. + NDS32_BUILTIN_GET_TRIG_TYPE,
  17471. + NDS32_BUILTIN_SIGNATURE_BEGIN,
  17472. + NDS32_BUILTIN_SIGNATURE_END,
  17473. + NDS32_BUILTIN_DSP_BEGIN,
  17474. + NDS32_BUILTIN_ADD16,
  17475. + NDS32_BUILTIN_V_UADD16,
  17476. + NDS32_BUILTIN_V_SADD16,
  17477. + NDS32_BUILTIN_RADD16,
  17478. + NDS32_BUILTIN_V_RADD16,
  17479. + NDS32_BUILTIN_URADD16,
  17480. + NDS32_BUILTIN_V_URADD16,
  17481. + NDS32_BUILTIN_KADD16,
  17482. + NDS32_BUILTIN_V_KADD16,
  17483. + NDS32_BUILTIN_UKADD16,
  17484. + NDS32_BUILTIN_V_UKADD16,
  17485. + NDS32_BUILTIN_SUB16,
  17486. + NDS32_BUILTIN_V_USUB16,
  17487. + NDS32_BUILTIN_V_SSUB16,
  17488. + NDS32_BUILTIN_RSUB16,
  17489. + NDS32_BUILTIN_V_RSUB16,
  17490. + NDS32_BUILTIN_URSUB16,
  17491. + NDS32_BUILTIN_V_URSUB16,
  17492. + NDS32_BUILTIN_KSUB16,
  17493. + NDS32_BUILTIN_V_KSUB16,
  17494. + NDS32_BUILTIN_UKSUB16,
  17495. + NDS32_BUILTIN_V_UKSUB16,
  17496. + NDS32_BUILTIN_CRAS16,
  17497. + NDS32_BUILTIN_V_UCRAS16,
  17498. + NDS32_BUILTIN_V_SCRAS16,
  17499. + NDS32_BUILTIN_RCRAS16,
  17500. + NDS32_BUILTIN_V_RCRAS16,
  17501. + NDS32_BUILTIN_URCRAS16,
  17502. + NDS32_BUILTIN_V_URCRAS16,
  17503. + NDS32_BUILTIN_KCRAS16,
  17504. + NDS32_BUILTIN_V_KCRAS16,
  17505. + NDS32_BUILTIN_UKCRAS16,
  17506. + NDS32_BUILTIN_V_UKCRAS16,
  17507. + NDS32_BUILTIN_CRSA16,
  17508. + NDS32_BUILTIN_V_UCRSA16,
  17509. + NDS32_BUILTIN_V_SCRSA16,
  17510. + NDS32_BUILTIN_RCRSA16,
  17511. + NDS32_BUILTIN_V_RCRSA16,
  17512. + NDS32_BUILTIN_URCRSA16,
  17513. + NDS32_BUILTIN_V_URCRSA16,
  17514. + NDS32_BUILTIN_KCRSA16,
  17515. + NDS32_BUILTIN_V_KCRSA16,
  17516. + NDS32_BUILTIN_UKCRSA16,
  17517. + NDS32_BUILTIN_V_UKCRSA16,
  17518. + NDS32_BUILTIN_ADD8,
  17519. + NDS32_BUILTIN_V_UADD8,
  17520. + NDS32_BUILTIN_V_SADD8,
  17521. + NDS32_BUILTIN_RADD8,
  17522. + NDS32_BUILTIN_V_RADD8,
  17523. + NDS32_BUILTIN_URADD8,
  17524. + NDS32_BUILTIN_V_URADD8,
  17525. + NDS32_BUILTIN_KADD8,
  17526. + NDS32_BUILTIN_V_KADD8,
  17527. + NDS32_BUILTIN_UKADD8,
  17528. + NDS32_BUILTIN_V_UKADD8,
  17529. + NDS32_BUILTIN_SUB8,
  17530. + NDS32_BUILTIN_V_USUB8,
  17531. + NDS32_BUILTIN_V_SSUB8,
  17532. + NDS32_BUILTIN_RSUB8,
  17533. + NDS32_BUILTIN_V_RSUB8,
  17534. + NDS32_BUILTIN_URSUB8,
  17535. + NDS32_BUILTIN_V_URSUB8,
  17536. + NDS32_BUILTIN_KSUB8,
  17537. + NDS32_BUILTIN_V_KSUB8,
  17538. + NDS32_BUILTIN_UKSUB8,
  17539. + NDS32_BUILTIN_V_UKSUB8,
  17540. + NDS32_BUILTIN_SRA16,
  17541. + NDS32_BUILTIN_V_SRA16,
  17542. + NDS32_BUILTIN_SRA16_U,
  17543. + NDS32_BUILTIN_V_SRA16_U,
  17544. + NDS32_BUILTIN_SRL16,
  17545. + NDS32_BUILTIN_V_SRL16,
  17546. + NDS32_BUILTIN_SRL16_U,
  17547. + NDS32_BUILTIN_V_SRL16_U,
  17548. + NDS32_BUILTIN_SLL16,
  17549. + NDS32_BUILTIN_V_SLL16,
  17550. + NDS32_BUILTIN_KSLL16,
  17551. + NDS32_BUILTIN_V_KSLL16,
  17552. + NDS32_BUILTIN_KSLRA16,
  17553. + NDS32_BUILTIN_V_KSLRA16,
  17554. + NDS32_BUILTIN_KSLRA16_U,
  17555. + NDS32_BUILTIN_V_KSLRA16_U,
  17556. + NDS32_BUILTIN_CMPEQ16,
  17557. + NDS32_BUILTIN_V_SCMPEQ16,
  17558. + NDS32_BUILTIN_V_UCMPEQ16,
  17559. + NDS32_BUILTIN_SCMPLT16,
  17560. + NDS32_BUILTIN_V_SCMPLT16,
  17561. + NDS32_BUILTIN_SCMPLE16,
  17562. + NDS32_BUILTIN_V_SCMPLE16,
  17563. + NDS32_BUILTIN_UCMPLT16,
  17564. + NDS32_BUILTIN_V_UCMPLT16,
  17565. + NDS32_BUILTIN_UCMPLE16,
  17566. + NDS32_BUILTIN_V_UCMPLE16,
  17567. + NDS32_BUILTIN_CMPEQ8,
  17568. + NDS32_BUILTIN_V_SCMPEQ8,
  17569. + NDS32_BUILTIN_V_UCMPEQ8,
  17570. + NDS32_BUILTIN_SCMPLT8,
  17571. + NDS32_BUILTIN_V_SCMPLT8,
  17572. + NDS32_BUILTIN_SCMPLE8,
  17573. + NDS32_BUILTIN_V_SCMPLE8,
  17574. + NDS32_BUILTIN_UCMPLT8,
  17575. + NDS32_BUILTIN_V_UCMPLT8,
  17576. + NDS32_BUILTIN_UCMPLE8,
  17577. + NDS32_BUILTIN_V_UCMPLE8,
  17578. + NDS32_BUILTIN_SMIN16,
  17579. + NDS32_BUILTIN_V_SMIN16,
  17580. + NDS32_BUILTIN_UMIN16,
  17581. + NDS32_BUILTIN_V_UMIN16,
  17582. + NDS32_BUILTIN_SMAX16,
  17583. + NDS32_BUILTIN_V_SMAX16,
  17584. + NDS32_BUILTIN_UMAX16,
  17585. + NDS32_BUILTIN_V_UMAX16,
  17586. + NDS32_BUILTIN_SCLIP16,
  17587. + NDS32_BUILTIN_V_SCLIP16,
  17588. + NDS32_BUILTIN_UCLIP16,
  17589. + NDS32_BUILTIN_V_UCLIP16,
  17590. + NDS32_BUILTIN_KHM16,
  17591. + NDS32_BUILTIN_V_KHM16,
  17592. + NDS32_BUILTIN_KHMX16,
  17593. + NDS32_BUILTIN_V_KHMX16,
  17594. + NDS32_BUILTIN_KABS16,
  17595. + NDS32_BUILTIN_V_KABS16,
  17596. + NDS32_BUILTIN_SMIN8,
  17597. + NDS32_BUILTIN_V_SMIN8,
  17598. + NDS32_BUILTIN_UMIN8,
  17599. + NDS32_BUILTIN_V_UMIN8,
  17600. + NDS32_BUILTIN_SMAX8,
  17601. + NDS32_BUILTIN_V_SMAX8,
  17602. + NDS32_BUILTIN_UMAX8,
  17603. + NDS32_BUILTIN_V_UMAX8,
  17604. + NDS32_BUILTIN_KABS8,
  17605. + NDS32_BUILTIN_V_KABS8,
  17606. + NDS32_BUILTIN_SUNPKD810,
  17607. + NDS32_BUILTIN_V_SUNPKD810,
  17608. + NDS32_BUILTIN_SUNPKD820,
  17609. + NDS32_BUILTIN_V_SUNPKD820,
  17610. + NDS32_BUILTIN_SUNPKD830,
  17611. + NDS32_BUILTIN_V_SUNPKD830,
  17612. + NDS32_BUILTIN_SUNPKD831,
  17613. + NDS32_BUILTIN_V_SUNPKD831,
  17614. + NDS32_BUILTIN_ZUNPKD810,
  17615. + NDS32_BUILTIN_V_ZUNPKD810,
  17616. + NDS32_BUILTIN_ZUNPKD820,
  17617. + NDS32_BUILTIN_V_ZUNPKD820,
  17618. + NDS32_BUILTIN_ZUNPKD830,
  17619. + NDS32_BUILTIN_V_ZUNPKD830,
  17620. + NDS32_BUILTIN_ZUNPKD831,
  17621. + NDS32_BUILTIN_V_ZUNPKD831,
  17622. + NDS32_BUILTIN_RADDW,
  17623. + NDS32_BUILTIN_URADDW,
  17624. + NDS32_BUILTIN_RSUBW,
  17625. + NDS32_BUILTIN_URSUBW,
  17626. + NDS32_BUILTIN_SRA_U,
  17627. + NDS32_BUILTIN_KSLL,
  17628. + NDS32_BUILTIN_PKBB16,
  17629. + NDS32_BUILTIN_V_PKBB16,
  17630. + NDS32_BUILTIN_PKBT16,
  17631. + NDS32_BUILTIN_V_PKBT16,
  17632. + NDS32_BUILTIN_PKTB16,
  17633. + NDS32_BUILTIN_V_PKTB16,
  17634. + NDS32_BUILTIN_PKTT16,
  17635. + NDS32_BUILTIN_V_PKTT16,
  17636. + NDS32_BUILTIN_SMMUL,
  17637. + NDS32_BUILTIN_SMMUL_U,
  17638. + NDS32_BUILTIN_KMMAC,
  17639. + NDS32_BUILTIN_KMMAC_U,
  17640. + NDS32_BUILTIN_KMMSB,
  17641. + NDS32_BUILTIN_KMMSB_U,
  17642. + NDS32_BUILTIN_KWMMUL,
  17643. + NDS32_BUILTIN_KWMMUL_U,
  17644. + NDS32_BUILTIN_SMMWB,
  17645. + NDS32_BUILTIN_V_SMMWB,
  17646. + NDS32_BUILTIN_SMMWB_U,
  17647. + NDS32_BUILTIN_V_SMMWB_U,
  17648. + NDS32_BUILTIN_SMMWT,
  17649. + NDS32_BUILTIN_V_SMMWT,
  17650. + NDS32_BUILTIN_SMMWT_U,
  17651. + NDS32_BUILTIN_V_SMMWT_U,
  17652. + NDS32_BUILTIN_KMMAWB,
  17653. + NDS32_BUILTIN_V_KMMAWB,
  17654. + NDS32_BUILTIN_KMMAWB_U,
  17655. + NDS32_BUILTIN_V_KMMAWB_U,
  17656. + NDS32_BUILTIN_KMMAWT,
  17657. + NDS32_BUILTIN_V_KMMAWT,
  17658. + NDS32_BUILTIN_KMMAWT_U,
  17659. + NDS32_BUILTIN_V_KMMAWT_U,
  17660. + NDS32_BUILTIN_SMBB,
  17661. + NDS32_BUILTIN_V_SMBB,
  17662. + NDS32_BUILTIN_SMBT,
  17663. + NDS32_BUILTIN_V_SMBT,
  17664. + NDS32_BUILTIN_SMTT,
  17665. + NDS32_BUILTIN_V_SMTT,
  17666. + NDS32_BUILTIN_KMDA,
  17667. + NDS32_BUILTIN_V_KMDA,
  17668. + NDS32_BUILTIN_KMXDA,
  17669. + NDS32_BUILTIN_V_KMXDA,
  17670. + NDS32_BUILTIN_SMDS,
  17671. + NDS32_BUILTIN_V_SMDS,
  17672. + NDS32_BUILTIN_SMDRS,
  17673. + NDS32_BUILTIN_V_SMDRS,
  17674. + NDS32_BUILTIN_SMXDS,
  17675. + NDS32_BUILTIN_V_SMXDS,
  17676. + NDS32_BUILTIN_KMABB,
  17677. + NDS32_BUILTIN_V_KMABB,
  17678. + NDS32_BUILTIN_KMABT,
  17679. + NDS32_BUILTIN_V_KMABT,
  17680. + NDS32_BUILTIN_KMATT,
  17681. + NDS32_BUILTIN_V_KMATT,
  17682. + NDS32_BUILTIN_KMADA,
  17683. + NDS32_BUILTIN_V_KMADA,
  17684. + NDS32_BUILTIN_KMAXDA,
  17685. + NDS32_BUILTIN_V_KMAXDA,
  17686. + NDS32_BUILTIN_KMADS,
  17687. + NDS32_BUILTIN_V_KMADS,
  17688. + NDS32_BUILTIN_KMADRS,
  17689. + NDS32_BUILTIN_V_KMADRS,
  17690. + NDS32_BUILTIN_KMAXDS,
  17691. + NDS32_BUILTIN_V_KMAXDS,
  17692. + NDS32_BUILTIN_KMSDA,
  17693. + NDS32_BUILTIN_V_KMSDA,
  17694. + NDS32_BUILTIN_KMSXDA,
  17695. + NDS32_BUILTIN_V_KMSXDA,
  17696. + NDS32_BUILTIN_SMAL,
  17697. + NDS32_BUILTIN_V_SMAL,
  17698. + NDS32_BUILTIN_BITREV,
  17699. + NDS32_BUILTIN_WEXT,
  17700. + NDS32_BUILTIN_BPICK,
  17701. + NDS32_BUILTIN_INSB,
  17702. + NDS32_BUILTIN_SADD64,
  17703. + NDS32_BUILTIN_UADD64,
  17704. + NDS32_BUILTIN_RADD64,
  17705. + NDS32_BUILTIN_URADD64,
  17706. + NDS32_BUILTIN_KADD64,
  17707. + NDS32_BUILTIN_UKADD64,
  17708. + NDS32_BUILTIN_SSUB64,
  17709. + NDS32_BUILTIN_USUB64,
  17710. + NDS32_BUILTIN_RSUB64,
  17711. + NDS32_BUILTIN_URSUB64,
  17712. + NDS32_BUILTIN_KSUB64,
  17713. + NDS32_BUILTIN_UKSUB64,
  17714. + NDS32_BUILTIN_SMAR64,
  17715. + NDS32_BUILTIN_SMSR64,
  17716. + NDS32_BUILTIN_UMAR64,
  17717. + NDS32_BUILTIN_UMSR64,
  17718. + NDS32_BUILTIN_KMAR64,
  17719. + NDS32_BUILTIN_KMSR64,
  17720. + NDS32_BUILTIN_UKMAR64,
  17721. + NDS32_BUILTIN_UKMSR64,
  17722. + NDS32_BUILTIN_SMALBB,
  17723. + NDS32_BUILTIN_V_SMALBB,
  17724. + NDS32_BUILTIN_SMALBT,
  17725. + NDS32_BUILTIN_V_SMALBT,
  17726. + NDS32_BUILTIN_SMALTT,
  17727. + NDS32_BUILTIN_V_SMALTT,
  17728. + NDS32_BUILTIN_SMALDA,
  17729. + NDS32_BUILTIN_V_SMALDA,
  17730. + NDS32_BUILTIN_SMALXDA,
  17731. + NDS32_BUILTIN_V_SMALXDA,
  17732. + NDS32_BUILTIN_SMALDS,
  17733. + NDS32_BUILTIN_V_SMALDS,
  17734. + NDS32_BUILTIN_SMALDRS,
  17735. + NDS32_BUILTIN_V_SMALDRS,
  17736. + NDS32_BUILTIN_SMALXDS,
  17737. + NDS32_BUILTIN_V_SMALXDS,
  17738. + NDS32_BUILTIN_SMUL16,
  17739. + NDS32_BUILTIN_V_SMUL16,
  17740. + NDS32_BUILTIN_SMULX16,
  17741. + NDS32_BUILTIN_V_SMULX16,
  17742. + NDS32_BUILTIN_UMUL16,
  17743. + NDS32_BUILTIN_V_UMUL16,
  17744. + NDS32_BUILTIN_UMULX16,
  17745. + NDS32_BUILTIN_V_UMULX16,
  17746. + NDS32_BUILTIN_SMSLDA,
  17747. + NDS32_BUILTIN_V_SMSLDA,
  17748. + NDS32_BUILTIN_SMSLXDA,
  17749. + NDS32_BUILTIN_V_SMSLXDA,
  17750. + NDS32_BUILTIN_UCLIP32,
  17751. + NDS32_BUILTIN_SCLIP32,
  17752. + NDS32_BUILTIN_KABS,
  17753. + NDS32_BUILTIN_DSP_END,
  17754. + NDS32_BUILTIN_NO_HWLOOP,
  17755. + NDS32_BUILTIN_UNALIGNED_FEATURE,
  17756. + NDS32_BUILTIN_ENABLE_UNALIGNED,
  17757. + NDS32_BUILTIN_DISABLE_UNALIGNED,
  17758. + NDS32_BUILTIN_COUNT
  17759. };
  17760. /* ------------------------------------------------------------------------ */
  17761. -#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
  17762. -#define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3)
  17763. -#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
  17764. +#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
  17765. + (nds32_isr_vector_size == 4)
  17766. +
  17767. +#define TARGET_ISA_V2 \
  17768. + (nds32_arch_option == ARCH_V2 || nds32_arch_option == ARCH_V2J)
  17769. +#define TARGET_ISA_V3 \
  17770. + (nds32_arch_option == ARCH_V3 \
  17771. + || nds32_arch_option == ARCH_V3J \
  17772. + || nds32_arch_option == ARCH_V3F \
  17773. + || nds32_arch_option == ARCH_V3S)
  17774. +#define TARGET_ISA_V3M \
  17775. + (nds32_arch_option == ARCH_V3M)
  17776. +
  17777. +#define TARGET_PIPELINE_N8 \
  17778. + (nds32_cpu_option == CPU_N7 || nds32_cpu_option == CPU_N8)
  17779. +#define TARGET_PIPELINE_N10 \
  17780. + (nds32_cpu_option == CPU_N9 || nds32_cpu_option == CPU_N10)
  17781. +#define TARGET_PIPELINE_N12 \
  17782. + (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13)
  17783. +#define TARGET_PIPELINE_SIMPLE \
  17784. + (nds32_cpu_option == CPU_SIMPLE)
  17785. +
  17786. +#define TARGET_CMODEL_SMALL \
  17787. + (nds32_cmodel_option == CMODEL_SMALL)
  17788. +#define TARGET_CMODEL_MEDIUM \
  17789. + (nds32_cmodel_option == CMODEL_MEDIUM)
  17790. +#define TARGET_CMODEL_LARGE \
  17791. + (nds32_cmodel_option == CMODEL_LARGE)
  17792. +
  17793. +/* When -mcmodel=small or -mcmodel=medium,
  17794. + compiler may generate gp-base instruction directly. */
  17795. +#define TARGET_GP_DIRECT \
  17796. + (nds32_cmodel_option == CMODEL_SMALL\
  17797. + || nds32_cmodel_option == CMODEL_MEDIUM)
  17798. +
  17799. +/* There are three kinds of mul configurations:
  17800. + 1-cycle fast mul, 2-cycle fast mul, and slow mul operation. */
  17801. +#define TARGET_MUL_FAST_1 \
  17802. + (nds32_mul_config == MUL_TYPE_FAST_1)
  17803. +#define TARGET_MUL_FAST_2 \
  17804. + (nds32_mul_config == MUL_TYPE_FAST_2)
  17805. +#define TARGET_MUL_SLOW \
  17806. + (nds32_mul_config == MUL_TYPE_SLOW)
  17807. +
  17808. +/* Run-time Target Specification. */
  17809. +#define TARGET_SOFT_FLOAT (nds32_float_abi == NDS32_FLOAT_ABI_SOFT)
  17810. +/* Use hardware floating point calling convention. */
  17811. +#define TARGET_HARD_FLOAT (nds32_float_abi == NDS32_FLOAT_ABI_HARD)
  17812. +
  17813. +/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
  17814. + 1 means hard ABI and using full floating-point instruction,
  17815. + 2 means hard ABI and only using single-precision floating-point
  17816. + instruction */
  17817. +#if TARGET_ARCH_DEFAULT == 1
  17818. +# define TARGET_DEFAULT_FLOAT_ABI NDS32_FLOAT_ABI_HARD
  17819. +# define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
  17820. +# define TARGET_DEFAULT_FPU_FMA 0
  17821. +#else
  17822. +# if TARGET_ARCH_DEFAULT == 2
  17823. +# define TARGET_DEFAULT_FLOAT_ABI NDS32_FLOAT_ABI_HARD
  17824. +# define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
  17825. +# define TARGET_DEFAULT_FPU_FMA 0
  17826. +# else
  17827. +# define TARGET_DEFAULT_FLOAT_ABI NDS32_FLOAT_ABI_SOFT
  17828. +# define TARGET_DEFAULT_FPU_ISA 0
  17829. +# define TARGET_DEFAULT_FPU_FMA 0
  17830. +# endif
  17831. +#endif
  17832. +
  17833. +#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
  17834. +
  17835. +/* ------------------------------------------------------------------------ */
  17836. +
  17837. +#ifdef TARGET_DEFAULT_RELAX
  17838. +# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}"
  17839. +#else
  17840. +# define NDS32_RELAX_SPEC " %{mrelax:--relax}"
  17841. +#endif
  17842. +
  17843. +#ifdef TARGET_OS_DEFAULT_IFC
  17844. +# define NDS32_IFC_SPEC " %{Os3|Os|mifc:%{!mno-ifc:--mifc}}"
  17845. +#else
  17846. +# define NDS32_IFC_SPEC " %{mifc:--mifc}"
  17847. +#endif
  17848. +
  17849. +#ifdef TARGET_OS_DEFAULT_EX9
  17850. +# define NDS32_EX9_SPEC " %{Os3|Os|mex9:%{!mno-ex9:--mex9}}"
  17851. +#else
  17852. +# define NDS32_EX9_SPEC " %{mex9:--mex9}"
  17853. +#endif
  17854. +
  17855. +#ifdef TARGET_DEFAULT_EXT_DSP
  17856. +# define NDS32_EXT_DSP_SPEC "%{!mno-ext-dsp:-mext-dsp}"
  17857. +#else
  17858. +# define NDS32_EXT_DSP_SPEC ""
  17859. +#endif
  17860. +
  17861. +#ifdef TARGET_DEFAULT_HWLOOP
  17862. +# define NDS32_HWLOOP_SPEC "%{!mno-ext-zol:-mext-zol}"
  17863. +#else
  17864. +# define NDS32_HWLOOP_SPEC ""
  17865. +#endif
  17866. +
  17867. +#ifdef TARGET_DEFAULT_16BIT
  17868. +# define NDS32_16BIT_SPEC "%{!mno-16-bit:%{!mno-16bit:-m16bit}}"
  17869. +#else
  17870. +# define NDS32_16BIT_SPEC "%{!m16-bit:%{!m16bit:-mno-16bit}}"
  17871. +#endif
  17872. /* ------------------------------------------------------------------------ */
  17873. /* Controlling the Compilation Driver. */
  17874. +#define DRIVER_SELF_SPECS \
  17875. + " %{mno-16bit|mno-16-bit:-mno-ifc -mno-ex9}" \
  17876. + NDS32_16BIT_SPEC
  17877. +
  17878. #define OPTION_DEFAULT_SPECS \
  17879. - {"arch", "%{!march=*:-march=%(VALUE)}" }
  17880. + {"arch", "%{!march=*:-march=%(VALUE)}" \
  17881. + "%{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
  17882. + " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
  17883. + " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
  17884. + "%{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
  17885. + " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
  17886. + {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
  17887. + {"memory_model", "%{!mmemory-model=*:-mmemory-model=%(VALUE)}"}, \
  17888. + {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
  17889. #define CC1_SPEC \
  17890. - ""
  17891. + " %{Os1:-Os -mno-ifc -mno-ex9;" \
  17892. + "Os2:-Os -minnermost-loop;" \
  17893. + "Os3:-Os}" \
  17894. + NDS32_EXT_DSP_SPEC \
  17895. + NDS32_HWLOOP_SPEC
  17896. #define ASM_SPEC \
  17897. - " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
  17898. -
  17899. -/* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
  17900. - we need to pass '--relax' to linker.
  17901. - Besides, for -mex9, we need to further pass '--mex9'. */
  17902. -#define LINK_SPEC \
  17903. " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
  17904. - " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
  17905. - " %{mex9:--mex9}"
  17906. -
  17907. -#define LIB_SPEC \
  17908. - " -lc -lgloss"
  17909. -
  17910. -/* The option -mno-ctor-dtor can disable constructor/destructor feature
  17911. - by applying different crt stuff. In the convention, crt0.o is the
  17912. - startup file without constructor/destructor;
  17913. - crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
  17914. - startup files with constructor/destructor.
  17915. - Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
  17916. - by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
  17917. - currently provided by GCC for nds32 target.
  17918. -
  17919. - For nds32 target so far:
  17920. - If -mno-ctor-dtor, we are going to link
  17921. - "crt0.o [user objects]".
  17922. - If general cases, we are going to link
  17923. - "crt1.o crtbegin1.o [user objects] crtend1.o". */
  17924. -#define STARTFILE_SPEC \
  17925. - " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
  17926. - " %{!mno-ctor-dtor:crtbegin1.o%s}"
  17927. -#define ENDFILE_SPEC \
  17928. - " %{!mno-ctor-dtor:crtend1.o%s}"
  17929. -
  17930. -/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
  17931. - with --target=nds32be-* setting.
  17932. - Check gcc/config.gcc for more information.
  17933. - In addition, currently we only have elf toolchain,
  17934. - where mgp-direct is always the default. */
  17935. + " %{march=*:-march=%*}" \
  17936. + " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \
  17937. + " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \
  17938. + " %{mfull-regs:-mfull-regs}" \
  17939. + " %{mreduced-regs:-mreduced-regs}" \
  17940. + " %{mfloat-abi=hard:-mabi=v2fpp}" \
  17941. + " %{mfloat-abi=soft:-mabi=v2}" \
  17942. + " %{mconfig-fpu=*:-mfpu-freg=%*}" \
  17943. + " %{mext-fpu-mac:-mmac}" \
  17944. + " %{mno-ext-fpu-mac:-mno-mac}" \
  17945. + " %{mext-fpu-sp:-mfpu-sp-ext}" \
  17946. + " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
  17947. + " %{mext-fpu-dp:-mfpu-dp-ext}" \
  17948. + " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \
  17949. + " %{mext-dsp:-mdsp-ext}" \
  17950. + " %{mext-zol:-mzol-ext}" \
  17951. + " %{O|O1|O2|O3|Ofast:-O1;:-Os}"
  17952. +
  17953. +/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
  17954. + configure gcc with --target=nds32be-* setting.
  17955. + Check gcc/config.gcc for more information. */
  17956. #ifdef TARGET_BIG_ENDIAN_DEFAULT
  17957. -#define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
  17958. +# define NDS32_ENDIAN_DEFAULT "mbig-endian"
  17959. +#else
  17960. +# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
  17961. +#endif
  17962. +
  17963. +/* Currently we only have elf toolchain,
  17964. + where -mcmodel=medium is always the default. */
  17965. +#if TARGET_ELF
  17966. +# define NDS32_CMODEL_DEFAULT "mcmodel=medium"
  17967. #else
  17968. -#define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
  17969. +# define NDS32_CMODEL_DEFAULT "mcmodel=medium"
  17970. #endif
  17971. +#define MULTILIB_DEFAULTS \
  17972. + { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
  17973. +
  17974. /* Run-time Target Specification. */
  17975. -#define TARGET_CPU_CPP_BUILTINS() \
  17976. - do \
  17977. - { \
  17978. - builtin_define ("__nds32__"); \
  17979. - \
  17980. - if (TARGET_ISA_V2) \
  17981. - builtin_define ("__NDS32_ISA_V2__"); \
  17982. - if (TARGET_ISA_V3) \
  17983. - builtin_define ("__NDS32_ISA_V3__"); \
  17984. - if (TARGET_ISA_V3M) \
  17985. - builtin_define ("__NDS32_ISA_V3M__"); \
  17986. - \
  17987. - if (TARGET_BIG_ENDIAN) \
  17988. - builtin_define ("__big_endian__"); \
  17989. - if (TARGET_REDUCED_REGS) \
  17990. - builtin_define ("__NDS32_REDUCED_REGS__"); \
  17991. - if (TARGET_CMOV) \
  17992. - builtin_define ("__NDS32_CMOV__"); \
  17993. - if (TARGET_PERF_EXT) \
  17994. - builtin_define ("__NDS32_PERF_EXT__"); \
  17995. - if (TARGET_16_BIT) \
  17996. - builtin_define ("__NDS32_16_BIT__"); \
  17997. - if (TARGET_GP_DIRECT) \
  17998. - builtin_define ("__NDS32_GP_DIRECT__"); \
  17999. - \
  18000. - builtin_assert ("cpu=nds32"); \
  18001. - builtin_assert ("machine=nds32"); \
  18002. - } while (0)
  18003. +#define TARGET_CPU_CPP_BUILTINS() \
  18004. + nds32_cpu_cpp_builtins (pfile)
  18005. /* Defining Data Structures for Per-function Information. */
  18006. @@ -446,10 +1059,20 @@
  18007. #define STACK_BOUNDARY 64
  18008. -#define FUNCTION_BOUNDARY 32
  18009. +#define FUNCTION_BOUNDARY \
  18010. + ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
  18011. #define BIGGEST_ALIGNMENT 64
  18012. +#define DATA_ALIGNMENT(constant, basic_align) \
  18013. + nds32_data_alignment (constant, basic_align)
  18014. +
  18015. +#define CONSTANT_ALIGNMENT(constant, basic_align) \
  18016. + nds32_constant_alignment (constant, basic_align)
  18017. +
  18018. +#define LOCAL_ALIGNMENT(type, basic_align) \
  18019. + nds32_local_alignment (type, basic_align)
  18020. +
  18021. #define EMPTY_FIELD_BOUNDARY 32
  18022. #define STRUCTURE_SIZE_BOUNDARY 8
  18023. @@ -474,8 +1097,8 @@
  18024. #define SIZE_TYPE "long unsigned int"
  18025. #define PTRDIFF_TYPE "long int"
  18026. -#define WCHAR_TYPE "short unsigned int"
  18027. -#define WCHAR_TYPE_SIZE 16
  18028. +#define WCHAR_TYPE "unsigned int"
  18029. +#define WCHAR_TYPE_SIZE 32
  18030. /* Register Usage. */
  18031. @@ -485,7 +1108,7 @@
  18032. from 0 to just below FIRST_PSEUDO_REGISTER.
  18033. All registers that the compiler knows about must be given numbers,
  18034. even those that are not normally considered general registers. */
  18035. -#define FIRST_PSEUDO_REGISTER 34
  18036. +#define FIRST_PSEUDO_REGISTER 101
  18037. /* An initializer that says which registers are used for fixed
  18038. purposes all throughout the compiled code and are therefore
  18039. @@ -496,24 +1119,38 @@
  18040. $r30 : $lp
  18041. $r31 : $sp
  18042. - caller-save registers: $r0 ~ $r5, $r16 ~ $r23
  18043. - callee-save registers: $r6 ~ $r10, $r11 ~ $r14
  18044. + caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
  18045. + callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
  18046. reserved for assembler : $r15
  18047. reserved for other use : $r24, $r25, $r26, $r27 */
  18048. -#define FIXED_REGISTERS \
  18049. -{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
  18050. - 0, 0, 0, 0, 0, 0, 0, 0, \
  18051. - /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
  18052. - 0, 0, 0, 0, 0, 0, 0, 1, \
  18053. - /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
  18054. - 0, 0, 0, 0, 0, 0, 0, 0, \
  18055. - /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
  18056. - 1, 1, 1, 1, 0, 1, 0, 1, \
  18057. - /* ARG_POINTER:32 */ \
  18058. - 1, \
  18059. - /* FRAME_POINTER:33 */ \
  18060. - 1 \
  18061. +#define FIXED_REGISTERS \
  18062. +{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
  18063. + 0, 0, 0, 0, 0, 0, 0, 0, \
  18064. + /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
  18065. + 0, 0, 0, 0, 0, 0, 0, 0, \
  18066. + /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
  18067. + 0, 0, 0, 0, 0, 0, 0, 0, \
  18068. + /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
  18069. + 0, 0, 1, 1, 0, 1, 0, 1, \
  18070. + /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
  18071. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18072. + /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
  18073. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18074. + /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
  18075. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18076. + /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
  18077. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18078. + /* fs30 fs31 fd16 fd17 fd18 */ \
  18079. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18080. + /* fd19 fd20 fd21 fd22 */ \
  18081. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18082. + /* fd23 fd24 fd25 fd26 */ \
  18083. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18084. + /* fd27 fd28 fd29 fd30 */ \
  18085. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18086. + /* fd31 LB LE LC */ \
  18087. + 1, 1, 1, 1, 1 \
  18088. }
  18089. /* Identifies the registers that are not available for
  18090. @@ -522,38 +1159,62 @@
  18091. 0 : callee-save registers
  18092. 1 : caller-save registers */
  18093. -#define CALL_USED_REGISTERS \
  18094. -{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
  18095. - 1, 1, 1, 1, 1, 1, 0, 0, \
  18096. - /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
  18097. - 0, 0, 0, 0, 0, 0, 0, 1, \
  18098. - /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
  18099. - 1, 1, 1, 1, 1, 1, 1, 1, \
  18100. - /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
  18101. - 1, 1, 1, 1, 0, 1, 0, 1, \
  18102. - /* ARG_POINTER:32 */ \
  18103. - 1, \
  18104. - /* FRAME_POINTER:33 */ \
  18105. - 1 \
  18106. +#define CALL_USED_REGISTERS \
  18107. +{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
  18108. + 1, 1, 1, 1, 1, 1, 0, 0, \
  18109. + /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
  18110. + 0, 0, 0, 0, 0, 0, 0, 1, \
  18111. + /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
  18112. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18113. + /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
  18114. + 1, 1, 1, 1, 0, 1, 0, 1, \
  18115. + /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
  18116. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18117. + /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
  18118. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18119. + /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
  18120. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18121. + /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
  18122. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18123. + /* fs30 fs31 fd16 fd17 fd18 */ \
  18124. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18125. + /* fd19 fd20 fd21 fd22 */ \
  18126. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18127. + /* fd23 fd24 fd25 fd26 */ \
  18128. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18129. + /* fd27 fd28 fd29 fd30 */ \
  18130. + 1, 1, 1, 1, 1, 1, 1, 1, \
  18131. + /* fd31 LB LE LC */ \
  18132. + 1, 1, 1, 1, 1 \
  18133. }
  18134. /* In nds32 target, we have three levels of registers:
  18135. LOW_COST_REGS : $r0 ~ $r7
  18136. MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
  18137. HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
  18138. -#define REG_ALLOC_ORDER \
  18139. -{ \
  18140. - 0, 1, 2, 3, 4, 5, 6, 7, \
  18141. - 8, 9, 10, 11, 16, 17, 18, 19, \
  18142. - 12, 13, 14, 15, 20, 21, 22, 23, \
  18143. - 24, 25, 26, 27, 28, 29, 30, 31, \
  18144. - 32, \
  18145. - 33 \
  18146. +#define REG_ALLOC_ORDER \
  18147. +{ 0, 1, 2, 3, 4, 5, 6, 7, \
  18148. + 16, 17, 18, 19, 9, 10, 11, 12, \
  18149. + 13, 14, 8, 15, 20, 21, 22, 23, \
  18150. + 24, 25, 26, 27, 28, 29, 30, 31, \
  18151. + 32, 33, 34, 35, 36, 37, 38, 39, \
  18152. + 40, 41, 42, 43, 44, 45, 46, 47, \
  18153. + 48, 49, 50, 51, 52, 53, 54, 55, \
  18154. + 56, 57, 58, 59, 60, 61, 62, 63, \
  18155. + 64, 65, 66, 67, 68, 69, 70, 71, \
  18156. + 72, 73, 74, 75, 76, 77, 78, 79, \
  18157. + 80, 81, 82, 83, 84, 85, 86, 87, \
  18158. + 88, 89, 90, 91, 92, 93, 94, 95, \
  18159. + 96, 97, 98, 99, 100, \
  18160. }
  18161. +/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
  18162. + to be rearranged based on optimizing for speed or size. */
  18163. +#define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
  18164. +
  18165. /* Tell IRA to use the order we define rather than messing it up with its
  18166. own cost calculations. */
  18167. -#define HONOR_REG_ALLOC_ORDER
  18168. +#define HONOR_REG_ALLOC_ORDER optimize_size
  18169. /* The number of consecutive hard regs needed starting at
  18170. reg "regno" for holding a value of mode "mode". */
  18171. @@ -587,13 +1248,18 @@
  18172. enum reg_class
  18173. {
  18174. NO_REGS,
  18175. + R5_REG,
  18176. + R8_REG,
  18177. R15_TA_REG,
  18178. STACK_REG,
  18179. + FRAME_POINTER_REG,
  18180. LOW_REGS,
  18181. MIDDLE_REGS,
  18182. HIGH_REGS,
  18183. GENERAL_REGS,
  18184. FRAME_REGS,
  18185. + FP_REGS,
  18186. + LOOP_REGS,
  18187. ALL_REGS,
  18188. LIM_REG_CLASSES
  18189. };
  18190. @@ -603,27 +1269,50 @@
  18191. #define REG_CLASS_NAMES \
  18192. { \
  18193. "NO_REGS", \
  18194. + "R5_REG", \
  18195. + "R8_REG", \
  18196. "R15_TA_REG", \
  18197. "STACK_REG", \
  18198. + "FRAME_POINTER_REG", \
  18199. "LOW_REGS", \
  18200. "MIDDLE_REGS", \
  18201. "HIGH_REGS", \
  18202. "GENERAL_REGS", \
  18203. "FRAME_REGS", \
  18204. + "FP_REGS", \
  18205. + "LOOP_REGS", \
  18206. "ALL_REGS" \
  18207. }
  18208. #define REG_CLASS_CONTENTS \
  18209. -{ \
  18210. - {0x00000000, 0x00000000}, /* NO_REGS : */ \
  18211. - {0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
  18212. - {0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
  18213. - {0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
  18214. - {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
  18215. - {0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
  18216. - {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
  18217. - {0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
  18218. - {0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
  18219. +{ /* NO_REGS */ \
  18220. + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
  18221. + /* R5_REG : 5 */ \
  18222. + {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
  18223. + /* R8_REG : 8 */ \
  18224. + {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
  18225. + /* R15_TA_REG : 15 */ \
  18226. + {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
  18227. + /* STACK_REG : 31 */ \
  18228. + {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
  18229. + /* FRAME_POINTER_REG : 28 */ \
  18230. + {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
  18231. + /* LOW_REGS : 0-7 */ \
  18232. + {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
  18233. + /* MIDDLE_REGS : 0-11, 16-19 */ \
  18234. + {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
  18235. + /* HIGH_REGS : 12-14, 20-31 */ \
  18236. + {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
  18237. + /* GENERAL_REGS : 0-31 */ \
  18238. + {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
  18239. + /* FRAME_REGS : 32, 33 */ \
  18240. + {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
  18241. + /* FP_REGS : 34-98 */ \
  18242. + {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
  18243. + /* LOOP_REGS 99-101 */ \
  18244. + {0x00000000, 0x00000000, 0x00000000, 0x0000001c}, \
  18245. + /* ALL_REGS : 0-101 */ \
  18246. + {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
  18247. }
  18248. #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
  18249. @@ -631,13 +1320,18 @@
  18250. #define BASE_REG_CLASS GENERAL_REGS
  18251. #define INDEX_REG_CLASS GENERAL_REGS
  18252. +#define TEST_REGNO(R, TEST, VALUE) \
  18253. + ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
  18254. +
  18255. /* Return nonzero if it is suitable for use as a
  18256. base register in operand addresses.
  18257. So far, we return nonzero only if "num" is a hard reg
  18258. of the suitable class or a pseudo register which is
  18259. allocated to a suitable hard reg. */
  18260. #define REGNO_OK_FOR_BASE_P(num) \
  18261. - ((num) < 32 || (unsigned) reg_renumber[num] < 32)
  18262. + (TEST_REGNO (num, <, 32) \
  18263. + || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
  18264. + || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
  18265. /* Return nonzero if it is suitable for use as a
  18266. index register in operand addresses.
  18267. @@ -647,7 +1341,15 @@
  18268. The difference between an index register and a base register is that
  18269. the index register may be scaled. */
  18270. #define REGNO_OK_FOR_INDEX_P(num) \
  18271. - ((num) < 32 || (unsigned) reg_renumber[num] < 32)
  18272. + (TEST_REGNO (num, <, 32) \
  18273. + || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
  18274. + || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
  18275. +
  18276. +/* Don't spill double-precision register to two singal-precision registers */
  18277. +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
  18278. + ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
  18279. + && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
  18280. + ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
  18281. /* Obsolete Macros for Defining Constraints. */
  18282. @@ -663,7 +1365,13 @@
  18283. #define STACK_POINTER_OFFSET 0
  18284. -#define FIRST_PARM_OFFSET(fundecl) 0
  18285. +#define FIRST_PARM_OFFSET(fundecl) \
  18286. + (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
  18287. +
  18288. +/* A C expression whose value is RTL representing the address in a stack frame
  18289. + where the pointer to the caller's frame is stored. */
  18290. +#define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
  18291. + nds32_dynamic_chain_address (frameaddr)
  18292. #define RETURN_ADDR_RTX(count, frameaddr) \
  18293. nds32_return_addr_rtx (count, frameaddr)
  18294. @@ -676,6 +1384,13 @@
  18295. #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
  18296. #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
  18297. +/* Use $r0 $r1 to pass exception handling information. */
  18298. +#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
  18299. +/* The register $r2 that represents a location in which to store a stack
  18300. + adjustment to be applied before function return.
  18301. + This is used to unwind the stack to an exception handler's call frame. */
  18302. +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
  18303. +
  18304. #define STACK_POINTER_REGNUM SP_REGNUM
  18305. #define FRAME_POINTER_REGNUM 33
  18306. @@ -704,12 +1419,11 @@
  18307. #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
  18308. nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
  18309. -/* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
  18310. - We better cast REGNO into signed integer so that we can avoid
  18311. - 'comparison of unsigned expression >= 0 is always true' warning. */
  18312. -#define FUNCTION_ARG_REGNO_P(regno) \
  18313. - (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \
  18314. - && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_REGS_FOR_ARGS))
  18315. +#define FUNCTION_ARG_REGNO_P(regno) \
  18316. + (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
  18317. + || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
  18318. + && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \
  18319. + NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
  18320. #define DEFAULT_PCC_STRUCT_RETURN 0
  18321. @@ -738,13 +1452,13 @@
  18322. The trampoline code for nds32 target must contains following parts:
  18323. 1. instructions (4 * 4 = 16 bytes):
  18324. - get $pc first
  18325. - load chain_value to static chain register via $pc
  18326. - load nested function address to $r15 via $pc
  18327. - jump to desired nested function via $r15
  18328. + get $pc first
  18329. + load chain_value to static chain register via $pc
  18330. + load nested function address to $r15 via $pc
  18331. + jump to desired nested function via $r15
  18332. 2. data (4 * 2 = 8 bytes):
  18333. - chain_value
  18334. - nested function address
  18335. + chain_value
  18336. + nested function address
  18337. Please check nds32.c implementation for more information. */
  18338. #define TRAMPOLINE_SIZE 24
  18339. @@ -769,9 +1483,16 @@
  18340. /* We have "LW.bi Rt, [Ra], Rb" instruction form. */
  18341. #define HAVE_POST_MODIFY_REG 1
  18342. +#define USE_LOAD_POST_INCREMENT(mode) \
  18343. + (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(DImode))
  18344. +#define USE_LOAD_POST_DECREMENT(mode) \
  18345. + (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(DImode))
  18346. +#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
  18347. +#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
  18348. +
  18349. #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
  18350. -#define MAX_REGS_PER_ADDRESS 2
  18351. +#define MAX_REGS_PER_ADDRESS 3
  18352. /* Anchored Addresses. */
  18353. @@ -785,7 +1506,11 @@
  18354. /* A C expression for the cost of a branch instruction.
  18355. A value of 1 is the default;
  18356. other values are interpreted relative to that. */
  18357. -#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
  18358. +#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
  18359. +
  18360. +/* Override BRANCH_COST heuristic which empirically produces worse
  18361. + performance for removing short circuiting from the logical ops. */
  18362. +#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
  18363. #define SLOW_BYTE_ACCESS 1
  18364. @@ -813,14 +1538,21 @@
  18365. /* Position Independent Code. */
  18366. +#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
  18367. +
  18368. +#define SYMBOLIC_CONST_P(X) \
  18369. +(GET_CODE (X) == SYMBOL_REF \
  18370. + || GET_CODE (X) == LABEL_REF \
  18371. + || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
  18372. +
  18373. /* Defining the Output Assembler Language. */
  18374. #define ASM_COMMENT_START "!"
  18375. -#define ASM_APP_ON "! #APP"
  18376. +#define ASM_APP_ON "! #APP\n.inline_asm_begin\n"
  18377. -#define ASM_APP_OFF "! #NO_APP\n"
  18378. +#define ASM_APP_OFF "! #NO_APP\n.inline_asm_end\n"
  18379. #define ASM_OUTPUT_LABELREF(stream, name) \
  18380. asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
  18381. @@ -833,14 +1565,56 @@
  18382. #define LOCAL_LABEL_PREFIX "."
  18383. -#define REGISTER_NAMES \
  18384. -{ \
  18385. - "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
  18386. +#define REGISTER_NAMES \
  18387. +{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
  18388. "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
  18389. "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
  18390. "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
  18391. - "$AP", \
  18392. - "$SFP" \
  18393. + "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
  18394. + "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
  18395. + "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
  18396. + "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
  18397. + "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
  18398. + "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
  18399. + "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
  18400. + "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
  18401. + "$fs62","$fs63", "LB", "LE", "LC" \
  18402. +}
  18403. +
  18404. +#define OVERLAPPING_REGISTER_NAMES \
  18405. +{ \
  18406. + {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \
  18407. + {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \
  18408. + {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \
  18409. + {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \
  18410. + {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \
  18411. + {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \
  18412. + {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \
  18413. + {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \
  18414. + {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \
  18415. + {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \
  18416. + {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \
  18417. + {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \
  18418. + {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \
  18419. + {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \
  18420. + {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \
  18421. + {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \
  18422. + {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \
  18423. + {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \
  18424. + {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \
  18425. + {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \
  18426. + {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \
  18427. + {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \
  18428. + {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \
  18429. + {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \
  18430. + {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \
  18431. + {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \
  18432. + {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \
  18433. + {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \
  18434. + {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \
  18435. + {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \
  18436. + {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \
  18437. + {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \
  18438. }
  18439. /* Output normal jump table entry. */
  18440. @@ -852,19 +1626,19 @@
  18441. do \
  18442. { \
  18443. switch (GET_MODE (body)) \
  18444. - { \
  18445. - case QImode: \
  18446. - asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
  18447. - break; \
  18448. - case HImode: \
  18449. - asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
  18450. - break; \
  18451. - case SImode: \
  18452. - asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
  18453. - break; \
  18454. - default: \
  18455. - gcc_unreachable(); \
  18456. - } \
  18457. + { \
  18458. + case QImode: \
  18459. + asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
  18460. + break; \
  18461. + case HImode: \
  18462. + asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
  18463. + break; \
  18464. + case SImode: \
  18465. + asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
  18466. + break; \
  18467. + default: \
  18468. + gcc_unreachable(); \
  18469. + } \
  18470. } while (0)
  18471. /* We have to undef it first because elfos.h formerly define it
  18472. @@ -881,10 +1655,10 @@
  18473. do \
  18474. { \
  18475. /* Because our jump table is in text section, \
  18476. - we need to make sure 2-byte alignment after \
  18477. - the jump table for instructions fetch. */ \
  18478. + we need to make sure 2-byte alignment after \
  18479. + the jump table for instructions fetch. */ \
  18480. if (GET_MODE (PATTERN (table)) == QImode) \
  18481. - ASM_OUTPUT_ALIGN (stream, 1); \
  18482. + ASM_OUTPUT_ALIGN (stream, 1); \
  18483. asm_fprintf (stream, "\t! Jump Table End\n"); \
  18484. } while (0)
  18485. @@ -948,9 +1722,7 @@
  18486. /* Return the preferred mode for and addr_diff_vec when the mininum
  18487. and maximum offset are known. */
  18488. #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
  18489. - ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
  18490. - : (max_offset >= 100) ? HImode \
  18491. - : QImode)
  18492. + nds32_case_vector_shorten_mode (min_offset, max_offset, body)
  18493. /* Generate pc relative jump table when -fpic or -Os. */
  18494. #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
  18495. @@ -983,6 +1755,11 @@
  18496. when the condition is true. */
  18497. #define STORE_FLAG_VALUE 1
  18498. +/* A C expression that indicates whether the architecture defines a value for
  18499. + clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined
  18500. + in ISA spec */
  18501. +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
  18502. +
  18503. /* An alias for the machine mode for pointers. */
  18504. #define Pmode SImode
  18505. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-hwloop.c gcc-4.9.4/gcc/config/nds32/nds32-hwloop.c
  18506. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-hwloop.c 1970-01-01 01:00:00.000000000 +0100
  18507. +++ gcc-4.9.4/gcc/config/nds32/nds32-hwloop.c 2016-08-08 20:37:45.502269936 +0200
  18508. @@ -0,0 +1,934 @@
  18509. +/* hwloop pass of Andes NDS32 cpu for GNU compiler
  18510. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  18511. + Contributed by Andes Technology Corporation.
  18512. +
  18513. + This file is part of GCC.
  18514. +
  18515. + GCC is free software; you can redistribute it and/or modify it
  18516. + under the terms of the GNU General Public License as published
  18517. + by the Free Software Foundation; either version 3, or (at your
  18518. + option) any later version.
  18519. +
  18520. + GCC is distributed in the hope that it will be useful, but WITHOUT
  18521. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  18522. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  18523. + License for more details.
  18524. +
  18525. + You should have received a copy of the GNU General Public License
  18526. + along with GCC; see the file COPYING3. If not see
  18527. + <http://www.gnu.org/licenses/>. */
  18528. +
  18529. +/* ------------------------------------------------------------------------ */
  18530. +#include "config.h"
  18531. +#include "system.h"
  18532. +#include "coretypes.h"
  18533. +#include "tm.h"
  18534. +#include "tree.h"
  18535. +#include "stor-layout.h"
  18536. +#include "varasm.h"
  18537. +#include "calls.h"
  18538. +#include "rtl.h"
  18539. +#include "regs.h"
  18540. +#include "hard-reg-set.h"
  18541. +#include "insn-config.h" /* Required by recog.h. */
  18542. +#include "conditions.h"
  18543. +#include "output.h"
  18544. +#include "insn-attr.h" /* For DFA state_t. */
  18545. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  18546. +#include "reload.h" /* For push_reload(). */
  18547. +#include "flags.h"
  18548. +#include "function.h"
  18549. +#include "expr.h"
  18550. +#include "recog.h"
  18551. +#include "diagnostic-core.h"
  18552. +#include "df.h"
  18553. +#include "tm_p.h"
  18554. +#include "tm-constrs.h"
  18555. +#include "optabs.h" /* For GEN_FCN. */
  18556. +#include "target.h"
  18557. +#include "target-def.h"
  18558. +#include "langhooks.h" /* For add_builtin_function(). */
  18559. +#include "ggc.h"
  18560. +#include "tree-pass.h"
  18561. +#include "basic-block.h"
  18562. +#include "cfgloop.h"
  18563. +#include "context.h"
  18564. +#include "params.h"
  18565. +#include "cpplib.h"
  18566. +#include "hw-doloop.h"
  18567. +
  18568. +static int hwloop_group_id = 0;
  18569. +
  18570. +/* A callback for the hw-doloop pass. This function examines INSN; if
  18571. + it is a doloop_end pattern we recognize, return the reg rtx for the
  18572. + loop counter. Otherwise, return NULL_RTX. */
  18573. +static rtx
  18574. +hwloop_pattern_reg (rtx insn)
  18575. +{
  18576. + rtx reg;
  18577. +
  18578. + if (!JUMP_P (insn) || recog_memoized (insn) != CODE_FOR_loop_end)
  18579. + return NULL_RTX;
  18580. +
  18581. + reg = SET_DEST (XVECEXP (PATTERN (insn), 0, 1));
  18582. + if (!REG_P (reg))
  18583. + return NULL_RTX;
  18584. + return reg;
  18585. +}
  18586. +
  18587. +/* Optimize Loop */
  18588. +static bool
  18589. +hwloop1_optimize (hwloop_info loop)
  18590. +{
  18591. + basic_block bb, new_bb, outer_new_bb;
  18592. + edge e, outer_e;
  18593. + edge_iterator ei, outer_ei;
  18594. + rtx insn, last_insn, cfg_insn, recog_insn;
  18595. + rtx start_label;
  18596. + rtx iter_reg;
  18597. + rtx seq, seq_end;
  18598. + hwloop_info inner;
  18599. + unsigned ix;
  18600. + bool same_depth_p = false;
  18601. +
  18602. + if (loop->jumps_outof)
  18603. + {
  18604. + if (dump_file)
  18605. + fprintf (dump_file, ";; loop %d jumps out of loop body.\n",
  18606. + loop->loop_no);
  18607. + return false;
  18608. + }
  18609. +
  18610. + if (!loop->incoming_dest)
  18611. + {
  18612. + if (dump_file)
  18613. + fprintf (dump_file, ";; loop %d has more than one entry\n",
  18614. + loop->loop_no);
  18615. + return true;
  18616. + }
  18617. +
  18618. + if (loop->incoming_dest != loop->head)
  18619. + {
  18620. + if (dump_file)
  18621. + fprintf (dump_file, ";; loop %d is not entered from head\n",
  18622. + loop->loop_no);
  18623. + return true;
  18624. + }
  18625. +
  18626. + if (loop->has_call || loop->has_asm)
  18627. + {
  18628. + if (dump_file)
  18629. + fprintf (dump_file, ";; loop %d has invalid insn\n",
  18630. + loop->loop_no);
  18631. + return false;
  18632. + }
  18633. +
  18634. + /* Get the loop iteration register. */
  18635. + iter_reg = loop->iter_reg;
  18636. +
  18637. + gcc_assert (REG_P (iter_reg));
  18638. +
  18639. + if (loop->incoming_src)
  18640. + {
  18641. + /* Make sure the predecessor is before the loop start label,
  18642. + as required by the loop setup instructions. */
  18643. + insn = BB_END (loop->incoming_src);
  18644. +
  18645. + if (vec_safe_length (loop->incoming) > 1
  18646. + || !(loop->incoming->last ()->flags & EDGE_FALLTHRU))
  18647. + {
  18648. + gcc_assert (JUMP_P (insn));
  18649. +
  18650. + if (dump_file)
  18651. + fprintf (dump_file, ";; loop %d loop setup space has jump insn,"
  18652. + " before loop_start\n", loop->loop_no);
  18653. + return true;
  18654. + }
  18655. +
  18656. + while (insn && insn != loop->start_label)
  18657. + insn = NEXT_INSN (insn);
  18658. +
  18659. + if (!insn)
  18660. + {
  18661. + if (dump_file)
  18662. + fprintf (dump_file, ";; loop %d loop setup not before loop_start\n",
  18663. + loop->loop_no);
  18664. + return true;
  18665. + }
  18666. + }
  18667. +
  18668. + /* Check if start_label appears before loop_end and. */
  18669. + insn = loop->start_label;
  18670. + while (insn && insn != loop->loop_end)
  18671. + insn = NEXT_INSN (insn);
  18672. +
  18673. + if (!insn)
  18674. + {
  18675. + if (dump_file)
  18676. + fprintf (dump_file, ";; loop %d start_label not before loop_end\n",
  18677. + loop->loop_no);
  18678. + return true;
  18679. + }
  18680. +
  18681. + /* There should be an instruction before the loop_end instruction
  18682. + in the same basic block. And the instruction must not be
  18683. + - JUMP
  18684. + - CONDITIONAL BRANCH
  18685. + - CALL
  18686. + - Returns */
  18687. +
  18688. + bb = loop->tail;
  18689. + last_insn = PREV_INSN (loop->loop_end);
  18690. +
  18691. + while (1)
  18692. + {
  18693. + for (; last_insn != BB_HEAD (bb);
  18694. + last_insn = PREV_INSN (last_insn))
  18695. + if (NONDEBUG_INSN_P (last_insn))
  18696. + break;
  18697. +
  18698. + if (last_insn != BB_HEAD (bb))
  18699. + break;
  18700. +
  18701. + if (single_pred_p (bb)
  18702. + && single_pred_edge (bb)->flags & EDGE_FALLTHRU
  18703. + && single_pred (bb) != ENTRY_BLOCK_PTR_FOR_FN (cfun))
  18704. + {
  18705. + bb = single_pred (bb);
  18706. + last_insn = BB_END (bb);
  18707. + continue;
  18708. + }
  18709. + else
  18710. + {
  18711. + last_insn = NULL;
  18712. + break;
  18713. + }
  18714. + }
  18715. +
  18716. + if (!last_insn)
  18717. + {
  18718. + if (dump_file)
  18719. + fprintf (dump_file, ";; loop %d has no last instruction\n",
  18720. + loop->loop_no);
  18721. + return true;
  18722. + }
  18723. +
  18724. + if (JUMP_P (last_insn) && !any_condjump_p (last_insn))
  18725. + {
  18726. + if (dump_file)
  18727. + fprintf (dump_file, ";; loop %d has bad last instruction\n",
  18728. + loop->loop_no);
  18729. + return true;
  18730. + }
  18731. +
  18732. + /* Check unspec_hwloop pattern on first basic block. */
  18733. + for (insn = BB_HEAD (loop->tail) ; insn != BB_END (loop->tail);
  18734. + insn = NEXT_INSN (insn))
  18735. + {
  18736. + if (recog_memoized (insn) == CODE_FOR_unspec_no_hwloop)
  18737. + {
  18738. + if (dump_file)
  18739. + fprintf (dump_file, ";; loop %d has bad instruction on first BB\n",
  18740. + loop->loop_no);
  18741. + return false;
  18742. + }
  18743. + }
  18744. +
  18745. + /* Check unspec_hwloop pattern on last basic block. */
  18746. + for (insn = BB_HEAD (loop->head); insn != BB_END (loop->head);
  18747. + insn = NEXT_INSN (insn))
  18748. + {
  18749. + if (recog_memoized (insn) == CODE_FOR_unspec_no_hwloop)
  18750. + {
  18751. + if (dump_file)
  18752. + fprintf (dump_file, ";; loop %d has bad instruction on last BB\n",
  18753. + loop->loop_no);
  18754. + return false;
  18755. + }
  18756. + }
  18757. +
  18758. + /* Check inner loop have Hardware loop. */
  18759. + for (ix = 0; loop->loops.iterate (ix, &inner); ix++)
  18760. + {
  18761. + if ((loop->loop_no != inner->loop_no)
  18762. + && !inner->bad)
  18763. + {
  18764. + if (dump_file)
  18765. + fprintf (dump_file, ";; Inner loop %d have HW-loop in loop: %d\n",
  18766. + inner->loop_no, loop->loop_no);
  18767. + return false;
  18768. + }
  18769. + }
  18770. +
  18771. + /* Check same loop depth in nesting loop. */
  18772. + for (ix = 0; loop->outermost->loops.iterate (ix, &inner); ix++)
  18773. + {
  18774. + /* Check real_depth same other loop real_depth. */
  18775. + if ((loop->loop_no != inner->loop_no)
  18776. + && (loop->real_depth == inner->real_depth))
  18777. + same_depth_p = true;
  18778. +
  18779. + if (dump_file)
  18780. + {
  18781. + fprintf (dump_file, ";;loop %d depth: %d",
  18782. + loop->loop_no, loop->depth);
  18783. + fprintf (dump_file, " inner %d depth %d\n",
  18784. + inner->loop_no, inner->real_depth);
  18785. + }
  18786. + }
  18787. +
  18788. + /* In all other cases, try to replace a bad last insn with a nop. */
  18789. + if (JUMP_P (last_insn)
  18790. + || CALL_P (last_insn)
  18791. + || recog_memoized (last_insn) == CODE_FOR_return_internal
  18792. + || GET_CODE (PATTERN (last_insn)) == ASM_INPUT
  18793. + || asm_noperands (PATTERN (last_insn)) >= 0)
  18794. + {
  18795. + if (dump_file)
  18796. + fprintf (dump_file, ";; loop %d has bad last insn; replace with nop\n",
  18797. + loop->loop_no);
  18798. +
  18799. + bb = BLOCK_FOR_INSN (last_insn);
  18800. + last_insn = emit_insn_after (gen_unspec_nop (), BB_HEAD (bb->next_bb));
  18801. + }
  18802. +
  18803. + loop->last_insn = last_insn;
  18804. +
  18805. + /* The loop is good for replacement. */
  18806. + start_label = loop->start_label;
  18807. + iter_reg = loop->iter_reg;
  18808. +
  18809. + SET_REGNO_REG_SET (loop->regs_set_in_loop, LC_REGNUM);
  18810. +
  18811. + /* Create a sequence containing the loop setup. */
  18812. + start_sequence ();
  18813. +
  18814. + if (loop->loop_no == loop->outermost->loop_no
  18815. + || same_depth_p)
  18816. + {
  18817. + /* Insert start place for LB. */
  18818. + recog_insn = emit_insn (gen_mtlbi_hint (gen_rtx_LABEL_REF (Pmode,
  18819. + start_label),
  18820. + GEN_INT (hwloop_group_id)));
  18821. + recog_memoized (recog_insn);
  18822. + }
  18823. +
  18824. + /* Insert counter for LC. */
  18825. + seq_end = emit_insn (gen_init_lc (iter_reg, GEN_INT (hwloop_group_id)));
  18826. + recog_memoized (seq_end);
  18827. +
  18828. + if (dump_file)
  18829. + {
  18830. + fprintf (dump_file, ";; replacing loop %d initializer with\n",
  18831. + loop->loop_no);
  18832. + print_rtl_single (dump_file, seq_end);
  18833. + fprintf (dump_file, ";; replacing loop %d terminator with\n",
  18834. + loop->loop_no);
  18835. + print_rtl_single (dump_file, loop->loop_end);
  18836. + }
  18837. +
  18838. + seq = get_insns ();
  18839. + end_sequence ();
  18840. +
  18841. + /* Create new basic block, before loop->head. */
  18842. + emit_insn_before (seq, BB_HEAD (loop->head));
  18843. + seq = emit_label_before (gen_label_rtx (), seq);
  18844. +
  18845. + new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb);
  18846. +
  18847. + /* Copy prev BB flags and frequency. */
  18848. + BB_COPY_PARTITION (new_bb, new_bb->prev_bb);
  18849. + new_bb->frequency = new_bb->prev_bb->frequency;
  18850. +
  18851. + FOR_EACH_EDGE (e, ei, loop->incoming)
  18852. + {
  18853. + if (!(e->flags & EDGE_FALLTHRU)
  18854. + || e->dest != loop->head)
  18855. + redirect_edge_and_branch_force (e, new_bb);
  18856. + else
  18857. + redirect_edge_succ (e, new_bb);
  18858. + }
  18859. +
  18860. + /* The new edge from outer_new_bb to loop->head
  18861. + is FALLTHRU. */
  18862. + make_single_succ_edge (new_bb, loop->head, EDGE_FALLTHRU);
  18863. +
  18864. + /* Get loop_insn note and delete loop_end insn. */
  18865. + rtx note = find_reg_note (loop->loop_end, REG_BR_PROB, 0);
  18866. + delete_insn (loop->loop_end);
  18867. +
  18868. + /* Insert the CFG information after the last instruction of the loop. */
  18869. + cfg_insn = emit_jump_insn_after (gen_hwloop_cfg (GEN_INT (hwloop_group_id),
  18870. + gen_rtx_LABEL_REF (Pmode, start_label)),
  18871. + BB_END (loop->tail));
  18872. + if (note)
  18873. + add_int_reg_note (cfg_insn, REG_BR_PROB, INTVAL (note));
  18874. +
  18875. + recog_memoized (cfg_insn);
  18876. + JUMP_LABEL (cfg_insn) = loop->start_label;
  18877. + LABEL_NUSES (loop->start_label)++;
  18878. +
  18879. + if (loop->loop_no != loop->outermost->loop_no
  18880. + && !same_depth_p)
  18881. + {
  18882. + start_sequence ();
  18883. + /* Insert start place for LB. */
  18884. + seq_end = emit_insn (gen_mtlbi_hint (gen_rtx_LABEL_REF (Pmode,
  18885. + start_label),
  18886. + GEN_INT (hwloop_group_id)));
  18887. + recog_memoized (seq_end);
  18888. + seq = get_insns ();
  18889. + end_sequence ();
  18890. +
  18891. + emit_insn_before (seq, BB_HEAD (loop->outermost->head));
  18892. + seq = emit_label_before (gen_label_rtx (), seq);
  18893. +
  18894. + /* Create new basic block, before loop->outermost->head. */
  18895. + outer_new_bb = create_basic_block (seq, seq_end,
  18896. + loop->outermost->head->prev_bb);
  18897. +
  18898. + /* Copy prev BB flags and frequency. */
  18899. + BB_COPY_PARTITION (outer_new_bb, outer_new_bb->prev_bb);
  18900. + outer_new_bb->frequency = outer_new_bb->prev_bb->frequency;
  18901. +
  18902. + FOR_EACH_EDGE (outer_e, outer_ei, loop->outermost->incoming)
  18903. + {
  18904. + if (!(outer_e->flags & EDGE_FALLTHRU)
  18905. + || outer_e->dest != loop->outermost->head)
  18906. + redirect_edge_and_branch_force (outer_e, outer_new_bb);
  18907. + else
  18908. + redirect_edge_succ (outer_e, outer_new_bb);
  18909. + }
  18910. +
  18911. + /* The new edge from outer_new_bb to loop->outermost->head
  18912. + is FALLTHRU. */
  18913. + make_single_succ_edge (outer_new_bb, loop->outermost->head,
  18914. + EDGE_FALLTHRU);
  18915. + }
  18916. + hwloop_group_id++;
  18917. + return true;
  18918. +}
  18919. +
  18920. +/* Optimize Loop */
  18921. +static bool
  18922. +hwloop2_optimize (hwloop_info loop)
  18923. +{
  18924. + basic_block bb, loop_bb;
  18925. + rtx insn, last_insn, iter_reg;
  18926. + rtx start_label, end_label;
  18927. + rtx lc_reg, lb_reg, le_reg;
  18928. + rtx seq, seq_end;
  18929. + hwloop_info inner;
  18930. + unsigned ix;
  18931. + bool same_depth_p = false;
  18932. +
  18933. + if (loop->jumps_outof)
  18934. + {
  18935. + if (dump_file)
  18936. + fprintf (dump_file, ";; loop %d jumps out of loop body.\n",
  18937. + loop->loop_no);
  18938. + return false;
  18939. + }
  18940. +
  18941. + if (!loop->incoming_dest)
  18942. + {
  18943. + if (dump_file)
  18944. + fprintf (dump_file, ";; loop %d has more than one entry\n",
  18945. + loop->loop_no);
  18946. + return false;
  18947. + }
  18948. +
  18949. + if (loop->incoming_dest != loop->head)
  18950. + {
  18951. + if (dump_file)
  18952. + fprintf (dump_file, ";; loop %d is not entered from head\n",
  18953. + loop->loop_no);
  18954. + return false;
  18955. + }
  18956. +
  18957. + if (loop->has_call || loop->has_asm)
  18958. + {
  18959. + if (dump_file)
  18960. + fprintf (dump_file, ";; loop %d has invalid insn\n",
  18961. + loop->loop_no);
  18962. + return false;
  18963. + }
  18964. +
  18965. + /* Scan all the blocks to make sure they don't use iter_reg. */
  18966. + if (loop->iter_reg_used || loop->iter_reg_used_outside)
  18967. + {
  18968. + if (dump_file)
  18969. + fprintf (dump_file, ";; loop %d uses iterator\n",
  18970. + loop->loop_no);
  18971. + return false;
  18972. + }
  18973. +
  18974. + /* Get the loop iteration register. */
  18975. + iter_reg = loop->iter_reg;
  18976. +
  18977. + gcc_assert (REG_P (iter_reg));
  18978. +
  18979. + if (loop->incoming_src)
  18980. + {
  18981. + /* Make sure the predecessor is before the loop start label,
  18982. + as required by the loop setup instructions. */
  18983. + insn = BB_END (loop->incoming_src);
  18984. +
  18985. + if (vec_safe_length (loop->incoming) > 1
  18986. + || !(loop->incoming->last ()->flags & EDGE_FALLTHRU))
  18987. + {
  18988. + gcc_assert (JUMP_P (insn));
  18989. +
  18990. + if (dump_file)
  18991. + fprintf (dump_file, ";; loop %d loop setup space has jump insn,"
  18992. + " before loop_start\n", loop->loop_no);
  18993. + return false;
  18994. + }
  18995. +
  18996. + while (insn && insn != loop->start_label)
  18997. + insn = NEXT_INSN (insn);
  18998. +
  18999. + if (!insn)
  19000. + {
  19001. + if (dump_file)
  19002. + fprintf (dump_file, ";; loop %d loop setup not before loop_start\n",
  19003. + loop->loop_no);
  19004. + return false;
  19005. + }
  19006. + }
  19007. +
  19008. + /* Check if start_label appears before loop_end and. */
  19009. + insn = loop->start_label;
  19010. + while (insn && insn != loop->loop_end)
  19011. + insn = NEXT_INSN (insn);
  19012. +
  19013. + if (!insn)
  19014. + {
  19015. + if (dump_file)
  19016. + fprintf (dump_file, ";; loop %d start_label not before loop_end\n",
  19017. + loop->loop_no);
  19018. + return false;
  19019. + }
  19020. +
  19021. + /* There should be an instruction before the loop_end instruction
  19022. + in the same basic block. And the instruction must not be
  19023. + - JUMP
  19024. + - CONDITIONAL BRANCH
  19025. + - CALL
  19026. + - Returns */
  19027. +
  19028. + bb = loop->tail;
  19029. + last_insn = PREV_INSN (loop->loop_end);
  19030. +
  19031. + while (1)
  19032. + {
  19033. + for (; last_insn != BB_HEAD (bb);
  19034. + last_insn = PREV_INSN (last_insn))
  19035. + if (NONDEBUG_INSN_P (last_insn))
  19036. + break;
  19037. +
  19038. + if (last_insn != BB_HEAD (bb))
  19039. + break;
  19040. +
  19041. + if (single_pred_p (bb)
  19042. + && single_pred_edge (bb)->flags & EDGE_FALLTHRU
  19043. + && single_pred (bb) != ENTRY_BLOCK_PTR_FOR_FN (cfun))
  19044. + {
  19045. + bb = single_pred (bb);
  19046. + last_insn = BB_END (bb);
  19047. + continue;
  19048. + }
  19049. + else
  19050. + {
  19051. + last_insn = NULL;
  19052. + break;
  19053. + }
  19054. + }
  19055. +
  19056. + if (!last_insn)
  19057. + {
  19058. + if (dump_file)
  19059. + fprintf (dump_file, ";; loop %d has no last instruction\n",
  19060. + loop->loop_no);
  19061. + return false;
  19062. + }
  19063. +
  19064. + if (JUMP_P (last_insn) && !any_condjump_p (last_insn))
  19065. + {
  19066. + if (dump_file)
  19067. + fprintf (dump_file, ";; loop %d has bad last instruction\n",
  19068. + loop->loop_no);
  19069. + return false;
  19070. + }
  19071. +
  19072. + /* Check unspec_hwloop pattern on first basic block. */
  19073. + for (insn = BB_HEAD (loop->tail) ; insn != BB_END (loop->tail);
  19074. + insn = NEXT_INSN (insn))
  19075. + {
  19076. + if (recog_memoized (insn) == CODE_FOR_unspec_no_hwloop)
  19077. + {
  19078. + if (dump_file)
  19079. + fprintf (dump_file, ";; loop %d has bad instruction on first BB\n",
  19080. + loop->loop_no);
  19081. + return false;
  19082. + }
  19083. + }
  19084. +
  19085. + /* Check unspec_hwloop pattern on last basic block. */
  19086. + for (insn = BB_HEAD (loop->head); insn != BB_END (loop->head);
  19087. + insn = NEXT_INSN (insn))
  19088. + {
  19089. + if (recog_memoized (insn) == CODE_FOR_unspec_no_hwloop)
  19090. + {
  19091. + if (dump_file)
  19092. + fprintf (dump_file, ";; loop %d has bad instruction on last BB\n",
  19093. + loop->loop_no);
  19094. + return false;
  19095. + }
  19096. + }
  19097. +
  19098. + /* Check inner loop have Hardware loop by hwloop pass. */
  19099. + for (ix = 0; loop->blocks.iterate (ix, &loop_bb); ix++)
  19100. + {
  19101. + for (insn = BB_HEAD (loop_bb);
  19102. + insn != NEXT_INSN (BB_END (loop_bb));
  19103. + insn = NEXT_INSN (insn))
  19104. + {
  19105. + if (recog_memoized (insn) == CODE_FOR_init_lc)
  19106. + {
  19107. + if (dump_file)
  19108. + fprintf (dump_file, ";; The inner loop %d has HW-loop\n",
  19109. + loop->loop_no);
  19110. + return false;
  19111. + }
  19112. + }
  19113. + }
  19114. +
  19115. + /* Check inner loop have Hardware loop. */
  19116. + for (ix = 0; loop->loops.iterate (ix, &inner); ix++)
  19117. + {
  19118. + if ((loop->loop_no != inner->loop_no)
  19119. + && !inner->bad)
  19120. + {
  19121. + if (dump_file)
  19122. + fprintf (dump_file, ";; Inner loop %d have HW-loop in loop: %d\n",
  19123. + inner->loop_no, loop->loop_no);
  19124. + return false;
  19125. + }
  19126. + }
  19127. +
  19128. + /* Check outer loop have Hardware loop. */
  19129. + for (ix = 0; loop->outermost->loops.iterate (ix, &inner); ix++)
  19130. + {
  19131. + if ((loop->loop_no != inner->loop_no)
  19132. + && !inner->bad)
  19133. + {
  19134. + if (dump_file)
  19135. + {
  19136. + fprintf (dump_file, ";;loop %d depth: %d",
  19137. + loop->loop_no, loop->depth);
  19138. + fprintf (dump_file, " inner %d depth %d\n",
  19139. + inner->loop_no, inner->real_depth);
  19140. + }
  19141. + return false;
  19142. + }
  19143. + }
  19144. +
  19145. + /* Check same loop depth in nesting loop. */
  19146. + for (ix = 0; loop->outermost->loops.iterate (ix, &inner); ix++)
  19147. + {
  19148. + /* Check real_depth same other loop real_depth. */
  19149. + if ((loop->loop_no != inner->loop_no)
  19150. + && (loop->real_depth == inner->real_depth))
  19151. + same_depth_p = true;
  19152. +
  19153. + if (dump_file)
  19154. + {
  19155. + fprintf (dump_file, ";;loop %d depth: %d",
  19156. + loop->loop_no, loop->depth);
  19157. + fprintf (dump_file, " inner %d depth %d\n",
  19158. + inner->loop_no, inner->real_depth);
  19159. + }
  19160. + }
  19161. +
  19162. + /* In all other cases, try to replace a bad last insn with a nop. */
  19163. + if (JUMP_P (last_insn)
  19164. + || CALL_P (last_insn)
  19165. + || recog_memoized (last_insn) == CODE_FOR_return_internal
  19166. + || GET_CODE (PATTERN (last_insn)) == ASM_INPUT
  19167. + || asm_noperands (PATTERN (last_insn)) >= 0)
  19168. + {
  19169. + if (dump_file)
  19170. + fprintf (dump_file, ";; loop %d has bad last insn; replace with nop\n",
  19171. + loop->loop_no);
  19172. + last_insn = emit_insn_after (gen_unspec_nop (), last_insn);
  19173. + }
  19174. +
  19175. + loop->last_insn = last_insn;
  19176. +
  19177. + /* The loop is good for replacement. */
  19178. + start_label = loop->start_label;
  19179. + end_label = gen_label_rtx ();
  19180. + iter_reg = loop->iter_reg;
  19181. +
  19182. + lb_reg = gen_rtx_REG (SImode, LB_REGNUM);
  19183. + le_reg = gen_rtx_REG (SImode, LE_REGNUM);
  19184. + lc_reg = gen_rtx_REG (SImode, LC_REGNUM);
  19185. + SET_REGNO_REG_SET (loop->regs_set_in_loop, LC_REGNUM);
  19186. +
  19187. + loop->end_label = end_label;
  19188. +
  19189. + /* Create a sequence containing the loop setup. */
  19190. + start_sequence ();
  19191. +
  19192. + if (loop->loop_no == loop->outermost->loop_no
  19193. + || same_depth_p)
  19194. + {
  19195. + /* Insert start place for LB. */
  19196. + emit_insn (gen_mtlbi (gen_rtx_LABEL_REF (Pmode, start_label)));
  19197. + /* Insert end place for LE. */
  19198. + emit_insn (gen_mtlei (gen_rtx_LABEL_REF (Pmode, end_label)));
  19199. +
  19200. + emit_insn (gen_rtx_USE (SImode, lb_reg));
  19201. + emit_insn (gen_rtx_USE (SImode, le_reg));
  19202. + }
  19203. +
  19204. + /* Insert counter for LC. */
  19205. + emit_move_insn (lc_reg, iter_reg);
  19206. + emit_insn (gen_rtx_USE (SImode, lc_reg));
  19207. +
  19208. + /* Insert ISB instruction. */
  19209. + seq_end = emit_insn (gen_unspec_volatile_isb ());
  19210. +
  19211. + if (dump_file)
  19212. + {
  19213. + fprintf (dump_file, ";; replacing loop %d initializer with\n",
  19214. + loop->loop_no);
  19215. + print_rtl_single (dump_file, seq_end);
  19216. + fprintf (dump_file, ";; replacing loop %d terminator with\n",
  19217. + loop->loop_no);
  19218. + print_rtl_single (dump_file, loop->loop_end);
  19219. + }
  19220. +
  19221. + seq = get_insns ();
  19222. + end_sequence ();
  19223. +
  19224. + if (loop->incoming_src)
  19225. + {
  19226. + rtx prev = BB_END (loop->incoming_src);
  19227. + emit_insn_after (seq, prev);
  19228. + }
  19229. + else
  19230. + {
  19231. + basic_block new_bb;
  19232. + edge e;
  19233. + edge_iterator ei;
  19234. +
  19235. + emit_insn_before (seq, BB_HEAD (loop->head));
  19236. + seq = emit_label_before (gen_label_rtx (), seq);
  19237. +
  19238. + new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb);
  19239. + FOR_EACH_EDGE (e, ei, loop->incoming)
  19240. + {
  19241. + if (!(e->flags & EDGE_FALLTHRU)
  19242. + || e->dest != loop->head)
  19243. + redirect_edge_and_branch_force (e, new_bb);
  19244. + else
  19245. + redirect_edge_succ (e, new_bb);
  19246. + }
  19247. + e = make_edge (new_bb, loop->head, 0);
  19248. + }
  19249. +
  19250. + delete_insn (loop->loop_end);
  19251. + /* Insert the loop end label before the last instruction of the loop. */
  19252. + emit_label_before (loop->end_label, loop->last_insn);
  19253. +
  19254. + /* The last_insn don't do ifcall. */
  19255. + if (TARGET_IFC)
  19256. + {
  19257. + emit_insn_before (gen_no_ifc_begin (), loop->last_insn);
  19258. + emit_insn_after (gen_no_ifc_end (), loop->last_insn);
  19259. + }
  19260. +
  19261. + /* The last_insn don't do ex9. */
  19262. + if (TARGET_EX9)
  19263. + {
  19264. + emit_insn_before (gen_no_ex9_begin (), loop->last_insn);
  19265. + emit_insn_after (gen_no_ex9_end (), loop->last_insn);
  19266. + }
  19267. +
  19268. + if (loop->loop_no != loop->outermost->loop_no
  19269. + && !same_depth_p)
  19270. + {
  19271. + start_sequence ();
  19272. + /* Insert start place for LB. */
  19273. + emit_insn (gen_mtlbi (gen_rtx_LABEL_REF (Pmode, start_label)));
  19274. + /* Insert end place for LE. */
  19275. + emit_insn (gen_mtlei (gen_rtx_LABEL_REF (Pmode, end_label)));
  19276. +
  19277. + emit_insn (gen_rtx_USE (SImode, lb_reg));
  19278. + seq_end = emit_insn (gen_rtx_USE (SImode, le_reg));
  19279. +
  19280. + seq = get_insns ();
  19281. + end_sequence ();
  19282. +
  19283. + if (loop->outermost->incoming_src)
  19284. + {
  19285. + rtx prev = BB_END (loop->outermost->incoming_src);
  19286. + if (vec_safe_length (loop->outermost->incoming) > 1
  19287. + || !(loop->outermost->incoming->last ()->flags & EDGE_FALLTHRU))
  19288. + {
  19289. + gcc_assert (JUMP_P (prev));
  19290. + prev = PREV_INSN (prev);
  19291. + }
  19292. + emit_insn_after (seq, prev);
  19293. + }
  19294. + else
  19295. + {
  19296. + basic_block outer_new_bb;
  19297. + edge outer_e;
  19298. + edge_iterator outer_ei;
  19299. +
  19300. + emit_insn_before (seq, BB_HEAD (loop->outermost->head));
  19301. + seq = emit_label_before (gen_label_rtx (), seq);
  19302. +
  19303. + outer_new_bb = create_basic_block (seq, seq_end,
  19304. + loop->outermost->head->prev_bb);
  19305. + FOR_EACH_EDGE (outer_e, outer_ei, loop->outermost->incoming)
  19306. + {
  19307. + if (!(outer_e->flags & EDGE_FALLTHRU)
  19308. + || outer_e->dest != loop->outermost->head)
  19309. + redirect_edge_and_branch_force (outer_e, outer_new_bb);
  19310. + else
  19311. + redirect_edge_succ (outer_e, outer_new_bb);
  19312. + }
  19313. + outer_e = make_edge (outer_new_bb, loop->outermost->head, 0);
  19314. + }
  19315. + }
  19316. + return true;
  19317. +}
  19318. +
  19319. +/* A callback for the hw-doloop pass. Called when a loop we have discovered
  19320. + turns out not to be optimizable; we have to split the doloop_end pattern
  19321. + into a subtract and a test. */
  19322. +static void
  19323. +hwloop_fail (hwloop_info loop)
  19324. +{
  19325. + rtx test;
  19326. + rtx insn = loop->loop_end;
  19327. +
  19328. + emit_insn_before (gen_addsi3 (loop->iter_reg,
  19329. + loop->iter_reg,
  19330. + constm1_rtx),
  19331. + loop->loop_end);
  19332. +
  19333. + test = gen_rtx_NE (VOIDmode, loop->iter_reg, const0_rtx);
  19334. + insn = emit_jump_insn_before (gen_cbranchsi4 (test,
  19335. + loop->iter_reg, const0_rtx,
  19336. + loop->start_label),
  19337. + loop->loop_end);
  19338. +
  19339. + JUMP_LABEL (insn) = loop->start_label;
  19340. + LABEL_NUSES (loop->start_label)++;
  19341. + delete_insn (loop->loop_end);
  19342. +}
  19343. +
  19344. +static struct hw_doloop_hooks nds32_doloop1_hooks =
  19345. +{
  19346. + hwloop_pattern_reg,
  19347. + hwloop1_optimize,
  19348. + hwloop_fail
  19349. +};
  19350. +
  19351. +static struct hw_doloop_hooks nds32_doloop2_hooks =
  19352. +{
  19353. + hwloop_pattern_reg,
  19354. + hwloop2_optimize,
  19355. + hwloop_fail
  19356. +};
  19357. +
  19358. +/* This pass looks for doloop_end insns and tries to rewrite the RTL
  19359. + of these loops so that proper NDS32 hardware loops are generated. */
  19360. +static unsigned int
  19361. +nds32_hwloop1 (void)
  19362. +{
  19363. + compute_bb_for_insn ();
  19364. + reorg_loops (false, &nds32_doloop1_hooks);
  19365. + return 1;
  19366. +}
  19367. +
  19368. +const pass_data pass_data_nds32_hwloop1_opt =
  19369. +{
  19370. + RTL_PASS, /* type */
  19371. + "hwloop1_opt", /* name */
  19372. + OPTGROUP_NONE, /* optinfo_flags */
  19373. + true, /* has_gate */
  19374. + true, /* has_execute */
  19375. + TV_MACH_DEP, /* tv_id */
  19376. + 0, /* properties_required */
  19377. + 0, /* properties_provided */
  19378. + 0, /* properties_destroyed */
  19379. + 0, /* todo_flags_start */
  19380. + ( TODO_df_finish | TODO_verify_rtl_sharing), /* todo_flags_finish */
  19381. +};
  19382. +
  19383. +class pass_nds32_hwloop1_opt : public rtl_opt_pass
  19384. +{
  19385. +public:
  19386. + pass_nds32_hwloop1_opt (gcc::context *ctxt)
  19387. + : rtl_opt_pass (pass_data_nds32_hwloop1_opt, ctxt)
  19388. + {}
  19389. +
  19390. + /* opt_pass methods: */
  19391. + bool gate () { return NDS32_HW_LOOP_P(); }
  19392. + unsigned int execute () { return nds32_hwloop1 (); }
  19393. +};
  19394. +
  19395. +rtl_opt_pass *
  19396. +make_pass_nds32_hwloop1_opt (gcc::context *ctxt)
  19397. +{
  19398. + return new pass_nds32_hwloop1_opt (ctxt);
  19399. +}
  19400. +
  19401. +/* This pass looks for doloop_end insns and tries to rewrite the RTL
  19402. + of these loops so that proper NDS32 hardware loops are generated. */
  19403. +static unsigned int
  19404. +nds32_hwloop2 (void)
  19405. +{
  19406. + compute_bb_for_insn ();
  19407. + reorg_loops (false, &nds32_doloop2_hooks);
  19408. + return 1;
  19409. +}
  19410. +
  19411. +const pass_data pass_data_nds32_hwloop2_opt =
  19412. +{
  19413. + RTL_PASS, /* type */
  19414. + "hwloop2_opt", /* name */
  19415. + OPTGROUP_NONE, /* optinfo_flags */
  19416. + true, /* has_gate */
  19417. + true, /* has_execute */
  19418. + TV_MACH_DEP, /* tv_id */
  19419. + 0, /* properties_required */
  19420. + 0, /* properties_provided */
  19421. + 0, /* properties_destroyed */
  19422. + 0, /* todo_flags_start */
  19423. + ( TODO_df_finish | TODO_verify_rtl_sharing), /* todo_flags_finish */
  19424. +};
  19425. +
  19426. +class pass_nds32_hwloop2_opt : public rtl_opt_pass
  19427. +{
  19428. +public:
  19429. + pass_nds32_hwloop2_opt (gcc::context *ctxt)
  19430. + : rtl_opt_pass (pass_data_nds32_hwloop2_opt, ctxt)
  19431. + {}
  19432. +
  19433. + /* opt_pass methods: */
  19434. + bool gate () { return NDS32_HW_LOOP_P(); }
  19435. + unsigned int execute () { return nds32_hwloop2 (); }
  19436. +};
  19437. +
  19438. +rtl_opt_pass *
  19439. +make_pass_nds32_hwloop2_opt (gcc::context *ctxt)
  19440. +{
  19441. + return new pass_nds32_hwloop2_opt (ctxt);
  19442. +}
  19443. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32_init.inc gcc-4.9.4/gcc/config/nds32/nds32_init.inc
  19444. --- gcc-4.9.4.orig/gcc/config/nds32/nds32_init.inc 1970-01-01 01:00:00.000000000 +0100
  19445. +++ gcc-4.9.4/gcc/config/nds32/nds32_init.inc 2016-08-08 20:37:45.590273343 +0200
  19446. @@ -0,0 +1,43 @@
  19447. +/*
  19448. + * nds32_init.inc
  19449. + *
  19450. + * NDS32 architecture startup assembler header file
  19451. + *
  19452. + */
  19453. +
  19454. +.macro nds32_init
  19455. +
  19456. + ! Initialize GP for data access
  19457. + la $gp, _SDA_BASE_
  19458. +
  19459. +#if defined(__NDS32_EXT_EX9__)
  19460. + ! Check HW for EX9
  19461. + mfsr $r0, $MSC_CFG
  19462. + li $r1, (1 << 24)
  19463. + and $r2, $r0, $r1
  19464. + beqz $r2, 1f
  19465. +
  19466. + ! Initialize the table base of EX9 instruction
  19467. + la $r0, _ITB_BASE_
  19468. + mtusr $r0, $ITB
  19469. +1:
  19470. +#endif
  19471. +
  19472. +#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__)
  19473. + ! Enable FPU
  19474. + mfsr $r0, $FUCOP_CTL
  19475. + ori $r0, $r0, #0x1
  19476. + mtsr $r0, $FUCOP_CTL
  19477. + dsb
  19478. +
  19479. + ! Enable denormalized flush-to-Zero mode
  19480. + fmfcsr $r0
  19481. + ori $r0,$r0,#0x1000
  19482. + fmtcsr $r0
  19483. + dsb
  19484. +#endif
  19485. +
  19486. + ! Initialize default stack pointer
  19487. + la $sp, _stack
  19488. +
  19489. +.endm
  19490. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-intrinsic.c gcc-4.9.4/gcc/config/nds32/nds32-intrinsic.c
  19491. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-intrinsic.c 1970-01-01 01:00:00.000000000 +0100
  19492. +++ gcc-4.9.4/gcc/config/nds32/nds32-intrinsic.c 2016-08-08 20:37:45.502269936 +0200
  19493. @@ -0,0 +1,1858 @@
  19494. +/* Intrinsic functions of Andes NDS32 cpu for GNU compiler
  19495. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  19496. + Contributed by Andes Technology Corporation.
  19497. +
  19498. + This file is part of GCC.
  19499. +
  19500. + GCC is free software; you can redistribute it and/or modify it
  19501. + under the terms of the GNU General Public License as published
  19502. + by the Free Software Foundation; either version 3, or (at your
  19503. + option) any later version.
  19504. +
  19505. + GCC is distributed in the hope that it will be useful, but WITHOUT
  19506. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  19507. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19508. + License for more details.
  19509. +
  19510. + You should have received a copy of the GNU General Public License
  19511. + along with GCC; see the file COPYING3. If not see
  19512. + <http://www.gnu.org/licenses/>. */
  19513. +
  19514. +/* ------------------------------------------------------------------------ */
  19515. +
  19516. +#include "config.h"
  19517. +#include "system.h"
  19518. +#include "coretypes.h"
  19519. +#include "tm.h"
  19520. +#include "tree.h"
  19521. +#include "rtl.h"
  19522. +#include "regs.h"
  19523. +#include "hard-reg-set.h"
  19524. +#include "insn-config.h" /* Required by recog.h. */
  19525. +#include "conditions.h"
  19526. +#include "output.h"
  19527. +#include "insn-attr.h" /* For DFA state_t. */
  19528. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  19529. +#include "reload.h" /* For push_reload(). */
  19530. +#include "flags.h"
  19531. +#include "function.h"
  19532. +#include "expr.h"
  19533. +#include "recog.h"
  19534. +#include "diagnostic-core.h"
  19535. +#include "df.h"
  19536. +#include "tm_p.h"
  19537. +#include "tm-constrs.h"
  19538. +#include "optabs.h" /* For GEN_FCN. */
  19539. +#include "target.h"
  19540. +#include "target-def.h"
  19541. +#include "langhooks.h" /* For def_builtin(). */
  19542. +#include "ggc.h"
  19543. +#include "stor-layout.h"
  19544. +
  19545. +/* ------------------------------------------------------------------------ */
  19546. +
  19547. +/* Read the requested argument from the EXP given by INDEX.
  19548. + Return the value as an rtx. */
  19549. +static rtx
  19550. +nds32_read_argument (tree exp, unsigned int index)
  19551. +{
  19552. + return expand_normal (CALL_EXPR_ARG (exp, index));
  19553. +}
  19554. +
  19555. +/* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
  19556. + if it's not null, has the right mode, and satisfies operand 0's
  19557. + predicate. */
  19558. +static rtx
  19559. +nds32_legitimize_target (enum insn_code icode, rtx target)
  19560. +{
  19561. + enum machine_mode mode = insn_data[icode].operand[0].mode;
  19562. +
  19563. + if (! target
  19564. + || GET_MODE (target) != mode
  19565. + || ! (*insn_data[icode].operand[0].predicate) (target, mode))
  19566. + return gen_reg_rtx (mode);
  19567. + else
  19568. + return target;
  19569. +}
  19570. +
  19571. +/* Given that ARG is being passed as operand OPNUM to instruction ICODE,
  19572. + check whether ARG satisfies the operand's constraints. If it doesn't,
  19573. + copy ARG to a temporary register and return that. Otherwise return ARG
  19574. + itself. */
  19575. +static rtx
  19576. +nds32_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
  19577. +{
  19578. + enum machine_mode mode = insn_data[icode].operand[opnum].mode;
  19579. +
  19580. + if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
  19581. + return arg;
  19582. + else if (VECTOR_MODE_P (mode) && CONST_INT_P (arg))
  19583. + {
  19584. + /* Handle CONST_INT covert to CONST_VECTOR. */
  19585. + int nunits = GET_MODE_NUNITS (mode);
  19586. + int i, shift = 0;
  19587. + rtvec v = rtvec_alloc (nunits);
  19588. + int val = INTVAL (arg);
  19589. + enum machine_mode val_mode = (mode == V4QImode) ? QImode : HImode;
  19590. + int shift_acc = (val_mode == QImode) ? 8 : 16;
  19591. + int mask = (val_mode == QImode) ? 0xff : 0xffff;
  19592. + int tmp_val = val;
  19593. +
  19594. + if (TARGET_BIG_ENDIAN)
  19595. + for (i = 0; i < nunits; i++)
  19596. + {
  19597. + tmp_val = (val >> shift) & mask;
  19598. + RTVEC_ELT (v, nunits - i - 1) = gen_int_mode (tmp_val, val_mode);
  19599. + shift += shift_acc;
  19600. + }
  19601. + else
  19602. + for (i = 0; i < nunits; i++)
  19603. + {
  19604. + tmp_val = (val >> shift) & mask;
  19605. + RTVEC_ELT (v, i) = gen_int_mode (tmp_val, val_mode);
  19606. + shift += shift_acc;
  19607. + }
  19608. +
  19609. + return copy_to_mode_reg (mode, gen_rtx_CONST_VECTOR (mode, v));
  19610. + }
  19611. + else if (VECTOR_MODE_P (mode)
  19612. + && !VECTOR_MODE_P (GET_MODE (arg)))
  19613. + {
  19614. + /* Handle non-Vector mode copy to Vector. */
  19615. + rtx tmp_rtx = gen_reg_rtx (mode);
  19616. + convert_move (tmp_rtx, arg, false);
  19617. + return tmp_rtx;
  19618. + }
  19619. + else
  19620. + return copy_to_mode_reg (mode, arg);
  19621. +}
  19622. +
  19623. +/* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
  19624. + The instruction should require a constant operand of some sort. The
  19625. + function prints an error if OPVAL is not valid. */
  19626. +static int
  19627. +nds32_check_constant_argument (enum insn_code icode, int opnum, rtx opval,
  19628. + const char *name)
  19629. +{
  19630. + if (GET_CODE (opval) != CONST_INT)
  19631. + {
  19632. + error ("invalid argument to built-in function %s", name);
  19633. + return false;
  19634. + }
  19635. + if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
  19636. + {
  19637. + error ("constant argument out of range for %s", name);
  19638. +
  19639. + return false;
  19640. + }
  19641. + return true;
  19642. +}
  19643. +
  19644. +/* Expand builtins that return target. */
  19645. +static rtx
  19646. +nds32_expand_noarg_builtin (enum insn_code icode, rtx target)
  19647. +{
  19648. + rtx pat;
  19649. +
  19650. + target = nds32_legitimize_target (icode, target);
  19651. +
  19652. + /* Emit and return the new instruction. */
  19653. + pat = GEN_FCN (icode) (target);
  19654. + if (! pat)
  19655. + return NULL_RTX;
  19656. +
  19657. + emit_insn (pat);
  19658. + return target;
  19659. +}
  19660. +
  19661. +/* Expand builtins that take one operand. */
  19662. +static rtx
  19663. +nds32_expand_unop_builtin (enum insn_code icode, tree exp, rtx target,
  19664. + bool return_p)
  19665. +{
  19666. + rtx pat;
  19667. + rtx op0 = nds32_read_argument (exp, 0);
  19668. + int op0_num = return_p ? 1 : 0;
  19669. +
  19670. + if (return_p)
  19671. + target = nds32_legitimize_target (icode, target);
  19672. +
  19673. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19674. +
  19675. + /* Emit and return the new instruction. */
  19676. + if (return_p)
  19677. + pat = GEN_FCN (icode) (target, op0);
  19678. + else
  19679. + pat = GEN_FCN (icode) (op0);
  19680. +
  19681. + if (! pat)
  19682. + return NULL_RTX;
  19683. +
  19684. + emit_insn (pat);
  19685. + return target;
  19686. +}
  19687. +
  19688. +/* Expand builtins that take one operands and the first is immediate. */
  19689. +static rtx
  19690. +nds32_expand_unopimm_builtin (enum insn_code icode, tree exp, rtx target,
  19691. + bool return_p, const char *name)
  19692. +{
  19693. + rtx pat;
  19694. + rtx op0 = nds32_read_argument (exp, 0);
  19695. + int op0_num = return_p ? 1 : 0;
  19696. +
  19697. + if (return_p)
  19698. + target = nds32_legitimize_target (icode, target);
  19699. +
  19700. + if (!nds32_check_constant_argument (icode, op0_num, op0, name))
  19701. + return NULL_RTX;
  19702. +
  19703. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19704. +
  19705. + /* Emit and return the new instruction. */
  19706. + if (return_p)
  19707. + pat = GEN_FCN (icode) (target, op0);
  19708. + else
  19709. + pat = GEN_FCN (icode) (op0);
  19710. +
  19711. + if (! pat)
  19712. + return NULL_RTX;
  19713. +
  19714. + emit_insn (pat);
  19715. + return target;
  19716. +}
  19717. +
  19718. +/* Expand builtins that take two operands. */
  19719. +static rtx
  19720. +nds32_expand_binop_builtin (enum insn_code icode, tree exp, rtx target,
  19721. + bool return_p)
  19722. +{
  19723. + rtx pat;
  19724. + rtx op0 = nds32_read_argument (exp, 0);
  19725. + rtx op1 = nds32_read_argument (exp, 1);
  19726. + int op0_num = return_p ? 1 : 0;
  19727. + int op1_num = return_p ? 2 : 1;
  19728. +
  19729. + if (return_p)
  19730. + target = nds32_legitimize_target (icode, target);
  19731. +
  19732. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19733. + op1 = nds32_legitimize_argument (icode, op1_num, op1);
  19734. +
  19735. + /* Emit and return the new instruction. */
  19736. + if (return_p)
  19737. + pat = GEN_FCN (icode) (target, op0, op1);
  19738. + else
  19739. + pat = GEN_FCN (icode) (op0, op1);
  19740. +
  19741. + if (! pat)
  19742. + return NULL_RTX;
  19743. +
  19744. + emit_insn (pat);
  19745. + return target;
  19746. +}
  19747. +
  19748. +/* Expand builtins that take two operands and the second is immediate. */
  19749. +static rtx
  19750. +nds32_expand_binopimm_builtin (enum insn_code icode, tree exp, rtx target,
  19751. + bool return_p, const char *name)
  19752. +{
  19753. + rtx pat;
  19754. + rtx op0 = nds32_read_argument (exp, 0);
  19755. + rtx op1 = nds32_read_argument (exp, 1);
  19756. + int op0_num = return_p ? 1 : 0;
  19757. + int op1_num = return_p ? 2 : 1;
  19758. +
  19759. + if (return_p)
  19760. + target = nds32_legitimize_target (icode, target);
  19761. +
  19762. + if (!nds32_check_constant_argument (icode, op1_num, op1, name))
  19763. + return NULL_RTX;
  19764. +
  19765. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19766. + op1 = nds32_legitimize_argument (icode, op1_num, op1);
  19767. +
  19768. + /* Emit and return the new instruction. */
  19769. + if (return_p)
  19770. + pat = GEN_FCN (icode) (target, op0, op1);
  19771. + else
  19772. + pat = GEN_FCN (icode) (op0, op1);
  19773. +
  19774. + if (! pat)
  19775. + return NULL_RTX;
  19776. +
  19777. + emit_insn (pat);
  19778. + return target;
  19779. +}
  19780. +
  19781. +/* Expand builtins that take three operands. */
  19782. +static rtx
  19783. +nds32_expand_triop_builtin (enum insn_code icode, tree exp, rtx target,
  19784. + bool return_p)
  19785. +{
  19786. + rtx pat;
  19787. + rtx op0 = nds32_read_argument (exp, 0);
  19788. + rtx op1 = nds32_read_argument (exp, 1);
  19789. + rtx op2 = nds32_read_argument (exp, 2);
  19790. + int op0_num = return_p ? 1 : 0;
  19791. + int op1_num = return_p ? 2 : 1;
  19792. + int op2_num = return_p ? 3 : 2;
  19793. +
  19794. + if (return_p)
  19795. + target = nds32_legitimize_target (icode, target);
  19796. +
  19797. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19798. + op1 = nds32_legitimize_argument (icode, op1_num, op1);
  19799. + op2 = nds32_legitimize_argument (icode, op2_num, op2);
  19800. +
  19801. + /* Emit and return the new instruction. */
  19802. + if (return_p)
  19803. + pat = GEN_FCN (icode) (target, op0, op1, op2);
  19804. + else
  19805. + pat = GEN_FCN (icode) (op0, op1, op2);
  19806. +
  19807. + if (! pat)
  19808. + return NULL_RTX;
  19809. +
  19810. + emit_insn (pat);
  19811. + return target;
  19812. +}
  19813. +
  19814. +/* Expand builtins that take three operands and the third is immediate. */
  19815. +static rtx
  19816. +nds32_expand_triopimm_builtin (enum insn_code icode, tree exp, rtx target,
  19817. + bool return_p, const char *name)
  19818. +{
  19819. + rtx pat;
  19820. + rtx op0 = nds32_read_argument (exp, 0);
  19821. + rtx op1 = nds32_read_argument (exp, 1);
  19822. + rtx op2 = nds32_read_argument (exp, 2);
  19823. + int op0_num = return_p ? 1 : 0;
  19824. + int op1_num = return_p ? 2 : 1;
  19825. + int op2_num = return_p ? 3 : 2;
  19826. +
  19827. + if (return_p)
  19828. + target = nds32_legitimize_target (icode, target);
  19829. +
  19830. + if (!nds32_check_constant_argument (icode, op2_num, op2, name))
  19831. + return NULL_RTX;
  19832. +
  19833. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19834. + op1 = nds32_legitimize_argument (icode, op1_num, op1);
  19835. + op2 = nds32_legitimize_argument (icode, op2_num, op2);
  19836. +
  19837. + /* Emit and return the new instruction. */
  19838. + if (return_p)
  19839. + pat = GEN_FCN (icode) (target, op0, op1, op2);
  19840. + else
  19841. + pat = GEN_FCN (icode) (op0, op1, op2);
  19842. +
  19843. + if (! pat)
  19844. + return NULL_RTX;
  19845. +
  19846. + emit_insn (pat);
  19847. + return target;
  19848. +}
  19849. +
  19850. +/* Expand builtins for load. */
  19851. +static rtx
  19852. +nds32_expand_builtin_load (enum insn_code icode, tree exp, rtx target)
  19853. +{
  19854. + /* Load address format is [$ra + $rb],
  19855. + but input arguments not enough,
  19856. + so we need another temp register as $rb.
  19857. + Generating assembly code:
  19858. + movi $temp, 0
  19859. + llw $rt, [$ra + $temp] */
  19860. + rtx pat;
  19861. + rtx op0 = nds32_read_argument (exp, 0);
  19862. + rtx addr_helper = gen_reg_rtx (insn_data[icode].operand[1].mode);
  19863. +
  19864. + target = nds32_legitimize_target (icode, target);
  19865. + op0 = nds32_legitimize_argument (icode, 1, op0);
  19866. +
  19867. + /* Emit and return the new instruction. */
  19868. + pat = GEN_FCN (icode) (target, op0, addr_helper);
  19869. + if (!pat)
  19870. + return NULL_RTX;
  19871. +
  19872. + emit_move_insn (addr_helper, GEN_INT (0));
  19873. + emit_insn (pat);
  19874. + return target;
  19875. +}
  19876. +
  19877. +/* Expand builtins for store. */
  19878. +static rtx
  19879. +nds32_expand_builtin_store (enum insn_code icode, tree exp, rtx target)
  19880. +{
  19881. + /* Store address format is [$ra + $rb],
  19882. + but input arguments not enough,
  19883. + so we need another temp register as $rb.
  19884. + Generating assembly code:
  19885. + movi $temp, 0
  19886. + store $rt, [$ra + $temp] */
  19887. + rtx pat;
  19888. + rtx op0 = nds32_read_argument (exp, 0);
  19889. + rtx op1 = nds32_read_argument (exp, 1);
  19890. + rtx addr_helper = gen_reg_rtx (insn_data[icode].operand[1].mode);
  19891. +
  19892. + op0 = nds32_legitimize_argument (icode, 0, op0);
  19893. + op1 = nds32_legitimize_argument (icode, 2, op1);
  19894. +
  19895. + /* Emit and return the new instruction. */
  19896. + pat = GEN_FCN (icode) (op0, addr_helper, op1);
  19897. + if (! pat)
  19898. + return NULL_RTX;
  19899. +
  19900. + emit_move_insn (addr_helper, GEN_INT (0));
  19901. + emit_insn (pat);
  19902. + return target;
  19903. +}
  19904. +
  19905. +/* Expand cctl builtins. */
  19906. +static rtx
  19907. +nds32_expand_cctl_builtin (enum insn_code icode, tree exp, rtx target,
  19908. + bool return_p, const char *name)
  19909. +{
  19910. + rtx pat;
  19911. + rtx op0 = nds32_read_argument (exp, 0);
  19912. + rtx op1 = nds32_read_argument (exp, 1);
  19913. + int op0_num = return_p ? 1 : 0;
  19914. + int op1_num = return_p ? 2 : 1;
  19915. +
  19916. + if (return_p)
  19917. + target = nds32_legitimize_target (icode, target);
  19918. +
  19919. + if (!nds32_check_constant_argument (icode, op0_num, op0, name))
  19920. + return NULL_RTX;
  19921. +
  19922. + op0 = nds32_legitimize_argument (icode, op0_num, op0);
  19923. + op1 = nds32_legitimize_argument (icode, op1_num, op1);
  19924. +
  19925. + /* Emit and return the new instruction. */
  19926. + if (icode == CODE_FOR_cctl_idx_write)
  19927. + {
  19928. + /* cctl_idx_write is three argument,
  19929. + so create operand2 for cctl_idx_write pattern. */
  19930. + rtx op2 = nds32_read_argument (exp, 2);
  19931. + op2 = nds32_legitimize_argument (icode, 2, op2);
  19932. + pat = GEN_FCN (icode) (op0, op1, op2);
  19933. + }
  19934. + else if (return_p)
  19935. + pat = GEN_FCN (icode) (target, op0, op1);
  19936. + else
  19937. + pat = GEN_FCN (icode) (op0, op1);
  19938. +
  19939. + if (! pat)
  19940. + return NULL_RTX;
  19941. +
  19942. + emit_insn (pat);
  19943. + return target;
  19944. +}
  19945. +
  19946. +/* Expand scw builtins. */
  19947. +static rtx
  19948. +nds32_expand_scw_builtin (enum insn_code icode, tree exp, rtx target)
  19949. +{
  19950. + /* SCW address format is [$ra + $rb], but input arguments not enough,
  19951. + so we need another temp register as $rb.
  19952. + Generating assembly code:
  19953. + movi $temp, 0
  19954. + scw $rt, [$ra + $temp] */
  19955. + rtx pat;
  19956. + rtx op0 = nds32_read_argument (exp, 0);
  19957. + rtx op1 = nds32_read_argument (exp, 1);
  19958. + rtx addr_helper = gen_reg_rtx (insn_data[icode].operand[1].mode);
  19959. +
  19960. + target = nds32_legitimize_target (icode, target);
  19961. + op0 = nds32_legitimize_argument (icode, 1, op0);
  19962. + op1 = nds32_legitimize_argument (icode, 2, op1);
  19963. +
  19964. + /* Emit and return the new instruction. */
  19965. + pat = GEN_FCN (icode) (target, op0, addr_helper, target);
  19966. +
  19967. + if (!pat)
  19968. + return NULL_RTX;
  19969. +
  19970. + emit_move_insn (addr_helper, GEN_INT (0));
  19971. + emit_move_insn (target, op1);
  19972. + emit_insn (pat);
  19973. + return target;
  19974. +}
  19975. +
  19976. +/* Expand set int priority builtins. */
  19977. +static rtx
  19978. +nds32_expand_priority_builtin (enum insn_code icode, tree exp, rtx target,
  19979. + const char *name)
  19980. +{
  19981. + rtx pat;
  19982. + rtx op0 = nds32_read_argument (exp, 0);
  19983. + rtx op1 = nds32_read_argument (exp, 1);
  19984. +
  19985. + /* set_int_priority intrinsic function that two arguments are immediate,
  19986. + so check whether auguments are immedite. */
  19987. +
  19988. + if (!nds32_check_constant_argument (icode, 0, op0, name))
  19989. + return NULL_RTX;
  19990. +
  19991. + if (!nds32_check_constant_argument (icode, 1, op1, name))
  19992. + return NULL_RTX;
  19993. +
  19994. + op0 = nds32_legitimize_argument (icode, 0, op0);
  19995. + op1 = nds32_legitimize_argument (icode, 1, op1);
  19996. +
  19997. + /* Emit and return the new instruction. */
  19998. + pat = GEN_FCN (icode) (op0, op1);
  19999. +
  20000. + if (! pat)
  20001. + return NULL_RTX;
  20002. +
  20003. + emit_insn (pat);
  20004. + return target;
  20005. +}
  20006. +
  20007. +struct builtin_description
  20008. +{
  20009. + const enum insn_code icode;
  20010. + const char *name;
  20011. + enum nds32_builtins code;
  20012. + bool return_p;
  20013. +};
  20014. +
  20015. +#define NDS32_BUILTIN(code, string, builtin) \
  20016. + { CODE_FOR_##code, "__nds32__" string, \
  20017. + NDS32_BUILTIN_##builtin, true },
  20018. +
  20019. +#define NDS32_NO_TARGET_BUILTIN(code, string, builtin) \
  20020. + { CODE_FOR_##code, "__nds32__" string, \
  20021. + NDS32_BUILTIN_##builtin, false },
  20022. +
  20023. +/* Intrinsics that no argument, and that return value. */
  20024. +static struct builtin_description bdesc_noarg[] =
  20025. +{
  20026. + NDS32_BUILTIN(unspec_fmfcfg, "fmfcfg", FMFCFG)
  20027. + NDS32_BUILTIN(unspec_fmfcsr, "fmfcsr", FMFCSR)
  20028. + NDS32_BUILTIN(unspec_rdov, "rdov", RDOV)
  20029. + NDS32_BUILTIN(unspec_get_current_sp, "get_current_sp", GET_CURRENT_SP)
  20030. + NDS32_BUILTIN(unspec_return_address, "return_address", RETURN_ADDRESS)
  20031. + NDS32_BUILTIN(unspec_get_all_pending_int, "get_all_pending_int",
  20032. + GET_ALL_PENDING_INT)
  20033. + NDS32_BUILTIN(unspec_unaligned_feature, "unaligned_feature",
  20034. + UNALIGNED_FEATURE)
  20035. + NDS32_NO_TARGET_BUILTIN(unspec_enable_unaligned, "enable_unaligned",
  20036. + ENABLE_UNALIGNED)
  20037. + NDS32_NO_TARGET_BUILTIN(unspec_disable_unaligned, "disable_unaligned",
  20038. + DISABLE_UNALIGNED)
  20039. +};
  20040. +
  20041. +/* Intrinsics that take just one argument. */
  20042. +static struct builtin_description bdesc_1arg[] =
  20043. +{
  20044. + NDS32_BUILTIN(unspec_ssabssi2, "abs", ABS)
  20045. + NDS32_BUILTIN(clzsi2, "clz", CLZ)
  20046. + NDS32_BUILTIN(unspec_clo, "clo", CLO)
  20047. + NDS32_BUILTIN(unspec_wsbh, "wsbh", WSBH)
  20048. + NDS32_BUILTIN(unspec_tlbop_pb, "tlbop_pb",TLBOP_PB)
  20049. + NDS32_BUILTIN(unaligned_load_hw, "unaligned_load_hw", UALOAD_HW)
  20050. + NDS32_BUILTIN(unaligned_loadsi, "unaligned_load_w", UALOAD_W)
  20051. + NDS32_BUILTIN(unaligned_loaddi, "unaligned_load_dw", UALOAD_DW)
  20052. + NDS32_NO_TARGET_BUILTIN(unspec_volatile_isync, "isync", ISYNC)
  20053. + NDS32_NO_TARGET_BUILTIN(unspec_fmtcsr, "fmtcsr", FMTCSR)
  20054. + NDS32_NO_TARGET_BUILTIN(unspec_jr_itoff, "jr_itoff", JR_ITOFF)
  20055. + NDS32_NO_TARGET_BUILTIN(unspec_jr_toff, "jr_toff", JR_TOFF)
  20056. + NDS32_NO_TARGET_BUILTIN(unspec_jral_ton, "jral_ton", JRAL_TON)
  20057. + NDS32_NO_TARGET_BUILTIN(unspec_ret_toff, "ret_toff", RET_TOFF)
  20058. + NDS32_NO_TARGET_BUILTIN(unspec_jral_iton, "jral_iton",JRAL_ITON)
  20059. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_trd, "tlbop_trd", TLBOP_TRD)
  20060. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_twr, "tlbop_twr", TLBOP_TWR)
  20061. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_rwr, "tlbop_rwr", TLBOP_RWR)
  20062. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_rwlk, "tlbop_rwlk", TLBOP_RWLK)
  20063. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_unlk, "tlbop_unlk", TLBOP_UNLK)
  20064. + NDS32_NO_TARGET_BUILTIN(unspec_tlbop_inv, "tlbop_inv", TLBOP_INV)
  20065. + NDS32_NO_TARGET_BUILTIN(unspec_ret_itoff, "ret_itoff", RET_ITOFF)
  20066. + NDS32_NO_TARGET_BUILTIN(unspec_set_current_sp,
  20067. + "set_current_sp", SET_CURRENT_SP)
  20068. + NDS32_BUILTIN(kabsv2hi2, "kabs16", KABS16)
  20069. + NDS32_BUILTIN(kabsv2hi2, "v_kabs16", V_KABS16)
  20070. + NDS32_BUILTIN(kabsv4qi2, "kabs8", KABS8)
  20071. + NDS32_BUILTIN(kabsv4qi2, "v_kabs8", V_KABS8)
  20072. + NDS32_BUILTIN(sunpkd810, "sunpkd810", SUNPKD810)
  20073. + NDS32_BUILTIN(sunpkd810, "v_sunpkd810", V_SUNPKD810)
  20074. + NDS32_BUILTIN(sunpkd820, "sunpkd820", SUNPKD820)
  20075. + NDS32_BUILTIN(sunpkd820, "v_sunpkd820", V_SUNPKD820)
  20076. + NDS32_BUILTIN(sunpkd830, "sunpkd830", SUNPKD830)
  20077. + NDS32_BUILTIN(sunpkd830, "v_sunpkd830", V_SUNPKD830)
  20078. + NDS32_BUILTIN(sunpkd831, "sunpkd831", SUNPKD831)
  20079. + NDS32_BUILTIN(sunpkd831, "v_sunpkd831", V_SUNPKD831)
  20080. + NDS32_BUILTIN(zunpkd810, "zunpkd810", ZUNPKD810)
  20081. + NDS32_BUILTIN(zunpkd810, "v_zunpkd810", V_ZUNPKD810)
  20082. + NDS32_BUILTIN(zunpkd820, "zunpkd820", ZUNPKD820)
  20083. + NDS32_BUILTIN(zunpkd820, "v_zunpkd820", V_ZUNPKD820)
  20084. + NDS32_BUILTIN(zunpkd830, "zunpkd830", ZUNPKD830)
  20085. + NDS32_BUILTIN(zunpkd830, "v_zunpkd830", V_ZUNPKD830)
  20086. + NDS32_BUILTIN(zunpkd831, "zunpkd831", ZUNPKD831)
  20087. + NDS32_BUILTIN(zunpkd831, "v_zunpkd831", V_ZUNPKD831)
  20088. + NDS32_BUILTIN(unspec_kabs, "kabs", KABS)
  20089. +};
  20090. +
  20091. +/* Intrinsics that take just one argument. and the argument is immediate. */
  20092. +static struct builtin_description bdesc_1argimm[] =
  20093. +{
  20094. + NDS32_BUILTIN(unspec_volatile_mfsr, "mfsr", MFSR)
  20095. + NDS32_BUILTIN(unspec_volatile_mfusr, "mfsr", MFUSR)
  20096. + NDS32_BUILTIN(unspec_get_pending_int, "get_pending_int", GET_PENDING_INT)
  20097. + NDS32_BUILTIN(unspec_get_int_priority, "get_int_priority", GET_INT_PRIORITY)
  20098. + NDS32_NO_TARGET_BUILTIN(unspec_trap, "trap", TRAP)
  20099. + NDS32_NO_TARGET_BUILTIN(unspec_break, "break", BREAK)
  20100. + NDS32_NO_TARGET_BUILTIN(unspec_syscall, "syscall", SYSCALL)
  20101. + NDS32_NO_TARGET_BUILTIN(unspec_enable_int, "enable_int", ENABLE_INT)
  20102. + NDS32_NO_TARGET_BUILTIN(unspec_disable_int, "disable_int", DISABLE_INT)
  20103. + NDS32_NO_TARGET_BUILTIN(unspec_clr_pending_hwint, "clr_pending_hwint",
  20104. + CLR_PENDING_HWINT)
  20105. + NDS32_NO_TARGET_BUILTIN(unspec_set_trig_level, "set_trig_level",
  20106. + SET_TRIG_LEVEL)
  20107. + NDS32_NO_TARGET_BUILTIN(unspec_set_trig_edge, "set_trig_edge",
  20108. + SET_TRIG_EDGE)
  20109. + NDS32_BUILTIN(unspec_get_trig_type, "get_trig_type", GET_TRIG_TYPE)
  20110. +};
  20111. +
  20112. +/* Intrinsics that take two arguments. */
  20113. +static struct builtin_description bdesc_2arg[] =
  20114. +{
  20115. + NDS32_BUILTIN(unspec_fcpynss, "fcpynss", FCPYNSS)
  20116. + NDS32_BUILTIN(unspec_fcpyss, "fcpyss", FCPYSS)
  20117. + NDS32_BUILTIN(unspec_fcpynsd, "fcpynsd", FCPYNSD)
  20118. + NDS32_BUILTIN(unspec_fcpysd, "fcpysd", FCPYSD)
  20119. + NDS32_BUILTIN(unspec_ave, "ave", AVE)
  20120. + NDS32_BUILTIN(unspec_pbsad, "pbsad", PBSAD)
  20121. + NDS32_BUILTIN(unspec_ffb, "ffb", FFB)
  20122. + NDS32_BUILTIN(unspec_ffmism, "ffmsim", FFMISM)
  20123. + NDS32_BUILTIN(unspec_flmism, "flmism", FLMISM)
  20124. + NDS32_BUILTIN(unspec_kaddw, "kaddw", KADDW)
  20125. + NDS32_BUILTIN(unspec_kaddh, "kaddh", KADDH)
  20126. + NDS32_BUILTIN(unspec_ksubw, "ksubw", KSUBW)
  20127. + NDS32_BUILTIN(unspec_ksubh, "ksubh", KSUBH)
  20128. + NDS32_BUILTIN(unspec_kdmbb, "kdmbb", KDMBB)
  20129. + NDS32_BUILTIN(unspec_kdmbb, "v_kdmbb", V_KDMBB)
  20130. + NDS32_BUILTIN(unspec_kdmbt, "kdmbt", KDMBT)
  20131. + NDS32_BUILTIN(unspec_kdmbt, "v_kdmbt", V_KDMBT)
  20132. + NDS32_BUILTIN(unspec_kdmtb, "kdmtb", KDMTB)
  20133. + NDS32_BUILTIN(unspec_kdmtb, "v_kdmtb", V_KDMTB)
  20134. + NDS32_BUILTIN(unspec_kdmtt, "kdmtt", KDMTT)
  20135. + NDS32_BUILTIN(unspec_kdmtt, "v_kdmtt", V_KDMTT)
  20136. + NDS32_BUILTIN(unspec_khmbb, "khmbb", KHMBB)
  20137. + NDS32_BUILTIN(unspec_khmbb, "v_khmbb", V_KHMBB)
  20138. + NDS32_BUILTIN(unspec_khmbt, "khmbt", KHMBT)
  20139. + NDS32_BUILTIN(unspec_khmbt, "v_khmbt", V_KHMBT)
  20140. + NDS32_BUILTIN(unspec_khmtb, "khmtb", KHMTB)
  20141. + NDS32_BUILTIN(unspec_khmtb, "v_khmtb", V_KHMTB)
  20142. + NDS32_BUILTIN(unspec_khmtt, "khmtt", KHMTT)
  20143. + NDS32_BUILTIN(unspec_khmtt, "v_khmtt", V_KHMTT)
  20144. + NDS32_BUILTIN(unspec_kslraw, "kslraw", KSLRAW)
  20145. + NDS32_BUILTIN(unspec_kslrawu, "kslraw_u", KSLRAW_U)
  20146. + NDS32_BUILTIN(rotrsi3, "rotr", ROTR)
  20147. + NDS32_BUILTIN(unspec_sva, "sva", SVA)
  20148. + NDS32_BUILTIN(unspec_svs, "svs", SVS)
  20149. + NDS32_NO_TARGET_BUILTIN(mtsr_isb, "mtsr_isb", MTSR_ISB)
  20150. + NDS32_NO_TARGET_BUILTIN(mtsr_dsb, "mtsr_dsb", MTSR_DSB)
  20151. + NDS32_NO_TARGET_BUILTIN(unspec_volatile_mtsr, "mtsr", MTSR)
  20152. + NDS32_NO_TARGET_BUILTIN(unspec_volatile_mtusr, "mtusr", MTUSR)
  20153. + NDS32_NO_TARGET_BUILTIN(unaligned_store_hw, "unaligned_store_hw", UASTORE_HW)
  20154. + NDS32_NO_TARGET_BUILTIN(unaligned_storesi, "unaligned_store_hw", UASTORE_W)
  20155. + NDS32_NO_TARGET_BUILTIN(unaligned_storedi, "unaligned_store_hw", UASTORE_DW)
  20156. + NDS32_BUILTIN(addv2hi3, "add16", ADD16)
  20157. + NDS32_BUILTIN(addv2hi3, "v_uadd16", V_UADD16)
  20158. + NDS32_BUILTIN(addv2hi3, "v_sadd16", V_SADD16)
  20159. + NDS32_BUILTIN(raddv2hi3, "radd16", RADD16)
  20160. + NDS32_BUILTIN(raddv2hi3, "v_radd16", V_RADD16)
  20161. + NDS32_BUILTIN(uraddv2hi3, "uradd16", URADD16)
  20162. + NDS32_BUILTIN(uraddv2hi3, "v_uradd16", V_URADD16)
  20163. + NDS32_BUILTIN(kaddv2hi3, "kadd16", KADD16)
  20164. + NDS32_BUILTIN(kaddv2hi3, "v_kadd16", V_KADD16)
  20165. + NDS32_BUILTIN(ukaddv2hi3, "ukadd16", UKADD16)
  20166. + NDS32_BUILTIN(ukaddv2hi3, "v_ukadd16", V_UKADD16)
  20167. + NDS32_BUILTIN(subv2hi3, "sub16", SUB16)
  20168. + NDS32_BUILTIN(subv2hi3, "v_usub16", V_USUB16)
  20169. + NDS32_BUILTIN(subv2hi3, "v_ssub16", V_SSUB16)
  20170. + NDS32_BUILTIN(rsubv2hi3, "rsub16", RSUB16)
  20171. + NDS32_BUILTIN(rsubv2hi3, "v_rsub16", V_RSUB16)
  20172. + NDS32_BUILTIN(ursubv2hi3, "ursub16", URSUB16)
  20173. + NDS32_BUILTIN(ursubv2hi3, "v_ursub16", V_URSUB16)
  20174. + NDS32_BUILTIN(ksubv2hi3, "ksub16", KSUB16)
  20175. + NDS32_BUILTIN(ksubv2hi3, "v_ksub16", V_KSUB16)
  20176. + NDS32_BUILTIN(uksubv2hi3, "uksub16", UKSUB16)
  20177. + NDS32_BUILTIN(uksubv2hi3, "v_uksub16", V_UKSUB16)
  20178. + NDS32_BUILTIN(cras16_1, "cras16", CRAS16)
  20179. + NDS32_BUILTIN(cras16_1, "v_ucras16", V_UCRAS16)
  20180. + NDS32_BUILTIN(cras16_1, "v_scras16", V_SCRAS16)
  20181. + NDS32_BUILTIN(rcras16_1, "rcras16", RCRAS16)
  20182. + NDS32_BUILTIN(rcras16_1, "v_rcras16", V_RCRAS16)
  20183. + NDS32_BUILTIN(urcras16_1, "urcras16", URCRAS16)
  20184. + NDS32_BUILTIN(urcras16_1, "v_urcras16", V_URCRAS16)
  20185. + NDS32_BUILTIN(kcras16_1, "kcras16", KCRAS16)
  20186. + NDS32_BUILTIN(kcras16_1, "v_kcras16", V_KCRAS16)
  20187. + NDS32_BUILTIN(ukcras16_1, "ukcras16", UKCRAS16)
  20188. + NDS32_BUILTIN(ukcras16_1, "v_ukcras16", V_UKCRAS16)
  20189. + NDS32_BUILTIN(crsa16_1, "crsa16", CRSA16)
  20190. + NDS32_BUILTIN(crsa16_1, "v_ucrsa16", V_UCRSA16)
  20191. + NDS32_BUILTIN(crsa16_1, "v_scrsa16", V_SCRSA16)
  20192. + NDS32_BUILTIN(rcrsa16_1, "rcrsa16", RCRSA16)
  20193. + NDS32_BUILTIN(rcrsa16_1, "v_rcrsa16", V_RCRSA16)
  20194. + NDS32_BUILTIN(urcrsa16_1, "urcrsa16", URCRSA16)
  20195. + NDS32_BUILTIN(urcrsa16_1, "v_urcrsa16", V_URCRSA16)
  20196. + NDS32_BUILTIN(kcrsa16_1, "kcrsa16", KCRSA16)
  20197. + NDS32_BUILTIN(kcrsa16_1, "v_kcrsa16", V_KCRSA16)
  20198. + NDS32_BUILTIN(ukcrsa16_1, "ukcrsa16", UKCRSA16)
  20199. + NDS32_BUILTIN(ukcrsa16_1, "v_ukcrsa16", V_UKCRSA16)
  20200. + NDS32_BUILTIN(addv4qi3, "add8", ADD8)
  20201. + NDS32_BUILTIN(addv4qi3, "v_uadd8", V_UADD8)
  20202. + NDS32_BUILTIN(addv4qi3, "v_sadd8", V_SADD8)
  20203. + NDS32_BUILTIN(raddv4qi3, "radd8", RADD8)
  20204. + NDS32_BUILTIN(raddv4qi3, "v_radd8", V_RADD8)
  20205. + NDS32_BUILTIN(uraddv4qi3, "uradd8", URADD8)
  20206. + NDS32_BUILTIN(uraddv4qi3, "v_uradd8", V_URADD8)
  20207. + NDS32_BUILTIN(kaddv4qi3, "kadd8", KADD8)
  20208. + NDS32_BUILTIN(kaddv4qi3, "v_kadd8", V_KADD8)
  20209. + NDS32_BUILTIN(ukaddv4qi3, "ukadd8", UKADD8)
  20210. + NDS32_BUILTIN(ukaddv4qi3, "v_ukadd8", V_UKADD8)
  20211. + NDS32_BUILTIN(subv4qi3, "sub8", SUB8)
  20212. + NDS32_BUILTIN(subv4qi3, "v_usub8", V_USUB8)
  20213. + NDS32_BUILTIN(subv4qi3, "v_ssub8", V_SSUB8)
  20214. + NDS32_BUILTIN(rsubv4qi3, "rsub8", RSUB8)
  20215. + NDS32_BUILTIN(rsubv4qi3, "v_rsub8", V_RSUB8)
  20216. + NDS32_BUILTIN(ursubv4qi3, "ursub8", URSUB8)
  20217. + NDS32_BUILTIN(ursubv4qi3, "v_ursub8", V_URSUB8)
  20218. + NDS32_BUILTIN(ksubv4qi3, "ksub8", KSUB8)
  20219. + NDS32_BUILTIN(ksubv4qi3, "v_ksub8", V_KSUB8)
  20220. + NDS32_BUILTIN(uksubv4qi3, "uksub8", UKSUB8)
  20221. + NDS32_BUILTIN(uksubv4qi3, "v_uksub8", V_UKSUB8)
  20222. + NDS32_BUILTIN(ashrv2hi3, "sra16", SRA16)
  20223. + NDS32_BUILTIN(ashrv2hi3, "v_sra16", V_SRA16)
  20224. + NDS32_BUILTIN(sra16_round, "sra16_u", SRA16_U)
  20225. + NDS32_BUILTIN(sra16_round, "v_sra16_u", V_SRA16_U)
  20226. + NDS32_BUILTIN(lshrv2hi3, "srl16", SRL16)
  20227. + NDS32_BUILTIN(lshrv2hi3, "v_srl16", V_SRL16)
  20228. + NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U)
  20229. + NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U)
  20230. + NDS32_BUILTIN(ashlv2hi3, "sll16", SLL16)
  20231. + NDS32_BUILTIN(ashlv2hi3, "v_sll16", V_SLL16)
  20232. + NDS32_BUILTIN(kslli16, "ksll16", KSLL16)
  20233. + NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16)
  20234. + NDS32_BUILTIN(kslra16, "kslra16", KSLRA16)
  20235. + NDS32_BUILTIN(kslra16, "v_kslra16", V_KSLRA16)
  20236. + NDS32_BUILTIN(kslra16_round, "kslra16_u", KSLRA16_U)
  20237. + NDS32_BUILTIN(kslra16_round, "v_kslra16_u", V_KSLRA16_U)
  20238. + NDS32_BUILTIN(cmpeq16, "cmpeq16", CMPEQ16)
  20239. + NDS32_BUILTIN(cmpeq16, "v_scmpeq16", V_SCMPEQ16)
  20240. + NDS32_BUILTIN(cmpeq16, "v_ucmpeq16", V_UCMPEQ16)
  20241. + NDS32_BUILTIN(scmplt16, "scmplt16", SCMPLT16)
  20242. + NDS32_BUILTIN(scmplt16, "v_scmplt16", V_SCMPLT16)
  20243. + NDS32_BUILTIN(scmple16, "scmple16", SCMPLE16)
  20244. + NDS32_BUILTIN(scmple16, "v_scmple16", V_SCMPLE16)
  20245. + NDS32_BUILTIN(ucmplt16, "ucmplt16", UCMPLT16)
  20246. + NDS32_BUILTIN(ucmplt16, "v_ucmplt16", V_UCMPLT16)
  20247. + NDS32_BUILTIN(ucmplt16, "ucmple16", UCMPLE16)
  20248. + NDS32_BUILTIN(ucmplt16, "v_ucmple16", V_UCMPLE16)
  20249. + NDS32_BUILTIN(cmpeq8, "cmpeq8", CMPEQ8)
  20250. + NDS32_BUILTIN(cmpeq8, "v_scmpeq8", V_SCMPEQ8)
  20251. + NDS32_BUILTIN(cmpeq8, "v_ucmpeq8", V_UCMPEQ8)
  20252. + NDS32_BUILTIN(scmplt8, "scmplt8", SCMPLT8)
  20253. + NDS32_BUILTIN(scmplt8, "v_scmplt8", V_SCMPLT8)
  20254. + NDS32_BUILTIN(scmple8, "scmple8", SCMPLE8)
  20255. + NDS32_BUILTIN(scmple8, "v_scmple8", V_SCMPLE8)
  20256. + NDS32_BUILTIN(ucmplt8, "ucmplt8", UCMPLT8)
  20257. + NDS32_BUILTIN(ucmplt8, "v_ucmplt8", V_UCMPLT8)
  20258. + NDS32_BUILTIN(ucmplt8, "ucmple8", UCMPLE8)
  20259. + NDS32_BUILTIN(ucmplt8, "v_ucmple8", V_UCMPLE8)
  20260. + NDS32_BUILTIN(sminv2hi3, "smin16", SMIN16)
  20261. + NDS32_BUILTIN(sminv2hi3, "v_smin16", V_SMIN16)
  20262. + NDS32_BUILTIN(uminv2hi3, "umin16", UMIN16)
  20263. + NDS32_BUILTIN(uminv2hi3, "v_umin16", V_UMIN16)
  20264. + NDS32_BUILTIN(smaxv2hi3, "smax16", SMAX16)
  20265. + NDS32_BUILTIN(smaxv2hi3, "v_smax16", V_SMAX16)
  20266. + NDS32_BUILTIN(umaxv2hi3, "umax16", UMAX16)
  20267. + NDS32_BUILTIN(umaxv2hi3, "v_umax16", V_UMAX16)
  20268. + NDS32_BUILTIN(khm16, "khm16", KHM16)
  20269. + NDS32_BUILTIN(khm16, "v_khm16", V_KHM16)
  20270. + NDS32_BUILTIN(khmx16, "khmx16", KHMX16)
  20271. + NDS32_BUILTIN(khmx16, "v_khmx16", V_KHMX16)
  20272. + NDS32_BUILTIN(sminv4qi3, "smin8", SMIN8)
  20273. + NDS32_BUILTIN(sminv4qi3, "v_smin8", V_SMIN8)
  20274. + NDS32_BUILTIN(uminv4qi3, "umin8", UMIN8)
  20275. + NDS32_BUILTIN(uminv4qi3, "v_umin8", V_UMIN8)
  20276. + NDS32_BUILTIN(smaxv4qi3, "smax8", SMAX8)
  20277. + NDS32_BUILTIN(smaxv4qi3, "v_smax8", V_SMAX8)
  20278. + NDS32_BUILTIN(umaxv4qi3, "umax8", UMAX8)
  20279. + NDS32_BUILTIN(umaxv4qi3, "v_umax8", V_UMAX8)
  20280. + NDS32_BUILTIN(raddsi3, "raddw", RADDW)
  20281. + NDS32_BUILTIN(uraddsi3, "uraddw", URADDW)
  20282. + NDS32_BUILTIN(rsubsi3, "rsubw", RSUBW)
  20283. + NDS32_BUILTIN(ursubsi3, "ursubw", URSUBW)
  20284. + NDS32_BUILTIN(sraiu, "sra_u", SRA_U)
  20285. + NDS32_BUILTIN(kssl, "ksll", KSLL)
  20286. + NDS32_BUILTIN(pkbb, "pkbb16", PKBB16)
  20287. + NDS32_BUILTIN(pkbb, "v_pkbb16", V_PKBB16)
  20288. + NDS32_BUILTIN(pkbt, "pkbt16", PKBT16)
  20289. + NDS32_BUILTIN(pkbt, "v_pkbt16", V_PKBT16)
  20290. + NDS32_BUILTIN(pktb, "pktb16", PKTB16)
  20291. + NDS32_BUILTIN(pktb, "v_pktb16", V_PKTB16)
  20292. + NDS32_BUILTIN(pktt, "pktt16", PKTT16)
  20293. + NDS32_BUILTIN(pktt, "v_pktt16", V_PKTT16)
  20294. + NDS32_BUILTIN(smulsi3_highpart, "smmul", SMMUL)
  20295. + NDS32_BUILTIN(smmul_round, "smmul_u", SMMUL_U)
  20296. + NDS32_BUILTIN(smmwb, "smmwb", SMMWB)
  20297. + NDS32_BUILTIN(smmwb, "v_smmwb", V_SMMWB)
  20298. + NDS32_BUILTIN(smmwb_round, "smmwb_u", SMMWB_U)
  20299. + NDS32_BUILTIN(smmwb_round, "v_smmwb_u", V_SMMWB_U)
  20300. + NDS32_BUILTIN(smmwt, "smmwt", SMMWT)
  20301. + NDS32_BUILTIN(smmwt, "v_smmwt", V_SMMWT)
  20302. + NDS32_BUILTIN(smmwt_round, "smmwt_u", SMMWT_U)
  20303. + NDS32_BUILTIN(smmwt_round, "v_smmwt_u", V_SMMWT_U)
  20304. + NDS32_BUILTIN(smbb, "smbb", SMBB)
  20305. + NDS32_BUILTIN(smbb, "v_smbb", V_SMBB)
  20306. + NDS32_BUILTIN(smbt, "smbt", SMBT)
  20307. + NDS32_BUILTIN(smbt, "v_smbt", V_SMBT)
  20308. + NDS32_BUILTIN(smtt, "smtt", SMTT)
  20309. + NDS32_BUILTIN(smtt, "v_smtt", V_SMTT)
  20310. + NDS32_BUILTIN(kmda, "kmda", KMDA)
  20311. + NDS32_BUILTIN(kmda, "v_kmda", V_KMDA)
  20312. + NDS32_BUILTIN(kmxda, "kmxda", KMXDA)
  20313. + NDS32_BUILTIN(kmxda, "v_kmxda", V_KMXDA)
  20314. + NDS32_BUILTIN(smds, "smds", SMDS)
  20315. + NDS32_BUILTIN(smds, "v_smds", V_SMDS)
  20316. + NDS32_BUILTIN(smdrs, "smdrs", SMDRS)
  20317. + NDS32_BUILTIN(smdrs, "v_smdrs", V_SMDRS)
  20318. + NDS32_BUILTIN(smxdsv, "smxds", SMXDS)
  20319. + NDS32_BUILTIN(smxdsv, "v_smxds", V_SMXDS)
  20320. + NDS32_BUILTIN(smal1, "smal", SMAL)
  20321. + NDS32_BUILTIN(smal1, "v_smal", V_SMAL)
  20322. + NDS32_BUILTIN(bitrev, "bitrev", BITREV)
  20323. + NDS32_BUILTIN(wext, "wext", WEXT)
  20324. + NDS32_BUILTIN(adddi3, "sadd64", SADD64)
  20325. + NDS32_BUILTIN(adddi3, "uadd64", UADD64)
  20326. + NDS32_BUILTIN(radddi3, "radd64", RADD64)
  20327. + NDS32_BUILTIN(uradddi3, "uradd64", URADD64)
  20328. + NDS32_BUILTIN(kadddi3, "kadd64", KADD64)
  20329. + NDS32_BUILTIN(ukadddi3, "ukadd64", UKADD64)
  20330. + NDS32_BUILTIN(subdi3, "ssub64", SSUB64)
  20331. + NDS32_BUILTIN(subdi3, "usub64", USUB64)
  20332. + NDS32_BUILTIN(rsubdi3, "rsub64", RSUB64)
  20333. + NDS32_BUILTIN(ursubdi3, "ursub64", URSUB64)
  20334. + NDS32_BUILTIN(ksubdi3, "ksub64", KSUB64)
  20335. + NDS32_BUILTIN(uksubdi3, "uksub64", UKSUB64)
  20336. + NDS32_BUILTIN(smul16, "smul16", SMUL16)
  20337. + NDS32_BUILTIN(smul16, "v_smul16", V_SMUL16)
  20338. + NDS32_BUILTIN(smulx16, "smulx16", SMULX16)
  20339. + NDS32_BUILTIN(smulx16, "v_smulx16", V_SMULX16)
  20340. + NDS32_BUILTIN(umul16, "umul16", UMUL16)
  20341. + NDS32_BUILTIN(umul16, "v_umul16", V_UMUL16)
  20342. + NDS32_BUILTIN(umulx16, "umulx16", UMULX16)
  20343. + NDS32_BUILTIN(umulx16, "v_umulx16", V_UMULX16)
  20344. + NDS32_BUILTIN(kwmmul, "kwmmul", KWMMUL)
  20345. + NDS32_BUILTIN(kwmmul_round, "kwmmul_u", KWMMUL_U)
  20346. +};
  20347. +
  20348. +/* Two-argument intrinsics with an immediate second argument. */
  20349. +static struct builtin_description bdesc_2argimm[] =
  20350. +{
  20351. + NDS32_BUILTIN(unspec_bclr, "bclr", BCLR)
  20352. + NDS32_BUILTIN(unspec_bset, "bset", BSET)
  20353. + NDS32_BUILTIN(unspec_btgl, "btgl", BTGL)
  20354. + NDS32_BUILTIN(unspec_btst, "btst", BTST)
  20355. + NDS32_BUILTIN(unspec_clip, "clip", CLIP)
  20356. + NDS32_BUILTIN(unspec_clips, "clips", CLIPS)
  20357. + NDS32_NO_TARGET_BUILTIN(unspec_teqz, "teqz", TEQZ)
  20358. + NDS32_NO_TARGET_BUILTIN(unspec_tnez, "tnez", TNEZ)
  20359. + NDS32_BUILTIN(ashrv2hi3, "srl16", SRL16)
  20360. + NDS32_BUILTIN(ashrv2hi3, "v_srl16", V_SRL16)
  20361. + NDS32_BUILTIN(srl16_round, "srl16_u", SRL16_U)
  20362. + NDS32_BUILTIN(srl16_round, "v_srl16_u", V_SRL16_U)
  20363. + NDS32_BUILTIN(kslli16, "ksll16", KSLL16)
  20364. + NDS32_BUILTIN(kslli16, "v_ksll16", V_KSLL16)
  20365. + NDS32_BUILTIN(sclip16, "sclip16", SCLIP16)
  20366. + NDS32_BUILTIN(sclip16, "v_sclip16", V_SCLIP16)
  20367. + NDS32_BUILTIN(uclip16, "uclip16", UCLIP16)
  20368. + NDS32_BUILTIN(uclip16, "v_uclip16", V_UCLIP16)
  20369. + NDS32_BUILTIN(sraiu, "sra_u", SRA_U)
  20370. + NDS32_BUILTIN(kssl, "ksll", KSLL)
  20371. + NDS32_BUILTIN(bitrev, "bitrev", BITREV)
  20372. + NDS32_BUILTIN(wext, "wext", WEXT)
  20373. + NDS32_BUILTIN(uclip32, "uclip32", UCLIP32)
  20374. + NDS32_BUILTIN(sclip32, "sclip32", SCLIP32)
  20375. +};
  20376. +
  20377. +/* Intrinsics that take three arguments. */
  20378. +static struct builtin_description bdesc_3arg[] =
  20379. +{
  20380. + NDS32_BUILTIN(unspec_pbsada, "pbsada", PBSADA)
  20381. + NDS32_NO_TARGET_BUILTIN(bse, "bse", BSE)
  20382. + NDS32_NO_TARGET_BUILTIN(bsp, "bsp", BSP)
  20383. + NDS32_BUILTIN(kmabb, "kmabb", KMABB)
  20384. + NDS32_BUILTIN(kmabb, "v_kmabb", V_KMABB)
  20385. + NDS32_BUILTIN(kmabt, "kmabt", KMABT)
  20386. + NDS32_BUILTIN(kmabt, "v_kmabt", V_KMABT)
  20387. + NDS32_BUILTIN(kmatt, "kmatt", KMATT)
  20388. + NDS32_BUILTIN(kmatt, "v_kmatt", V_KMATT)
  20389. + NDS32_BUILTIN(kmada, "kmada", KMADA)
  20390. + NDS32_BUILTIN(kmada, "v_kmada", V_KMADA)
  20391. + NDS32_BUILTIN(kmaxda, "kmaxda", KMAXDA)
  20392. + NDS32_BUILTIN(kmaxda, "v_kmaxda", V_KMAXDA)
  20393. + NDS32_BUILTIN(kmads, "kmads", KMADS)
  20394. + NDS32_BUILTIN(kmads, "v_kmads", V_KMADS)
  20395. + NDS32_BUILTIN(kmadrs, "kmadrs", KMADRS)
  20396. + NDS32_BUILTIN(kmadrs, "v_kmadrs", V_KMADRS)
  20397. + NDS32_BUILTIN(kmaxds, "kmaxds", KMAXDS)
  20398. + NDS32_BUILTIN(kmaxds, "v_kmaxds", V_KMAXDS)
  20399. + NDS32_BUILTIN(kmsda, "kmsda", KMSDA)
  20400. + NDS32_BUILTIN(kmsda, "v_kmsda", V_KMSDA)
  20401. + NDS32_BUILTIN(kmsxda, "kmsxda", KMSXDA)
  20402. + NDS32_BUILTIN(kmsxda, "v_kmsxda", V_KMSXDA)
  20403. + NDS32_BUILTIN(bpick1, "bpick", BPICK)
  20404. + NDS32_BUILTIN(smar64_1, "smar64", SMAR64)
  20405. + NDS32_BUILTIN(smsr64, "smsr64", SMSR64)
  20406. + NDS32_BUILTIN(umar64_1, "umar64", UMAR64)
  20407. + NDS32_BUILTIN(umsr64, "umsr64", UMSR64)
  20408. + NDS32_BUILTIN(kmar64_1, "kmar64", KMAR64)
  20409. + NDS32_BUILTIN(kmsr64, "kmsr64", KMSR64)
  20410. + NDS32_BUILTIN(ukmar64_1, "ukmar64", UKMAR64)
  20411. + NDS32_BUILTIN(ukmsr64, "ukmsr64", UKMSR64)
  20412. + NDS32_BUILTIN(smalbb, "smalbb", SMALBB)
  20413. + NDS32_BUILTIN(smalbb, "v_smalbb", V_SMALBB)
  20414. + NDS32_BUILTIN(smalbt, "smalbt", SMALBT)
  20415. + NDS32_BUILTIN(smalbt, "v_smalbt", V_SMALBT)
  20416. + NDS32_BUILTIN(smaltt, "smaltt", SMALTT)
  20417. + NDS32_BUILTIN(smaltt, "v_smaltt", V_SMALTT)
  20418. + NDS32_BUILTIN(smalda1, "smalda", SMALDA)
  20419. + NDS32_BUILTIN(smalda1, "v_smalda", V_SMALDA)
  20420. + NDS32_BUILTIN(smalxda1, "smalxda", SMALXDA)
  20421. + NDS32_BUILTIN(smalxda1, "v_smalxda", V_SMALXDA)
  20422. + NDS32_BUILTIN(smalds1, "smalds", SMALDS)
  20423. + NDS32_BUILTIN(smalds1, "v_smalds", V_SMALDS)
  20424. + NDS32_BUILTIN(smaldrs3, "smaldrs", SMALDRS)
  20425. + NDS32_BUILTIN(smaldrs3, "v_smaldrs", V_SMALDRS)
  20426. + NDS32_BUILTIN(smalxds1, "smalxds", SMALXDS)
  20427. + NDS32_BUILTIN(smalxds1, "v_smalxds", V_SMALXDS)
  20428. + NDS32_BUILTIN(smslda1, "smslda", SMSLDA)
  20429. + NDS32_BUILTIN(smslda1, "v_smslda", V_SMSLDA)
  20430. + NDS32_BUILTIN(smslxda1, "smslxda", SMSLXDA)
  20431. + NDS32_BUILTIN(smslxda1, "v_smslxda", V_SMSLXDA)
  20432. + NDS32_BUILTIN(kmmawb, "kmmawb", KMMAWB)
  20433. + NDS32_BUILTIN(kmmawb, "v_kmmawb", V_KMMAWB)
  20434. + NDS32_BUILTIN(kmmawb_round, "kmmawb_u", KMMAWB_U)
  20435. + NDS32_BUILTIN(kmmawb_round, "v_kmmawb_u", V_KMMAWB_U)
  20436. + NDS32_BUILTIN(kmmawt, "kmmawt", KMMAWT)
  20437. + NDS32_BUILTIN(kmmawt, "v_kmmawt", V_KMMAWT)
  20438. + NDS32_BUILTIN(kmmawt_round, "kmmawt_u", KMMAWT_U)
  20439. + NDS32_BUILTIN(kmmawt_round, "v_kmmawt_u", V_KMMAWT_U)
  20440. + NDS32_BUILTIN(kmmac, "kmmac", KMMAC)
  20441. + NDS32_BUILTIN(kmmac_round, "kmmac_u", KMMAC_U)
  20442. + NDS32_BUILTIN(kmmsb, "kmmsb", KMMSB)
  20443. + NDS32_BUILTIN(kmmsb_round, "kmmsb_u", KMMSB_U)
  20444. +};
  20445. +
  20446. +/* Three-argument intrinsics with an immediate third argument. */
  20447. +static struct builtin_description bdesc_3argimm[] =
  20448. +{
  20449. + NDS32_NO_TARGET_BUILTIN(prefetch_qw, "prefetch_qw", DPREF_QW)
  20450. + NDS32_NO_TARGET_BUILTIN(prefetch_hw, "prefetch_hw", DPREF_HW)
  20451. + NDS32_NO_TARGET_BUILTIN(prefetch_w, "prefetch_w", DPREF_W)
  20452. + NDS32_NO_TARGET_BUILTIN(prefetch_dw, "prefetch_dw", DPREF_DW)
  20453. + NDS32_BUILTIN(insb, "insb", INSB)
  20454. +};
  20455. +
  20456. +/* Intrinsics that load a value. */
  20457. +static struct builtin_description bdesc_load[] =
  20458. +{
  20459. + NDS32_BUILTIN(unspec_volatile_llw, "llw", LLW)
  20460. + NDS32_BUILTIN(unspec_lwup, "lwup", LWUP)
  20461. + NDS32_BUILTIN(unspec_lbup, "lbup", LBUP)
  20462. +};
  20463. +
  20464. +/* Intrinsics that store a value. */
  20465. +static struct builtin_description bdesc_store[] =
  20466. +{
  20467. + NDS32_BUILTIN(unspec_swup, "swup", SWUP)
  20468. + NDS32_BUILTIN(unspec_sbup, "sbup", SBUP)
  20469. +};
  20470. +
  20471. +static struct builtin_description bdesc_cctl[] =
  20472. +{
  20473. + NDS32_BUILTIN(cctl_idx_read, "cctl_idx_read", CCTL_IDX_READ)
  20474. + NDS32_NO_TARGET_BUILTIN(cctl_idx_write, "cctl_idx_write", CCTL_IDX_WRITE)
  20475. + NDS32_NO_TARGET_BUILTIN(cctl_va_lck, "cctl_va_lck", CCTL_VA_LCK)
  20476. + NDS32_NO_TARGET_BUILTIN(cctl_idx_wbinval,
  20477. + "cctl_idx_wbinval", CCTL_IDX_WBINVAL)
  20478. + NDS32_NO_TARGET_BUILTIN(cctl_va_wbinval_l1,
  20479. + "cctl_va_wbinval_l1", CCTL_VA_WBINVAL_L1)
  20480. + NDS32_NO_TARGET_BUILTIN(cctl_va_wbinval_la,
  20481. + "cctl_va_wbinval_la", CCTL_VA_WBINVAL_LA)
  20482. +};
  20483. +
  20484. +rtx
  20485. +nds32_expand_builtin_impl (tree exp,
  20486. + rtx target,
  20487. + rtx subtarget ATTRIBUTE_UNUSED,
  20488. + enum machine_mode mode ATTRIBUTE_UNUSED,
  20489. + int ignore ATTRIBUTE_UNUSED)
  20490. +{
  20491. + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
  20492. + unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
  20493. + unsigned i;
  20494. + struct builtin_description *d;
  20495. +
  20496. + if (!NDS32_EXT_DSP_P ()
  20497. + && fcode > NDS32_BUILTIN_DSP_BEGIN
  20498. + && fcode < NDS32_BUILTIN_DSP_END)
  20499. + error ("don't support DSP extension instructions");
  20500. +
  20501. + switch (fcode)
  20502. + {
  20503. + /* FPU Register Transfer. */
  20504. + case NDS32_BUILTIN_FMFCFG:
  20505. + case NDS32_BUILTIN_FMFCSR:
  20506. + case NDS32_BUILTIN_FMTCSR:
  20507. + case NDS32_BUILTIN_FCPYNSS:
  20508. + case NDS32_BUILTIN_FCPYSS:
  20509. + /* Both v3s and v3f toolchains define TARGET_FPU_SINGLE. */
  20510. + if (!TARGET_FPU_SINGLE)
  20511. + {
  20512. + error ("this builtin function is only available "
  20513. + "on the v3s or v3f toolchain");
  20514. + return NULL_RTX;
  20515. + }
  20516. + break;
  20517. +
  20518. + /* FPU Register Transfer. */
  20519. + case NDS32_BUILTIN_FCPYNSD:
  20520. + case NDS32_BUILTIN_FCPYSD:
  20521. + /* Only v3f toolchain defines TARGET_FPU_DOUBLE. */
  20522. + if (!TARGET_FPU_DOUBLE)
  20523. + {
  20524. + error ("this builtin function is only available "
  20525. + "on the v3f toolchain");
  20526. + return NULL_RTX;
  20527. + }
  20528. + break;
  20529. +
  20530. + /* Load and Store */
  20531. + case NDS32_BUILTIN_LLW:
  20532. + case NDS32_BUILTIN_LWUP:
  20533. + case NDS32_BUILTIN_LBUP:
  20534. + case NDS32_BUILTIN_SCW:
  20535. + case NDS32_BUILTIN_SWUP:
  20536. + case NDS32_BUILTIN_SBUP:
  20537. + if (TARGET_ISA_V3M)
  20538. + {
  20539. + error ("this builtin function not support "
  20540. + "on the v3m toolchain");
  20541. + return NULL_RTX;
  20542. + }
  20543. + break;
  20544. +
  20545. + /* Performance Extension */
  20546. + case NDS32_BUILTIN_ABS:
  20547. + case NDS32_BUILTIN_AVE:
  20548. + case NDS32_BUILTIN_BCLR:
  20549. + case NDS32_BUILTIN_BSET:
  20550. + case NDS32_BUILTIN_BTGL:
  20551. + case NDS32_BUILTIN_BTST:
  20552. + case NDS32_BUILTIN_CLIP:
  20553. + case NDS32_BUILTIN_CLIPS:
  20554. + case NDS32_BUILTIN_CLZ:
  20555. + case NDS32_BUILTIN_CLO:
  20556. + if (!TARGET_EXT_PERF)
  20557. + {
  20558. + error ("don't support performance extension instructions");
  20559. + return NULL_RTX;
  20560. + }
  20561. + break;
  20562. +
  20563. + /* Performance Extension 2 */
  20564. + case NDS32_BUILTIN_PBSAD:
  20565. + case NDS32_BUILTIN_PBSADA:
  20566. + case NDS32_BUILTIN_BSE:
  20567. + case NDS32_BUILTIN_BSP:
  20568. + if (!TARGET_EXT_PERF2)
  20569. + {
  20570. + error ("don't support performance extension "
  20571. + "version 2 instructions");
  20572. + return NULL_RTX;
  20573. + }
  20574. + break;
  20575. +
  20576. + /* String Extension */
  20577. + case NDS32_BUILTIN_FFB:
  20578. + case NDS32_BUILTIN_FFMISM:
  20579. + case NDS32_BUILTIN_FLMISM:
  20580. + if (!TARGET_EXT_STRING)
  20581. + {
  20582. + error ("don't support string extension instructions");
  20583. + return NULL_RTX;
  20584. + }
  20585. + break;
  20586. +
  20587. + default:
  20588. + break;
  20589. + }
  20590. +
  20591. + /* Since there are no result and operands, we can simply emit this rtx. */
  20592. + switch (fcode)
  20593. + {
  20594. + case NDS32_BUILTIN_ISB:
  20595. + emit_insn (gen_unspec_volatile_isb ());
  20596. + return target;
  20597. + case NDS32_BUILTIN_DSB:
  20598. + emit_insn (gen_unspec_dsb ());
  20599. + return target;
  20600. + case NDS32_BUILTIN_MSYNC_ALL:
  20601. + emit_insn (gen_unspec_msync_all ());
  20602. + return target;
  20603. + case NDS32_BUILTIN_MSYNC_STORE:
  20604. + emit_insn (gen_unspec_msync_store ());
  20605. + return target;
  20606. + case NDS32_BUILTIN_SETGIE_EN:
  20607. + emit_insn (gen_unspec_volatile_setgie_en ());
  20608. + emit_insn (gen_unspec_dsb ());
  20609. + return target;
  20610. + case NDS32_BUILTIN_SETGIE_DIS:
  20611. + emit_insn (gen_unspec_volatile_setgie_dis ());
  20612. + emit_insn (gen_unspec_dsb ());
  20613. + return target;
  20614. + case NDS32_BUILTIN_GIE_DIS:
  20615. + emit_insn (gen_unspec_volatile_setgie_dis ());
  20616. + emit_insn (gen_unspec_dsb ());
  20617. + return target;
  20618. + case NDS32_BUILTIN_GIE_EN:
  20619. + emit_insn (gen_unspec_volatile_setgie_en ());
  20620. + emit_insn (gen_unspec_dsb ());
  20621. + return target;
  20622. + case NDS32_BUILTIN_SET_PENDING_SWINT:
  20623. + emit_insn (gen_unspec_set_pending_swint ());
  20624. + return target;
  20625. + case NDS32_BUILTIN_CLR_PENDING_SWINT:
  20626. + emit_insn (gen_unspec_clr_pending_swint ());
  20627. + return target;
  20628. + case NDS32_BUILTIN_CCTL_L1D_INVALALL:
  20629. + emit_insn (gen_cctl_l1d_invalall());
  20630. + return target;
  20631. + case NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL:
  20632. + emit_insn (gen_cctl_l1d_wball_alvl());
  20633. + return target;
  20634. + case NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL:
  20635. + emit_insn (gen_cctl_l1d_wball_one_lvl());
  20636. + return target;
  20637. + case NDS32_BUILTIN_CLROV:
  20638. + emit_insn (gen_unspec_clrov ());
  20639. + return target;
  20640. + case NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT:
  20641. + emit_insn (gen_unspec_standby_no_wake_grant ());
  20642. + return target;
  20643. + case NDS32_BUILTIN_STANDBY_WAKE_GRANT:
  20644. + emit_insn (gen_unspec_standby_wake_grant ());
  20645. + return target;
  20646. + case NDS32_BUILTIN_STANDBY_WAKE_DONE:
  20647. + emit_insn (gen_unspec_standby_wait_done ());
  20648. + return target;
  20649. + case NDS32_BUILTIN_SETEND_BIG:
  20650. + emit_insn (gen_unspec_setend_big ());
  20651. + return target;
  20652. + case NDS32_BUILTIN_SETEND_LITTLE:
  20653. + emit_insn (gen_unspec_setend_little ());
  20654. + return target;
  20655. + case NDS32_BUILTIN_NOP:
  20656. + emit_insn (gen_unspec_nop ());
  20657. + return target;
  20658. + case NDS32_BUILTIN_SCHE_BARRIER:
  20659. + emit_insn (gen_blockage ());
  20660. + return target;
  20661. + case NDS32_BUILTIN_TLBOP_FLUA:
  20662. + emit_insn (gen_unspec_tlbop_flua ());
  20663. + return target;
  20664. + /* Instruction sequence protection */
  20665. + case NDS32_BUILTIN_SIGNATURE_BEGIN:
  20666. + emit_insn (gen_unspec_signature_begin ());
  20667. + return target;
  20668. + case NDS32_BUILTIN_SIGNATURE_END:
  20669. + emit_insn (gen_unspec_signature_end ());
  20670. + return target;
  20671. + case NDS32_BUILTIN_SCW:
  20672. + return nds32_expand_scw_builtin (CODE_FOR_unspec_volatile_scw,
  20673. + exp, target);
  20674. + case NDS32_BUILTIN_SET_INT_PRIORITY:
  20675. + return nds32_expand_priority_builtin (CODE_FOR_unspec_set_int_priority,
  20676. + exp, target,
  20677. + "__nds32__set_int_priority");
  20678. + case NDS32_BUILTIN_NO_HWLOOP:
  20679. + emit_insn (gen_no_hwloop ());
  20680. + return target;
  20681. + default:
  20682. + break;
  20683. + }
  20684. +
  20685. + /* Expand groups of builtins. */
  20686. + for (i = 0, d = bdesc_noarg; i < ARRAY_SIZE (bdesc_noarg); i++, d++)
  20687. + if (d->code == fcode)
  20688. + return nds32_expand_noarg_builtin (d->icode, target);
  20689. +
  20690. + for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
  20691. + if (d->code == fcode)
  20692. + return nds32_expand_unop_builtin (d->icode, exp, target, d->return_p);
  20693. +
  20694. + for (i = 0, d = bdesc_1argimm; i < ARRAY_SIZE (bdesc_1argimm); i++, d++)
  20695. + if (d->code == fcode)
  20696. + return nds32_expand_unopimm_builtin (d->icode, exp, target,
  20697. + d->return_p, d->name);
  20698. +
  20699. + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
  20700. + if (d->code == fcode)
  20701. + return nds32_expand_binop_builtin (d->icode, exp, target, d->return_p);
  20702. +
  20703. + for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
  20704. + if (d->code == fcode)
  20705. + return nds32_expand_binopimm_builtin (d->icode, exp, target,
  20706. + d->return_p, d->name);
  20707. +
  20708. + for (i = 0, d = bdesc_3arg; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
  20709. + if (d->code == fcode)
  20710. + return nds32_expand_triop_builtin (d->icode, exp, target, d->return_p);
  20711. +
  20712. + for (i = 0, d = bdesc_3argimm; i < ARRAY_SIZE (bdesc_3argimm); i++, d++)
  20713. + if (d->code == fcode)
  20714. + return nds32_expand_triopimm_builtin (d->icode, exp, target,
  20715. + d->return_p, d->name);
  20716. +
  20717. + for (i = 0, d = bdesc_load; i < ARRAY_SIZE (bdesc_load); i++, d++)
  20718. + if (d->code == fcode)
  20719. + return nds32_expand_builtin_load (d->icode, exp, target);
  20720. +
  20721. + for (i = 0, d = bdesc_store; i < ARRAY_SIZE (bdesc_store); i++, d++)
  20722. + if (d->code == fcode)
  20723. + return nds32_expand_builtin_store (d->icode, exp, target);
  20724. +
  20725. + for (i = 0, d = bdesc_cctl; i < ARRAY_SIZE (bdesc_cctl); i++, d++)
  20726. + if (d->code == fcode)
  20727. + return nds32_expand_cctl_builtin (d->icode, exp, target,
  20728. + d->return_p, d->name);
  20729. +
  20730. + return NULL_RTX;
  20731. +}
  20732. +
  20733. +static GTY(()) tree nds32_builtin_decls[NDS32_BUILTIN_COUNT];
  20734. +
  20735. +/* Return the NDS32 builtin for CODE. */
  20736. +tree
  20737. +nds32_builtin_decl_impl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
  20738. +{
  20739. + if (code >= NDS32_BUILTIN_COUNT)
  20740. + return error_mark_node;
  20741. +
  20742. + return nds32_builtin_decls[code];
  20743. +}
  20744. +
  20745. +void
  20746. +nds32_init_builtins_impl (void)
  20747. +{
  20748. +#define ADD_NDS32_BUILTIN0(NAME, RET_TYPE, CODE) \
  20749. + nds32_builtin_decls[NDS32_BUILTIN_ ## CODE] = \
  20750. + add_builtin_function ("__builtin_nds32_" NAME, \
  20751. + build_function_type_list (RET_TYPE##_type_node, \
  20752. + NULL_TREE), \
  20753. + NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE)
  20754. +
  20755. +#define ADD_NDS32_BUILTIN1(NAME, RET_TYPE, ARG_TYPE, CODE) \
  20756. + nds32_builtin_decls[NDS32_BUILTIN_ ## CODE] = \
  20757. + add_builtin_function ("__builtin_nds32_" NAME, \
  20758. + build_function_type_list (RET_TYPE##_type_node, \
  20759. + ARG_TYPE##_type_node, \
  20760. + NULL_TREE), \
  20761. + NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE)
  20762. +
  20763. +#define ADD_NDS32_BUILTIN2(NAME, RET_TYPE, ARG_TYPE1, ARG_TYPE2, CODE) \
  20764. + nds32_builtin_decls[NDS32_BUILTIN_ ## CODE] = \
  20765. + add_builtin_function ("__builtin_nds32_" NAME, \
  20766. + build_function_type_list (RET_TYPE##_type_node, \
  20767. + ARG_TYPE1##_type_node,\
  20768. + ARG_TYPE2##_type_node,\
  20769. + NULL_TREE), \
  20770. + NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE)
  20771. +
  20772. +#define ADD_NDS32_BUILTIN3(NAME, RET_TYPE, \
  20773. + ARG_TYPE1, ARG_TYPE2, ARG_TYPE3, CODE) \
  20774. + nds32_builtin_decls[NDS32_BUILTIN_ ## CODE] = \
  20775. + add_builtin_function ("__builtin_nds32_" NAME, \
  20776. + build_function_type_list (RET_TYPE##_type_node, \
  20777. + ARG_TYPE1##_type_node,\
  20778. + ARG_TYPE2##_type_node,\
  20779. + ARG_TYPE3##_type_node,\
  20780. + NULL_TREE), \
  20781. + NDS32_BUILTIN_ ## CODE, BUILT_IN_MD, NULL, NULL_TREE)
  20782. +
  20783. + /* Looking for return type and argument can be found in tree.h file. */
  20784. + tree ptr_uchar_type_node = build_pointer_type (unsigned_char_type_node);
  20785. + tree ptr_ushort_type_node = build_pointer_type (short_unsigned_type_node);
  20786. + tree ptr_uint_type_node = build_pointer_type (unsigned_type_node);
  20787. + tree ptr_ulong_type_node = build_pointer_type (long_long_unsigned_type_node);
  20788. + tree v4qi_type_node = build_vector_type (intQI_type_node, 4);
  20789. + tree u_v4qi_type_node = build_vector_type (unsigned_intQI_type_node, 4);
  20790. + tree v2hi_type_node = build_vector_type (intHI_type_node, 2);
  20791. + tree u_v2hi_type_node = build_vector_type (unsigned_intHI_type_node, 2);
  20792. + tree v2si_type_node = build_vector_type (intSI_type_node, 2);
  20793. + tree u_v2si_type_node = build_vector_type (unsigned_intSI_type_node, 2);
  20794. +
  20795. + /* Cache. */
  20796. + ADD_NDS32_BUILTIN1 ("isync", void, ptr_uint, ISYNC);
  20797. + ADD_NDS32_BUILTIN0 ("isb", void, ISB);
  20798. + ADD_NDS32_BUILTIN0 ("dsb", void, DSB);
  20799. + ADD_NDS32_BUILTIN0 ("msync_all", void, MSYNC_ALL);
  20800. + ADD_NDS32_BUILTIN0 ("msync_store", void, MSYNC_STORE);
  20801. +
  20802. + /* Register Transfer. */
  20803. + ADD_NDS32_BUILTIN1 ("mfsr", unsigned, integer, MFSR);
  20804. + ADD_NDS32_BUILTIN1 ("mfusr", unsigned, integer, MFUSR);
  20805. + ADD_NDS32_BUILTIN2 ("mtsr", void, unsigned, integer, MTSR);
  20806. + ADD_NDS32_BUILTIN2 ("mtsr_isb", void, unsigned, integer, MTSR_ISB);
  20807. + ADD_NDS32_BUILTIN2 ("mtsr_dsb", void, unsigned, integer, MTSR_DSB);
  20808. + ADD_NDS32_BUILTIN2 ("mtusr", void, unsigned, integer, MTUSR);
  20809. +
  20810. + /* FPU Register Transfer. */
  20811. + ADD_NDS32_BUILTIN0 ("fmfcsr", unsigned, FMFCSR);
  20812. + ADD_NDS32_BUILTIN1 ("fmtcsr", void, unsigned, FMTCSR);
  20813. + ADD_NDS32_BUILTIN0 ("fmfcfg", unsigned, FMFCFG);
  20814. + ADD_NDS32_BUILTIN2 ("fcpyss", float, float, float, FCPYSS);
  20815. + ADD_NDS32_BUILTIN2 ("fcpynss", float, float, float, FCPYNSS);
  20816. + ADD_NDS32_BUILTIN2 ("fcpysd", double, double, double, FCPYSD);
  20817. + ADD_NDS32_BUILTIN2 ("fcpynsd", double, double, double, FCPYNSD);
  20818. +
  20819. + /* Interrupt. */
  20820. + ADD_NDS32_BUILTIN0 ("setgie_en", void, SETGIE_EN);
  20821. + ADD_NDS32_BUILTIN0 ("setgie_dis", void, SETGIE_DIS);
  20822. + ADD_NDS32_BUILTIN0 ("gie_en", void, GIE_EN);
  20823. + ADD_NDS32_BUILTIN0 ("gie_dis", void, GIE_DIS);
  20824. + ADD_NDS32_BUILTIN1 ("enable_int", void, integer, ENABLE_INT);
  20825. + ADD_NDS32_BUILTIN1 ("disable_int", void, integer, DISABLE_INT);
  20826. + ADD_NDS32_BUILTIN0 ("set_pending_swint", void, SET_PENDING_SWINT);
  20827. + ADD_NDS32_BUILTIN0 ("clr_pending_swint", void, CLR_PENDING_SWINT);
  20828. + ADD_NDS32_BUILTIN0 ("get_all_pending_int", unsigned, GET_ALL_PENDING_INT);
  20829. + ADD_NDS32_BUILTIN1 ("get_pending_int", unsigned, integer, GET_PENDING_INT);
  20830. + ADD_NDS32_BUILTIN1 ("get_int_priority", unsigned, integer, GET_INT_PRIORITY);
  20831. + ADD_NDS32_BUILTIN2 ("set_int_priority", void, integer, integer,
  20832. + SET_INT_PRIORITY);
  20833. + ADD_NDS32_BUILTIN1 ("clr_pending_hwint", void, integer, CLR_PENDING_HWINT);
  20834. + ADD_NDS32_BUILTIN1 ("set_trig_level", void, integer, SET_TRIG_LEVEL);
  20835. + ADD_NDS32_BUILTIN1 ("set_trig_edge", void, integer, SET_TRIG_EDGE);
  20836. + ADD_NDS32_BUILTIN1 ("get_trig_type", unsigned, integer, GET_TRIG_TYPE);
  20837. +
  20838. + /* Load and Store */
  20839. + ADD_NDS32_BUILTIN1 ("llw", unsigned, ptr_uint, LLW);
  20840. + ADD_NDS32_BUILTIN1 ("lwup", unsigned, ptr_uint, LWUP);
  20841. + ADD_NDS32_BUILTIN1 ("lbup", char, ptr_uchar, LBUP);
  20842. + ADD_NDS32_BUILTIN2 ("scw", unsigned, ptr_uint, unsigned, SCW);
  20843. + ADD_NDS32_BUILTIN2 ("swup", void, ptr_uint, unsigned, SWUP);
  20844. + ADD_NDS32_BUILTIN2 ("sbup", void, ptr_uchar, char, SBUP);
  20845. +
  20846. + /* CCTL */
  20847. + ADD_NDS32_BUILTIN0 ("cctl_l1d_invalall", void, CCTL_L1D_INVALALL);
  20848. + ADD_NDS32_BUILTIN0 ("cctl_l1d_wball_alvl", void, CCTL_L1D_WBALL_ALVL);
  20849. + ADD_NDS32_BUILTIN0 ("cctl_l1d_wball_one_lvl", void, CCTL_L1D_WBALL_ONE_LVL);
  20850. + ADD_NDS32_BUILTIN2 ("cctl_va_lck", void, integer, ptr_uint, CCTL_VA_LCK);
  20851. + ADD_NDS32_BUILTIN2 ("cctl_idx_wbinval", void, integer, unsigned,
  20852. + CCTL_IDX_WBINVAL);
  20853. + ADD_NDS32_BUILTIN2 ("cctl_va_wbinval_l1", void, integer, ptr_uint,
  20854. + CCTL_VA_WBINVAL_L1);
  20855. + ADD_NDS32_BUILTIN2 ("cctl_va_wbinval_la", void, integer, ptr_uint,
  20856. + CCTL_VA_WBINVAL_LA);
  20857. + ADD_NDS32_BUILTIN2 ("cctl_idx_read", unsigned, integer, unsigned,
  20858. + CCTL_IDX_READ);
  20859. + ADD_NDS32_BUILTIN3 ("cctl_idx_write", void, integer, unsigned, unsigned,
  20860. + CCTL_IDX_WRITE);
  20861. +
  20862. + /* PREFETCH */
  20863. + ADD_NDS32_BUILTIN3 ("dpref_qw", void, ptr_uchar, unsigned, integer, DPREF_QW);
  20864. + ADD_NDS32_BUILTIN3 ("dpref_hw", void, ptr_ushort, unsigned, integer,
  20865. + DPREF_HW);
  20866. + ADD_NDS32_BUILTIN3 ("dpref_w", void, ptr_uint, unsigned, integer, DPREF_W);
  20867. + ADD_NDS32_BUILTIN3 ("dpref_dw", void, ptr_ulong, unsigned, integer, DPREF_DW);
  20868. +
  20869. + /* Performance Extension */
  20870. + ADD_NDS32_BUILTIN1 ("pe_abs", integer, integer, ABS);
  20871. + ADD_NDS32_BUILTIN2 ("pe_ave", integer, integer, integer, AVE);
  20872. + ADD_NDS32_BUILTIN2 ("pe_bclr", unsigned, unsigned, unsigned, BCLR);
  20873. + ADD_NDS32_BUILTIN2 ("pe_bset", unsigned, unsigned, unsigned, BSET);
  20874. + ADD_NDS32_BUILTIN2 ("pe_btgl", unsigned, unsigned, unsigned, BTGL);
  20875. + ADD_NDS32_BUILTIN2 ("pe_btst", unsigned, unsigned, unsigned, BTST);
  20876. + ADD_NDS32_BUILTIN2 ("pe_clip", unsigned, integer, unsigned, CLIP);
  20877. + ADD_NDS32_BUILTIN2 ("pe_clips", integer, integer, unsigned, CLIPS);
  20878. + ADD_NDS32_BUILTIN1 ("pe_clz", unsigned, unsigned, CLZ);
  20879. + ADD_NDS32_BUILTIN1 ("pe_clo", unsigned, unsigned, CLO);
  20880. +
  20881. + /* Performance Extension 2 */
  20882. + ADD_NDS32_BUILTIN3 ("pe2_bse", void, ptr_uint, unsigned, ptr_uint, BSE);
  20883. + ADD_NDS32_BUILTIN3 ("pe2_bsp", void, ptr_uint, unsigned, ptr_uint, BSP);
  20884. + ADD_NDS32_BUILTIN2 ("pe2_pbsad", unsigned, unsigned, unsigned, PBSAD);
  20885. + ADD_NDS32_BUILTIN3 ("pe2_pbsada", unsigned, unsigned, unsigned, unsigned,
  20886. + PBSADA);
  20887. +
  20888. + /* String Extension */
  20889. + ADD_NDS32_BUILTIN2 ("se_ffb", integer, unsigned, unsigned, FFB);
  20890. + ADD_NDS32_BUILTIN2 ("se_ffmism", integer, unsigned, unsigned, FFMISM);
  20891. + ADD_NDS32_BUILTIN2 ("se_flmism", integer, unsigned, unsigned, FLMISM);
  20892. +
  20893. + /* SATURATION */
  20894. + ADD_NDS32_BUILTIN2 ("kaddw", integer, integer, integer, KADDW);
  20895. + ADD_NDS32_BUILTIN2 ("ksubw", integer, integer, integer, KSUBW);
  20896. + ADD_NDS32_BUILTIN2 ("kaddh", integer, integer, integer, KADDH);
  20897. + ADD_NDS32_BUILTIN2 ("ksubh", integer, integer, integer, KSUBH);
  20898. + ADD_NDS32_BUILTIN2 ("kdmbb", integer, unsigned, unsigned, KDMBB);
  20899. + ADD_NDS32_BUILTIN2 ("v_kdmbb", integer, v2hi, v2hi, V_KDMBB);
  20900. + ADD_NDS32_BUILTIN2 ("kdmbt", integer, unsigned, unsigned, KDMBT);
  20901. + ADD_NDS32_BUILTIN2 ("v_kdmbt", integer, v2hi, v2hi, V_KDMBT);
  20902. + ADD_NDS32_BUILTIN2 ("kdmtb", integer, unsigned, unsigned, KDMTB);
  20903. + ADD_NDS32_BUILTIN2 ("v_kdmtb", integer, v2hi, v2hi, V_KDMTB);
  20904. + ADD_NDS32_BUILTIN2 ("kdmtt", integer, unsigned, unsigned, KDMTT);
  20905. + ADD_NDS32_BUILTIN2 ("v_kdmtt", integer, v2hi, v2hi, V_KDMTT);
  20906. + ADD_NDS32_BUILTIN2 ("khmbb", integer, unsigned, unsigned, KHMBB);
  20907. + ADD_NDS32_BUILTIN2 ("v_khmbb", integer, v2hi, v2hi, V_KHMBB);
  20908. + ADD_NDS32_BUILTIN2 ("khmbt", integer, unsigned, unsigned, KHMBT);
  20909. + ADD_NDS32_BUILTIN2 ("v_khmbt", integer, v2hi, v2hi, V_KHMBT);
  20910. + ADD_NDS32_BUILTIN2 ("khmtb", integer, unsigned, unsigned, KHMTB);
  20911. + ADD_NDS32_BUILTIN2 ("v_khmtb", integer, v2hi, v2hi, V_KHMTB);
  20912. + ADD_NDS32_BUILTIN2 ("khmtt", integer, unsigned, unsigned, KHMTT);
  20913. + ADD_NDS32_BUILTIN2 ("v_khmtt", integer, v2hi, v2hi, V_KHMTT);
  20914. + ADD_NDS32_BUILTIN2 ("kslraw", integer, integer, integer, KSLRAW);
  20915. + ADD_NDS32_BUILTIN2 ("kslraw_u", integer, integer, integer, KSLRAW_U);
  20916. + ADD_NDS32_BUILTIN0 ("rdov", unsigned, RDOV);
  20917. + ADD_NDS32_BUILTIN0 ("clrov", void, CLROV);
  20918. +
  20919. + /* ROTR */
  20920. + ADD_NDS32_BUILTIN2 ("rotr", unsigned, unsigned, unsigned, ROTR);
  20921. +
  20922. + /* Swap */
  20923. + ADD_NDS32_BUILTIN1 ("wsbh", unsigned, unsigned, WSBH);
  20924. +
  20925. + /* System */
  20926. + ADD_NDS32_BUILTIN2 ("svs", unsigned, integer, integer, SVS);
  20927. + ADD_NDS32_BUILTIN2 ("sva", unsigned, integer, integer, SVA);
  20928. + ADD_NDS32_BUILTIN1 ("jr_itoff", void, unsigned, JR_ITOFF);
  20929. + ADD_NDS32_BUILTIN1 ("jr_toff", void, unsigned, JR_TOFF);
  20930. + ADD_NDS32_BUILTIN1 ("jral_iton", void, unsigned, JRAL_ITON);
  20931. + ADD_NDS32_BUILTIN1 ("jral_ton", void, unsigned, JRAL_TON);
  20932. + ADD_NDS32_BUILTIN1 ("ret_itoff", void, unsigned, RET_ITOFF);
  20933. + ADD_NDS32_BUILTIN1 ("ret_toff", void, unsigned, RET_TOFF);
  20934. + ADD_NDS32_BUILTIN0 ("standby_no_wake_grant", void, STANDBY_NO_WAKE_GRANT);
  20935. + ADD_NDS32_BUILTIN0 ("standby_wake_grant", void, STANDBY_WAKE_GRANT);
  20936. + ADD_NDS32_BUILTIN0 ("standby_wait_done", void, STANDBY_WAKE_DONE);
  20937. + ADD_NDS32_BUILTIN1 ("break", void, unsigned, BREAK);
  20938. + ADD_NDS32_BUILTIN1 ("syscall", void, unsigned, SYSCALL);
  20939. + ADD_NDS32_BUILTIN0 ("nop", void, NOP);
  20940. + ADD_NDS32_BUILTIN0 ("get_current_sp", unsigned, GET_CURRENT_SP);
  20941. + ADD_NDS32_BUILTIN1 ("set_current_sp", void, unsigned, SET_CURRENT_SP);
  20942. + ADD_NDS32_BUILTIN2 ("teqz", void, unsigned, unsigned, TEQZ);
  20943. + ADD_NDS32_BUILTIN2 ("tnez", void, unsigned, unsigned, TNEZ);
  20944. + ADD_NDS32_BUILTIN1 ("trap", void, unsigned, TRAP);
  20945. + ADD_NDS32_BUILTIN0 ("return_address", unsigned, RETURN_ADDRESS);
  20946. + ADD_NDS32_BUILTIN0 ("setend_big", void, SETEND_BIG);
  20947. + ADD_NDS32_BUILTIN0 ("setend_little", void, SETEND_LITTLE);
  20948. +
  20949. + /* Schedule Barrier */
  20950. + ADD_NDS32_BUILTIN0 ("schedule_barrier", void, SCHE_BARRIER);
  20951. +
  20952. + /* TLBOP */
  20953. + ADD_NDS32_BUILTIN1 ("tlbop_trd", void, unsigned, TLBOP_TRD);
  20954. + ADD_NDS32_BUILTIN1 ("tlbop_twr", void, unsigned, TLBOP_TWR);
  20955. + ADD_NDS32_BUILTIN1 ("tlbop_rwr", void, unsigned, TLBOP_RWR);
  20956. + ADD_NDS32_BUILTIN1 ("tlbop_rwlk", void, unsigned, TLBOP_RWLK);
  20957. + ADD_NDS32_BUILTIN1 ("tlbop_unlk", void, unsigned, TLBOP_UNLK);
  20958. + ADD_NDS32_BUILTIN1 ("tlbop_pb", unsigned, unsigned, TLBOP_PB);
  20959. + ADD_NDS32_BUILTIN1 ("tlbop_inv", void, unsigned, TLBOP_INV);
  20960. + ADD_NDS32_BUILTIN0 ("tlbop_flua", void, TLBOP_FLUA);
  20961. +
  20962. + /* Unaligned Load/Store */
  20963. + ADD_NDS32_BUILTIN1 ("unaligned_load_hw", short_unsigned, ptr_ushort,
  20964. + UALOAD_HW);
  20965. + ADD_NDS32_BUILTIN1 ("unaligned_load_w", unsigned, ptr_uint, UALOAD_W);
  20966. + ADD_NDS32_BUILTIN1 ("unaligned_load_dw", long_long_unsigned, ptr_ulong,
  20967. + UALOAD_DW);
  20968. + ADD_NDS32_BUILTIN2 ("unaligned_store_hw", void, ptr_ushort, short_unsigned,
  20969. + UASTORE_HW);
  20970. + ADD_NDS32_BUILTIN2 ("unaligned_store_w", void, ptr_uint, unsigned, UASTORE_W);
  20971. + ADD_NDS32_BUILTIN2 ("unaligned_store_dw", void, ptr_ulong, long_long_unsigned,
  20972. + UASTORE_DW);
  20973. + ADD_NDS32_BUILTIN0 ("unaligned_feature", unsigned, UNALIGNED_FEATURE);
  20974. + ADD_NDS32_BUILTIN0 ("enable_unaligned", void, ENABLE_UNALIGNED);
  20975. + ADD_NDS32_BUILTIN0 ("disable_unaligned", void, DISABLE_UNALIGNED);
  20976. +
  20977. + /* Instruction sequence protection */
  20978. + ADD_NDS32_BUILTIN0 ("signature_begin", void, SIGNATURE_BEGIN);
  20979. + ADD_NDS32_BUILTIN0 ("signature_end", void, SIGNATURE_END);
  20980. +
  20981. + /* DSP Extension: SIMD 16bit Add and Subtract. */
  20982. + ADD_NDS32_BUILTIN2 ("add16", unsigned, unsigned, unsigned, ADD16);
  20983. + ADD_NDS32_BUILTIN2 ("v_uadd16", u_v2hi, u_v2hi, u_v2hi, V_UADD16);
  20984. + ADD_NDS32_BUILTIN2 ("v_sadd16", v2hi, v2hi, v2hi, V_SADD16);
  20985. + ADD_NDS32_BUILTIN2 ("radd16", unsigned, unsigned, unsigned, RADD16);
  20986. + ADD_NDS32_BUILTIN2 ("v_radd16", v2hi, v2hi, v2hi, V_RADD16);
  20987. + ADD_NDS32_BUILTIN2 ("uradd16", unsigned, unsigned, unsigned, URADD16);
  20988. + ADD_NDS32_BUILTIN2 ("v_uradd16", u_v2hi, u_v2hi, u_v2hi, V_URADD16);
  20989. + ADD_NDS32_BUILTIN2 ("kadd16", unsigned, unsigned, unsigned, KADD16);
  20990. + ADD_NDS32_BUILTIN2 ("v_kadd16", v2hi, v2hi, v2hi, V_KADD16);
  20991. + ADD_NDS32_BUILTIN2 ("ukadd16", unsigned, unsigned, unsigned, UKADD16);
  20992. + ADD_NDS32_BUILTIN2 ("v_ukadd16", u_v2hi, u_v2hi, u_v2hi, V_UKADD16);
  20993. + ADD_NDS32_BUILTIN2 ("sub16", unsigned, unsigned, unsigned, SUB16);
  20994. + ADD_NDS32_BUILTIN2 ("v_usub16", u_v2hi, u_v2hi, u_v2hi, V_USUB16);
  20995. + ADD_NDS32_BUILTIN2 ("v_ssub16", v2hi, v2hi, v2hi, V_SSUB16);
  20996. + ADD_NDS32_BUILTIN2 ("rsub16", unsigned, unsigned, unsigned, RSUB16);
  20997. + ADD_NDS32_BUILTIN2 ("v_rsub16", v2hi, v2hi, v2hi, V_RSUB16);
  20998. + ADD_NDS32_BUILTIN2 ("ursub16", unsigned, unsigned, unsigned, URSUB16);
  20999. + ADD_NDS32_BUILTIN2 ("v_ursub16", u_v2hi, u_v2hi, u_v2hi, V_URSUB16);
  21000. + ADD_NDS32_BUILTIN2 ("ksub16", unsigned, unsigned, unsigned, KSUB16);
  21001. + ADD_NDS32_BUILTIN2 ("v_ksub16", v2hi, v2hi, v2hi, V_KSUB16);
  21002. + ADD_NDS32_BUILTIN2 ("uksub16", unsigned, unsigned, unsigned, UKSUB16);
  21003. + ADD_NDS32_BUILTIN2 ("v_uksub16", u_v2hi, u_v2hi, u_v2hi, V_UKSUB16);
  21004. + ADD_NDS32_BUILTIN2 ("cras16", unsigned, unsigned, unsigned, CRAS16);
  21005. + ADD_NDS32_BUILTIN2 ("v_ucras16", u_v2hi, u_v2hi, u_v2hi, V_UCRAS16);
  21006. + ADD_NDS32_BUILTIN2 ("v_scras16", v2hi, v2hi, v2hi, V_SCRAS16);
  21007. + ADD_NDS32_BUILTIN2 ("rcras16", unsigned, unsigned, unsigned, RCRAS16);
  21008. + ADD_NDS32_BUILTIN2 ("v_rcras16", v2hi, v2hi, v2hi, V_RCRAS16);
  21009. + ADD_NDS32_BUILTIN2 ("urcras16", unsigned, unsigned, unsigned, URCRAS16);
  21010. + ADD_NDS32_BUILTIN2 ("v_urcras16", u_v2hi, u_v2hi, u_v2hi, V_URCRAS16);
  21011. + ADD_NDS32_BUILTIN2 ("kcras16", unsigned, unsigned, unsigned, KCRAS16);
  21012. + ADD_NDS32_BUILTIN2 ("v_kcras16", v2hi, v2hi, v2hi, V_KCRAS16);
  21013. + ADD_NDS32_BUILTIN2 ("ukcras16", unsigned, unsigned, unsigned, UKCRAS16);
  21014. + ADD_NDS32_BUILTIN2 ("v_ukcras16", u_v2hi, u_v2hi, u_v2hi, V_UKCRAS16);
  21015. + ADD_NDS32_BUILTIN2 ("crsa16", unsigned, unsigned, unsigned, CRSA16);
  21016. + ADD_NDS32_BUILTIN2 ("v_ucrsa16", u_v2hi, u_v2hi, u_v2hi, V_UCRSA16);
  21017. + ADD_NDS32_BUILTIN2 ("v_scrsa16", v2hi, v2hi, v2hi, V_SCRSA16);
  21018. + ADD_NDS32_BUILTIN2 ("rcrsa16", unsigned, unsigned, unsigned, RCRSA16);
  21019. + ADD_NDS32_BUILTIN2 ("v_rcrsa16", v2hi, v2hi, v2hi, V_RCRSA16);
  21020. + ADD_NDS32_BUILTIN2 ("urcrsa16", unsigned, unsigned, unsigned, URCRSA16);
  21021. + ADD_NDS32_BUILTIN2 ("v_urcrsa16", u_v2hi, u_v2hi, u_v2hi, V_URCRSA16);
  21022. + ADD_NDS32_BUILTIN2 ("kcrsa16", unsigned, unsigned, unsigned, KCRSA16);
  21023. + ADD_NDS32_BUILTIN2 ("v_kcrsa16", v2hi, v2hi, v2hi, V_KCRSA16);
  21024. + ADD_NDS32_BUILTIN2 ("ukcrsa16", unsigned, unsigned, unsigned, UKCRSA16);
  21025. + ADD_NDS32_BUILTIN2 ("v_ukcrsa16", u_v2hi, u_v2hi, u_v2hi, V_UKCRSA16);
  21026. +
  21027. + /* DSP Extension: SIMD 8bit Add and Subtract. */
  21028. + ADD_NDS32_BUILTIN2 ("add8", integer, integer, integer, ADD8);
  21029. + ADD_NDS32_BUILTIN2 ("v_uadd8", u_v4qi, u_v4qi, u_v4qi, V_UADD8);
  21030. + ADD_NDS32_BUILTIN2 ("v_sadd8", v4qi, v4qi, v4qi, V_SADD8);
  21031. + ADD_NDS32_BUILTIN2 ("radd8", unsigned, unsigned, unsigned, RADD8);
  21032. + ADD_NDS32_BUILTIN2 ("v_radd8", v4qi, v4qi, v4qi, V_RADD8);
  21033. + ADD_NDS32_BUILTIN2 ("uradd8", unsigned, unsigned, unsigned, URADD8);
  21034. + ADD_NDS32_BUILTIN2 ("v_uradd8", u_v4qi, u_v4qi, u_v4qi, V_URADD8);
  21035. + ADD_NDS32_BUILTIN2 ("kadd8", unsigned, unsigned, unsigned, KADD8);
  21036. + ADD_NDS32_BUILTIN2 ("v_kadd8", v4qi, v4qi, v4qi, V_KADD8);
  21037. + ADD_NDS32_BUILTIN2 ("ukadd8", unsigned, unsigned, unsigned, UKADD8);
  21038. + ADD_NDS32_BUILTIN2 ("v_ukadd8", u_v4qi, u_v4qi, u_v4qi, V_UKADD8);
  21039. + ADD_NDS32_BUILTIN2 ("sub8", integer, integer, integer, SUB8);
  21040. + ADD_NDS32_BUILTIN2 ("v_usub8", u_v4qi, u_v4qi, u_v4qi, V_USUB8);
  21041. + ADD_NDS32_BUILTIN2 ("v_ssub8", v4qi, v4qi, v4qi, V_SSUB8);
  21042. + ADD_NDS32_BUILTIN2 ("rsub8", unsigned, unsigned, unsigned, RSUB8);
  21043. + ADD_NDS32_BUILTIN2 ("v_rsub8", v4qi, v4qi, v4qi, V_RSUB8);
  21044. + ADD_NDS32_BUILTIN2 ("ursub8", unsigned, unsigned, unsigned, URSUB8);
  21045. + ADD_NDS32_BUILTIN2 ("v_ursub8", u_v4qi, u_v4qi, u_v4qi, V_URSUB8);
  21046. + ADD_NDS32_BUILTIN2 ("ksub8", unsigned, unsigned, unsigned, KSUB8);
  21047. + ADD_NDS32_BUILTIN2 ("v_ksub8", v4qi, v4qi, v4qi, V_KSUB8);
  21048. + ADD_NDS32_BUILTIN2 ("uksub8", unsigned, unsigned, unsigned, UKSUB8);
  21049. + ADD_NDS32_BUILTIN2 ("v_uksub8", u_v4qi, u_v4qi, u_v4qi, V_UKSUB8);
  21050. +
  21051. + /* DSP Extension: SIMD 16bit Shift. */
  21052. + ADD_NDS32_BUILTIN2 ("sra16", unsigned, unsigned, unsigned, SRA16);
  21053. + ADD_NDS32_BUILTIN2 ("v_sra16", v2hi, v2hi, unsigned, V_SRA16);
  21054. + ADD_NDS32_BUILTIN2 ("sra16_u", unsigned, unsigned, unsigned, SRA16_U);
  21055. + ADD_NDS32_BUILTIN2 ("v_sra16_u", v2hi, v2hi, unsigned, V_SRA16_U);
  21056. + ADD_NDS32_BUILTIN2 ("srl16", unsigned, unsigned, unsigned, SRL16);
  21057. + ADD_NDS32_BUILTIN2 ("v_srl16", u_v2hi, u_v2hi, unsigned, V_SRL16);
  21058. + ADD_NDS32_BUILTIN2 ("srl16_u", unsigned, unsigned, unsigned, SRL16_U);
  21059. + ADD_NDS32_BUILTIN2 ("v_srl16_u", u_v2hi, u_v2hi, unsigned, V_SRL16_U);
  21060. + ADD_NDS32_BUILTIN2 ("sll16", unsigned, unsigned, unsigned, SLL16);
  21061. + ADD_NDS32_BUILTIN2 ("v_sll16", u_v2hi, u_v2hi, unsigned, V_SLL16);
  21062. + ADD_NDS32_BUILTIN2 ("ksll16", unsigned, unsigned, unsigned, KSLL16);
  21063. + ADD_NDS32_BUILTIN2 ("v_ksll16", v2hi, v2hi, unsigned, V_KSLL16);
  21064. + ADD_NDS32_BUILTIN2 ("kslra16", unsigned, unsigned, unsigned, KSLRA16);
  21065. + ADD_NDS32_BUILTIN2 ("v_kslra16", v2hi, v2hi, unsigned, V_KSLRA16);
  21066. + ADD_NDS32_BUILTIN2 ("kslra16_u", unsigned, unsigned, unsigned, KSLRA16_U);
  21067. + ADD_NDS32_BUILTIN2 ("v_kslra16_u", v2hi, v2hi, unsigned, V_KSLRA16_U);
  21068. +
  21069. + /* DSP Extension: 16bit Compare. */
  21070. + ADD_NDS32_BUILTIN2 ("cmpeq16", unsigned, unsigned, unsigned, CMPEQ16);
  21071. + ADD_NDS32_BUILTIN2 ("v_scmpeq16", u_v2hi, v2hi, v2hi, V_SCMPEQ16);
  21072. + ADD_NDS32_BUILTIN2 ("v_ucmpeq16", u_v2hi, u_v2hi, u_v2hi, V_UCMPEQ16);
  21073. + ADD_NDS32_BUILTIN2 ("scmplt16", unsigned, unsigned, unsigned, SCMPLT16);
  21074. + ADD_NDS32_BUILTIN2 ("v_scmplt16", u_v2hi, v2hi, v2hi, V_SCMPLT16);
  21075. + ADD_NDS32_BUILTIN2 ("scmple16", unsigned, unsigned, unsigned, SCMPLE16);
  21076. + ADD_NDS32_BUILTIN2 ("v_scmple16", u_v2hi, v2hi, v2hi, V_SCMPLE16);
  21077. + ADD_NDS32_BUILTIN2 ("ucmplt16", unsigned, unsigned, unsigned, UCMPLT16);
  21078. + ADD_NDS32_BUILTIN2 ("v_ucmplt16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLT16);
  21079. + ADD_NDS32_BUILTIN2 ("ucmple16", unsigned, unsigned, unsigned, UCMPLE16);
  21080. + ADD_NDS32_BUILTIN2 ("v_ucmple16", u_v2hi, u_v2hi, u_v2hi, V_UCMPLE16);
  21081. +
  21082. + /* DSP Extension: 8bit Compare. */
  21083. + ADD_NDS32_BUILTIN2 ("cmpeq8", unsigned, unsigned, unsigned, CMPEQ8);
  21084. + ADD_NDS32_BUILTIN2 ("v_scmpeq8", u_v4qi, v4qi, v4qi, V_SCMPEQ8);
  21085. + ADD_NDS32_BUILTIN2 ("v_ucmpeq8", u_v4qi, u_v4qi, u_v4qi, V_UCMPEQ8);
  21086. + ADD_NDS32_BUILTIN2 ("scmplt8", unsigned, unsigned, unsigned, SCMPLT8);
  21087. + ADD_NDS32_BUILTIN2 ("v_scmplt8", u_v4qi, v4qi, v4qi, V_SCMPLT8);
  21088. + ADD_NDS32_BUILTIN2 ("scmple8", unsigned, unsigned, unsigned, SCMPLE8);
  21089. + ADD_NDS32_BUILTIN2 ("v_scmple8", u_v4qi, v4qi, v4qi, V_SCMPLE8);
  21090. + ADD_NDS32_BUILTIN2 ("ucmplt8", unsigned, unsigned, unsigned, UCMPLT8);
  21091. + ADD_NDS32_BUILTIN2 ("v_ucmplt8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLT8);
  21092. + ADD_NDS32_BUILTIN2 ("ucmple8", unsigned, unsigned, unsigned, UCMPLE8);
  21093. + ADD_NDS32_BUILTIN2 ("v_ucmple8", u_v4qi, u_v4qi, u_v4qi, V_UCMPLE8);
  21094. +
  21095. + /* DSP Extension: SIMD 16bit MISC. */
  21096. + ADD_NDS32_BUILTIN2 ("smin16", unsigned, unsigned, unsigned, SMIN16);
  21097. + ADD_NDS32_BUILTIN2 ("v_smin16", v2hi, v2hi, v2hi, V_SMIN16);
  21098. + ADD_NDS32_BUILTIN2 ("umin16", unsigned, unsigned, unsigned, UMIN16);
  21099. + ADD_NDS32_BUILTIN2 ("v_umin16", u_v2hi, u_v2hi, u_v2hi, V_UMIN16);
  21100. + ADD_NDS32_BUILTIN2 ("smax16", unsigned, unsigned, unsigned, SMAX16);
  21101. + ADD_NDS32_BUILTIN2 ("v_smax16", v2hi, v2hi, v2hi, V_SMAX16);
  21102. + ADD_NDS32_BUILTIN2 ("umax16", unsigned, unsigned, unsigned, UMAX16);
  21103. + ADD_NDS32_BUILTIN2 ("v_umax16", u_v2hi, u_v2hi, u_v2hi, V_UMAX16);
  21104. + ADD_NDS32_BUILTIN2 ("sclip16", unsigned, unsigned, unsigned, SCLIP16);
  21105. + ADD_NDS32_BUILTIN2 ("v_sclip16", v2hi, v2hi, unsigned, V_SCLIP16);
  21106. + ADD_NDS32_BUILTIN2 ("uclip16", unsigned, unsigned, unsigned, UCLIP16);
  21107. + ADD_NDS32_BUILTIN2 ("v_uclip16", v2hi, v2hi, unsigned, V_UCLIP16);
  21108. + ADD_NDS32_BUILTIN2 ("khm16", unsigned, unsigned, unsigned, KHM16);
  21109. + ADD_NDS32_BUILTIN2 ("v_khm16", v2hi, v2hi, v2hi, V_KHM16);
  21110. + ADD_NDS32_BUILTIN2 ("khmx16", unsigned, unsigned, unsigned, KHMX16);
  21111. + ADD_NDS32_BUILTIN2 ("v_khmx16", v2hi, v2hi, v2hi, V_KHMX16);
  21112. + ADD_NDS32_BUILTIN1 ("kabs16", unsigned, unsigned, KABS16);
  21113. + ADD_NDS32_BUILTIN1 ("v_kabs16", v2hi, v2hi, V_KABS16);
  21114. + ADD_NDS32_BUILTIN2 ("smul16", long_long_unsigned, unsigned, unsigned, SMUL16);
  21115. + ADD_NDS32_BUILTIN2 ("v_smul16", v2si, v2hi, v2hi, V_SMUL16);
  21116. + ADD_NDS32_BUILTIN2 ("smulx16",
  21117. + long_long_unsigned, unsigned, unsigned, SMULX16);
  21118. + ADD_NDS32_BUILTIN2 ("v_smulx16", v2si, v2hi, v2hi, V_SMULX16);
  21119. + ADD_NDS32_BUILTIN2 ("umul16", long_long_unsigned, unsigned, unsigned, UMUL16);
  21120. + ADD_NDS32_BUILTIN2 ("v_umul16", u_v2si, u_v2hi, u_v2hi, V_UMUL16);
  21121. + ADD_NDS32_BUILTIN2 ("umulx16",
  21122. + long_long_unsigned, unsigned, unsigned, UMULX16);
  21123. + ADD_NDS32_BUILTIN2 ("v_umulx16", u_v2si, u_v2hi, u_v2hi, V_UMULX16);
  21124. +
  21125. + /* DSP Extension: SIMD 8bit MISC. */
  21126. + ADD_NDS32_BUILTIN2 ("smin8", unsigned, unsigned, unsigned, SMIN8);
  21127. + ADD_NDS32_BUILTIN2 ("v_smin8", v4qi, v4qi, v4qi, V_SMIN8);
  21128. + ADD_NDS32_BUILTIN2 ("umin8", unsigned, unsigned, unsigned, UMIN8);
  21129. + ADD_NDS32_BUILTIN2 ("v_umin8", u_v4qi, u_v4qi, u_v4qi, V_UMIN8);
  21130. + ADD_NDS32_BUILTIN2 ("smax8", unsigned, unsigned, unsigned, SMAX8);
  21131. + ADD_NDS32_BUILTIN2 ("v_smax8", v4qi, v4qi, v4qi, V_SMAX8);
  21132. + ADD_NDS32_BUILTIN2 ("umax8", unsigned, unsigned, unsigned, UMAX8);
  21133. + ADD_NDS32_BUILTIN2 ("v_umax8", u_v4qi, u_v4qi, u_v4qi, V_UMAX8);
  21134. + ADD_NDS32_BUILTIN1 ("kabs8", unsigned, unsigned, KABS8);
  21135. + ADD_NDS32_BUILTIN1 ("v_kabs8", v4qi, v4qi, V_KABS8);
  21136. +
  21137. + /* DSP Extension: 8bit Unpacking. */
  21138. + ADD_NDS32_BUILTIN1 ("sunpkd810", unsigned, unsigned, SUNPKD810);
  21139. + ADD_NDS32_BUILTIN1 ("v_sunpkd810", v2hi, v4qi, V_SUNPKD810);
  21140. + ADD_NDS32_BUILTIN1 ("sunpkd820", unsigned, unsigned, SUNPKD820);
  21141. + ADD_NDS32_BUILTIN1 ("v_sunpkd820", v2hi, v4qi, V_SUNPKD820);
  21142. + ADD_NDS32_BUILTIN1 ("sunpkd830", unsigned, unsigned, SUNPKD830);
  21143. + ADD_NDS32_BUILTIN1 ("v_sunpkd830", v2hi, v4qi, V_SUNPKD830);
  21144. + ADD_NDS32_BUILTIN1 ("sunpkd831", unsigned, unsigned, SUNPKD831);
  21145. + ADD_NDS32_BUILTIN1 ("v_sunpkd831", v2hi, v4qi, V_SUNPKD831);
  21146. + ADD_NDS32_BUILTIN1 ("zunpkd810", unsigned, unsigned, ZUNPKD810);
  21147. + ADD_NDS32_BUILTIN1 ("v_zunpkd810", u_v2hi, u_v4qi, V_ZUNPKD810);
  21148. + ADD_NDS32_BUILTIN1 ("zunpkd820", unsigned, unsigned, ZUNPKD820);
  21149. + ADD_NDS32_BUILTIN1 ("v_zunpkd820", u_v2hi, u_v4qi, V_ZUNPKD820);
  21150. + ADD_NDS32_BUILTIN1 ("zunpkd830", unsigned, unsigned, ZUNPKD830);
  21151. + ADD_NDS32_BUILTIN1 ("v_zunpkd830", u_v2hi, u_v4qi, V_ZUNPKD830);
  21152. + ADD_NDS32_BUILTIN1 ("zunpkd831", unsigned, unsigned, ZUNPKD831);
  21153. + ADD_NDS32_BUILTIN1 ("v_zunpkd831", u_v2hi, u_v4qi, V_ZUNPKD831);
  21154. +
  21155. + /* DSP Extension: 32bit Add and Subtract. */
  21156. + ADD_NDS32_BUILTIN2 ("raddw", integer, integer, integer, RADDW);
  21157. + ADD_NDS32_BUILTIN2 ("uraddw", unsigned, unsigned, unsigned, URADDW);
  21158. + ADD_NDS32_BUILTIN2 ("rsubw", integer, integer, integer, RSUBW);
  21159. + ADD_NDS32_BUILTIN2 ("ursubw", unsigned, unsigned, unsigned, URSUBW);
  21160. +
  21161. + /* DSP Extension: 32bit Shift. */
  21162. + ADD_NDS32_BUILTIN2 ("sra_u", integer, integer, unsigned, SRA_U);
  21163. + ADD_NDS32_BUILTIN2 ("ksll", integer, integer, unsigned, KSLL);
  21164. +
  21165. + /* DSP Extension: 16bit Packing. */
  21166. + ADD_NDS32_BUILTIN2 ("pkbb16", unsigned, unsigned, unsigned, PKBB16);
  21167. + ADD_NDS32_BUILTIN2 ("v_pkbb16", u_v2hi, u_v2hi, u_v2hi, V_PKBB16);
  21168. + ADD_NDS32_BUILTIN2 ("pkbt16", unsigned, unsigned, unsigned, PKBT16);
  21169. + ADD_NDS32_BUILTIN2 ("v_pkbt16", u_v2hi, u_v2hi, u_v2hi, V_PKBT16);
  21170. + ADD_NDS32_BUILTIN2 ("pktb16", unsigned, unsigned, unsigned, PKTB16);
  21171. + ADD_NDS32_BUILTIN2 ("v_pktb16", u_v2hi, u_v2hi, u_v2hi, V_PKTB16);
  21172. + ADD_NDS32_BUILTIN2 ("pktt16", unsigned, unsigned, unsigned, PKTT16);
  21173. + ADD_NDS32_BUILTIN2 ("v_pktt16", u_v2hi, u_v2hi, u_v2hi, V_PKTT16);
  21174. +
  21175. + /* DSP Extension: Signed MSW 32x32 Multiply and ADD. */
  21176. + ADD_NDS32_BUILTIN2 ("smmul", integer, integer, integer, SMMUL);
  21177. + ADD_NDS32_BUILTIN2 ("smmul_u", integer, integer, integer, SMMUL_U);
  21178. + ADD_NDS32_BUILTIN3 ("kmmac", integer, integer, integer, integer, KMMAC);
  21179. + ADD_NDS32_BUILTIN3 ("kmmac_u", integer, integer, integer, integer, KMMAC_U);
  21180. + ADD_NDS32_BUILTIN3 ("kmmsb", integer, integer, integer, integer, KMMSB);
  21181. + ADD_NDS32_BUILTIN3 ("kmmsb_u", integer, integer, integer, integer, KMMSB_U);
  21182. + ADD_NDS32_BUILTIN2 ("kwmmul", integer, integer, integer, KWMMUL);
  21183. + ADD_NDS32_BUILTIN2 ("kwmmul_u", integer, integer, integer, KWMMUL_U);
  21184. +
  21185. + /* DSP Extension: Most Significant Word 32x16 Multiply and ADD. */
  21186. + ADD_NDS32_BUILTIN2 ("smmwb", integer, integer, unsigned, SMMWB);
  21187. + ADD_NDS32_BUILTIN2 ("v_smmwb", integer, integer, v2hi, V_SMMWB);
  21188. + ADD_NDS32_BUILTIN2 ("smmwb_u", integer, integer, unsigned, SMMWB_U);
  21189. + ADD_NDS32_BUILTIN2 ("v_smmwb_u", integer, integer, v2hi, V_SMMWB_U);
  21190. + ADD_NDS32_BUILTIN2 ("smmwt", integer, integer, unsigned, SMMWT);
  21191. + ADD_NDS32_BUILTIN2 ("v_smmwt", integer, integer, v2hi, V_SMMWT);
  21192. + ADD_NDS32_BUILTIN2 ("smmwt_u", integer, integer, unsigned, SMMWT_U);
  21193. + ADD_NDS32_BUILTIN2 ("v_smmwt_u", integer, integer, v2hi, V_SMMWT_U);
  21194. + ADD_NDS32_BUILTIN3 ("kmmawb", integer, integer, integer, unsigned, KMMAWB);
  21195. + ADD_NDS32_BUILTIN3 ("v_kmmawb", integer, integer, integer, v2hi, V_KMMAWB);
  21196. + ADD_NDS32_BUILTIN3 ("kmmawb_u",
  21197. + integer, integer, integer, unsigned, KMMAWB_U);
  21198. + ADD_NDS32_BUILTIN3 ("v_kmmawb_u",
  21199. + integer, integer, integer, v2hi, V_KMMAWB_U);
  21200. + ADD_NDS32_BUILTIN3 ("kmmawt", integer, integer, integer, unsigned, KMMAWT);
  21201. + ADD_NDS32_BUILTIN3 ("v_kmmawt", integer, integer, integer, v2hi, V_KMMAWT);
  21202. + ADD_NDS32_BUILTIN3 ("kmmawt_u",
  21203. + integer, integer, integer, unsigned, KMMAWT_U);
  21204. + ADD_NDS32_BUILTIN3 ("v_kmmawt_u",
  21205. + integer, integer, integer, v2hi, V_KMMAWT_U);
  21206. +
  21207. + /* DSP Extension: Signed 16bit Multiply with ADD/Subtract. */
  21208. + ADD_NDS32_BUILTIN2 ("smbb", integer, unsigned, unsigned, SMBB);
  21209. + ADD_NDS32_BUILTIN2 ("v_smbb", integer, v2hi, v2hi, V_SMBB);
  21210. + ADD_NDS32_BUILTIN2 ("smbt", integer, unsigned, unsigned, SMBT);
  21211. + ADD_NDS32_BUILTIN2 ("v_smbt", integer, v2hi, v2hi, V_SMBT);
  21212. + ADD_NDS32_BUILTIN2 ("smtt", integer, unsigned, unsigned, SMTT);
  21213. + ADD_NDS32_BUILTIN2 ("v_smtt", integer, v2hi, v2hi, V_SMTT);
  21214. + ADD_NDS32_BUILTIN2 ("kmda", integer, unsigned, unsigned, KMDA);
  21215. + ADD_NDS32_BUILTIN2 ("v_kmda", integer, v2hi, v2hi, V_KMDA);
  21216. + ADD_NDS32_BUILTIN2 ("kmxda", integer, unsigned, unsigned, KMXDA);
  21217. + ADD_NDS32_BUILTIN2 ("v_kmxda", integer, v2hi, v2hi, V_KMXDA);
  21218. + ADD_NDS32_BUILTIN2 ("smds", integer, unsigned, unsigned, SMDS);
  21219. + ADD_NDS32_BUILTIN2 ("v_smds", integer, v2hi, v2hi, V_SMDS);
  21220. + ADD_NDS32_BUILTIN2 ("smdrs", integer, unsigned, unsigned, SMDRS);
  21221. + ADD_NDS32_BUILTIN2 ("v_smdrs", integer, v2hi, v2hi, V_SMDRS);
  21222. + ADD_NDS32_BUILTIN2 ("smxds", integer, unsigned, unsigned, SMXDS);
  21223. + ADD_NDS32_BUILTIN2 ("v_smxds", integer, v2hi, v2hi, V_SMXDS);
  21224. + ADD_NDS32_BUILTIN3 ("kmabb", integer, integer, unsigned, unsigned, KMABB);
  21225. + ADD_NDS32_BUILTIN3 ("v_kmabb", integer, integer, v2hi, v2hi, V_KMABB);
  21226. + ADD_NDS32_BUILTIN3 ("kmabt", integer, integer, unsigned, unsigned, KMABT);
  21227. + ADD_NDS32_BUILTIN3 ("v_kmabt", integer, integer, v2hi, v2hi, V_KMABT);
  21228. + ADD_NDS32_BUILTIN3 ("kmatt", integer, integer, unsigned, unsigned, KMATT);
  21229. + ADD_NDS32_BUILTIN3 ("v_kmatt", integer, integer, v2hi, v2hi, V_KMATT);
  21230. + ADD_NDS32_BUILTIN3 ("kmada", integer, integer, unsigned, unsigned, KMADA);
  21231. + ADD_NDS32_BUILTIN3 ("v_kmada", integer, integer, v2hi, v2hi, V_KMADA);
  21232. + ADD_NDS32_BUILTIN3 ("kmaxda", integer, integer, unsigned, unsigned, KMAXDA);
  21233. + ADD_NDS32_BUILTIN3 ("v_kmaxda", integer, integer, v2hi, v2hi, V_KMAXDA);
  21234. + ADD_NDS32_BUILTIN3 ("kmads", integer, integer, unsigned, unsigned, KMADS);
  21235. + ADD_NDS32_BUILTIN3 ("v_kmads", integer, integer, v2hi, v2hi, V_KMADS);
  21236. + ADD_NDS32_BUILTIN3 ("kmadrs", integer, integer, unsigned, unsigned, KMADRS);
  21237. + ADD_NDS32_BUILTIN3 ("v_kmadrs", integer, integer, v2hi, v2hi, V_KMADRS);
  21238. + ADD_NDS32_BUILTIN3 ("kmaxds", integer, integer, unsigned, unsigned, KMAXDS);
  21239. + ADD_NDS32_BUILTIN3 ("v_kmaxds", integer, integer, v2hi, v2hi, V_KMAXDS);
  21240. + ADD_NDS32_BUILTIN3 ("kmsda", integer, integer, unsigned, unsigned, KMSDA);
  21241. + ADD_NDS32_BUILTIN3 ("v_kmsda", integer, integer, v2hi, v2hi, V_KMSDA);
  21242. + ADD_NDS32_BUILTIN3 ("kmsxda", integer, integer, unsigned, unsigned, KMSXDA);
  21243. + ADD_NDS32_BUILTIN3 ("v_kmsxda", integer, integer, v2hi, v2hi, V_KMSXDA);
  21244. +
  21245. + /* DSP Extension: Signed 16bit Multiply with 64bit ADD/Subtract. */
  21246. + ADD_NDS32_BUILTIN2 ("smal", long_long_integer,
  21247. + long_long_integer, unsigned, SMAL);
  21248. + ADD_NDS32_BUILTIN2 ("v_smal", long_long_integer,
  21249. + long_long_integer, v2hi, V_SMAL);
  21250. +
  21251. + /* DSP Extension: 32bit MISC. */
  21252. + ADD_NDS32_BUILTIN2 ("bitrev", unsigned, unsigned, unsigned, BITREV);
  21253. + ADD_NDS32_BUILTIN2 ("wext", unsigned, long_long_integer, unsigned, WEXT);
  21254. + ADD_NDS32_BUILTIN3 ("bpick", unsigned, unsigned, unsigned, unsigned, BPICK);
  21255. + ADD_NDS32_BUILTIN3 ("insb", unsigned, unsigned, unsigned, unsigned, INSB);
  21256. +
  21257. + /* DSP Extension: 64bit Add and Subtract. */
  21258. + ADD_NDS32_BUILTIN2 ("sadd64", long_long_integer,
  21259. + long_long_integer, long_long_integer, SADD64);
  21260. + ADD_NDS32_BUILTIN2 ("uadd64", long_long_unsigned,
  21261. + long_long_unsigned, long_long_unsigned, UADD64);
  21262. + ADD_NDS32_BUILTIN2 ("radd64", long_long_integer,
  21263. + long_long_integer, long_long_integer, RADD64);
  21264. + ADD_NDS32_BUILTIN2 ("uradd64", long_long_unsigned,
  21265. + long_long_unsigned, long_long_unsigned, URADD64);
  21266. + ADD_NDS32_BUILTIN2 ("kadd64", long_long_integer,
  21267. + long_long_integer, long_long_integer, KADD64);
  21268. + ADD_NDS32_BUILTIN2 ("ukadd64", long_long_unsigned,
  21269. + long_long_unsigned, long_long_unsigned, UKADD64);
  21270. + ADD_NDS32_BUILTIN2 ("ssub64", long_long_integer,
  21271. + long_long_integer, long_long_integer, SSUB64);
  21272. + ADD_NDS32_BUILTIN2 ("usub64", long_long_unsigned,
  21273. + long_long_unsigned, long_long_unsigned, USUB64);
  21274. + ADD_NDS32_BUILTIN2 ("rsub64", long_long_integer,
  21275. + long_long_integer, long_long_integer, RSUB64);
  21276. + ADD_NDS32_BUILTIN2 ("ursub64", long_long_unsigned,
  21277. + long_long_unsigned, long_long_unsigned, URSUB64);
  21278. + ADD_NDS32_BUILTIN2 ("ksub64", long_long_integer,
  21279. + long_long_integer, long_long_integer, KSUB64);
  21280. + ADD_NDS32_BUILTIN2 ("uksub64", long_long_unsigned,
  21281. + long_long_unsigned, long_long_unsigned, UKSUB64);
  21282. +
  21283. + /* DSP Extension: 32bit Multiply with 64bit Add/Subtract. */
  21284. + ADD_NDS32_BUILTIN3 ("smar64", long_long_integer,
  21285. + long_long_integer, integer, integer, SMAR64);
  21286. + ADD_NDS32_BUILTIN3 ("smsr64", long_long_integer,
  21287. + long_long_integer, integer, integer, SMSR64);
  21288. + ADD_NDS32_BUILTIN3 ("umar64", long_long_unsigned,
  21289. + long_long_unsigned, unsigned, unsigned, UMAR64);
  21290. + ADD_NDS32_BUILTIN3 ("umsr64", long_long_unsigned,
  21291. + long_long_unsigned, unsigned, unsigned, UMSR64);
  21292. + ADD_NDS32_BUILTIN3 ("kmar64", long_long_integer,
  21293. + long_long_integer, integer, integer, KMAR64);
  21294. + ADD_NDS32_BUILTIN3 ("kmsr64", long_long_integer,
  21295. + long_long_integer, integer, integer, KMSR64);
  21296. + ADD_NDS32_BUILTIN3 ("ukmar64", long_long_unsigned,
  21297. + long_long_unsigned, unsigned, unsigned, UKMAR64);
  21298. + ADD_NDS32_BUILTIN3 ("ukmsr64", long_long_unsigned,
  21299. + long_long_unsigned, unsigned, unsigned, UKMSR64);
  21300. +
  21301. + /* DSP Extension: Signed 16bit Multiply with 64bit Add/Subtract. */
  21302. + ADD_NDS32_BUILTIN3 ("smalbb", long_long_integer,
  21303. + long_long_integer, unsigned, unsigned, SMALBB);
  21304. + ADD_NDS32_BUILTIN3 ("v_smalbb", long_long_integer,
  21305. + long_long_integer, v2hi, v2hi, V_SMALBB);
  21306. + ADD_NDS32_BUILTIN3 ("smalbt", long_long_integer,
  21307. + long_long_integer, unsigned, unsigned, SMALBT);
  21308. + ADD_NDS32_BUILTIN3 ("v_smalbt", long_long_integer,
  21309. + long_long_integer, v2hi, v2hi, V_SMALBT);
  21310. + ADD_NDS32_BUILTIN3 ("smaltt", long_long_integer,
  21311. + long_long_integer, unsigned, unsigned, SMALTT);
  21312. + ADD_NDS32_BUILTIN3 ("v_smaltt", long_long_integer,
  21313. + long_long_integer, v2hi, v2hi, V_SMALTT);
  21314. + ADD_NDS32_BUILTIN3 ("smalda", long_long_integer,
  21315. + long_long_integer, unsigned, unsigned, SMALDA);
  21316. + ADD_NDS32_BUILTIN3 ("v_smalda", long_long_integer,
  21317. + long_long_integer, v2hi, v2hi, V_SMALDA);
  21318. + ADD_NDS32_BUILTIN3 ("smalxda", long_long_integer,
  21319. + long_long_integer, unsigned, unsigned, SMALXDA);
  21320. + ADD_NDS32_BUILTIN3 ("v_smalxda", long_long_integer,
  21321. + long_long_integer, v2hi, v2hi, V_SMALXDA);
  21322. + ADD_NDS32_BUILTIN3 ("smalds", long_long_integer,
  21323. + long_long_integer, unsigned, unsigned, SMALDS);
  21324. + ADD_NDS32_BUILTIN3 ("v_smalds", long_long_integer,
  21325. + long_long_integer, v2hi, v2hi, V_SMALDS);
  21326. + ADD_NDS32_BUILTIN3 ("smaldrs", long_long_integer,
  21327. + long_long_integer, unsigned, unsigned, SMALDRS);
  21328. + ADD_NDS32_BUILTIN3 ("v_smaldrs", long_long_integer,
  21329. + long_long_integer, v2hi, v2hi, V_SMALDRS);
  21330. + ADD_NDS32_BUILTIN3 ("smalxds", long_long_integer,
  21331. + long_long_integer, unsigned, unsigned, SMALXDS);
  21332. + ADD_NDS32_BUILTIN3 ("v_smalxds", long_long_integer,
  21333. + long_long_integer, v2hi, v2hi, V_SMALXDS);
  21334. + ADD_NDS32_BUILTIN3 ("smslda", long_long_integer,
  21335. + long_long_integer, unsigned, unsigned, SMSLDA);
  21336. + ADD_NDS32_BUILTIN3 ("v_smslda", long_long_integer,
  21337. + long_long_integer, v2hi, v2hi, V_SMSLDA);
  21338. + ADD_NDS32_BUILTIN3 ("smslxda", long_long_integer,
  21339. + long_long_integer, unsigned, unsigned, SMSLXDA);
  21340. + ADD_NDS32_BUILTIN3 ("v_smslxda", long_long_integer,
  21341. + long_long_integer, v2hi, v2hi, V_SMSLXDA);
  21342. +
  21343. + /* DSP Extension: augmented baseline. */
  21344. + ADD_NDS32_BUILTIN2 ("uclip32", unsigned, integer, unsigned, UCLIP32);
  21345. + ADD_NDS32_BUILTIN2 ("sclip32", integer, integer, unsigned, SCLIP32);
  21346. + ADD_NDS32_BUILTIN1 ("kabs", integer, integer, KABS);
  21347. +
  21348. + /* The builtin turn off hwloop optimization. */
  21349. + ADD_NDS32_BUILTIN0 ("no_ext_zol", void, NO_HWLOOP);
  21350. +}
  21351. +/* ------------------------------------------------------------------------ */
  21352. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32_intrinsic.h gcc-4.9.4/gcc/config/nds32/nds32_intrinsic.h
  21353. --- gcc-4.9.4.orig/gcc/config/nds32/nds32_intrinsic.h 2014-01-02 23:23:26.000000000 +0100
  21354. +++ gcc-4.9.4/gcc/config/nds32/nds32_intrinsic.h 2016-08-08 20:37:45.594273497 +0200
  21355. @@ -1,5 +1,5 @@
  21356. /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
  21357. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  21358. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  21359. Contributed by Andes Technology Corporation.
  21360. This file is part of GCC.
  21361. @@ -26,12 +26,1319 @@
  21362. #ifndef _NDS32_INTRINSIC_H
  21363. #define _NDS32_INTRINSIC_H
  21364. +typedef signed char int8x4_t __attribute ((vector_size(4)));
  21365. +typedef short int16x2_t __attribute ((vector_size(4)));
  21366. +typedef int int32x2_t __attribute__((vector_size(8)));
  21367. +typedef unsigned char uint8x4_t __attribute__ ((vector_size (4)));
  21368. +typedef unsigned short uint16x2_t __attribute__ ((vector_size (4)));
  21369. +typedef unsigned int uint32x2_t __attribute__((vector_size(8)));
  21370. +
  21371. +/* General instrinsic register names. */
  21372. enum nds32_intrinsic_registers
  21373. {
  21374. - __NDS32_REG_PSW__ = 1024,
  21375. + __NDS32_REG_CPU_VER__ = 1024,
  21376. + __NDS32_REG_ICM_CFG__,
  21377. + __NDS32_REG_DCM_CFG__,
  21378. + __NDS32_REG_MMU_CFG__,
  21379. + __NDS32_REG_MSC_CFG__,
  21380. + __NDS32_REG_MSC_CFG2__,
  21381. + __NDS32_REG_CORE_ID__,
  21382. + __NDS32_REG_FUCOP_EXIST__,
  21383. +
  21384. + __NDS32_REG_PSW__,
  21385. __NDS32_REG_IPSW__,
  21386. + __NDS32_REG_P_IPSW__,
  21387. + __NDS32_REG_IVB__,
  21388. + __NDS32_REG_EVA__,
  21389. + __NDS32_REG_P_EVA__,
  21390. __NDS32_REG_ITYPE__,
  21391. - __NDS32_REG_IPC__
  21392. + __NDS32_REG_P_ITYPE__,
  21393. +
  21394. + __NDS32_REG_MERR__,
  21395. + __NDS32_REG_IPC__,
  21396. + __NDS32_REG_P_IPC__,
  21397. + __NDS32_REG_OIPC__,
  21398. + __NDS32_REG_P_P0__,
  21399. + __NDS32_REG_P_P1__,
  21400. +
  21401. + __NDS32_REG_INT_MASK__,
  21402. + __NDS32_REG_INT_MASK2__,
  21403. + __NDS32_REG_INT_PEND__,
  21404. + __NDS32_REG_INT_PEND2__,
  21405. + __NDS32_REG_SP_USR__,
  21406. + __NDS32_REG_SP_PRIV__,
  21407. + __NDS32_REG_INT_PRI__,
  21408. + __NDS32_REG_INT_PRI2__,
  21409. + __NDS32_REG_INT_CTRL__,
  21410. + __NDS32_REG_INT_TRIGGER__,
  21411. + __NDS32_REG_INT_GPR_PUSH_DIS__,
  21412. +
  21413. + __NDS32_REG_MMU_CTL__,
  21414. + __NDS32_REG_L1_PPTB__,
  21415. + __NDS32_REG_TLB_VPN__,
  21416. + __NDS32_REG_TLB_DATA__,
  21417. + __NDS32_REG_TLB_MISC__,
  21418. + __NDS32_REG_VLPT_IDX__,
  21419. + __NDS32_REG_ILMB__,
  21420. + __NDS32_REG_DLMB__,
  21421. +
  21422. + __NDS32_REG_CACHE_CTL__,
  21423. + __NDS32_REG_HSMP_SADDR__,
  21424. + __NDS32_REG_HSMP_EADDR__,
  21425. + __NDS32_REG_SDZ_CTL__,
  21426. + __NDS32_REG_N12MISC_CTL__,
  21427. + __NDS32_REG_MISC_CTL__,
  21428. + __NDS32_REG_ECC_MISC__,
  21429. +
  21430. + __NDS32_REG_BPC0__,
  21431. + __NDS32_REG_BPC1__,
  21432. + __NDS32_REG_BPC2__,
  21433. + __NDS32_REG_BPC3__,
  21434. + __NDS32_REG_BPC4__,
  21435. + __NDS32_REG_BPC5__,
  21436. + __NDS32_REG_BPC6__,
  21437. + __NDS32_REG_BPC7__,
  21438. +
  21439. + __NDS32_REG_BPA0__,
  21440. + __NDS32_REG_BPA1__,
  21441. + __NDS32_REG_BPA2__,
  21442. + __NDS32_REG_BPA3__,
  21443. + __NDS32_REG_BPA4__,
  21444. + __NDS32_REG_BPA5__,
  21445. + __NDS32_REG_BPA6__,
  21446. + __NDS32_REG_BPA7__,
  21447. +
  21448. + __NDS32_REG_BPAM0__,
  21449. + __NDS32_REG_BPAM1__,
  21450. + __NDS32_REG_BPAM2__,
  21451. + __NDS32_REG_BPAM3__,
  21452. + __NDS32_REG_BPAM4__,
  21453. + __NDS32_REG_BPAM5__,
  21454. + __NDS32_REG_BPAM6__,
  21455. + __NDS32_REG_BPAM7__,
  21456. +
  21457. + __NDS32_REG_BPV0__,
  21458. + __NDS32_REG_BPV1__,
  21459. + __NDS32_REG_BPV2__,
  21460. + __NDS32_REG_BPV3__,
  21461. + __NDS32_REG_BPV4__,
  21462. + __NDS32_REG_BPV5__,
  21463. + __NDS32_REG_BPV6__,
  21464. + __NDS32_REG_BPV7__,
  21465. +
  21466. + __NDS32_REG_BPCID0__,
  21467. + __NDS32_REG_BPCID1__,
  21468. + __NDS32_REG_BPCID2__,
  21469. + __NDS32_REG_BPCID3__,
  21470. + __NDS32_REG_BPCID4__,
  21471. + __NDS32_REG_BPCID5__,
  21472. + __NDS32_REG_BPCID6__,
  21473. + __NDS32_REG_BPCID7__,
  21474. +
  21475. + __NDS32_REG_EDM_CFG__,
  21476. + __NDS32_REG_EDMSW__,
  21477. + __NDS32_REG_EDM_CTL__,
  21478. + __NDS32_REG_EDM_DTR__,
  21479. + __NDS32_REG_BPMTC__,
  21480. + __NDS32_REG_DIMBR__,
  21481. +
  21482. + __NDS32_REG_TECR0__,
  21483. + __NDS32_REG_TECR1__,
  21484. + __NDS32_REG_PFMC0__,
  21485. + __NDS32_REG_PFMC1__,
  21486. + __NDS32_REG_PFMC2__,
  21487. + __NDS32_REG_PFM_CTL__,
  21488. + __NDS32_REG_PFT_CTL__,
  21489. + __NDS32_REG_HSP_CTL__,
  21490. + __NDS32_REG_SP_BOUND__,
  21491. + __NDS32_REG_SP_BOUND_PRIV__,
  21492. + __NDS32_REG_FUCOP_CTL__,
  21493. + __NDS32_REG_PRUSR_ACC_CTL__,
  21494. +
  21495. + __NDS32_REG_DMA_CFG__,
  21496. + __NDS32_REG_DMA_GCSW__,
  21497. + __NDS32_REG_DMA_CHNSEL__,
  21498. + __NDS32_REG_DMA_ACT__,
  21499. + __NDS32_REG_DMA_SETUP__,
  21500. + __NDS32_REG_DMA_ISADDR__,
  21501. + __NDS32_REG_DMA_ESADDR__,
  21502. + __NDS32_REG_DMA_TCNT__,
  21503. + __NDS32_REG_DMA_STATUS__,
  21504. + __NDS32_REG_DMA_2DSET__,
  21505. + __NDS32_REG_DMA_2DSCTL__,
  21506. + __NDS32_REG_DMA_RCNT__,
  21507. + __NDS32_REG_DMA_HSTATUS__,
  21508. +
  21509. + __NDS32_REG_PC__,
  21510. + __NDS32_REG_SP_USR1__,
  21511. + __NDS32_REG_SP_USR2__,
  21512. + __NDS32_REG_SP_USR3__,
  21513. + __NDS32_REG_SP_PRIV1__,
  21514. + __NDS32_REG_SP_PRIV2__,
  21515. + __NDS32_REG_SP_PRIV3__,
  21516. + __NDS32_REG_BG_REGION__,
  21517. + __NDS32_REG_SFCR__,
  21518. + __NDS32_REG_SIGN__,
  21519. + __NDS32_REG_ISIGN__,
  21520. + __NDS32_REG_P_ISIGN__,
  21521. + __NDS32_REG_IFC_LP__,
  21522. + __NDS32_REG_ITB__
  21523. +};
  21524. +
  21525. +/* The cctl subtype for intrinsic. */
  21526. +enum nds32_cctl_valck
  21527. +{
  21528. + __NDS32_CCTL_L1D_VA_FILLCK__,
  21529. + __NDS32_CCTL_L1D_VA_ULCK__,
  21530. + __NDS32_CCTL_L1I_VA_FILLCK__,
  21531. + __NDS32_CCTL_L1I_VA_ULCK__
  21532. +};
  21533. +
  21534. +enum nds32_cctl_idxwbinv
  21535. +{
  21536. + __NDS32_CCTL_L1D_IX_WBINVAL__,
  21537. + __NDS32_CCTL_L1D_IX_INVAL__,
  21538. + __NDS32_CCTL_L1D_IX_WB__,
  21539. + __NDS32_CCTL_L1I_IX_INVAL__
  21540. };
  21541. +enum nds32_cctl_vawbinv
  21542. +{
  21543. + __NDS32_CCTL_L1D_VA_INVAL__,
  21544. + __NDS32_CCTL_L1D_VA_WB__,
  21545. + __NDS32_CCTL_L1D_VA_WBINVAL__,
  21546. + __NDS32_CCTL_L1I_VA_INVAL__
  21547. +};
  21548. +
  21549. +enum nds32_cctl_idxread
  21550. +{
  21551. + __NDS32_CCTL_L1D_IX_RTAG__,
  21552. + __NDS32_CCTL_L1D_IX_RWD__,
  21553. + __NDS32_CCTL_L1I_IX_RTAG__,
  21554. + __NDS32_CCTL_L1I_IX_RWD__
  21555. +};
  21556. +
  21557. +enum nds32_cctl_idxwrite
  21558. +{
  21559. + __NDS32_CCTL_L1D_IX_WTAG__,
  21560. + __NDS32_CCTL_L1D_IX_WWD__,
  21561. + __NDS32_CCTL_L1I_IX_WTAG__,
  21562. + __NDS32_CCTL_L1I_IX_WWD__
  21563. +};
  21564. +
  21565. +enum nds32_dpref
  21566. +{
  21567. + __NDS32_DPREF_SRD__,
  21568. + __NDS32_DPREF_MRD__,
  21569. + __NDS32_DPREF_SWR__,
  21570. + __NDS32_DPREF_MWR__,
  21571. + __NDS32_DPREF_PTE__,
  21572. + __NDS32_DPREF_CLWR__
  21573. +};
  21574. +
  21575. +/* ------------------------------------------------------------------------ */
  21576. +
  21577. +/* Define interrupt number for intrinsic function. */
  21578. +#define NDS32_INT_H0 0
  21579. +#define NDS32_INT_H1 1
  21580. +#define NDS32_INT_H2 2
  21581. +#define NDS32_INT_H3 3
  21582. +#define NDS32_INT_H4 4
  21583. +#define NDS32_INT_H5 5
  21584. +#define NDS32_INT_H6 6
  21585. +#define NDS32_INT_H7 7
  21586. +#define NDS32_INT_H8 8
  21587. +#define NDS32_INT_H9 9
  21588. +#define NDS32_INT_H10 10
  21589. +#define NDS32_INT_H11 11
  21590. +#define NDS32_INT_H12 12
  21591. +#define NDS32_INT_H13 13
  21592. +#define NDS32_INT_H14 14
  21593. +#define NDS32_INT_H15 15
  21594. +#define NDS32_INT_SWI 16
  21595. +#define NDS32_INT_ALZ 29
  21596. +#define NDS32_INT_IDIVZE 30
  21597. +#define NDS32_INT_DSSIM 31
  21598. +#define NDS32_INT_H16 32
  21599. +#define NDS32_INT_H17 33
  21600. +#define NDS32_INT_H18 34
  21601. +#define NDS32_INT_H19 35
  21602. +#define NDS32_INT_H20 36
  21603. +#define NDS32_INT_H21 37
  21604. +#define NDS32_INT_H22 38
  21605. +#define NDS32_INT_H23 39
  21606. +#define NDS32_INT_H24 40
  21607. +#define NDS32_INT_H25 41
  21608. +#define NDS32_INT_H26 42
  21609. +#define NDS32_INT_H27 43
  21610. +#define NDS32_INT_H28 44
  21611. +#define NDS32_INT_H29 45
  21612. +#define NDS32_INT_H30 46
  21613. +#define NDS32_INT_H31 47
  21614. +
  21615. +/* ------------------------------------------------------------------------ */
  21616. +
  21617. +/* Define intrinsic register name macro for compatibility. */
  21618. +#define NDS32_SR_CPU_VER __NDS32_REG_CPU_VER__
  21619. +#define NDS32_SR_ICM_CFG __NDS32_REG_ICM_CFG__
  21620. +#define NDS32_SR_DCM_CFG __NDS32_REG_DCM_CFG__
  21621. +#define NDS32_SR_MMU_CFG __NDS32_REG_MMU_CFG__
  21622. +#define NDS32_SR_MSC_CFG __NDS32_REG_MSC_CFG__
  21623. +#define NDS32_SR_MSC_CFG2 __NDS32_REG_MSC_CFG2__
  21624. +#define NDS32_SR_CORE_ID __NDS32_REG_CORE_ID__
  21625. +#define NDS32_SR_FUCOP_EXIST __NDS32_REG_FUCOP_EXIST__
  21626. +#define NDS32_SR_PSW __NDS32_REG_PSW__
  21627. +#define NDS32_SR_IPSW __NDS32_REG_IPSW__
  21628. +#define NDS32_SR_P_IPSW __NDS32_REG_P_IPSW__
  21629. +#define NDS32_SR_IVB __NDS32_REG_IVB__
  21630. +#define NDS32_SR_EVA __NDS32_REG_EVA__
  21631. +#define NDS32_SR_P_EVA __NDS32_REG_P_EVA__
  21632. +#define NDS32_SR_ITYPE __NDS32_REG_ITYPE__
  21633. +#define NDS32_SR_P_ITYPE __NDS32_REG_P_ITYPE__
  21634. +#define NDS32_SR_MERR __NDS32_REG_MERR__
  21635. +#define NDS32_SR_IPC __NDS32_REG_IPC__
  21636. +#define NDS32_SR_P_IPC __NDS32_REG_P_IPC__
  21637. +#define NDS32_SR_OIPC __NDS32_REG_OIPC__
  21638. +#define NDS32_SR_P_P0 __NDS32_REG_P_P0__
  21639. +#define NDS32_SR_P_P1 __NDS32_REG_P_P1__
  21640. +#define NDS32_SR_INT_MASK __NDS32_REG_INT_MASK__
  21641. +#define NDS32_SR_INT_MASK2 __NDS32_REG_INT_MASK2__
  21642. +#define NDS32_SR_INT_PEND __NDS32_REG_INT_PEND__
  21643. +#define NDS32_SR_INT_PEND2 __NDS32_REG_INT_PEND2__
  21644. +#define NDS32_SR_SP_USR __NDS32_REG_SP_USR__
  21645. +#define NDS32_SR_SP_PRIV __NDS32_REG_SP_PRIV__
  21646. +#define NDS32_SR_INT_PRI __NDS32_REG_INT_PRI__
  21647. +#define NDS32_SR_INT_PRI2 __NDS32_REG_INT_PRI2__
  21648. +#define NDS32_SR_INT_CTRL __NDS32_REG_INT_CTRL__
  21649. +#define NDS32_SR_INT_TRIGGER __NDS32_REG_INT_TRIGGER__
  21650. +#define NDS32_SR_INT_GPR_PUSH_DIS __NDS32_REG_INT_GPR_PUSH_DIS__
  21651. +#define NDS32_SR_MMU_CTL __NDS32_REG_MMU_CTL__
  21652. +#define NDS32_SR_L1_PPTB __NDS32_REG_L1_PPTB__
  21653. +#define NDS32_SR_TLB_VPN __NDS32_REG_TLB_VPN__
  21654. +#define NDS32_SR_TLB_DATA __NDS32_REG_TLB_DATA__
  21655. +#define NDS32_SR_TLB_MISC __NDS32_REG_TLB_MISC__
  21656. +#define NDS32_SR_VLPT_IDX __NDS32_REG_VLPT_IDX__
  21657. +#define NDS32_SR_ILMB __NDS32_REG_ILMB__
  21658. +#define NDS32_SR_DLMB __NDS32_REG_DLMB__
  21659. +#define NDS32_SR_CACHE_CTL __NDS32_REG_CACHE_CTL__
  21660. +#define NDS32_SR_HSMP_SADDR __NDS32_REG_HSMP_SADDR__
  21661. +#define NDS32_SR_HSMP_EADDR __NDS32_REG_HSMP_EADDR__
  21662. +#define NDS32_SR_SDZ_CTL __NDS32_REG_SDZ_CTL__
  21663. +#define NDS32_SR_N12MISC_CTL __NDS32_REG_N12MISC_CTL__
  21664. +#define NDS32_SR_MISC_CTL __NDS32_REG_MISC_CTL__
  21665. +#define NDS32_SR_ECC_MISC __NDS32_REG_ECC_MISC__
  21666. +#define NDS32_SR_BPC0 __NDS32_REG_BPC0__
  21667. +#define NDS32_SR_BPC1 __NDS32_REG_BPC1__
  21668. +#define NDS32_SR_BPC2 __NDS32_REG_BPC2__
  21669. +#define NDS32_SR_BPC3 __NDS32_REG_BPC3__
  21670. +#define NDS32_SR_BPC4 __NDS32_REG_BPC4__
  21671. +#define NDS32_SR_BPC5 __NDS32_REG_BPC5__
  21672. +#define NDS32_SR_BPC6 __NDS32_REG_BPC6__
  21673. +#define NDS32_SR_BPC7 __NDS32_REG_BPC7__
  21674. +#define NDS32_SR_BPA0 __NDS32_REG_BPA0__
  21675. +#define NDS32_SR_BPA1 __NDS32_REG_BPA1__
  21676. +#define NDS32_SR_BPA2 __NDS32_REG_BPA2__
  21677. +#define NDS32_SR_BPA3 __NDS32_REG_BPA3__
  21678. +#define NDS32_SR_BPA4 __NDS32_REG_BPA4__
  21679. +#define NDS32_SR_BPA5 __NDS32_REG_BPA5__
  21680. +#define NDS32_SR_BPA6 __NDS32_REG_BPA6__
  21681. +#define NDS32_SR_BPA7 __NDS32_REG_BPA7__
  21682. +#define NDS32_SR_BPAM0 __NDS32_REG_BPAM0__
  21683. +#define NDS32_SR_BPAM1 __NDS32_REG_BPAM1__
  21684. +#define NDS32_SR_BPAM2 __NDS32_REG_BPAM2__
  21685. +#define NDS32_SR_BPAM3 __NDS32_REG_BPAM3__
  21686. +#define NDS32_SR_BPAM4 __NDS32_REG_BPAM4__
  21687. +#define NDS32_SR_BPAM5 __NDS32_REG_BPAM5__
  21688. +#define NDS32_SR_BPAM6 __NDS32_REG_BPAM6__
  21689. +#define NDS32_SR_BPAM7 __NDS32_REG_BPAM7__
  21690. +#define NDS32_SR_BPV0 __NDS32_REG_BPV0__
  21691. +#define NDS32_SR_BPV1 __NDS32_REG_BPV1__
  21692. +#define NDS32_SR_BPV2 __NDS32_REG_BPV2__
  21693. +#define NDS32_SR_BPV3 __NDS32_REG_BPV3__
  21694. +#define NDS32_SR_BPV4 __NDS32_REG_BPV4__
  21695. +#define NDS32_SR_BPV5 __NDS32_REG_BPV5__
  21696. +#define NDS32_SR_BPV6 __NDS32_REG_BPV6__
  21697. +#define NDS32_SR_BPV7 __NDS32_REG_BPV7__
  21698. +#define NDS32_SR_BPCID0 __NDS32_REG_BPCID0__
  21699. +#define NDS32_SR_BPCID1 __NDS32_REG_BPCID1__
  21700. +#define NDS32_SR_BPCID2 __NDS32_REG_BPCID2__
  21701. +#define NDS32_SR_BPCID3 __NDS32_REG_BPCID3__
  21702. +#define NDS32_SR_BPCID4 __NDS32_REG_BPCID4__
  21703. +#define NDS32_SR_BPCID5 __NDS32_REG_BPCID5__
  21704. +#define NDS32_SR_BPCID6 __NDS32_REG_BPCID6__
  21705. +#define NDS32_SR_BPCID7 __NDS32_REG_BPCID7__
  21706. +#define NDS32_SR_EDM_CFG __NDS32_REG_EDM_CFG__
  21707. +#define NDS32_SR_EDMSW __NDS32_REG_EDMSW__
  21708. +#define NDS32_SR_EDM_CTL __NDS32_REG_EDM_CTL__
  21709. +#define NDS32_SR_EDM_DTR __NDS32_REG_EDM_DTR__
  21710. +#define NDS32_SR_BPMTC __NDS32_REG_BPMTC__
  21711. +#define NDS32_SR_DIMBR __NDS32_REG_DIMBR__
  21712. +#define NDS32_SR_TECR0 __NDS32_REG_TECR0__
  21713. +#define NDS32_SR_TECR1 __NDS32_REG_TECR1__
  21714. +#define NDS32_SR_PFMC0 __NDS32_REG_PFMC0__
  21715. +#define NDS32_SR_PFMC1 __NDS32_REG_PFMC1__
  21716. +#define NDS32_SR_PFMC2 __NDS32_REG_PFMC2__
  21717. +#define NDS32_SR_PFM_CTL __NDS32_REG_PFM_CTL__
  21718. +#define NDS32_SR_HSP_CTL __NDS32_REG_HSP_CTL__
  21719. +#define NDS32_SR_SP_BOUND __NDS32_REG_SP_BOUND__
  21720. +#define NDS32_SR_SP_BOUND_PRIV __NDS32_REG_SP_BOUND_PRIV__
  21721. +#define NDS32_SR_FUCOP_CTL __NDS32_REG_FUCOP_CTL__
  21722. +#define NDS32_SR_PRUSR_ACC_CTL __NDS32_REG_PRUSR_ACC_CTL__
  21723. +#define NDS32_SR_DMA_CFG __NDS32_REG_DMA_CFG__
  21724. +#define NDS32_SR_DMA_GCSW __NDS32_REG_DMA_GCSW__
  21725. +#define NDS32_SR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__
  21726. +#define NDS32_SR_DMA_ACT __NDS32_REG_DMA_ACT__
  21727. +#define NDS32_SR_DMA_SETUP __NDS32_REG_DMA_SETUP__
  21728. +#define NDS32_SR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__
  21729. +#define NDS32_SR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__
  21730. +#define NDS32_SR_DMA_TCNT __NDS32_REG_DMA_TCNT__
  21731. +#define NDS32_SR_DMA_STATUS __NDS32_REG_DMA_STATUS__
  21732. +#define NDS32_SR_DMA_2DSET __NDS32_REG_DMA_2DSET__
  21733. +#define NDS32_SR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__
  21734. +#define NDS32_SR_DMA_RCNT __NDS32_REG_DMA_RCNT__
  21735. +#define NDS32_SR_DMA_HSTATUS __NDS32_REG_DMA_HSTATUS__
  21736. +#define NDS32_SR_SP_USR1 __NDS32_REG_SP_USR1__
  21737. +#define NDS32_SR_SP_USR2 __NDS32_REG_SP_USR2__
  21738. +#define NDS32_SR_SP_USR3 __NDS32_REG_SP_USR3__
  21739. +#define NDS32_SR_SP_PRIV1 __NDS32_REG_SP_PRIV1__
  21740. +#define NDS32_SR_SP_PRIV2 __NDS32_REG_SP_PRIV2__
  21741. +#define NDS32_SR_SP_PRIV3 __NDS32_REG_SP_PRIV3__
  21742. +#define NDS32_SR_BG_REGION __NDS32_REG_BG_REGION__
  21743. +#define NDS32_SR_SFCR __NDS32_REG_SFCR__
  21744. +#define NDS32_SR_SIGN __NDS32_REG_SIGN__
  21745. +#define NDS32_SR_ISIGN __NDS32_REG_ISIGN__
  21746. +#define NDS32_SR_P_ISIGN __NDS32_REG_P_ISIGN__
  21747. +
  21748. +#define NDS32_USR_PC __NDS32_REG_PC__
  21749. +#define NDS32_USR_DMA_CFG __NDS32_REG_DMA_CFG__
  21750. +#define NDS32_USR_DMA_GCSW __NDS32_REG_DMA_GCSW__
  21751. +#define NDS32_USR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__
  21752. +#define NDS32_USR_DMA_ACT __NDS32_REG_DMA_ACT__
  21753. +#define NDS32_USR_DMA_SETUP __NDS32_REG_DMA_SETUP__
  21754. +#define NDS32_USR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__
  21755. +#define NDS32_USR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__
  21756. +#define NDS32_USR_DMA_TCNT __NDS32_REG_DMA_TCNT__
  21757. +#define NDS32_USR_DMA_STATUS __NDS32_REG_DMA_STATUS__
  21758. +#define NDS32_USR_DMA_2DSET __NDS32_REG_DMA_2DSET__
  21759. +#define NDS32_USR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__
  21760. +#define NDS32_USR_PFMC0 __NDS32_REG_PFMC0__
  21761. +#define NDS32_USR_PFMC1 __NDS32_REG_PFMC1__
  21762. +#define NDS32_USR_PFMC2 __NDS32_REG_PFMC2__
  21763. +#define NDS32_USR_PFM_CTL __NDS32_REG_PFM_CTL__
  21764. +#define NDS32_USR_IFC_LP __NDS32_REG_IFC_LP__
  21765. +#define NDS32_USR_ITB __NDS32_REG_ITB__
  21766. +
  21767. +#define NDS32_CCTL_L1D_VA_FILLCK __NDS32_CCTL_L1D_VA_FILLCK__
  21768. +#define NDS32_CCTL_L1D_VA_ULCK __NDS32_CCTL_L1D_VA_ULCK__
  21769. +#define NDS32_CCTL_L1I_VA_FILLCK __NDS32_CCTL_L1I_VA_FILLCK__
  21770. +#define NDS32_CCTL_L1I_VA_ULCK __NDS32_CCTL_L1I_VA_ULCK__
  21771. +
  21772. +#define NDS32_CCTL_L1D_IX_WBINVAL __NDS32_CCTL_L1D_IX_WBINVAL__
  21773. +#define NDS32_CCTL_L1D_IX_INVAL __NDS32_CCTL_L1D_IX_INVAL__
  21774. +#define NDS32_CCTL_L1D_IX_WB __NDS32_CCTL_L1D_IX_WB__
  21775. +#define NDS32_CCTL_L1I_IX_INVAL __NDS32_CCTL_L1I_IX_INVAL__
  21776. +
  21777. +#define NDS32_CCTL_L1D_VA_INVAL __NDS32_CCTL_L1D_VA_INVAL__
  21778. +#define NDS32_CCTL_L1D_VA_WB __NDS32_CCTL_L1D_VA_WB__
  21779. +#define NDS32_CCTL_L1D_VA_WBINVAL __NDS32_CCTL_L1D_VA_WBINVAL__
  21780. +#define NDS32_CCTL_L1I_VA_INVAL __NDS32_CCTL_L1I_VA_INVAL__
  21781. +
  21782. +#define NDS32_CCTL_L1D_IX_RTAG __NDS32_CCTL_L1D_IX_RTAG__
  21783. +#define NDS32_CCTL_L1D_IX_RWD __NDS32_CCTL_L1D_IX_RWD__
  21784. +#define NDS32_CCTL_L1I_IX_RTAG __NDS32_CCTL_L1I_IX_RTAG__
  21785. +#define NDS32_CCTL_L1I_IX_RWD __NDS32_CCTL_L1I_IX_RWD__
  21786. +
  21787. +#define NDS32_CCTL_L1D_IX_WTAG __NDS32_CCTL_L1D_IX_WTAG__
  21788. +#define NDS32_CCTL_L1D_IX_WWD __NDS32_CCTL_L1D_IX_WWD__
  21789. +#define NDS32_CCTL_L1I_IX_WTAG __NDS32_CCTL_L1I_IX_WTAG__
  21790. +#define NDS32_CCTL_L1I_IX_WWD __NDS32_CCTL_L1I_IX_WWD__
  21791. +
  21792. +#define NDS32_DPREF_SRD __NDS32_DPREF_SRD__
  21793. +#define NDS32_DPREF_MRD __NDS32_DPREF_MRD__
  21794. +#define NDS32_DPREF_SWR __NDS32_DPREF_SWR__
  21795. +#define NDS32_DPREF_MWR __NDS32_DPREF_MWR__
  21796. +#define NDS32_DPREF_PTE __NDS32_DPREF_PTE__
  21797. +#define NDS32_DPREF_CLWR __NDS32_DPREF_CLWR__
  21798. +
  21799. +/* ------------------------------------------------------------------------ */
  21800. +
  21801. +/* Define user friendly macro. */
  21802. +#define SIGNATURE_BEGIN __nds32__signature_begin ()
  21803. +#define SIGNATURE_END __nds32__signature_end ()
  21804. +
  21805. +/* Map __nds32__xxx() to __builtin_xxx() functions for compatibility. */
  21806. +#define __nds32__llw(a) \
  21807. + (__builtin_nds32_llw ((a)))
  21808. +#define __nds32__lwup(a) \
  21809. + (__builtin_nds32_lwup ((a)))
  21810. +#define __nds32__lbup(a) \
  21811. + (__builtin_nds32_lbup ((a)))
  21812. +#define __nds32__scw(a, b) \
  21813. + (__builtin_nds32_scw ((a), (b)))
  21814. +#define __nds32__swup(a, b) \
  21815. + (__builtin_nds32_swup ((a), (b)))
  21816. +#define __nds32__sbup(a, b) \
  21817. + (__builtin_nds32_sbup ((a), (b)))
  21818. +
  21819. +#define __nds32__mfsr(srname) \
  21820. + (__builtin_nds32_mfsr ((srname)))
  21821. +#define __nds32__mfusr(usrname) \
  21822. + (__builtin_nds32_mfusr ((usrname)))
  21823. +#define __nds32__mtsr(val, srname) \
  21824. + (__builtin_nds32_mtsr ((val), (srname)))
  21825. +#define __nds32__mtsr_isb(val, srname) \
  21826. + (__builtin_nds32_mtsr_isb ((val), (srname)))
  21827. +#define __nds32__mtsr_dsb(val, srname) \
  21828. + (__builtin_nds32_mtsr_dsb ((val), (srname)))
  21829. +#define __nds32__mtusr(val, usrname) \
  21830. + (__builtin_nds32_mtusr ((val), (usrname)))
  21831. +
  21832. +#define __nds32__break(swid) \
  21833. + (__builtin_nds32_break(swid))
  21834. +#define __nds32__cctlva_lck(subtype, va) \
  21835. + (__builtin_nds32_cctl_va_lck ((subtype), (va)))
  21836. +#define __nds32__cctlidx_wbinval(subtype, idx) \
  21837. + (__builtin_nds32_cctl_idx_wbinval ((subtype), (idx)))
  21838. +#define __nds32__cctlva_wbinval_alvl(subtype, va) \
  21839. + (__builtin_nds32_cctl_va_wbinval_la ((subtype), (va)))
  21840. +#define __nds32__cctlva_wbinval_one_lvl(subtype, va) \
  21841. + (__builtin_nds32_cctl_va_wbinval_l1 ((subtype), (va)))
  21842. +#define __nds32__cctlidx_read(subtype, idx) \
  21843. + (__builtin_nds32_cctl_idx_read ((subtype), (idx)))
  21844. +#define __nds32__cctlidx_write(subtype, b, idxw) \
  21845. + (__builtin_nds32_cctl_idx_write ((subtype), (b), (idxw)))
  21846. +#define __nds32__cctl_l1d_invalall() \
  21847. + (__builtin_nds32_cctl_l1d_invalall())
  21848. +#define __nds32__cctl_l1d_wball_alvl() \
  21849. + (__builtin_nds32_cctl_l1d_wball_alvl())
  21850. +#define __nds32__cctl_l1d_wball_one_lvl() \
  21851. + (__builtin_nds32_cctl_l1d_wball_one_lvl())
  21852. +
  21853. +#define __nds32__dsb() \
  21854. + (__builtin_nds32_dsb())
  21855. +#define __nds32__isb() \
  21856. + (__builtin_nds32_isb())
  21857. +#define __nds32__msync_store() \
  21858. + (__builtin_nds32_msync_store())
  21859. +#define __nds32__msync_all() \
  21860. + (__builtin_nds32_msync_all())
  21861. +#define __nds32__nop() \
  21862. + (__builtin_nds32_nop())
  21863. +
  21864. +#define __nds32__standby_wait_done() \
  21865. + (__builtin_nds32_standby_wait_done())
  21866. +#define __nds32__standby_no_wake_grant() \
  21867. + (__builtin_nds32_standby_no_wake_grant())
  21868. +#define __nds32__standby_wake_grant() \
  21869. + (__builtin_nds32_standby_wake_grant())
  21870. +#define __nds32__schedule_barrier() \
  21871. + (__builtin_nds32_schedule_barrier())
  21872. +#define __nds32__setend_big() \
  21873. + (__builtin_nds32_setend_big())
  21874. +#define __nds32__setend_little() \
  21875. + (__builtin_nds32_setend_little())
  21876. +#define __nds32__setgie_en() \
  21877. + (__builtin_nds32_setgie_en())
  21878. +#define __nds32__setgie_dis() \
  21879. + (__builtin_nds32_setgie_dis())
  21880. +
  21881. +#define __nds32__jr_itoff(a) \
  21882. + (__builtin_nds32_jr_itoff ((a)))
  21883. +#define __nds32__jr_toff(a) \
  21884. + (__builtin_nds32_jr_toff ((a)))
  21885. +#define __nds32__jral_iton(a) \
  21886. + (__builtin_nds32_jral_iton ((a)))
  21887. +#define __nds32__jral_ton(a) \
  21888. + (__builtin_nds32_jral_ton ((a)))
  21889. +#define __nds32__ret_itoff(a) \
  21890. + (__builtin_nds32_ret_itoff ((a)))
  21891. +#define __nds32__ret_toff(a) \
  21892. + (__builtin_nds32_ret_toff ((a)))
  21893. +#define __nds32__svs(a, b) \
  21894. + (__builtin_nds32_svs ((a), (b)))
  21895. +#define __nds32__sva(a, b) \
  21896. + (__builtin_nds32_sva ((a), (b)))
  21897. +#define __nds32__dpref_qw(a, b, subtype) \
  21898. + (__builtin_nds32_dpref_qw ((a), (b), (subtype)))
  21899. +#define __nds32__dpref_hw(a, b, subtype) \
  21900. + (__builtin_nds32_dpref_hw ((a), (b), (subtype)))
  21901. +#define __nds32__dpref_w(a, b, subtype) \
  21902. + (__builtin_nds32_dpref_w ((a), (b), (subtype)))
  21903. +#define __nds32__dpref_dw(a, b, subtype) \
  21904. + (__builtin_nds32_dpref_dw ((a), (b), (subtype)))
  21905. +
  21906. +#define __nds32__teqz(a, swid) \
  21907. + (__builtin_nds32_teqz ((a), (swid)))
  21908. +#define __nds32__tnez(a, swid) \
  21909. + ( __builtin_nds32_tnez ((a), (swid)))
  21910. +#define __nds32__trap(swid) \
  21911. + (__builtin_nds32_trap ((swid)))
  21912. +#define __nds32__isync(a) \
  21913. + (__builtin_nds32_isync ((a)))
  21914. +#define __nds32__rotr(val, ror) \
  21915. + (__builtin_nds32_rotr ((val), (ror)))
  21916. +#define __nds32__wsbh(a) \
  21917. + (__builtin_nds32_wsbh ((a)))
  21918. +#define __nds32__syscall(a) \
  21919. + (__builtin_nds32_syscall ((a)))
  21920. +#define __nds32__return_address() \
  21921. + (__builtin_nds32_return_address())
  21922. +#define __nds32__get_current_sp() \
  21923. + (__builtin_nds32_get_current_sp())
  21924. +#define __nds32__set_current_sp(a) \
  21925. + (__builtin_nds32_set_current_sp ((a)))
  21926. +#define __nds32__abs(a) \
  21927. + (__builtin_nds32_pe_abs ((a)))
  21928. +#define __nds32__ave(a, b) \
  21929. + (__builtin_nds32_pe_ave ((a), (b)))
  21930. +#define __nds32__bclr(a, pos) \
  21931. + (__builtin_nds32_pe_bclr ((a), (pos)))
  21932. +#define __nds32__bset(a, pos) \
  21933. + (__builtin_nds32_pe_bset ((a), (pos)))
  21934. +#define __nds32__btgl(a, pos) \
  21935. + (__builtin_nds32_pe_btgl ((a), (pos)))
  21936. +#define __nds32__btst(a, pos) \
  21937. + (__builtin_nds32_pe_btst ((a), (pos)))
  21938. +
  21939. +#define __nds32__clip(a, imm) \
  21940. + (__builtin_nds32_pe_clip ((a), (imm)))
  21941. +#define __nds32__clips(a, imm) \
  21942. + (__builtin_nds32_pe_clips ((a), (imm)))
  21943. +#define __nds32__clz(a) \
  21944. + (__builtin_nds32_pe_clz ((a)))
  21945. +#define __nds32__clo(a) \
  21946. + (__builtin_nds32_pe_clo ((a)))
  21947. +#define __nds32__bse(r, a, b) \
  21948. + (__builtin_nds32_pe2_bse ((r), (a), (b)))
  21949. +#define __nds32__bsp(r, a, b) \
  21950. + (__builtin_nds32_pe2_bsp ((r), (a), (b)))
  21951. +#define __nds32__pbsad(a, b) \
  21952. + (__builtin_nds32_pe2_pbsad ((a), (b)))
  21953. +#define __nds32__pbsada(acc, a, b) \
  21954. + (__builtin_nds32_pe2_pbsada ((acc), (a), (b)))
  21955. +
  21956. +#define __nds32__ffb(a, b) \
  21957. + (__builtin_nds32_se_ffb ((a), (b)))
  21958. +#define __nds32__ffmism(a, b) \
  21959. + (__builtin_nds32_se_ffmism ((a), (b)))
  21960. +#define __nds32__flmism(a, b) \
  21961. + (__builtin_nds32_se_flmism ((a), (b)))
  21962. +#define __nds32__fcpynsd(a, b) \
  21963. + (__builtin_nds32_fcpynsd ((a), (b)))
  21964. +#define __nds32__fcpynss(a, b) \
  21965. + (__builtin_nds32_fcpynss ((a), (b)))
  21966. +#define __nds32__fcpysd(a, b) \
  21967. + (__builtin_nds32_fcpysd ((a), (b)))
  21968. +#define __nds32__fcpyss(a, b) \
  21969. + (__builtin_nds32_fcpyss ((a), (b)))
  21970. +#define __nds32__fmfcsr() \
  21971. + (__builtin_nds32_fmfcsr())
  21972. +#define __nds32__fmtcsr(fpcsr) \
  21973. + (__builtin_nds32_fmtcsr ((fpcsr)))
  21974. +#define __nds32__fmfcfg() \
  21975. + (__builtin_nds32_fmfcfg())
  21976. +
  21977. +#define __nds32__tlbop_trd(a) \
  21978. + (__builtin_nds32_tlbop_trd ((a)))
  21979. +#define __nds32__tlbop_twr(a) \
  21980. + (__builtin_nds32_tlbop_twr ((a)))
  21981. +#define __nds32__tlbop_rwr(a) \
  21982. + (__builtin_nds32_tlbop_rwr ((a)))
  21983. +#define __nds32__tlbop_rwlk(a) \
  21984. + (__builtin_nds32_tlbop_rwlk ((a)))
  21985. +#define __nds32__tlbop_unlk(a) \
  21986. + (__builtin_nds32_tlbop_unlk ((a)))
  21987. +#define __nds32__tlbop_pb(a) \
  21988. + (__builtin_nds32_tlbop_pb ((a)))
  21989. +#define __nds32__tlbop_inv(a) \
  21990. + (__builtin_nds32_tlbop_inv ((a)))
  21991. +#define __nds32__tlbop_flua() \
  21992. +(__builtin_nds32_tlbop_flua())
  21993. +
  21994. +#define __nds32__kaddw(a, b) \
  21995. + (__builtin_nds32_kaddw ((a), (b)))
  21996. +#define __nds32__kaddh(a, b) \
  21997. + (__builtin_nds32_kaddh ((a), (b)))
  21998. +#define __nds32__ksubw(a, b) \
  21999. + (__builtin_nds32_ksubw ((a), (b)))
  22000. +#define __nds32__ksubh(a, b) \
  22001. + (__builtin_nds32_ksubh ((a), (b)))
  22002. +#define __nds32__kdmbb(a, b) \
  22003. + (__builtin_nds32_kdmbb ((a), (b)))
  22004. +#define __nds32__v_kdmbb(a, b) \
  22005. + (__builtin_nds32_v_kdmbb ((a), (b)))
  22006. +#define __nds32__kdmbt(a, b) \
  22007. + (__builtin_nds32_kdmbt ((a), (b)))
  22008. +#define __nds32__v_kdmbt(a, b) \
  22009. + (__builtin_nds32_v_kdmbt ((a), (b)))
  22010. +#define __nds32__kdmtb(a, b) \
  22011. + (__builtin_nds32_kdmtb ((a), (b)))
  22012. +#define __nds32__v_kdmtb(a, b) \
  22013. + (__builtin_nds32_v_kdmtb ((a), (b)))
  22014. +#define __nds32__kdmtt(a, b) \
  22015. + (__builtin_nds32_kdmtt ((a), (b)))
  22016. +#define __nds32__v_kdmtt(a, b) \
  22017. + (__builtin_nds32_v_kdmtt ((a), (b)))
  22018. +#define __nds32__khmbb(a, b) \
  22019. + (__builtin_nds32_khmbb ((a), (b)))
  22020. +#define __nds32__v_khmbb(a, b) \
  22021. + (__builtin_nds32_v_khmbb ((a), (b)))
  22022. +#define __nds32__khmbt(a, b) \
  22023. + (__builtin_nds32_khmbt ((a), (b)))
  22024. +#define __nds32__v_khmbt(a, b) \
  22025. + (__builtin_nds32_v_khmbt ((a), (b)))
  22026. +#define __nds32__khmtb(a, b) \
  22027. + (__builtin_nds32_khmtb ((a), (b)))
  22028. +#define __nds32__v_khmtb(a, b) \
  22029. + (__builtin_nds32_v_khmtb ((a), (b)))
  22030. +#define __nds32__khmtt(a, b) \
  22031. + (__builtin_nds32_khmtt ((a), (b)))
  22032. +#define __nds32__v_khmtt(a, b) \
  22033. + (__builtin_nds32_v_khmtt ((a), (b)))
  22034. +#define __nds32__kslraw(a, b) \
  22035. + (__builtin_nds32_kslraw ((a), (b)))
  22036. +#define __nds32__kslraw_u(a, b) \
  22037. + (__builtin_nds32_kslraw_u ((a), (b)))
  22038. +
  22039. +#define __nds32__rdov() \
  22040. + (__builtin_nds32_rdov())
  22041. +#define __nds32__clrov() \
  22042. + (__builtin_nds32_clrov())
  22043. +#define __nds32__gie_dis() \
  22044. + (__builtin_nds32_gie_dis())
  22045. +#define __nds32__gie_en() \
  22046. + (__builtin_nds32_gie_en())
  22047. +#define __nds32__enable_int(a) \
  22048. + (__builtin_nds32_enable_int ((a)))
  22049. +#define __nds32__disable_int(a) \
  22050. + (__builtin_nds32_disable_int ((a)))
  22051. +#define __nds32__set_pending_swint() \
  22052. + (__builtin_nds32_set_pending_swint())
  22053. +#define __nds32__clr_pending_swint() \
  22054. + (__builtin_nds32_clr_pending_swint())
  22055. +#define __nds32__clr_pending_hwint(a) \
  22056. + (__builtin_nds32_clr_pending_hwint(a))
  22057. +#define __nds32__get_all_pending_int() \
  22058. + (__builtin_nds32_get_all_pending_int())
  22059. +#define __nds32__get_pending_int(a) \
  22060. + (__builtin_nds32_get_pending_int ((a)))
  22061. +#define __nds32__set_int_priority(a, b) \
  22062. + (__builtin_nds32_set_int_priority ((a), (b)))
  22063. +#define __nds32__get_int_priority(a) \
  22064. + (__builtin_nds32_get_int_priority ((a)))
  22065. +#define __nds32__set_trig_type_level(a) \
  22066. + (__builtin_nds32_set_trig_level(a))
  22067. +#define __nds32__set_trig_type_edge(a) \
  22068. + (__builtin_nds32_set_trig_edge(a))
  22069. +#define __nds32__get_trig_type(a) \
  22070. + (__builtin_nds32_get_trig_type ((a)))
  22071. +
  22072. +#define __nds32__get_unaligned_hw(a) \
  22073. + (__builtin_nds32_unaligned_load_hw ((a)))
  22074. +#define __nds32__get_unaligned_w(a) \
  22075. + (__builtin_nds32_unaligned_load_w ((a)))
  22076. +#define __nds32__get_unaligned_dw(a) \
  22077. + (__builtin_nds32_unaligned_load_dw ((a)))
  22078. +#define __nds32__put_unaligned_hw(a, data) \
  22079. + (__builtin_nds32_unaligned_store_hw ((a), (data)))
  22080. +#define __nds32__put_unaligned_w(a, data) \
  22081. + (__builtin_nds32_unaligned_store_w ((a), (data)))
  22082. +#define __nds32__put_unaligned_dw(a, data) \
  22083. + (__builtin_nds32_unaligned_store_dw ((a), (data)))
  22084. +
  22085. +#define __nds32__signature_begin() \
  22086. + (__builtin_nds32_signature_begin ())
  22087. +#define __nds32__signature_end() \
  22088. + (__builtin_nds32_signature_end ())
  22089. +
  22090. +#define __nds32__add16(a, b) \
  22091. + (__builtin_nds32_add16 ((a), (b)))
  22092. +#define __nds32__v_uadd16(a, b) \
  22093. + (__builtin_nds32_v_uadd16 ((a), (b)))
  22094. +#define __nds32__v_sadd16(a, b) \
  22095. + (__builtin_nds32_v_sadd16 ((a), (b)))
  22096. +#define __nds32__radd16(a, b) \
  22097. + (__builtin_nds32_radd16 ((a), (b)))
  22098. +#define __nds32__v_radd16(a, b) \
  22099. + (__builtin_nds32_v_radd16 ((a), (b)))
  22100. +#define __nds32__uradd16(a, b) \
  22101. + (__builtin_nds32_uradd16 ((a), (b)))
  22102. +#define __nds32__v_uradd16(a, b) \
  22103. + (__builtin_nds32_v_uradd16 ((a), (b)))
  22104. +#define __nds32__kadd16(a, b) \
  22105. + (__builtin_nds32_kadd16 ((a), (b)))
  22106. +#define __nds32__v_kadd16(a, b) \
  22107. + (__builtin_nds32_v_kadd16 ((a), (b)))
  22108. +#define __nds32__ukadd16(a, b) \
  22109. + (__builtin_nds32_ukadd16 ((a), (b)))
  22110. +#define __nds32__v_ukadd16(a, b) \
  22111. + (__builtin_nds32_v_ukadd16 ((a), (b)))
  22112. +#define __nds32__sub16(a, b) \
  22113. + (__builtin_nds32_sub16 ((a), (b)))
  22114. +#define __nds32__v_usub16(a, b) \
  22115. + (__builtin_nds32_v_usub16 ((a), (b)))
  22116. +#define __nds32__v_ssub16(a, b) \
  22117. + (__builtin_nds32_v_ssub16 ((a), (b)))
  22118. +#define __nds32__rsub16(a, b) \
  22119. + (__builtin_nds32_rsub16 ((a), (b)))
  22120. +#define __nds32__v_rsub16(a, b) \
  22121. + (__builtin_nds32_v_rsub16 ((a), (b)))
  22122. +#define __nds32__ursub16(a, b) \
  22123. + (__builtin_nds32_ursub16 ((a), (b)))
  22124. +#define __nds32__v_ursub16(a, b) \
  22125. + (__builtin_nds32_v_ursub16 ((a), (b)))
  22126. +#define __nds32__ksub16(a, b) \
  22127. + (__builtin_nds32_ksub16 ((a), (b)))
  22128. +#define __nds32__v_ksub16(a, b) \
  22129. + (__builtin_nds32_v_ksub16 ((a), (b)))
  22130. +#define __nds32__uksub16(a, b) \
  22131. + (__builtin_nds32_uksub16 ((a), (b)))
  22132. +#define __nds32__v_uksub16(a, b) \
  22133. + (__builtin_nds32_v_uksub16 ((a), (b)))
  22134. +#define __nds32__cras16(a, b) \
  22135. + (__builtin_nds32_cras16 ((a), (b)))
  22136. +#define __nds32__v_ucras16(a, b) \
  22137. + (__builtin_nds32_v_ucras16 ((a), (b)))
  22138. +#define __nds32__v_scras16(a, b) \
  22139. + (__builtin_nds32_v_scras16 ((a), (b)))
  22140. +#define __nds32__rcras16(a, b) \
  22141. + (__builtin_nds32_rcras16 ((a), (b)))
  22142. +#define __nds32__v_rcras16(a, b) \
  22143. + (__builtin_nds32_v_rcras16 ((a), (b)))
  22144. +#define __nds32__urcras16(a, b) \
  22145. + (__builtin_nds32_urcras16 ((a), (b)))
  22146. +#define __nds32__v_urcras16(a, b) \
  22147. + (__builtin_nds32_v_urcras16 ((a), (b)))
  22148. +#define __nds32__kcras16(a, b) \
  22149. + (__builtin_nds32_kcras16 ((a), (b)))
  22150. +#define __nds32__v_kcras16(a, b) \
  22151. + (__builtin_nds32_v_kcras16 ((a), (b)))
  22152. +#define __nds32__ukcras16(a, b) \
  22153. + (__builtin_nds32_ukcras16 ((a), (b)))
  22154. +#define __nds32__v_ukcras16(a, b) \
  22155. + (__builtin_nds32_v_ukcras16 ((a), (b)))
  22156. +#define __nds32__crsa16(a, b) \
  22157. + (__builtin_nds32_crsa16 ((a), (b)))
  22158. +#define __nds32__v_ucrsa16(a, b) \
  22159. + (__builtin_nds32_v_ucrsa16 ((a), (b)))
  22160. +#define __nds32__v_scrsa16(a, b) \
  22161. + (__builtin_nds32_v_scrsa16 ((a), (b)))
  22162. +#define __nds32__rcrsa16(a, b) \
  22163. + (__builtin_nds32_rcrsa16 ((a), (b)))
  22164. +#define __nds32__v_rcrsa16(a, b) \
  22165. + (__builtin_nds32_v_rcrsa16 ((a), (b)))
  22166. +#define __nds32__urcrsa16(a, b) \
  22167. + (__builtin_nds32_urcrsa16 ((a), (b)))
  22168. +#define __nds32__v_urcrsa16(a, b) \
  22169. + (__builtin_nds32_v_urcrsa16 ((a), (b)))
  22170. +#define __nds32__kcrsa16(a, b) \
  22171. + (__builtin_nds32_kcrsa16 ((a), (b)))
  22172. +#define __nds32__v_kcrsa16(a, b) \
  22173. + (__builtin_nds32_v_kcrsa16 ((a), (b)))
  22174. +#define __nds32__ukcrsa16(a, b) \
  22175. + (__builtin_nds32_ukcrsa16 ((a), (b)))
  22176. +#define __nds32__v_ukcrsa16(a, b) \
  22177. + (__builtin_nds32_v_ukcrsa16 ((a), (b)))
  22178. +
  22179. +#define __nds32__add8(a, b) \
  22180. + (__builtin_nds32_add8 ((a), (b)))
  22181. +#define __nds32__v_uadd8(a, b) \
  22182. + (__builtin_nds32_v_uadd8 ((a), (b)))
  22183. +#define __nds32__v_sadd8(a, b) \
  22184. + (__builtin_nds32_v_sadd8 ((a), (b)))
  22185. +#define __nds32__radd8(a, b) \
  22186. + (__builtin_nds32_radd8 ((a), (b)))
  22187. +#define __nds32__v_radd8(a, b) \
  22188. + (__builtin_nds32_v_radd8 ((a), (b)))
  22189. +#define __nds32__uradd8(a, b) \
  22190. + (__builtin_nds32_uradd8 ((a), (b)))
  22191. +#define __nds32__v_uradd8(a, b) \
  22192. + (__builtin_nds32_v_uradd8 ((a), (b)))
  22193. +#define __nds32__kadd8(a, b) \
  22194. + (__builtin_nds32_kadd8 ((a), (b)))
  22195. +#define __nds32__v_kadd8(a, b) \
  22196. + (__builtin_nds32_v_kadd8 ((a), (b)))
  22197. +#define __nds32__ukadd8(a, b) \
  22198. + (__builtin_nds32_ukadd8 ((a), (b)))
  22199. +#define __nds32__v_ukadd8(a, b) \
  22200. + (__builtin_nds32_v_ukadd8 ((a), (b)))
  22201. +#define __nds32__sub8(a, b) \
  22202. + (__builtin_nds32_sub8 ((a), (b)))
  22203. +#define __nds32__v_usub8(a, b) \
  22204. + (__builtin_nds32_v_usub8 ((a), (b)))
  22205. +#define __nds32__v_ssub8(a, b) \
  22206. + (__builtin_nds32_v_ssub8 ((a), (b)))
  22207. +#define __nds32__rsub8(a, b) \
  22208. + (__builtin_nds32_rsub8 ((a), (b)))
  22209. +#define __nds32__v_rsub8(a, b) \
  22210. + (__builtin_nds32_v_rsub8 ((a), (b)))
  22211. +#define __nds32__ursub8(a, b) \
  22212. + (__builtin_nds32_ursub8 ((a), (b)))
  22213. +#define __nds32__v_ursub8(a, b) \
  22214. + (__builtin_nds32_v_ursub8 ((a), (b)))
  22215. +#define __nds32__ksub8(a, b) \
  22216. + (__builtin_nds32_ksub8 ((a), (b)))
  22217. +#define __nds32__v_ksub8(a, b) \
  22218. + (__builtin_nds32_v_ksub8 ((a), (b)))
  22219. +#define __nds32__uksub8(a, b) \
  22220. + (__builtin_nds32_uksub8 ((a), (b)))
  22221. +#define __nds32__v_uksub8(a, b) \
  22222. + (__builtin_nds32_v_uksub8 ((a), (b)))
  22223. +
  22224. +#define __nds32__sra16(a, b) \
  22225. + (__builtin_nds32_sra16 ((a), (b)))
  22226. +#define __nds32__v_sra16(a, b) \
  22227. + (__builtin_nds32_v_sra16 ((a), (b)))
  22228. +#define __nds32__sra16_u(a, b) \
  22229. + (__builtin_nds32_sra16_u ((a), (b)))
  22230. +#define __nds32__v_sra16_u(a, b) \
  22231. + (__builtin_nds32_v_sra16_u ((a), (b)))
  22232. +#define __nds32__srl16(a, b) \
  22233. + (__builtin_nds32_srl16 ((a), (b)))
  22234. +#define __nds32__v_srl16(a, b) \
  22235. + (__builtin_nds32_v_srl16 ((a), (b)))
  22236. +#define __nds32__srl16_u(a, b) \
  22237. + (__builtin_nds32_srl16_u ((a), (b)))
  22238. +#define __nds32__v_srl16_u(a, b) \
  22239. + (__builtin_nds32_v_srl16_u ((a), (b)))
  22240. +#define __nds32__sll16(a, b) \
  22241. + (__builtin_nds32_sll16 ((a), (b)))
  22242. +#define __nds32__v_sll16(a, b) \
  22243. + (__builtin_nds32_v_sll16 ((a), (b)))
  22244. +#define __nds32__ksll16(a, b) \
  22245. + (__builtin_nds32_ksll16 ((a), (b)))
  22246. +#define __nds32__v_ksll16(a, b) \
  22247. + (__builtin_nds32_v_ksll16 ((a), (b)))
  22248. +#define __nds32__kslra16(a, b) \
  22249. + (__builtin_nds32_kslra16 ((a), (b)))
  22250. +#define __nds32__v_kslra16(a, b) \
  22251. + (__builtin_nds32_v_kslra16 ((a), (b)))
  22252. +#define __nds32__kslra16_u(a, b) \
  22253. + (__builtin_nds32_kslra16_u ((a), (b)))
  22254. +#define __nds32__v_kslra16_u(a, b) \
  22255. + (__builtin_nds32_v_kslra16_u ((a), (b)))
  22256. +
  22257. +#define __nds32__cmpeq16(a, b) \
  22258. + (__builtin_nds32_cmpeq16 ((a), (b)))
  22259. +#define __nds32__v_scmpeq16(a, b) \
  22260. + (__builtin_nds32_v_scmpeq16 ((a), (b)))
  22261. +#define __nds32__v_ucmpeq16(a, b) \
  22262. + (__builtin_nds32_v_ucmpeq16 ((a), (b)))
  22263. +#define __nds32__scmplt16(a, b) \
  22264. + (__builtin_nds32_scmplt16 ((a), (b)))
  22265. +#define __nds32__v_scmplt16(a, b) \
  22266. + (__builtin_nds32_v_scmplt16 ((a), (b)))
  22267. +#define __nds32__scmple16(a, b) \
  22268. + (__builtin_nds32_scmple16 ((a), (b)))
  22269. +#define __nds32__v_scmple16(a, b) \
  22270. + (__builtin_nds32_v_scmple16 ((a), (b)))
  22271. +#define __nds32__ucmplt16(a, b) \
  22272. + (__builtin_nds32_ucmplt16 ((a), (b)))
  22273. +#define __nds32__v_ucmplt16(a, b) \
  22274. + (__builtin_nds32_v_ucmplt16 ((a), (b)))
  22275. +#define __nds32__ucmple16(a, b) \
  22276. + (__builtin_nds32_ucmple16 ((a), (b)))
  22277. +#define __nds32__v_ucmple16(a, b) \
  22278. + (__builtin_nds32_v_ucmple16 ((a), (b)))
  22279. +
  22280. +#define __nds32__cmpeq8(a, b) \
  22281. + (__builtin_nds32_cmpeq8 ((a), (b)))
  22282. +#define __nds32__v_scmpeq8(a, b) \
  22283. + (__builtin_nds32_v_scmpeq8 ((a), (b)))
  22284. +#define __nds32__v_ucmpeq8(a, b) \
  22285. + (__builtin_nds32_v_ucmpeq8 ((a), (b)))
  22286. +#define __nds32__scmplt8(a, b) \
  22287. + (__builtin_nds32_scmplt8 ((a), (b)))
  22288. +#define __nds32__v_scmplt8(a, b) \
  22289. + (__builtin_nds32_v_scmplt8 ((a), (b)))
  22290. +#define __nds32__scmple8(a, b) \
  22291. + (__builtin_nds32_scmple8 ((a), (b)))
  22292. +#define __nds32__v_scmple8(a, b) \
  22293. + (__builtin_nds32_v_scmple8 ((a), (b)))
  22294. +#define __nds32__ucmplt8(a, b) \
  22295. + (__builtin_nds32_ucmplt8 ((a), (b)))
  22296. +#define __nds32__v_ucmplt8(a, b) \
  22297. + (__builtin_nds32_v_ucmplt8 ((a), (b)))
  22298. +#define __nds32__ucmple8(a, b) \
  22299. + (__builtin_nds32_ucmple8 ((a), (b)))
  22300. +#define __nds32__v_ucmple8(a, b) \
  22301. + (__builtin_nds32_v_ucmple8 ((a), (b)))
  22302. +
  22303. +#define __nds32__smin16(a, b) \
  22304. + (__builtin_nds32_smin16 ((a), (b)))
  22305. +#define __nds32__v_smin16(a, b) \
  22306. + (__builtin_nds32_v_smin16 ((a), (b)))
  22307. +#define __nds32__umin16(a, b) \
  22308. + (__builtin_nds32_umin16 ((a), (b)))
  22309. +#define __nds32__v_umin16(a, b) \
  22310. + (__builtin_nds32_v_umin16 ((a), (b)))
  22311. +#define __nds32__smax16(a, b) \
  22312. + (__builtin_nds32_smax16 ((a), (b)))
  22313. +#define __nds32__v_smax16(a, b) \
  22314. + (__builtin_nds32_v_smax16 ((a), (b)))
  22315. +#define __nds32__umax16(a, b) \
  22316. + (__builtin_nds32_umax16 ((a), (b)))
  22317. +#define __nds32__v_umax16(a, b) \
  22318. + (__builtin_nds32_v_umax16 ((a), (b)))
  22319. +#define __nds32__sclip16(a, b) \
  22320. + (__builtin_nds32_sclip16 ((a), (b)))
  22321. +#define __nds32__v_sclip16(a, b) \
  22322. + (__builtin_nds32_v_sclip16 ((a), (b)))
  22323. +#define __nds32__uclip16(a, b) \
  22324. + (__builtin_nds32_uclip16 ((a), (b)))
  22325. +#define __nds32__v_uclip16(a, b) \
  22326. + (__builtin_nds32_v_uclip16 ((a), (b)))
  22327. +#define __nds32__khm16(a, b) \
  22328. + (__builtin_nds32_khm16 ((a), (b)))
  22329. +#define __nds32__v_khm16(a, b) \
  22330. + (__builtin_nds32_v_khm16 ((a), (b)))
  22331. +#define __nds32__khmx16(a, b) \
  22332. + (__builtin_nds32_khmx16 ((a), (b)))
  22333. +#define __nds32__v_khmx16(a, b) \
  22334. + (__builtin_nds32_v_khmx16 ((a), (b)))
  22335. +#define __nds32__kabs16(a) \
  22336. + (__builtin_nds32_kabs16 ((a)))
  22337. +#define __nds32__v_kabs16(a) \
  22338. + (__builtin_nds32_v_kabs16 ((a)))
  22339. +
  22340. +#define __nds32__smin8(a, b) \
  22341. + (__builtin_nds32_smin8 ((a), (b)))
  22342. +#define __nds32__v_smin8(a, b) \
  22343. + (__builtin_nds32_v_smin8 ((a), (b)))
  22344. +#define __nds32__umin8(a, b) \
  22345. + (__builtin_nds32_umin8 ((a), (b)))
  22346. +#define __nds32__v_umin8(a, b) \
  22347. + (__builtin_nds32_v_umin8 ((a), (b)))
  22348. +#define __nds32__smax8(a, b) \
  22349. + (__builtin_nds32_smax8 ((a), (b)))
  22350. +#define __nds32__v_smax8(a, b) \
  22351. + (__builtin_nds32_v_smax8 ((a), (b)))
  22352. +#define __nds32__umax8(a, b) \
  22353. + (__builtin_nds32_umax8 ((a), (b)))
  22354. +#define __nds32__v_umax8(a, b) \
  22355. + (__builtin_nds32_v_umax8 ((a), (b)))
  22356. +#define __nds32__kabs8(a) \
  22357. + (__builtin_nds32_kabs8 ((a)))
  22358. +#define __nds32__v_kabs8(a) \
  22359. + (__builtin_nds32_v_kabs8 ((a)))
  22360. +
  22361. +#define __nds32__sunpkd810(a) \
  22362. + (__builtin_nds32_sunpkd810 ((a)))
  22363. +#define __nds32__v_sunpkd810(a) \
  22364. + (__builtin_nds32_v_sunpkd810 ((a)))
  22365. +#define __nds32__sunpkd820(a) \
  22366. + (__builtin_nds32_sunpkd820 ((a)))
  22367. +#define __nds32__v_sunpkd820(a) \
  22368. + (__builtin_nds32_v_sunpkd820 ((a)))
  22369. +#define __nds32__sunpkd830(a) \
  22370. + (__builtin_nds32_sunpkd830 ((a)))
  22371. +#define __nds32__v_sunpkd830(a) \
  22372. + (__builtin_nds32_v_sunpkd830 ((a)))
  22373. +#define __nds32__sunpkd831(a) \
  22374. + (__builtin_nds32_sunpkd831 ((a)))
  22375. +#define __nds32__v_sunpkd831(a) \
  22376. + (__builtin_nds32_v_sunpkd831 ((a)))
  22377. +#define __nds32__zunpkd810(a) \
  22378. + (__builtin_nds32_zunpkd810 ((a)))
  22379. +#define __nds32__v_zunpkd810(a) \
  22380. + (__builtin_nds32_v_zunpkd810 ((a)))
  22381. +#define __nds32__zunpkd820(a) \
  22382. + (__builtin_nds32_zunpkd820 ((a)))
  22383. +#define __nds32__v_zunpkd820(a) \
  22384. + (__builtin_nds32_v_zunpkd820 ((a)))
  22385. +#define __nds32__zunpkd830(a) \
  22386. + (__builtin_nds32_zunpkd830 ((a)))
  22387. +#define __nds32__v_zunpkd830(a) \
  22388. + (__builtin_nds32_v_zunpkd830 ((a)))
  22389. +#define __nds32__zunpkd831(a) \
  22390. + (__builtin_nds32_zunpkd831 ((a)))
  22391. +#define __nds32__v_zunpkd831(a) \
  22392. + (__builtin_nds32_v_zunpkd831 ((a)))
  22393. +
  22394. +#define __nds32__raddw(a, b) \
  22395. + (__builtin_nds32_raddw ((a), (b)))
  22396. +#define __nds32__uraddw(a, b) \
  22397. + (__builtin_nds32_uraddw ((a), (b)))
  22398. +#define __nds32__rsubw(a, b) \
  22399. + (__builtin_nds32_rsubw ((a), (b)))
  22400. +#define __nds32__ursubw(a, b) \
  22401. + (__builtin_nds32_ursubw ((a), (b)))
  22402. +
  22403. +#define __nds32__sra_u(a, b) \
  22404. + (__builtin_nds32_sra_u ((a), (b)))
  22405. +#define __nds32__ksll(a, b) \
  22406. + (__builtin_nds32_ksll ((a), (b)))
  22407. +#define __nds32__pkbb16(a, b) \
  22408. + (__builtin_nds32_pkbb16 ((a), (b)))
  22409. +#define __nds32__v_pkbb16(a, b) \
  22410. + (__builtin_nds32_v_pkbb16 ((a), (b)))
  22411. +#define __nds32__pkbt16(a, b) \
  22412. + (__builtin_nds32_pkbt16 ((a), (b)))
  22413. +#define __nds32__v_pkbt16(a, b) \
  22414. + (__builtin_nds32_v_pkbt16 ((a), (b)))
  22415. +#define __nds32__pktb16(a, b) \
  22416. + (__builtin_nds32_pktb16 ((a), (b)))
  22417. +#define __nds32__v_pktb16(a, b) \
  22418. + (__builtin_nds32_v_pktb16 ((a), (b)))
  22419. +#define __nds32__pktt16(a, b) \
  22420. + (__builtin_nds32_pktt16 ((a), (b)))
  22421. +#define __nds32__v_pktt16(a, b) \
  22422. + (__builtin_nds32_v_pktt16 ((a), (b)))
  22423. +
  22424. +#define __nds32__smmul(a, b) \
  22425. + (__builtin_nds32_smmul ((a), (b)))
  22426. +#define __nds32__smmul_u(a, b) \
  22427. + (__builtin_nds32_smmul_u ((a), (b)))
  22428. +#define __nds32__kmmac(r, a, b) \
  22429. + (__builtin_nds32_kmmac ((r), (a), (b)))
  22430. +#define __nds32__kmmac_u(r, a, b) \
  22431. + (__builtin_nds32_kmmac_u ((r), (a), (b)))
  22432. +#define __nds32__kmmsb(r, a, b) \
  22433. + (__builtin_nds32_kmmsb ((r), (a), (b)))
  22434. +#define __nds32__kmmsb_u(r, a, b) \
  22435. + (__builtin_nds32_kmmsb_u ((r), (a), (b)))
  22436. +#define __nds32__kwmmul(a, b) \
  22437. + (__builtin_nds32_kwmmul ((a), (b)))
  22438. +#define __nds32__kwmmul_u(a, b) \
  22439. + (__builtin_nds32_kwmmul_u ((a), (b)))
  22440. +
  22441. +#define __nds32__smmwb(a, b) \
  22442. + (__builtin_nds32_smmwb ((a), (b)))
  22443. +#define __nds32__v_smmwb(a, b) \
  22444. + (__builtin_nds32_v_smmwb ((a), (b)))
  22445. +#define __nds32__smmwb_u(a, b) \
  22446. + (__builtin_nds32_smmwb_u ((a), (b)))
  22447. +#define __nds32__v_smmwb_u(a, b) \
  22448. + (__builtin_nds32_v_smmwb_u ((a), (b)))
  22449. +#define __nds32__smmwt(a, b) \
  22450. + (__builtin_nds32_smmwt ((a), (b)))
  22451. +#define __nds32__v_smmwt(a, b) \
  22452. + (__builtin_nds32_v_smmwt ((a), (b)))
  22453. +#define __nds32__smmwt_u(a, b) \
  22454. + (__builtin_nds32_smmwt_u ((a), (b)))
  22455. +#define __nds32__v_smmwt_u(a, b) \
  22456. + (__builtin_nds32_v_smmwt_u ((a), (b)))
  22457. +#define __nds32__kmmawb(r, a, b) \
  22458. + (__builtin_nds32_kmmawb ((r), (a), (b)))
  22459. +#define __nds32__v_kmmawb(r, a, b) \
  22460. + (__builtin_nds32_v_kmmawb ((r), (a), (b)))
  22461. +#define __nds32__kmmawb_u(r, a, b) \
  22462. + (__builtin_nds32_kmmawb_u ((r), (a), (b)))
  22463. +#define __nds32__v_kmmawb_u(r, a, b) \
  22464. + (__builtin_nds32_v_kmmawb_u ((r), (a), (b)))
  22465. +#define __nds32__kmmawt(r, a, b) \
  22466. + (__builtin_nds32_kmmawt ((r), (a), (b)))
  22467. +#define __nds32__v_kmmawt(r, a, b) \
  22468. + (__builtin_nds32_v_kmmawt ((r), (a), (b)))
  22469. +#define __nds32__kmmawt_u(r, a, b) \
  22470. + (__builtin_nds32_kmmawt_u ((r), (a), (b)))
  22471. +#define __nds32__v_kmmawt_u(r, a, b) \
  22472. + (__builtin_nds32_v_kmmawt_u ((r), (a), (b)))
  22473. +
  22474. +#define __nds32__smbb(a, b) \
  22475. + (__builtin_nds32_smbb ((a), (b)))
  22476. +#define __nds32__v_smbb(a, b) \
  22477. + (__builtin_nds32_v_smbb ((a), (b)))
  22478. +#define __nds32__smbt(a, b) \
  22479. + (__builtin_nds32_smbt ((a), (b)))
  22480. +#define __nds32__v_smbt(a, b) \
  22481. + (__builtin_nds32_v_smbt ((a), (b)))
  22482. +#define __nds32__smtt(a, b) \
  22483. + (__builtin_nds32_smtt ((a), (b)))
  22484. +#define __nds32__v_smtt(a, b) \
  22485. + (__builtin_nds32_v_smtt ((a), (b)))
  22486. +#define __nds32__kmda(a, b) \
  22487. + (__builtin_nds32_kmda ((a), (b)))
  22488. +#define __nds32__v_kmda(a, b) \
  22489. + (__builtin_nds32_v_kmda ((a), (b)))
  22490. +#define __nds32__kmxda(a, b) \
  22491. + (__builtin_nds32_kmxda ((a), (b)))
  22492. +#define __nds32__v_kmxda(a, b) \
  22493. + (__builtin_nds32_v_kmxda ((a), (b)))
  22494. +#define __nds32__smds(a, b) \
  22495. + (__builtin_nds32_smds ((a), (b)))
  22496. +#define __nds32__v_smds(a, b) \
  22497. + (__builtin_nds32_v_smds ((a), (b)))
  22498. +#define __nds32__smdrs(a, b) \
  22499. + (__builtin_nds32_smdrs ((a), (b)))
  22500. +#define __nds32__v_smdrs(a, b) \
  22501. + (__builtin_nds32_v_smdrs ((a), (b)))
  22502. +#define __nds32__smxds(a, b) \
  22503. + (__builtin_nds32_smxds ((a), (b)))
  22504. +#define __nds32__v_smxds(a, b) \
  22505. + (__builtin_nds32_v_smxds ((a), (b)))
  22506. +#define __nds32__kmabb(r, a, b) \
  22507. + (__builtin_nds32_kmabb ((r), (a), (b)))
  22508. +#define __nds32__v_kmabb(r, a, b) \
  22509. + (__builtin_nds32_v_kmabb ((r), (a), (b)))
  22510. +#define __nds32__kmabt(r, a, b) \
  22511. + (__builtin_nds32_kmabt ((r), (a), (b)))
  22512. +#define __nds32__v_kmabt(r, a, b) \
  22513. + (__builtin_nds32_v_kmabt ((r), (a), (b)))
  22514. +#define __nds32__kmatt(r, a, b) \
  22515. + (__builtin_nds32_kmatt ((r), (a), (b)))
  22516. +#define __nds32__v_kmatt(r, a, b) \
  22517. + (__builtin_nds32_v_kmatt ((r), (a), (b)))
  22518. +#define __nds32__kmada(r, a, b) \
  22519. + (__builtin_nds32_kmada ((r), (a), (b)))
  22520. +#define __nds32__v_kmada(r, a, b) \
  22521. + (__builtin_nds32_v_kmada ((r), (a), (b)))
  22522. +#define __nds32__kmaxda(r, a, b) \
  22523. + (__builtin_nds32_kmaxda ((r), (a), (b)))
  22524. +#define __nds32__v_kmaxda(r, a, b) \
  22525. + (__builtin_nds32_v_kmaxda ((r), (a), (b)))
  22526. +#define __nds32__kmads(r, a, b) \
  22527. + (__builtin_nds32_kmads ((r), (a), (b)))
  22528. +#define __nds32__v_kmads(r, a, b) \
  22529. + (__builtin_nds32_v_kmads ((r), (a), (b)))
  22530. +#define __nds32__kmadrs(r, a, b) \
  22531. + (__builtin_nds32_kmadrs ((r), (a), (b)))
  22532. +#define __nds32__v_kmadrs(r, a, b) \
  22533. + (__builtin_nds32_v_kmadrs ((r), (a), (b)))
  22534. +#define __nds32__kmaxds(r, a, b) \
  22535. + (__builtin_nds32_kmaxds ((r), (a), (b)))
  22536. +#define __nds32__v_kmaxds(r, a, b) \
  22537. + (__builtin_nds32_v_kmaxds ((r), (a), (b)))
  22538. +#define __nds32__kmsda(r, a, b) \
  22539. + (__builtin_nds32_kmsda ((r), (a), (b)))
  22540. +#define __nds32__v_kmsda(r, a, b) \
  22541. + (__builtin_nds32_v_kmsda ((r), (a), (b)))
  22542. +#define __nds32__kmsxda(r, a, b) \
  22543. + (__builtin_nds32_kmsxda ((r), (a), (b)))
  22544. +#define __nds32__v_kmsxda(r, a, b) \
  22545. + (__builtin_nds32_v_kmsxda ((r), (a), (b)))
  22546. +
  22547. +#define __nds32__smal(a, b) \
  22548. + (__builtin_nds32_smal ((a), (b)))
  22549. +#define __nds32__v_smal(a, b) \
  22550. + (__builtin_nds32_v_smal ((a), (b)))
  22551. +
  22552. +#define __nds32__bitrev(a, b) \
  22553. + (__builtin_nds32_bitrev ((a), (b)))
  22554. +#define __nds32__wext(a, b) \
  22555. + (__builtin_nds32_wext ((a), (b)))
  22556. +#define __nds32__bpick(r, a, b) \
  22557. + (__builtin_nds32_bpick ((r), (a), (b)))
  22558. +#define __nds32__insb(r, a, b) \
  22559. + (__builtin_nds32_insb ((r), (a), (b)))
  22560. +
  22561. +#define __nds32__sadd64(a, b) \
  22562. + (__builtin_nds32_sadd64 ((a), (b)))
  22563. +#define __nds32__uadd64(a, b) \
  22564. + (__builtin_nds32_uadd64 ((a), (b)))
  22565. +#define __nds32__radd64(a, b) \
  22566. + (__builtin_nds32_radd64 ((a), (b)))
  22567. +#define __nds32__uradd64(a, b) \
  22568. + (__builtin_nds32_uradd64 ((a), (b)))
  22569. +#define __nds32__kadd64(a, b) \
  22570. + (__builtin_nds32_kadd64 ((a), (b)))
  22571. +#define __nds32__ukadd64(a, b) \
  22572. + (__builtin_nds32_ukadd64 ((a), (b)))
  22573. +#define __nds32__ssub64(a, b) \
  22574. + (__builtin_nds32_ssub64 ((a), (b)))
  22575. +#define __nds32__usub64(a, b) \
  22576. + (__builtin_nds32_usub64 ((a), (b)))
  22577. +#define __nds32__rsub64(a, b) \
  22578. + (__builtin_nds32_rsub64 ((a), (b)))
  22579. +#define __nds32__ursub64(a, b) \
  22580. + (__builtin_nds32_ursub64 ((a), (b)))
  22581. +#define __nds32__ksub64(a, b) \
  22582. + (__builtin_nds32_ksub64 ((a), (b)))
  22583. +#define __nds32__uksub64(a, b) \
  22584. + (__builtin_nds32_uksub64 ((a), (b)))
  22585. +
  22586. +#define __nds32__smar64(r, a, b) \
  22587. + (__builtin_nds32_smar64 ((r), (a), (b)))
  22588. +#define __nds32__smsr64(r, a, b) \
  22589. + (__builtin_nds32_smsr64 ((r), (a), (b)))
  22590. +#define __nds32__umar64(r, a, b) \
  22591. + (__builtin_nds32_umar64 ((r), (a), (b)))
  22592. +#define __nds32__umsr64(r, a, b) \
  22593. + (__builtin_nds32_umsr64 ((r), (a), (b)))
  22594. +#define __nds32__kmar64(r, a, b) \
  22595. + (__builtin_nds32_kmar64 ((r), (a), (b)))
  22596. +#define __nds32__kmsr64(r, a, b) \
  22597. + (__builtin_nds32_kmsr64 ((r), (a), (b)))
  22598. +#define __nds32__ukmar64(r, a, b) \
  22599. + (__builtin_nds32_ukmar64 ((r), (a), (b)))
  22600. +#define __nds32__ukmsr64(r, a, b) \
  22601. + (__builtin_nds32_ukmsr64 ((r), (a), (b)))
  22602. +
  22603. +#define __nds32__smalbb(r, a, b) \
  22604. + (__builtin_nds32_smalbb ((r), (a), (b)))
  22605. +#define __nds32__v_smalbb(r, a, b) \
  22606. + (__builtin_nds32_v_smalbb ((r), (a), (b)))
  22607. +#define __nds32__smalbt(r, a, b) \
  22608. + (__builtin_nds32_smalbt ((r), (a), (b)))
  22609. +#define __nds32__v_smalbt(r, a, b) \
  22610. + (__builtin_nds32_v_smalbt ((r), (a), (b)))
  22611. +#define __nds32__smaltt(r, a, b) \
  22612. + (__builtin_nds32_smaltt ((r), (a), (b)))
  22613. +#define __nds32__v_smaltt(r, a, b) \
  22614. + (__builtin_nds32_v_smaltt ((r), (a), (b)))
  22615. +#define __nds32__smalda(r, a, b) \
  22616. + (__builtin_nds32_smalda ((r), (a), (b)))
  22617. +#define __nds32__v_smalda(r, a, b) \
  22618. + (__builtin_nds32_v_smalda ((r), (a), (b)))
  22619. +#define __nds32__smalxda(r, a, b) \
  22620. + (__builtin_nds32_smalxda ((r), (a), (b)))
  22621. +#define __nds32__v_smalxda(r, a, b) \
  22622. + (__builtin_nds32_v_smalxda ((r), (a), (b)))
  22623. +#define __nds32__smalds(r, a, b) \
  22624. + (__builtin_nds32_smalds ((r), (a), (b)))
  22625. +#define __nds32__v_smalds(r, a, b) \
  22626. + (__builtin_nds32_v_smalds ((r), (a), (b)))
  22627. +#define __nds32__smaldrs(r, a, b) \
  22628. + (__builtin_nds32_smaldrs ((r), (a), (b)))
  22629. +#define __nds32__v_smaldrs(r, a, b) \
  22630. + (__builtin_nds32_v_smaldrs ((r), (a), (b)))
  22631. +#define __nds32__smalxds(r, a, b) \
  22632. + (__builtin_nds32_smalxds ((r), (a), (b)))
  22633. +#define __nds32__v_smalxds(r, a, b) \
  22634. + (__builtin_nds32_v_smalxds ((r), (a), (b)))
  22635. +#define __nds32__smslda(r, a, b) \
  22636. + (__builtin_nds32_smslda ((r), (a), (b)))
  22637. +#define __nds32__v_smslda(r, a, b) \
  22638. + (__builtin_nds32_v_smslda ((r), (a), (b)))
  22639. +#define __nds32__smslxda(r, a, b) \
  22640. + (__builtin_nds32_smslxda ((r), (a), (b)))
  22641. +#define __nds32__v_smslxda(r, a, b) \
  22642. + (__builtin_nds32_v_smslxda ((r), (a), (b)))
  22643. +
  22644. +#define __nds32__smul16(a, b) \
  22645. + (__builtin_nds32_smul16 ((a), (b)))
  22646. +#define __nds32__v_smul16(a, b) \
  22647. + (__builtin_nds32_v_smul16 ((a), (b)))
  22648. +#define __nds32__smulx16(a, b) \
  22649. + (__builtin_nds32_smulx16 ((a), (b)))
  22650. +#define __nds32__v_smulx16(a, b) \
  22651. + (__builtin_nds32_v_smulx16 ((a), (b)))
  22652. +#define __nds32__umul16(a, b) \
  22653. + (__builtin_nds32_umul16 ((a), (b)))
  22654. +#define __nds32__v_umul16(a, b) \
  22655. + (__builtin_nds32_v_umul16 ((a), (b)))
  22656. +#define __nds32__umulx16(a, b) \
  22657. + (__builtin_nds32_umulx16 ((a), (b)))
  22658. +#define __nds32__v_umulx16(a, b) \
  22659. + (__builtin_nds32_v_umulx16 ((a), (b)))
  22660. +
  22661. +#define __nds32__uclip32(a, imm) \
  22662. + (__builtin_nds32_uclip32 ((a), (imm)))
  22663. +#define __nds32__sclip32(a, imm) \
  22664. + (__builtin_nds32_sclip32 ((a), (imm)))
  22665. +#define __nds32__kabs(a) \
  22666. + (__builtin_nds32_kabs ((a)))
  22667. +
  22668. +#define __nds32__no_ext_zol() \
  22669. + (__builtin_nds32_no_ext_zol())
  22670. +
  22671. +#define __nds32__unaligned_feature() \
  22672. + (__builtin_nds32_unaligned_feature())
  22673. +#define __nds32__enable_unaligned() \
  22674. + (__builtin_nds32_enable_unaligned())
  22675. +#define __nds32__disable_unaligned() \
  22676. + (__builtin_nds32_disable_unaligned())
  22677. +
  22678. +#define NDS32ATTR_SIGNATURE __attribute__((signature))
  22679. +
  22680. #endif /* nds32_intrinsic.h */
  22681. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-intrinsic.md gcc-4.9.4/gcc/config/nds32/nds32-intrinsic.md
  22682. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-intrinsic.md 2014-01-02 23:23:26.000000000 +0100
  22683. +++ gcc-4.9.4/gcc/config/nds32/nds32-intrinsic.md 2016-08-08 20:37:45.502269936 +0200
  22684. @@ -1,5 +1,5 @@
  22685. ;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
  22686. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  22687. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  22688. ;; Contributed by Andes Technology Corporation.
  22689. ;;
  22690. ;; This file is part of GCC.
  22691. @@ -40,6 +40,26 @@
  22692. (set_attr "length" "4")]
  22693. )
  22694. +(define_expand "mtsr_isb"
  22695. + [(set (match_operand:SI 0 "register_operand" "")
  22696. + (match_operand:SI 1 "immediate_operand" ""))]
  22697. + ""
  22698. +{
  22699. + emit_insn (gen_unspec_volatile_mtsr (operands[0], operands[1]));
  22700. + emit_insn (gen_unspec_volatile_isb());
  22701. + DONE;
  22702. +})
  22703. +
  22704. +(define_expand "mtsr_dsb"
  22705. + [(set (match_operand:SI 0 "register_operand" "")
  22706. + (match_operand:SI 1 "immediate_operand" ""))]
  22707. + ""
  22708. +{
  22709. + emit_insn (gen_unspec_volatile_mtsr (operands[0], operands[1]));
  22710. + emit_insn (gen_unspec_dsb());
  22711. + DONE;
  22712. +})
  22713. +
  22714. (define_insn "unspec_volatile_mtsr"
  22715. [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
  22716. (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
  22717. @@ -58,6 +78,74 @@
  22718. (set_attr "length" "4")]
  22719. )
  22720. +;; FPU Register Transfer.
  22721. +
  22722. +(define_insn "unspec_fcpynsd"
  22723. + [(set (match_operand:DF 0 "register_operand" "=f")
  22724. + (unspec:DF [(match_operand:DF 1 "register_operand" "f")
  22725. + (match_operand:DF 2 "register_operand" "f")] UNSPEC_FCPYNSD))]
  22726. + ""
  22727. + "fcpynsd\t%0, %1, %2"
  22728. + [(set_attr "type" "misc")
  22729. + (set_attr "length" "4")]
  22730. +)
  22731. +
  22732. +(define_insn "unspec_fcpynss"
  22733. + [(set (match_operand:SF 0 "register_operand" "=f")
  22734. + (unspec:SF [(match_operand:SF 1 "register_operand" "f")
  22735. + (match_operand:SF 2 "register_operand" "f")] UNSPEC_FCPYNSS))]
  22736. + ""
  22737. + "fcpynss\t%0, %1, %2"
  22738. + [(set_attr "type" "misc")
  22739. + (set_attr "length" "4")]
  22740. +)
  22741. +
  22742. +(define_insn "unspec_fcpysd"
  22743. + [(set (match_operand:DF 0 "register_operand" "=f")
  22744. + (unspec:DF [(match_operand:DF 1 "register_operand" "f")
  22745. + (match_operand:DF 2 "register_operand" "f")] UNSPEC_FCPYSD))]
  22746. + ""
  22747. + "fcpysd\t%0, %1, %2"
  22748. + [(set_attr "type" "misc")
  22749. + (set_attr "length" "4")]
  22750. +)
  22751. +
  22752. +(define_insn "unspec_fcpyss"
  22753. + [(set (match_operand:SF 0 "register_operand" "=f")
  22754. + (unspec:SF [(match_operand:SF 1 "register_operand" "f")
  22755. + (match_operand:SF 2 "register_operand" "f")] UNSPEC_FCPYSS))]
  22756. + ""
  22757. + "fcpyss\t%0, %1, %2"
  22758. + [(set_attr "type" "misc")
  22759. + (set_attr "length" "4")]
  22760. +)
  22761. +
  22762. +(define_insn "unspec_fmfcsr"
  22763. + [(set (match_operand:SI 0 "register_operand" "=r")
  22764. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_FMFCSR))]
  22765. + ""
  22766. + "fmfcsr\t%0"
  22767. + [(set_attr "type" "misc")
  22768. + (set_attr "length" "4")]
  22769. +)
  22770. +
  22771. +(define_insn "unspec_fmtcsr"
  22772. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_FMTCSR)]
  22773. + ""
  22774. + "fmtcsr\t%0"
  22775. + [(set_attr "type" "misc")
  22776. + (set_attr "length" "4")]
  22777. +)
  22778. +
  22779. +(define_insn "unspec_fmfcfg"
  22780. + [(set (match_operand:SI 0 "register_operand" "=r")
  22781. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_FMFCFG))]
  22782. + ""
  22783. + "fmfcfg\t%0"
  22784. + [(set_attr "type" "misc")
  22785. + (set_attr "length" "4")]
  22786. +)
  22787. +
  22788. ;; ------------------------------------------------------------------------
  22789. ;; Interrupt Instructions.
  22790. @@ -76,6 +164,330 @@
  22791. [(set_attr "type" "misc")]
  22792. )
  22793. +(define_expand "unspec_enable_int"
  22794. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")] UNSPEC_VOLATILE_ENABLE_INT)]
  22795. + ""
  22796. +{
  22797. + rtx system_reg;
  22798. + rtx temp_reg = gen_reg_rtx (SImode);
  22799. +
  22800. + /* Set system register form nds32_intrinsic_register_names[]. */
  22801. + if ((INTVAL (operands[0]) >= NDS32_INT_H16)
  22802. + && (INTVAL (operands[0]) <= NDS32_INT_H31))
  22803. + {
  22804. + /* The $INT_MASK2 sixteenth bit correspond to H16, so need
  22805. + subtract 16. */
  22806. + system_reg = GEN_INT (__NDS32_REG_INT_MASK2__);
  22807. + operands[0] = GEN_INT (1 << ((INTVAL (operands[0]) - 16)));
  22808. + }
  22809. + else
  22810. + {
  22811. + system_reg = GEN_INT (__NDS32_REG_INT_MASK__);
  22812. + operands[0] = GEN_INT (1 << (INTVAL (operands[0])));
  22813. + }
  22814. +
  22815. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22816. + emit_insn (gen_iorsi3 (temp_reg, temp_reg, operands[0]));
  22817. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  22818. + emit_insn (gen_unspec_dsb ());
  22819. + DONE;
  22820. +})
  22821. +
  22822. +(define_expand "unspec_disable_int"
  22823. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")] UNSPEC_VOLATILE_DISABLE_INT)]
  22824. + ""
  22825. +{
  22826. + rtx system_reg;
  22827. + rtx temp_reg = gen_reg_rtx (SImode);
  22828. +
  22829. + /* Set system register form nds32_intrinsic_register_names[]. */
  22830. + if ((INTVAL (operands[0]) >= NDS32_INT_H16)
  22831. + && (INTVAL (operands[0]) <= NDS32_INT_H31))
  22832. + {
  22833. + system_reg = GEN_INT (__NDS32_REG_INT_MASK2__);
  22834. + /* The $INT_MASK2 sixteenth bit correspond to H16, so need
  22835. + subtract 16. */
  22836. + operands[0] = GEN_INT ( ~(1 << (INTVAL (operands[0]) - 16)));
  22837. + }
  22838. + else
  22839. + {
  22840. + system_reg = GEN_INT (__NDS32_REG_INT_MASK__);
  22841. + operands[0] = GEN_INT ( ~(1 << (INTVAL (operands[0]))));
  22842. + }
  22843. +
  22844. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22845. + emit_insn (gen_andsi3 (temp_reg, temp_reg, operands[0]));
  22846. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  22847. + emit_insn (gen_unspec_dsb ());
  22848. + DONE;
  22849. +})
  22850. +
  22851. +(define_expand "unspec_set_pending_swint"
  22852. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SET_PENDING_SWINT)]
  22853. + ""
  22854. +{
  22855. + /* Get $INT_PEND system register form nds32_intrinsic_register_names[] */
  22856. + rtx system_reg = GEN_INT (__NDS32_REG_INT_PEND__);
  22857. + rtx temp_reg = gen_reg_rtx (SImode);
  22858. +
  22859. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22860. + emit_insn (gen_iorsi3 (temp_reg, temp_reg, GEN_INT (65536)));
  22861. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  22862. + emit_insn (gen_unspec_dsb ());
  22863. + DONE;
  22864. +})
  22865. +
  22866. +(define_expand "unspec_clr_pending_swint"
  22867. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CLR_PENDING_SWINT)]
  22868. + ""
  22869. +{
  22870. + /* Get $INT_PEND system register form nds32_intrinsic_register_names[] */
  22871. + rtx system_reg = GEN_INT (__NDS32_REG_INT_PEND__);
  22872. + rtx temp_reg = gen_reg_rtx (SImode);
  22873. +
  22874. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22875. + emit_insn (gen_andsi3 (temp_reg, temp_reg, GEN_INT (~(1 << 16))));
  22876. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  22877. + emit_insn (gen_unspec_dsb ());
  22878. + DONE;
  22879. +})
  22880. +
  22881. +(define_expand "unspec_clr_pending_hwint"
  22882. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")] UNSPEC_VOLATILE_CLR_PENDING_HWINT)]
  22883. + ""
  22884. +{
  22885. + rtx system_reg;
  22886. + rtx temp_reg = gen_reg_rtx (SImode);
  22887. + rtx clr_hwint;
  22888. +
  22889. + /* Set system register form nds32_intrinsic_register_names[]. */
  22890. + if ((INTVAL (operands[0]) >= NDS32_INT_H0)
  22891. + && (INTVAL (operands[0]) <= NDS32_INT_H15))
  22892. + {
  22893. + system_reg = GEN_INT (__NDS32_REG_INT_PEND__);
  22894. + clr_hwint = GEN_INT (~(1 << INTVAL (operands[0])));
  22895. + }
  22896. + else if ((INTVAL (operands[0]) >= NDS32_INT_H16)
  22897. + && (INTVAL (operands[0]) <= NDS32_INT_H31))
  22898. + {
  22899. + system_reg = GEN_INT (__NDS32_REG_INT_PEND2__);
  22900. + /* The $INT_PEND2 sixteenth bit correspond to H16, so need
  22901. + subtract 16. */
  22902. + clr_hwint = GEN_INT (~(1 << (INTVAL (operands[0]) - 16)));
  22903. + }
  22904. + else
  22905. + error ("__nds32__clr_pending_hwint not support NDS32_INT_SWI,"
  22906. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  22907. +
  22908. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22909. + emit_insn (gen_andsi3 (temp_reg, temp_reg, clr_hwint));
  22910. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  22911. + emit_insn (gen_unspec_dsb ());
  22912. + DONE;
  22913. +})
  22914. +
  22915. +(define_expand "unspec_get_all_pending_int"
  22916. + [(set (match_operand:SI 0 "register_operand" "")
  22917. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_GET_ALL_PENDING_INT))]
  22918. + ""
  22919. +{
  22920. + rtx system_reg = GEN_INT (__NDS32_REG_INT_PEND__);
  22921. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  22922. + emit_insn (gen_unspec_dsb ());
  22923. + DONE;
  22924. +})
  22925. +
  22926. +(define_expand "unspec_get_pending_int"
  22927. + [(set (match_operand:SI 0 "register_operand" "")
  22928. + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_VOLATILE_GET_PENDING_INT))]
  22929. + ""
  22930. +{
  22931. + rtx system_reg;
  22932. +
  22933. + /* Set system register form nds32_intrinsic_register_names[]. */
  22934. + if ((INTVAL (operands[1]) >= NDS32_INT_H0)
  22935. + && (INTVAL (operands[1]) <= NDS32_INT_SWI))
  22936. + {
  22937. + system_reg = GEN_INT (__NDS32_REG_INT_PEND__);
  22938. + operands[2] = GEN_INT (31 - INTVAL (operands[1]));
  22939. + }
  22940. + else if ((INTVAL (operands[1]) >= NDS32_INT_H16)
  22941. + && (INTVAL (operands[1]) <= NDS32_INT_H31))
  22942. + {
  22943. + system_reg = GEN_INT (__NDS32_REG_INT_PEND2__);
  22944. + /* The $INT_PEND2 sixteenth bit correspond to H16, so need
  22945. + subtract 16. */
  22946. + operands[2] = GEN_INT (31 - (INTVAL (operands[1]) - 16));
  22947. + }
  22948. + else
  22949. + error ("get_pending_int not support NDS32_INT_ALZ,"
  22950. + " NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  22951. +
  22952. + /* mfsr op0, sytem_reg */
  22953. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  22954. + emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
  22955. + emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (31)));
  22956. + emit_insn (gen_unspec_dsb ());
  22957. + DONE;
  22958. +})
  22959. +
  22960. +(define_expand "unspec_set_int_priority"
  22961. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")
  22962. + (match_operand:SI 1 "immediate_operand" "")] UNSPEC_VOLATILE_SET_INT_PRIORITY)]
  22963. + ""
  22964. +{
  22965. + rtx system_reg;
  22966. + rtx priority;
  22967. + rtx mask;
  22968. + rtx temp_reg = gen_reg_rtx (SImode);
  22969. + rtx mask_reg = gen_reg_rtx (SImode);
  22970. + rtx set_reg = gen_reg_rtx (SImode);
  22971. +
  22972. + /* Get system register form nds32_intrinsic_register_names[]. */
  22973. + if (INTVAL (operands[0]) <= NDS32_INT_H15)
  22974. + {
  22975. + system_reg = GEN_INT (__NDS32_REG_INT_PRI__);
  22976. + mask = GEN_INT (~(3 << 2 * INTVAL (operands[0])));
  22977. + priority = GEN_INT ((int) (INTVAL (operands[1])
  22978. + << (INTVAL (operands[0]) * 2)));
  22979. + }
  22980. + else if (INTVAL (operands[0]) >= NDS32_INT_H16
  22981. + && INTVAL (operands[0]) <= NDS32_INT_H31)
  22982. + {
  22983. + system_reg = GEN_INT (__NDS32_REG_INT_PRI2__);
  22984. + /* The $INT_PRI2 first bit correspond to H16, so need
  22985. + subtract 32. */
  22986. + mask = GEN_INT (~(3 << 2 * (INTVAL (operands[0]) - 32)));
  22987. + priority = GEN_INT ((int) (INTVAL (operands[1])
  22988. + << ((INTVAL (operands[0]) - 32) * 2)));
  22989. + }
  22990. + else
  22991. + error ("set_int_priority not support NDS32_INT_SWI,"
  22992. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  22993. +
  22994. + emit_move_insn (mask_reg, mask);
  22995. + emit_move_insn (set_reg, priority);
  22996. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  22997. + emit_insn (gen_andsi3 (temp_reg, temp_reg, mask_reg));
  22998. + emit_insn (gen_iorsi3 (temp_reg, temp_reg, set_reg));
  22999. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  23000. + emit_insn (gen_unspec_dsb ());
  23001. + DONE;
  23002. +})
  23003. +
  23004. +(define_expand "unspec_get_int_priority"
  23005. + [(set (match_operand:SI 0 "register_operand" "")
  23006. + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_VOLATILE_GET_INT_PRIORITY))]
  23007. + ""
  23008. +{
  23009. + rtx system_reg;
  23010. +
  23011. + /* Get system register form nds32_intrinsic_register_names[] */
  23012. + if (INTVAL (operands[1]) <= NDS32_INT_H15)
  23013. + {
  23014. + system_reg = GEN_INT (__NDS32_REG_INT_PRI__);
  23015. + operands[2] = GEN_INT (31 - 2 * INTVAL (operands[1]));
  23016. + }
  23017. + else if (INTVAL (operands[1]) >= NDS32_INT_H16
  23018. + && INTVAL (operands[1]) <= NDS32_INT_H31)
  23019. + {
  23020. + system_reg = GEN_INT (__NDS32_REG_INT_PRI2__);
  23021. + /* The $INT_PRI2 first bit correspond to H16, so need
  23022. + subtract 32. */
  23023. + operands[2] = GEN_INT (31 - 2 * (INTVAL (operands[1]) - 32));
  23024. + }
  23025. + else
  23026. + error ("set_int_priority not support NDS32_INT_SWI,"
  23027. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  23028. +
  23029. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  23030. + emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
  23031. + emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (30)));
  23032. + emit_insn (gen_unspec_dsb ());
  23033. + DONE;
  23034. +})
  23035. +
  23036. +(define_expand "unspec_set_trig_level"
  23037. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")] UNSPEC_VOLATILE_SET_TRIG_LEVEL)]
  23038. + ""
  23039. +{
  23040. + rtx system_reg = GEN_INT (__NDS32_REG_INT_TRIGGER__);
  23041. + rtx temp_reg = gen_reg_rtx (SImode);
  23042. + rtx set_level;
  23043. +
  23044. + if ((INTVAL (operands[0]) == NDS32_INT_SWI)
  23045. + || (INTVAL (operands[0]) == NDS32_INT_ALZ)
  23046. + || (INTVAL (operands[0]) == NDS32_INT_IDIVZE)
  23047. + || (INTVAL (operands[0]) == NDS32_INT_DSSIM))
  23048. + error ("__nds32__set_trig_type_level not support NDS32_INT_SWI,"
  23049. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  23050. +
  23051. + /* TRIGGER register, 0 mean level triggered and 1 mean edge triggered. */
  23052. + if (INTVAL (operands[0]) > NDS32_INT_H15)
  23053. + set_level = GEN_INT (~(1 << (INTVAL (operands[0]) - 16)));
  23054. + else
  23055. + set_level = GEN_INT (~(1 << INTVAL (operands[0])));
  23056. +
  23057. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  23058. + emit_insn (gen_andsi3 (temp_reg, temp_reg, set_level));
  23059. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  23060. + DONE;
  23061. +})
  23062. +
  23063. +(define_expand "unspec_set_trig_edge"
  23064. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "")] UNSPEC_VOLATILE_SET_TRIG_EDGE)]
  23065. + ""
  23066. +{
  23067. + rtx system_reg = GEN_INT (__NDS32_REG_INT_TRIGGER__);
  23068. + rtx temp_reg = gen_reg_rtx (SImode);
  23069. + rtx set_level;
  23070. +
  23071. + if ((INTVAL (operands[0]) == NDS32_INT_SWI)
  23072. + || (INTVAL (operands[0]) == NDS32_INT_ALZ)
  23073. + || (INTVAL (operands[0]) == NDS32_INT_IDIVZE)
  23074. + || (INTVAL (operands[0]) == NDS32_INT_DSSIM))
  23075. + error ("__nds32__set_trig_type_edge not support NDS32_INT_SWI,"
  23076. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  23077. +
  23078. + /* TRIGGER register, 0 mean level triggered and 1 mean edge triggered. */
  23079. + if (INTVAL (operands[0]) > NDS32_INT_H15)
  23080. + set_level = GEN_INT ((1 << (INTVAL (operands[0]) - 16)));
  23081. + else
  23082. + set_level = GEN_INT ((1 << INTVAL (operands[0])));
  23083. +
  23084. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  23085. + emit_insn (gen_iorsi3 (temp_reg, temp_reg, set_level));
  23086. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  23087. + DONE;
  23088. +})
  23089. +
  23090. +(define_expand "unspec_get_trig_type"
  23091. + [(set (match_operand:SI 0 "register_operand" "")
  23092. + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_VOLATILE_GET_TRIG_TYPE))]
  23093. + ""
  23094. +{
  23095. + rtx system_reg = GEN_INT (__NDS32_REG_INT_TRIGGER__);
  23096. + rtx trig_type;
  23097. +
  23098. + if ((INTVAL (operands[1]) == NDS32_INT_SWI)
  23099. + || (INTVAL (operands[1]) == NDS32_INT_ALZ)
  23100. + || (INTVAL (operands[1]) == NDS32_INT_IDIVZE)
  23101. + || (INTVAL (operands[1]) == NDS32_INT_DSSIM))
  23102. + error ("__nds32__get_trig_type not support NDS32_INT_SWI,"
  23103. + " NDS32_INT_ALZ, NDS32_INT_IDIVZE, NDS32_INT_DSSIM");
  23104. +
  23105. + if (INTVAL (operands[1]) > NDS32_INT_H15)
  23106. + trig_type = GEN_INT (31 - (INTVAL (operands[1]) - 16));
  23107. + else
  23108. + trig_type = GEN_INT (31 - INTVAL (operands[1]));
  23109. +
  23110. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  23111. + emit_insn (gen_ashlsi3 (operands[0], operands[0], trig_type));
  23112. + emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (31)));
  23113. + emit_insn (gen_unspec_dsb ());
  23114. + DONE;
  23115. +})
  23116. +
  23117. ;; ------------------------------------------------------------------------
  23118. ;; Cache Synchronization Instructions
  23119. @@ -84,7 +496,7 @@
  23120. [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
  23121. ""
  23122. "isync\t%0"
  23123. - [(set_attr "type" "misc")]
  23124. + [(set_attr "type" "mmu")]
  23125. )
  23126. (define_insn "unspec_volatile_isb"
  23127. @@ -94,4 +506,1061 @@
  23128. [(set_attr "type" "misc")]
  23129. )
  23130. +(define_insn "unspec_dsb"
  23131. + [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_DSB)]
  23132. + ""
  23133. + "dsb"
  23134. + [(set_attr "type" "misc")]
  23135. +)
  23136. +
  23137. +(define_insn "unspec_msync"
  23138. + [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_MSYNC)]
  23139. + ""
  23140. + "msync\t%0"
  23141. + [(set_attr "type" "misc")]
  23142. +)
  23143. +
  23144. +(define_insn "unspec_msync_all"
  23145. + [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_MSYNC_ALL)]
  23146. + ""
  23147. + "msync\tall"
  23148. + [(set_attr "type" "misc")]
  23149. +)
  23150. +
  23151. +(define_insn "unspec_msync_store"
  23152. + [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_MSYNC_STORE)]
  23153. + ""
  23154. + "msync\tstore"
  23155. + [(set_attr "type" "misc")]
  23156. +)
  23157. +
  23158. +;; Load and Store
  23159. +
  23160. +(define_insn "unspec_volatile_llw"
  23161. + [(set (match_operand:SI 0 "register_operand" "=r")
  23162. + (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
  23163. + (match_operand:SI 2 "register_operand" "r")))] UNSPEC_VOLATILE_LLW))]
  23164. + ""
  23165. + "llw\t%0, [%1 + %2]"
  23166. + [(set_attr "length" "4")]
  23167. +)
  23168. +
  23169. +(define_insn "unspec_lwup"
  23170. + [(set (match_operand:SI 0 "register_operand" "=r")
  23171. + (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
  23172. + (match_operand:SI 2 "register_operand" "r")))] UNSPEC_LWUP))]
  23173. + ""
  23174. + "lwup\t%0, [%1 + %2]"
  23175. + [(set_attr "length" "4")]
  23176. +)
  23177. +
  23178. +(define_insn "unspec_lbup"
  23179. + [(set (match_operand:SI 0 "register_operand" "=r")
  23180. + (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
  23181. + (match_operand:SI 2 "register_operand" "r")))] UNSPEC_LBUP))]
  23182. + ""
  23183. + "lbup\t%0, [%1 + %2]"
  23184. + [(set_attr "length" "4")]
  23185. +)
  23186. +
  23187. +(define_insn "unspec_volatile_scw"
  23188. + [(set (match_operand:SI 0 "register_operand" "=r")
  23189. + (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
  23190. + (match_operand:SI 2 "register_operand" "r")))
  23191. + (match_operand:SI 3 "register_operand" "0")] UNSPEC_VOLATILE_SCW))]
  23192. + ""
  23193. + "scw\t%0, [%1 + %2]"
  23194. + [(set_attr "length" "4")]
  23195. +)
  23196. +
  23197. +(define_insn "unspec_swup"
  23198. + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
  23199. + (match_operand:SI 1 "register_operand" "r")))
  23200. + (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_SWUP))]
  23201. + ""
  23202. + "swup\t%2, [%0 + %1]"
  23203. + [(set_attr "length" "4")]
  23204. +)
  23205. +
  23206. +(define_insn "unspec_sbup"
  23207. + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
  23208. + (match_operand:SI 1 "register_operand" "r")))
  23209. + (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_SBUP))]
  23210. + ""
  23211. + "sbup\t%2, [%0 + %1]"
  23212. + [(set_attr "length" "4")]
  23213. +)
  23214. +
  23215. +;; CCTL
  23216. +
  23217. +(define_insn "cctl_l1d_invalall"
  23218. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_INVALALL)]
  23219. + ""
  23220. + "cctl\tL1D_INVALALL"
  23221. + [(set_attr "type" "mmu")]
  23222. +)
  23223. +
  23224. +(define_insn "cctl_l1d_wball_alvl"
  23225. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_WBALL_ALVL)]
  23226. + ""
  23227. + "cctl\tL1D_WBALL, alevel"
  23228. + [(set_attr "type" "mmu")]
  23229. +)
  23230. +
  23231. +(define_insn "cctl_l1d_wball_one_lvl"
  23232. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_WBALL_ONE_LVL)]
  23233. + ""
  23234. + "cctl\tL1D_WBALL, 1level"
  23235. + [(set_attr "type" "mmu")]
  23236. +)
  23237. +
  23238. +(define_insn "cctl_idx_read"
  23239. + [(set (match_operand:SI 0 "register_operand" "=r")
  23240. + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")
  23241. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_READ))]
  23242. + ""
  23243. + "cctl\t%0, %2, %X1"
  23244. + [(set_attr "type" "mmu")]
  23245. +)
  23246. +
  23247. +(define_insn "cctl_idx_write"
  23248. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
  23249. + (match_operand:SI 1 "register_operand" "r")
  23250. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_WRITE)]
  23251. + ""
  23252. + "cctl\t%1, %2, %W0"
  23253. + [(set_attr "type" "mmu")]
  23254. +)
  23255. +
  23256. +(define_insn "cctl_va_wbinval_l1"
  23257. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
  23258. + (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_WBINVAL_L1)]
  23259. + ""
  23260. + "cctl\t%1, %U0, 1level"
  23261. + [(set_attr "type" "mmu")]
  23262. +)
  23263. +
  23264. +(define_insn "cctl_va_wbinval_la"
  23265. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
  23266. + (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_WBINVAL_LA)]
  23267. + ""
  23268. + "cctl\t%1, %U0, alevel"
  23269. + [(set_attr "type" "mmu")]
  23270. +)
  23271. +
  23272. +(define_insn "cctl_idx_wbinval"
  23273. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
  23274. + (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_WBINVAL)]
  23275. + ""
  23276. + "cctl\t%1, %T0"
  23277. + [(set_attr "type" "mmu")]
  23278. +)
  23279. +
  23280. +(define_insn "cctl_va_lck"
  23281. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
  23282. + (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_LCK)]
  23283. + ""
  23284. + "cctl\t%1, %R0"
  23285. + [(set_attr "type" "mmu")]
  23286. +)
  23287. +
  23288. +;;PREFETCH
  23289. +
  23290. +(define_insn "prefetch_qw"
  23291. + [(unspec_volatile:QI [(match_operand:SI 0 "register_operand" "r")
  23292. + (match_operand:SI 1 "nonmemory_operand" "r")
  23293. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_VOLATILE_DPREF_QW)]
  23294. + ""
  23295. + "dpref\t%Z2, [%0 + %1]"
  23296. + [(set_attr "type" "misc")]
  23297. +)
  23298. +
  23299. +(define_insn "prefetch_hw"
  23300. + [(unspec_volatile:HI [(match_operand:SI 0 "register_operand" "r")
  23301. + (match_operand:SI 1 "nonmemory_operand" "r")
  23302. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_VOLATILE_DPREF_HW)]
  23303. + ""
  23304. + "dpref\t%Z2, [%0 + (%1<<1)]"
  23305. + [(set_attr "type" "misc")]
  23306. +)
  23307. +
  23308. +(define_insn "prefetch_w"
  23309. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" " r, r")
  23310. + (match_operand:SI 1 "nonmemory_operand" "Is15, r")
  23311. + (match_operand:SI 2 "immediate_operand" " i, i")] UNSPEC_VOLATILE_DPREF_W)]
  23312. + ""
  23313. + "@
  23314. + dprefi.w\t%Z2, [%0 + %1]
  23315. + dpref\t%Z2, [%0 + (%1<<2)]"
  23316. + [(set_attr "type" "misc")]
  23317. +)
  23318. +
  23319. +(define_insn "prefetch_dw"
  23320. + [(unspec_volatile:DI [(match_operand:SI 0 "register_operand" " r, r")
  23321. + (match_operand:SI 1 "nonmemory_operand" "Is15, r")
  23322. + (match_operand:SI 2 "immediate_operand" " i, i")] UNSPEC_VOLATILE_DPREF_DW)]
  23323. + ""
  23324. + "@
  23325. + dprefi.d\t%Z2, [%0 + %1]
  23326. + dpref\t%Z2, [%0 + (%1<<3)]"
  23327. + [(set_attr "type" "misc")]
  23328. +)
  23329. +
  23330. +;; Performance Extension
  23331. +
  23332. +(define_insn "unspec_ave"
  23333. + [(set (match_operand:SI 0 "register_operand" "=r")
  23334. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23335. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_AVE))]
  23336. + ""
  23337. + "ave\t%0, %1, %2"
  23338. + [(set_attr "type" "alu")
  23339. + (set_attr "length" "4")]
  23340. +)
  23341. +
  23342. +(define_insn "unspec_bclr"
  23343. + [(set (match_operand:SI 0 "register_operand" "=r")
  23344. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23345. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_BCLR))]
  23346. + ""
  23347. + "bclr\t%0, %1, %2"
  23348. + [(set_attr "type" "alu")
  23349. + (set_attr "length" "4")]
  23350. +)
  23351. +
  23352. +(define_insn "unspec_bset"
  23353. + [(set (match_operand:SI 0 "register_operand" "=r")
  23354. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23355. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_BSET))]
  23356. + ""
  23357. + "bset\t%0, %1, %2"
  23358. + [(set_attr "type" "alu")
  23359. + (set_attr "length" "4")]
  23360. +)
  23361. +
  23362. +(define_insn "unspec_btgl"
  23363. + [(set (match_operand:SI 0 "register_operand" "=r")
  23364. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23365. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_BTGL))]
  23366. + ""
  23367. + "btgl\t%0, %1, %2"
  23368. + [(set_attr "type" "alu")
  23369. + (set_attr "length" "4")]
  23370. +)
  23371. +
  23372. +(define_insn "unspec_btst"
  23373. + [(set (match_operand:SI 0 "register_operand" "=r")
  23374. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23375. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_BTST))]
  23376. + ""
  23377. + "btst\t%0, %1, %2"
  23378. + [(set_attr "type" "alu")
  23379. + (set_attr "length" "4")]
  23380. +)
  23381. +
  23382. +(define_insn "unspec_clip"
  23383. + [(set (match_operand:SI 0 "register_operand" "=r")
  23384. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23385. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP))]
  23386. + ""
  23387. + "clip\t%0, %1, %2"
  23388. + [(set_attr "type" "alu")
  23389. + (set_attr "length" "4")]
  23390. +)
  23391. +
  23392. +(define_insn "unspec_clips"
  23393. + [(set (match_operand:SI 0 "register_operand" "=r")
  23394. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23395. + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS))]
  23396. + ""
  23397. + "clips\t%0, %1, %2"
  23398. + [(set_attr "type" "alu")
  23399. + (set_attr "length" "4")]
  23400. +)
  23401. +
  23402. +(define_insn "unspec_clo"
  23403. + [(set (match_operand:SI 0 "register_operand" "=r")
  23404. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CLO))]
  23405. + ""
  23406. + "clo\t%0, %1"
  23407. + [(set_attr "type" "alu")
  23408. + (set_attr "length" "4")]
  23409. +)
  23410. +
  23411. +(define_insn "unspec_ssabssi2"
  23412. + [(set (match_operand:SI 0 "register_operand" "=r")
  23413. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_ABS))]
  23414. + ""
  23415. + "abs\t%0, %1"
  23416. + [(set_attr "type" "alu")
  23417. + (set_attr "length" "4")]
  23418. +)
  23419. +
  23420. +;; Performance extension 2
  23421. +
  23422. +(define_insn "unspec_pbsad"
  23423. + [(set (match_operand:SI 0 "register_operand" "=r")
  23424. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23425. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_PBSAD))]
  23426. + ""
  23427. + "pbsad\t%0, %1, %2"
  23428. + [(set_attr "type" "pbsad")
  23429. + (set_attr "length" "4")]
  23430. +)
  23431. +
  23432. +(define_insn "unspec_pbsada"
  23433. + [(set (match_operand:SI 0 "register_operand" "=r")
  23434. + (unspec:SI [(match_operand:SI 1 "register_operand" "0")
  23435. + (match_operand:SI 2 "register_operand" "r")
  23436. + (match_operand:SI 3 "register_operand" "r")] UNSPEC_PBSADA))]
  23437. + ""
  23438. + "pbsada\t%0, %2, %3"
  23439. + [(set_attr "type" "pbsada")
  23440. + (set_attr "length" "4")]
  23441. +)
  23442. +
  23443. +(define_expand "bse"
  23444. + [(match_operand:SI 0 "register_operand" "")
  23445. + (match_operand:SI 1 "register_operand" "")
  23446. + (match_operand:SI 2 "register_operand" "")]
  23447. + ""
  23448. + {
  23449. + rtx temp0 = gen_reg_rtx (SImode);
  23450. + rtx temp2 = gen_reg_rtx (SImode);
  23451. +
  23452. + emit_move_insn (temp0, gen_rtx_MEM (Pmode, operands[0]));
  23453. + emit_move_insn (temp2, gen_rtx_MEM (Pmode, operands[2]));
  23454. + emit_insn (gen_unspec_bse (temp0, operands[1], temp2, temp0, temp2));
  23455. + emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp0);
  23456. + emit_move_insn (gen_rtx_MEM (Pmode, operands[2]), temp2);
  23457. + DONE;
  23458. + }
  23459. +)
  23460. +
  23461. +(define_insn "unspec_bse"
  23462. + [(set (match_operand:SI 0 "register_operand" "=r")
  23463. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23464. + (match_operand:SI 2 "register_operand" "r")
  23465. + (match_operand:SI 3 "register_operand" "0")] UNSPEC_BSE))
  23466. + (set (match_operand:SI 4 "register_operand" "=2")
  23467. + (unspec:SI [(match_dup 1)
  23468. + (match_dup 2)
  23469. + (match_dup 0)] UNSPEC_BSE_2))]
  23470. + ""
  23471. + "bse\t%0, %1, %2"
  23472. + [(set_attr "type" "alu")
  23473. + (set_attr "length" "4")]
  23474. +)
  23475. +
  23476. +(define_expand "bsp"
  23477. + [(match_operand:SI 0 "register_operand" "")
  23478. + (match_operand:SI 1 "register_operand" "")
  23479. + (match_operand:SI 2 "register_operand" "")]
  23480. + ""
  23481. + {
  23482. + rtx temp0 = gen_reg_rtx (SImode);
  23483. + rtx temp2 = gen_reg_rtx (SImode);
  23484. +
  23485. + emit_move_insn (temp0, gen_rtx_MEM (Pmode, operands[0]));
  23486. + emit_move_insn (temp2, gen_rtx_MEM (Pmode, operands[2]));
  23487. + emit_insn (gen_unspec_bsp (temp0, operands[1], temp2, temp0, temp2));
  23488. + emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp0);
  23489. + emit_move_insn (gen_rtx_MEM (Pmode, operands[2]), temp2);
  23490. + DONE;
  23491. + }
  23492. +)
  23493. +
  23494. +(define_insn "unspec_bsp"
  23495. + [(set (match_operand:SI 0 "register_operand" "=r")
  23496. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23497. + (match_operand:SI 2 "register_operand" "r")
  23498. + (match_operand:SI 3 "register_operand" "0")] UNSPEC_BSP))
  23499. + (set (match_operand:SI 4 "register_operand" "=2")
  23500. + (unspec:SI [(match_dup 1)
  23501. + (match_dup 2)
  23502. + (match_dup 0)] UNSPEC_BSP_2))]
  23503. + ""
  23504. + "bsp\t%0, %1, %2"
  23505. + [(set_attr "type" "alu")
  23506. + (set_attr "length" "4")]
  23507. +)
  23508. +
  23509. +;; String Extension
  23510. +
  23511. +(define_insn "unspec_ffb"
  23512. + [(set (match_operand:SI 0 "register_operand" "=r, r")
  23513. + (unspec:SI [(match_operand:SI 1 "register_operand" "r, r")
  23514. + (match_operand:SI 2 "nonmemory_operand" "Iu08, r")] UNSPEC_FFB))]
  23515. + ""
  23516. + "@
  23517. + ffbi\t%0, %1, %2
  23518. + ffb\t%0, %1, %2"
  23519. + [(set_attr "type" "alu")
  23520. + (set_attr "length" "4")]
  23521. +)
  23522. +
  23523. +(define_insn "unspec_ffmism"
  23524. + [(set (match_operand:SI 0 "register_operand" "=r")
  23525. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23526. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_FFMISM))]
  23527. + ""
  23528. + "ffmism\t%0, %1, %2"
  23529. + [(set_attr "type" "alu")
  23530. + (set_attr "length" "4")]
  23531. +)
  23532. +
  23533. +(define_insn "unspec_flmism"
  23534. + [(set (match_operand:SI 0 "register_operand" "=r")
  23535. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23536. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_FLMISM))]
  23537. + ""
  23538. + "flmism\t%0, %1, %2"
  23539. + [(set_attr "type" "alu")
  23540. + (set_attr "length" "4")]
  23541. +)
  23542. +
  23543. +;; SATURATION
  23544. +
  23545. +(define_insn "unspec_kaddw"
  23546. + [(set (match_operand:SI 0 "register_operand" "=r")
  23547. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23548. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KADDW))]
  23549. + ""
  23550. + "kaddw\t%0, %1, %2"
  23551. + [(set_attr "type" "alu")
  23552. + (set_attr "length" "4")]
  23553. +)
  23554. +
  23555. +(define_insn "unspec_ksubw"
  23556. + [(set (match_operand:SI 0 "register_operand" "=r")
  23557. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23558. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSUBW))]
  23559. + ""
  23560. + "ksubw\t%0, %1, %2"
  23561. + [(set_attr "type" "alu")
  23562. + (set_attr "length" "4")]
  23563. +)
  23564. +
  23565. +(define_insn "unspec_kaddh"
  23566. + [(set (match_operand:SI 0 "register_operand" "=r")
  23567. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23568. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KADDH))]
  23569. + ""
  23570. + "kaddh\t%0, %1, %2"
  23571. + [(set_attr "type" "alu")
  23572. + (set_attr "length" "4")]
  23573. +)
  23574. +
  23575. +(define_insn "unspec_ksubh"
  23576. + [(set (match_operand:SI 0 "register_operand" "=r")
  23577. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23578. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSUBH))]
  23579. + ""
  23580. + "ksubh\t%0, %1, %2"
  23581. + [(set_attr "type" "alu")
  23582. + (set_attr "length" "4")]
  23583. +)
  23584. +
  23585. +(define_insn "unspec_kdmbb"
  23586. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23587. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23588. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBB))]
  23589. + ""
  23590. + "kdmbb\t%0, %1, %2"
  23591. + [(set_attr "type" "mul")
  23592. + (set_attr "length" "4")]
  23593. +)
  23594. +
  23595. +(define_insn "unspec_kdmbt"
  23596. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23597. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23598. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMBT))]
  23599. + ""
  23600. + "kdmbt\t%0, %1, %2"
  23601. + [(set_attr "type" "mul")
  23602. + (set_attr "length" "4")]
  23603. +)
  23604. +
  23605. +(define_insn "unspec_kdmtb"
  23606. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23607. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23608. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTB))]
  23609. + ""
  23610. + "kdmtb\t%0, %1, %2"
  23611. + [(set_attr "type" "mul")
  23612. + (set_attr "length" "4")]
  23613. +)
  23614. +
  23615. +(define_insn "unspec_kdmtt"
  23616. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23617. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23618. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KDMTT))]
  23619. + ""
  23620. + "kdmtt\t%0, %1, %2"
  23621. + [(set_attr "type" "mul")
  23622. + (set_attr "length" "4")]
  23623. +)
  23624. +
  23625. +(define_insn "unspec_khmbb"
  23626. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23627. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23628. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBB))]
  23629. + ""
  23630. + "khmbb\t%0, %1, %2"
  23631. + [(set_attr "type" "mul")
  23632. + (set_attr "length" "4")]
  23633. +)
  23634. +
  23635. +(define_insn "unspec_khmbt"
  23636. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23637. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23638. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMBT))]
  23639. + ""
  23640. + "khmbt\t%0, %1, %2"
  23641. + [(set_attr "type" "mul")
  23642. + (set_attr "length" "4")]
  23643. +)
  23644. +
  23645. +(define_insn "unspec_khmtb"
  23646. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23647. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23648. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTB))]
  23649. + ""
  23650. + "khmtb\t%0, %1, %2"
  23651. + [(set_attr "type" "mul")
  23652. + (set_attr "length" "4")]
  23653. +)
  23654. +
  23655. +(define_insn "unspec_khmtt"
  23656. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  23657. + (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "r")
  23658. + (match_operand:V2HI 2 "register_operand" "r")] UNSPEC_KHMTT))]
  23659. + ""
  23660. + "khmtt\t%0, %1, %2"
  23661. + [(set_attr "type" "mul")
  23662. + (set_attr "length" "4")]
  23663. +)
  23664. +
  23665. +(define_insn "unspec_kslraw"
  23666. + [(set (match_operand:SI 0 "register_operand" "=r")
  23667. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23668. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAW))]
  23669. + ""
  23670. + "kslraw\t%0, %1, %2"
  23671. + [(set_attr "type" "alu")
  23672. + (set_attr "length" "4")]
  23673. +)
  23674. +
  23675. +(define_insn "unspec_kslrawu"
  23676. + [(set (match_operand:SI 0 "register_operand" "=r")
  23677. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23678. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAWU))]
  23679. + ""
  23680. + "kslraw.u\t%0, %1, %2"
  23681. + [(set_attr "type" "alu")
  23682. + (set_attr "length" "4")]
  23683. +)
  23684. +
  23685. +(define_insn "unspec_rdov"
  23686. + [(set (match_operand:SI 0 "register_operand" "=r")
  23687. + (unspec:SI [(const_int 0)] UNSPEC_RDOV))]
  23688. + ""
  23689. + "rdov\t%0"
  23690. + [(set_attr "type" "misc")
  23691. + (set_attr "length" "4")]
  23692. +)
  23693. +
  23694. +(define_insn "unspec_clrov"
  23695. + [(unspec:SI [(const_int 0)] UNSPEC_CLROV)]
  23696. + ""
  23697. + "clrov"
  23698. + [(set_attr "type" "misc")
  23699. + (set_attr "length" "4")]
  23700. +)
  23701. +
  23702. +;; System
  23703. +
  23704. +(define_insn "unspec_sva"
  23705. + [(set (match_operand:SI 0 "register_operand" "=r")
  23706. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23707. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_SVA))]
  23708. + ""
  23709. + "sva\t%0, %1, %2"
  23710. + [(set_attr "type" "alu")
  23711. + (set_attr "length" "4")]
  23712. +)
  23713. +
  23714. +(define_insn "unspec_svs"
  23715. + [(set (match_operand:SI 0 "register_operand" "=r")
  23716. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")
  23717. + (match_operand:SI 2 "register_operand" "r")] UNSPEC_SVS))]
  23718. + ""
  23719. + "svs\t%0, %1, %2"
  23720. + [(set_attr "type" "alu")
  23721. + (set_attr "length" "4")]
  23722. +)
  23723. +
  23724. +(define_insn "unspec_jr_itoff"
  23725. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JR_ITOFF)]
  23726. + ""
  23727. + "jr.itoff\t%0"
  23728. + [(set_attr "type" "misc")]
  23729. +)
  23730. +
  23731. +(define_insn "unspec_jr_toff"
  23732. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JR_TOFF)]
  23733. + ""
  23734. + "jr.toff\t%0"
  23735. + [(set_attr "type" "branch")]
  23736. +)
  23737. +
  23738. +(define_insn "unspec_jral_iton"
  23739. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JRAL_ITON)]
  23740. + ""
  23741. + "jral.iton\t%0"
  23742. + [(set_attr "type" "branch")]
  23743. +)
  23744. +
  23745. +(define_insn "unspec_jral_ton"
  23746. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JRAL_TON)]
  23747. + ""
  23748. + "jral.ton\t%0"
  23749. + [(set_attr "type" "branch")]
  23750. +)
  23751. +
  23752. +(define_insn "unspec_ret_itoff"
  23753. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_RET_ITOFF)]
  23754. + ""
  23755. + "ret.itoff\t%0"
  23756. + [(set_attr "type" "branch")]
  23757. +)
  23758. +
  23759. +(define_insn "unspec_ret_toff"
  23760. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_RET_TOFF)]
  23761. + ""
  23762. + "ret.toff\t%0"
  23763. + [(set_attr "type" "branch")]
  23764. +)
  23765. +
  23766. +(define_insn "unspec_standby_no_wake_grant"
  23767. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_NO_WAKE_GRANT)]
  23768. + ""
  23769. + "standby\tno_wake_grant"
  23770. + [(set_attr "type" "misc")]
  23771. +)
  23772. +
  23773. +(define_insn "unspec_standby_wake_grant"
  23774. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_WAKE_GRANT)]
  23775. + ""
  23776. + "standby\twake_grant"
  23777. + [(set_attr "type" "misc")]
  23778. +)
  23779. +
  23780. +(define_insn "unspec_standby_wait_done"
  23781. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_WAKE_DONE)]
  23782. + ""
  23783. + "standby\twait_done"
  23784. + [(set_attr "type" "misc")]
  23785. +)
  23786. +
  23787. +(define_insn "unspec_teqz"
  23788. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
  23789. + (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_TEQZ)]
  23790. + ""
  23791. + "teqz\t%0, %1"
  23792. + [(set_attr "type" "misc")]
  23793. +)
  23794. +
  23795. +(define_insn "unspec_tnez"
  23796. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
  23797. + (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_TNEZ)]
  23798. + ""
  23799. + "tnez\t%0, %1"
  23800. + [(set_attr "type" "misc")]
  23801. +)
  23802. +
  23803. +(define_insn "unspec_trap"
  23804. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_TRAP)]
  23805. + ""
  23806. + "trap\t%0"
  23807. + [(set_attr "type" "misc")]
  23808. +)
  23809. +
  23810. +(define_insn "unspec_setend_big"
  23811. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETEND_BIG)]
  23812. + ""
  23813. + "setend.b"
  23814. + [(set_attr "type" "misc")]
  23815. +)
  23816. +
  23817. +(define_insn "unspec_setend_little"
  23818. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETEND_LITTLE)]
  23819. + ""
  23820. + "setend.l"
  23821. + [(set_attr "type" "misc")]
  23822. +)
  23823. +
  23824. +(define_insn "unspec_break"
  23825. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_BREAK)]
  23826. + ""
  23827. + "break\t%0"
  23828. + [(set_attr "type" "misc")]
  23829. +)
  23830. +
  23831. +(define_insn "unspec_syscall"
  23832. + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_SYSCALL)]
  23833. + ""
  23834. + "syscall\t%0"
  23835. + [(set_attr "type" "misc")]
  23836. +)
  23837. +
  23838. +(define_insn "unspec_nop"
  23839. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NOP)]
  23840. + ""
  23841. + "nop"
  23842. + [(set_attr "type" "misc")]
  23843. +)
  23844. +
  23845. +(define_insn "unspec_get_current_sp"
  23846. + [(set (match_operand:SI 0 "register_operand" "=r")
  23847. + (unspec_volatile:SI [(reg:SI SP_REGNUM)] UNSPEC_VOLATILE_GET_CURRENT_SP))]
  23848. + ""
  23849. + "mov55\t%0, $sp"
  23850. + [(set_attr "type" "misc")]
  23851. +)
  23852. +
  23853. +(define_insn "unspec_set_current_sp"
  23854. + [(set (reg:SI SP_REGNUM)
  23855. + (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_SET_CURRENT_SP))]
  23856. + ""
  23857. + "mov55\t$sp, %0"
  23858. + [(set_attr "type" "misc")]
  23859. +)
  23860. +
  23861. +(define_insn "unspec_return_address"
  23862. + [(set (match_operand:SI 0 "register_operand" "=r")
  23863. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_RETURN_ADDRESS))]
  23864. + ""
  23865. + "mov55\t%0, $lp"
  23866. + [(set_attr "type" "misc")]
  23867. +)
  23868. +
  23869. +(define_insn "unspec_signature_begin"
  23870. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SIGNATURE_BEGIN)]
  23871. + ""
  23872. + "isps"
  23873. + [(set_attr "length" "4")]
  23874. +)
  23875. +
  23876. +(define_insn "unspec_signature_end"
  23877. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SIGNATURE_END)]
  23878. + ""
  23879. + "! -----\;.signature_end\;j8 2\;! -----"
  23880. + [(set_attr "length" "2")]
  23881. +)
  23882. +
  23883. +;; Swap
  23884. +
  23885. +(define_insn "unspec_wsbh"
  23886. + [(set (match_operand:SI 0 "register_operand" "=r")
  23887. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_WSBH))]
  23888. + ""
  23889. + "wsbh\t%0, %1"
  23890. + [(set_attr "type" "alu")
  23891. + (set_attr "length" "4")]
  23892. +)
  23893. +
  23894. +;; TLBOP Intrinsic
  23895. +
  23896. +(define_insn "unspec_tlbop_trd"
  23897. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_TRD)]
  23898. + ""
  23899. + "tlbop\t%0, TRD"
  23900. + [(set_attr "type" "mmu")]
  23901. +)
  23902. +
  23903. +(define_insn "unspec_tlbop_twr"
  23904. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_TWR)]
  23905. + ""
  23906. + "tlbop\t%0, TWR"
  23907. + [(set_attr "type" "mmu")]
  23908. +)
  23909. +
  23910. +(define_insn "unspec_tlbop_rwr"
  23911. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_RWR)]
  23912. + ""
  23913. + "tlbop\t%0, RWR"
  23914. + [(set_attr "type" "mmu")]
  23915. +)
  23916. +
  23917. +(define_insn "unspec_tlbop_rwlk"
  23918. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_RWLK)]
  23919. + ""
  23920. + "tlbop\t%0, RWLK"
  23921. + [(set_attr "type" "mmu")]
  23922. +)
  23923. +
  23924. +(define_insn "unspec_tlbop_unlk"
  23925. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_UNLK)]
  23926. + ""
  23927. + "tlbop\t%0, UNLK"
  23928. + [(set_attr "type" "mmu")]
  23929. +)
  23930. +
  23931. +(define_insn "unspec_tlbop_pb"
  23932. + [(set (match_operand:SI 0 "register_operand" "=r")
  23933. + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_PB))]
  23934. + ""
  23935. + "tlbop\t%0, %1, PB"
  23936. + [(set_attr "type" "mmu")]
  23937. +)
  23938. +
  23939. +(define_insn "unspec_tlbop_inv"
  23940. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_TLBOP_INV)]
  23941. + ""
  23942. + "tlbop\t%0, INV"
  23943. + [(set_attr "type" "mmu")]
  23944. +)
  23945. +
  23946. +(define_insn "unspec_tlbop_flua"
  23947. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_TLBOP_FLUA)]
  23948. + ""
  23949. + "tlbop\tFLUA"
  23950. + [(set_attr "type" "mmu")]
  23951. +)
  23952. +
  23953. +;;Unaligned Load/Store
  23954. +
  23955. +(define_expand "unaligned_load_hw"
  23956. + [(set (match_operand:HI 0 "register_operand" "")
  23957. + (unspec:HI [(mem:HI (match_operand:SI 1 "register_operand" ""))] UNSPEC_UALOAD_HW))]
  23958. + ""
  23959. +{
  23960. + operands[0] = simplify_gen_subreg (SImode, operands[0],
  23961. + GET_MODE (operands[0]), 0);
  23962. + if (TARGET_ISA_V3M)
  23963. + {
  23964. + nds32_expand_unaligned_load (operands, HImode);
  23965. + }
  23966. + else
  23967. + {
  23968. + emit_insn (gen_unaligned_load_w (operands[0],
  23969. + gen_rtx_MEM (SImode, operands[1])));
  23970. +
  23971. + if (WORDS_BIG_ENDIAN)
  23972. + emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT(16)));
  23973. + else
  23974. + emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (0xffff)));
  23975. + }
  23976. +
  23977. + DONE;
  23978. +})
  23979. +
  23980. +(define_expand "unaligned_loadsi"
  23981. + [(set (match_operand:SI 0 "register_operand" "=r")
  23982. + (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))]
  23983. + ""
  23984. +{
  23985. + if (TARGET_ISA_V3M)
  23986. + nds32_expand_unaligned_load (operands, SImode);
  23987. + else
  23988. + emit_insn (gen_unaligned_load_w (operands[0],
  23989. + gen_rtx_MEM (SImode, (operands[1]))));
  23990. + DONE;
  23991. +})
  23992. +
  23993. +(define_insn "unaligned_load_w"
  23994. + [(set (match_operand:SI 0 "register_operand" "= r")
  23995. + (unspec:SI [(match_operand:SI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))]
  23996. + ""
  23997. +{
  23998. + return nds32_output_lmw_single_word (operands);
  23999. +}
  24000. + [(set_attr "type" "load")
  24001. + (set_attr "length" "4")]
  24002. +)
  24003. +
  24004. +(define_expand "unaligned_loaddi"
  24005. + [(set (match_operand:DI 0 "register_operand" "=r")
  24006. + (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
  24007. + ""
  24008. +{
  24009. + if (TARGET_ISA_V3M)
  24010. + {
  24011. + nds32_expand_unaligned_load (operands, DImode);
  24012. + }
  24013. + else
  24014. + emit_insn (gen_unaligned_load_dw (operands[0], operands[1]));
  24015. + DONE;
  24016. +})
  24017. +
  24018. +(define_insn "unaligned_load_dw"
  24019. + [(set (match_operand:DI 0 "register_operand" "=r")
  24020. + (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
  24021. + ""
  24022. +{
  24023. + rtx otherops[3];
  24024. + otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
  24025. + otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
  24026. + otherops[2] = operands[1];
  24027. +
  24028. + output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
  24029. + return "";
  24030. +}
  24031. + [(set_attr "type" "load")
  24032. + (set_attr "length" "4")]
  24033. +)
  24034. +
  24035. +(define_expand "unaligned_store_hw"
  24036. + [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
  24037. + (unspec:HI [(match_operand:HI 1 "register_operand" "")] UNSPEC_UASTORE_HW))]
  24038. + ""
  24039. +{
  24040. + operands[1] = simplify_gen_subreg (SImode, operands[1],
  24041. + GET_MODE (operands[1]), 0);
  24042. + nds32_expand_unaligned_store (operands, HImode);
  24043. + DONE;
  24044. +})
  24045. +
  24046. +(define_expand "unaligned_storesi"
  24047. + [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
  24048. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_UASTORE_W))]
  24049. + ""
  24050. +{
  24051. + if (TARGET_ISA_V3M)
  24052. + nds32_expand_unaligned_store (operands, SImode);
  24053. + else
  24054. + emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[0]),
  24055. + operands[1]));
  24056. + DONE;
  24057. +})
  24058. +
  24059. +(define_insn "unaligned_store_w"
  24060. + [(set (match_operand:SI 0 "nds32_lmw_smw_base_operand" "=Umw")
  24061. + (unspec:SI [(match_operand:SI 1 "register_operand" " r")] UNSPEC_UASTORE_W))]
  24062. + ""
  24063. +{
  24064. + return nds32_output_smw_single_word (operands);
  24065. +}
  24066. + [(set_attr "type" "store")
  24067. + (set_attr "length" "4")]
  24068. +)
  24069. +
  24070. +(define_expand "unaligned_storedi"
  24071. + [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
  24072. + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
  24073. + ""
  24074. +{
  24075. + if (TARGET_ISA_V3M)
  24076. + nds32_expand_unaligned_store (operands, DImode);
  24077. + else
  24078. + emit_insn (gen_unaligned_store_dw (operands[0], operands[1]));
  24079. + DONE;
  24080. +})
  24081. +
  24082. +(define_insn "unaligned_store_dw"
  24083. + [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
  24084. + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
  24085. + ""
  24086. +{
  24087. + rtx otherops[3];
  24088. + otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
  24089. + otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
  24090. + otherops[2] = operands[0];
  24091. +
  24092. + output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
  24093. + return "";
  24094. +}
  24095. + [(set_attr "type" "store")
  24096. + (set_attr "length" "4")]
  24097. +)
  24098. +
  24099. +(define_expand "unspec_unaligned_feature"
  24100. + [(set (match_operand:SI 0 "register_operand" "")
  24101. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_UNALIGNED_FEATURE))]
  24102. + ""
  24103. +{
  24104. + /* Get $MMU_CTL system register form nds32_intrinsic_register_names[] */
  24105. + rtx system_reg = GEN_INT (__NDS32_REG_MMU_CTL__);
  24106. + rtx temp_reg = gen_reg_rtx (SImode);
  24107. + rtx temp2_reg = gen_reg_rtx (SImode);
  24108. +
  24109. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  24110. + emit_move_insn (temp_reg, operands[0]);
  24111. + emit_move_insn (temp2_reg, GEN_INT (0x800 << 12));
  24112. + emit_insn (gen_iorsi3 (operands[0], operands[0], temp2_reg));
  24113. + emit_insn (gen_unspec_volatile_mtsr (operands[0], system_reg));
  24114. + emit_insn (gen_unspec_dsb ());
  24115. +
  24116. + emit_insn (gen_unspec_volatile_mfsr (operands[0], system_reg));
  24117. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  24118. + emit_insn (gen_unspec_dsb ());
  24119. +
  24120. + emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (8)));
  24121. + emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (31)));
  24122. + DONE;
  24123. +})
  24124. +
  24125. +(define_expand "unspec_enable_unaligned"
  24126. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_UNALIGNED_FEATURE)]
  24127. + ""
  24128. +{
  24129. + /* Get $MMU_CTL system register form nds32_intrinsic_register_names[] */
  24130. + rtx system_reg = GEN_INT (__NDS32_REG_MMU_CTL__);
  24131. + rtx temp_reg = gen_reg_rtx (SImode);
  24132. + rtx temp2_reg = gen_reg_rtx (SImode);
  24133. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  24134. + emit_move_insn (temp2_reg, GEN_INT (0x800 << 12));
  24135. + emit_insn (gen_iorsi3 (temp_reg, temp_reg, temp2_reg));
  24136. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  24137. + emit_insn (gen_unspec_dsb ());
  24138. + DONE;
  24139. +})
  24140. +
  24141. +(define_expand "unspec_disable_unaligned"
  24142. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_UNALIGNED_FEATURE)]
  24143. + ""
  24144. +{
  24145. + /* Get $MMU_CTL system register form nds32_intrinsic_register_names[] */
  24146. + rtx system_reg = GEN_INT (__NDS32_REG_MMU_CTL__);
  24147. + rtx temp_reg = gen_reg_rtx (SImode);
  24148. + rtx temp2_reg = gen_reg_rtx (SImode);
  24149. + emit_insn (gen_unspec_volatile_mfsr (temp_reg, system_reg));
  24150. + emit_move_insn (temp2_reg, GEN_INT (0x800 << 12));
  24151. + emit_insn (gen_one_cmplsi2 (temp2_reg, temp2_reg));
  24152. + emit_insn (gen_andsi3 (temp_reg, temp_reg, temp2_reg));
  24153. + emit_insn (gen_unspec_volatile_mtsr (temp_reg, system_reg));
  24154. + emit_insn (gen_unspec_dsb ());
  24155. + DONE;
  24156. +})
  24157. +
  24158. +;; abs alias kabs
  24159. +
  24160. +(define_insn "unspec_kabs"
  24161. + [(set (match_operand:SI 0 "register_operand" "=r")
  24162. + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_KABS))]
  24163. + ""
  24164. + "kabs\t%0, %1"
  24165. + [(set_attr "type" "alu")
  24166. + (set_attr "length" "4")]
  24167. +)
  24168. +
  24169. +(define_expand "no_hwloop"
  24170. + [(const_int 0)]
  24171. + ""
  24172. +{
  24173. + if (NDS32_HW_LOOP_P ())
  24174. + emit_insn (gen_unspec_no_hwloop ());
  24175. + else
  24176. + emit_insn (gen_nop ());
  24177. +
  24178. + DONE;
  24179. +})
  24180. +
  24181. +(define_insn "unspec_no_hwloop"
  24182. + [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_NO_HWLOOP)]
  24183. + ""
  24184. + ""
  24185. + [(set_attr "type" "misc")]
  24186. +)
  24187. ;; ------------------------------------------------------------------------
  24188. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-isr.c gcc-4.9.4/gcc/config/nds32/nds32-isr.c
  24189. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-isr.c 1970-01-01 01:00:00.000000000 +0100
  24190. +++ gcc-4.9.4/gcc/config/nds32/nds32-isr.c 2016-08-08 20:37:45.502269936 +0200
  24191. @@ -0,0 +1,972 @@
  24192. +/* Subroutines used for ISR of Andes NDS32 cpu for GNU compiler
  24193. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  24194. + Contributed by Andes Technology Corporation.
  24195. +
  24196. + This file is part of GCC.
  24197. +
  24198. + GCC is free software; you can redistribute it and/or modify it
  24199. + under the terms of the GNU General Public License as published
  24200. + by the Free Software Foundation; either version 3, or (at your
  24201. + option) any later version.
  24202. +
  24203. + GCC is distributed in the hope that it will be useful, but WITHOUT
  24204. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24205. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  24206. + License for more details.
  24207. +
  24208. + You should have received a copy of the GNU General Public License
  24209. + along with GCC; see the file COPYING3. If not see
  24210. + <http://www.gnu.org/licenses/>. */
  24211. +
  24212. +/* ------------------------------------------------------------------------ */
  24213. +
  24214. +#include "config.h"
  24215. +#include "system.h"
  24216. +#include "coretypes.h"
  24217. +#include "tm.h"
  24218. +#include "tree.h"
  24219. +#include "rtl.h"
  24220. +#include "regs.h"
  24221. +#include "hard-reg-set.h"
  24222. +#include "insn-config.h" /* Required by recog.h. */
  24223. +#include "conditions.h"
  24224. +#include "output.h"
  24225. +#include "insn-attr.h" /* For DFA state_t. */
  24226. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  24227. +#include "reload.h" /* For push_reload(). */
  24228. +#include "flags.h"
  24229. +#include "function.h"
  24230. +#include "expr.h"
  24231. +#include "recog.h"
  24232. +#include "diagnostic-core.h"
  24233. +#include "df.h"
  24234. +#include "tm_p.h"
  24235. +#include "tm-constrs.h"
  24236. +#include "optabs.h" /* For GEN_FCN. */
  24237. +#include "target.h"
  24238. +#include "target-def.h"
  24239. +#include "langhooks.h" /* For add_builtin_function(). */
  24240. +#include "ggc.h"
  24241. +
  24242. +/* ------------------------------------------------------------------------ */
  24243. +
  24244. +/* Refer to nds32.h, there are maximum 73 isr vectors in nds32 architecture.
  24245. + 0 for reset handler with __attribute__((reset())),
  24246. + 1-8 for exception handler with __attribute__((exception(1,...,8))),
  24247. + and 9-72 for interrupt handler with __attribute__((interrupt(0,...,63))).
  24248. + We use an array to record essential information for each vector. */
  24249. +static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS];
  24250. +
  24251. +/* ------------------------------------------------------------- */
  24252. +/* FIXME:
  24253. + FOR BACKWARD COMPATIBILITY, we need to support following patterns:
  24254. +
  24255. + __attribute__((interrupt("XXX;YYY;id=ZZZ")))
  24256. + __attribute__((exception("XXX;YYY;id=ZZZ")))
  24257. + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
  24258. +
  24259. + We provide several functions to parse the strings. */
  24260. +
  24261. +static void
  24262. +nds32_interrupt_attribute_parse_string (const char *original_str,
  24263. + const char *func_name)
  24264. +{
  24265. + char target_str[100];
  24266. + enum nds32_isr_save_reg save_reg;
  24267. + enum nds32_isr_nested_type nested_type;
  24268. +
  24269. + char *save_all_regs_str, *save_caller_regs_str;
  24270. + char *nested_str, *not_nested_str, *ready_nested_str, *critical_str;
  24271. + char *id_str, *value_str;
  24272. +
  24273. + /* Copy original string into a character array so that
  24274. + the string APIs can handle it. */
  24275. + strcpy (target_str, original_str);
  24276. +
  24277. + /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL
  24278. + 'save_caller_regs' : NDS32_PARTIAL_SAVE */
  24279. + save_all_regs_str = strstr (target_str, "save_all_regs");
  24280. + save_caller_regs_str = strstr (target_str, "save_caller_regs");
  24281. +
  24282. + /* Note that if no argument is found,
  24283. + use NDS32_PARTIAL_SAVE by default. */
  24284. + if (save_all_regs_str)
  24285. + save_reg = NDS32_SAVE_ALL;
  24286. + else if (save_caller_regs_str)
  24287. + save_reg = NDS32_PARTIAL_SAVE;
  24288. + else
  24289. + save_reg = NDS32_PARTIAL_SAVE;
  24290. +
  24291. + /* 2. Detect 'nested' : NDS32_NESTED
  24292. + 'not_nested' : NDS32_NOT_NESTED
  24293. + 'ready_nested' : NDS32_NESTED_READY
  24294. + 'critical' : NDS32_CRITICAL */
  24295. + nested_str = strstr (target_str, "nested");
  24296. + not_nested_str = strstr (target_str, "not_nested");
  24297. + ready_nested_str = strstr (target_str, "ready_nested");
  24298. + critical_str = strstr (target_str, "critical");
  24299. +
  24300. + /* Note that if no argument is found,
  24301. + use NDS32_NOT_NESTED by default.
  24302. + Also, since 'not_nested' and 'ready_nested' both contains
  24303. + 'nested' string, we check 'nested' with lowest priority. */
  24304. + if (not_nested_str)
  24305. + nested_type = NDS32_NOT_NESTED;
  24306. + else if (ready_nested_str)
  24307. + nested_type = NDS32_NESTED_READY;
  24308. + else if (nested_str)
  24309. + nested_type = NDS32_NESTED;
  24310. + else if (critical_str)
  24311. + nested_type = NDS32_CRITICAL;
  24312. + else
  24313. + nested_type = NDS32_NOT_NESTED;
  24314. +
  24315. + /* 3. Traverse each id value and set corresponding information. */
  24316. + id_str = strstr (target_str, "id=");
  24317. +
  24318. + /* If user forgets to assign 'id', issue an error message. */
  24319. + if (id_str == NULL)
  24320. + error ("require id argument in the string");
  24321. + /* Extract the value_str first. */
  24322. + id_str = strtok (id_str, "=");
  24323. + value_str = strtok (NULL, ";");
  24324. +
  24325. + /* Pick up the first id value token. */
  24326. + value_str = strtok (value_str, ",");
  24327. + while (value_str != NULL)
  24328. + {
  24329. + int i;
  24330. + i = atoi (value_str);
  24331. +
  24332. + /* For interrupt(0..63), the actual vector number is (9..72). */
  24333. + i = i + 9;
  24334. + if (i < 9 || i > 72)
  24335. + error ("invalid id value for interrupt attribute");
  24336. +
  24337. + /* Setup nds32_isr_vectors[] array. */
  24338. + nds32_isr_vectors[i].category = NDS32_ISR_INTERRUPT;
  24339. + strcpy (nds32_isr_vectors[i].func_name, func_name);
  24340. + nds32_isr_vectors[i].save_reg = save_reg;
  24341. + nds32_isr_vectors[i].nested_type = nested_type;
  24342. +
  24343. + /* Fetch next token. */
  24344. + value_str = strtok (NULL, ",");
  24345. + }
  24346. +
  24347. + return;
  24348. +}
  24349. +
  24350. +static void
  24351. +nds32_exception_attribute_parse_string (const char *original_str,
  24352. + const char *func_name)
  24353. +{
  24354. + char target_str[100];
  24355. + enum nds32_isr_save_reg save_reg;
  24356. + enum nds32_isr_nested_type nested_type;
  24357. +
  24358. + char *save_all_regs_str, *save_caller_regs_str;
  24359. + char *nested_str, *not_nested_str, *ready_nested_str, *critical_str;
  24360. + char *id_str, *value_str;
  24361. +
  24362. + /* Copy original string into a character array so that
  24363. + the string APIs can handle it. */
  24364. + strcpy (target_str, original_str);
  24365. +
  24366. + /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL
  24367. + 'save_caller_regs' : NDS32_PARTIAL_SAVE */
  24368. + save_all_regs_str = strstr (target_str, "save_all_regs");
  24369. + save_caller_regs_str = strstr (target_str, "save_caller_regs");
  24370. +
  24371. + /* Note that if no argument is found,
  24372. + use NDS32_PARTIAL_SAVE by default. */
  24373. + if (save_all_regs_str)
  24374. + save_reg = NDS32_SAVE_ALL;
  24375. + else if (save_caller_regs_str)
  24376. + save_reg = NDS32_PARTIAL_SAVE;
  24377. + else
  24378. + save_reg = NDS32_PARTIAL_SAVE;
  24379. +
  24380. + /* 2. Detect 'nested' : NDS32_NESTED
  24381. + 'not_nested' : NDS32_NOT_NESTED
  24382. + 'ready_nested' : NDS32_NESTED_READY
  24383. + 'critical' : NDS32_CRITICAL */
  24384. + nested_str = strstr (target_str, "nested");
  24385. + not_nested_str = strstr (target_str, "not_nested");
  24386. + ready_nested_str = strstr (target_str, "ready_nested");
  24387. + critical_str = strstr (target_str, "critical");
  24388. +
  24389. + /* Note that if no argument is found,
  24390. + use NDS32_NOT_NESTED by default.
  24391. + Also, since 'not_nested' and 'ready_nested' both contains
  24392. + 'nested' string, we check 'nested' with lowest priority. */
  24393. + if (not_nested_str)
  24394. + nested_type = NDS32_NOT_NESTED;
  24395. + else if (ready_nested_str)
  24396. + nested_type = NDS32_NESTED_READY;
  24397. + else if (nested_str)
  24398. + nested_type = NDS32_NESTED;
  24399. + else if (critical_str)
  24400. + nested_type = NDS32_CRITICAL;
  24401. + else
  24402. + nested_type = NDS32_NOT_NESTED;
  24403. +
  24404. + /* 3. Traverse each id value and set corresponding information. */
  24405. + id_str = strstr (target_str, "id=");
  24406. +
  24407. + /* If user forgets to assign 'id', issue an error message. */
  24408. + if (id_str == NULL)
  24409. + error ("require id argument in the string");
  24410. + /* Extract the value_str first. */
  24411. + id_str = strtok (id_str, "=");
  24412. + value_str = strtok (NULL, ";");
  24413. +
  24414. + /* Pick up the first id value token. */
  24415. + value_str = strtok (value_str, ",");
  24416. + while (value_str != NULL)
  24417. + {
  24418. + int i;
  24419. + i = atoi (value_str);
  24420. +
  24421. + /* For exception(1..8), the actual vector number is (1..8). */
  24422. + if (i < 1 || i > 8)
  24423. + error ("invalid id value for exception attribute");
  24424. +
  24425. + /* Setup nds32_isr_vectors[] array. */
  24426. + nds32_isr_vectors[i].category = NDS32_ISR_EXCEPTION;
  24427. + strcpy (nds32_isr_vectors[i].func_name, func_name);
  24428. + nds32_isr_vectors[i].save_reg = save_reg;
  24429. + nds32_isr_vectors[i].nested_type = nested_type;
  24430. +
  24431. + /* Fetch next token. */
  24432. + value_str = strtok (NULL, ",");
  24433. + }
  24434. +
  24435. + return;
  24436. +}
  24437. +
  24438. +static void
  24439. +nds32_reset_attribute_parse_string (const char *original_str,
  24440. + const char *func_name)
  24441. +{
  24442. + char target_str[100];
  24443. + char *vectors_str, *nmi_str, *warm_str, *value_str;
  24444. +
  24445. + /* Deal with reset attribute. Its vector number is always 0. */
  24446. + nds32_isr_vectors[0].category = NDS32_ISR_RESET;
  24447. +
  24448. +
  24449. + /* 1. Parse 'vectors=XXXX'. */
  24450. +
  24451. + /* Copy original string into a character array so that
  24452. + the string APIs can handle it. */
  24453. + strcpy (target_str, original_str);
  24454. + vectors_str = strstr (target_str, "vectors=");
  24455. + /* The total vectors = interrupt + exception numbers + reset.
  24456. + There are 8 exception and 1 reset in nds32 architecture.
  24457. + If user forgets to assign 'vectors', user default 16 interrupts. */
  24458. + if (vectors_str != NULL)
  24459. + {
  24460. + /* Extract the value_str. */
  24461. + vectors_str = strtok (vectors_str, "=");
  24462. + value_str = strtok (NULL, ";");
  24463. + nds32_isr_vectors[0].total_n_vectors = atoi (value_str) + 8 + 1;
  24464. + }
  24465. + else
  24466. + nds32_isr_vectors[0].total_n_vectors = 16 + 8 + 1;
  24467. + strcpy (nds32_isr_vectors[0].func_name, func_name);
  24468. +
  24469. +
  24470. + /* 2. Parse 'nmi_func=YYYY'. */
  24471. +
  24472. + /* Copy original string into a character array so that
  24473. + the string APIs can handle it. */
  24474. + strcpy (target_str, original_str);
  24475. + nmi_str = strstr (target_str, "nmi_func=");
  24476. + if (nmi_str != NULL)
  24477. + {
  24478. + /* Extract the value_str. */
  24479. + nmi_str = strtok (nmi_str, "=");
  24480. + value_str = strtok (NULL, ";");
  24481. + strcpy (nds32_isr_vectors[0].nmi_name, value_str);
  24482. + }
  24483. +
  24484. + /* 3. Parse 'warm_func=ZZZZ'. */
  24485. +
  24486. + /* Copy original string into a character array so that
  24487. + the string APIs can handle it. */
  24488. + strcpy (target_str, original_str);
  24489. + warm_str = strstr (target_str, "warm_func=");
  24490. + if (warm_str != NULL)
  24491. + {
  24492. + /* Extract the value_str. */
  24493. + warm_str = strtok (warm_str, "=");
  24494. + value_str = strtok (NULL, ";");
  24495. + strcpy (nds32_isr_vectors[0].warm_name, value_str);
  24496. + }
  24497. +
  24498. + return;
  24499. +}
  24500. +/* ------------------------------------------------------------- */
  24501. +
  24502. +/* A helper function to emit section head template. */
  24503. +static void
  24504. +nds32_emit_section_head_template (char section_name[],
  24505. + char symbol_name[],
  24506. + int align_value,
  24507. + bool object_p)
  24508. +{
  24509. + const char *flags_str;
  24510. + const char *type_str;
  24511. +
  24512. + flags_str = (object_p) ? "\"a\"" : "\"ax\"";
  24513. + type_str = (object_p) ? "@object" : "@function";
  24514. +
  24515. + fprintf (asm_out_file, "\t.section\t%s, %s\n", section_name, flags_str);
  24516. + fprintf (asm_out_file, "\t.align\t%d\n", align_value);
  24517. + fprintf (asm_out_file, "\t.global\t%s\n", symbol_name);
  24518. + fprintf (asm_out_file, "\t.type\t%s, %s\n", symbol_name, type_str);
  24519. + fprintf (asm_out_file, "%s:\n", symbol_name);
  24520. +}
  24521. +
  24522. +/* A helper function to emit section tail template. */
  24523. +static void
  24524. +nds32_emit_section_tail_template (char symbol_name[])
  24525. +{
  24526. + fprintf (asm_out_file, "\t.size\t%s, .-%s\n", symbol_name, symbol_name);
  24527. +}
  24528. +
  24529. +/* Function to emit isr jump table section. */
  24530. +static void
  24531. +nds32_emit_isr_jmptbl_section (int vector_id)
  24532. +{
  24533. + char section_name[100];
  24534. + char symbol_name[100];
  24535. +
  24536. + /* A critical isr does not need jump table section because
  24537. + its behavior is not performed by two-level handler. */
  24538. + if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL)
  24539. + {
  24540. + fprintf (asm_out_file, "\t! The vector %02d is a critical isr !\n",
  24541. + vector_id);
  24542. + return;
  24543. + }
  24544. +
  24545. + /* Prepare jmptbl section and symbol name. */
  24546. + snprintf (section_name, sizeof (section_name),
  24547. + ".nds32_jmptbl.%02d", vector_id);
  24548. + snprintf (symbol_name, sizeof (symbol_name),
  24549. + "_nds32_jmptbl_%02d", vector_id);
  24550. +
  24551. + nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  24552. + fprintf (asm_out_file, "\t.word\t%s\n",
  24553. + nds32_isr_vectors[vector_id].func_name);
  24554. + nds32_emit_section_tail_template (symbol_name);
  24555. +}
  24556. +
  24557. +/* Function to emit isr vector section. */
  24558. +static void
  24559. +nds32_emit_isr_vector_section (int vector_id)
  24560. +{
  24561. + unsigned int vector_number_offset = 0;
  24562. + const char *c_str = "CATEGORY";
  24563. + const char *sr_str = "SR";
  24564. + const char *nt_str = "NT";
  24565. + char first_level_handler_name[100];
  24566. + char section_name[100];
  24567. + char symbol_name[100];
  24568. +
  24569. + /* Set the vector number offset so that we can calculate
  24570. + the value that user specifies in the attribute.
  24571. + We also prepare the category string for first level handler name. */
  24572. + switch (nds32_isr_vectors[vector_id].category)
  24573. + {
  24574. + case NDS32_ISR_INTERRUPT:
  24575. + vector_number_offset = 9;
  24576. + c_str = "i";
  24577. + break;
  24578. + case NDS32_ISR_EXCEPTION:
  24579. + vector_number_offset = 0;
  24580. + c_str = "e";
  24581. + break;
  24582. + case NDS32_ISR_NONE:
  24583. + case NDS32_ISR_RESET:
  24584. + /* Normally it should not be here. */
  24585. + gcc_unreachable ();
  24586. + break;
  24587. + }
  24588. +
  24589. + /* Prepare save reg string for first level handler name. */
  24590. + switch (nds32_isr_vectors[vector_id].save_reg)
  24591. + {
  24592. + case NDS32_SAVE_ALL:
  24593. + sr_str = "sa";
  24594. + break;
  24595. + case NDS32_PARTIAL_SAVE:
  24596. + sr_str = "ps";
  24597. + break;
  24598. + }
  24599. +
  24600. + /* Prepare nested type string for first level handler name. */
  24601. + switch (nds32_isr_vectors[vector_id].nested_type)
  24602. + {
  24603. + case NDS32_NESTED:
  24604. + nt_str = "ns";
  24605. + break;
  24606. + case NDS32_NOT_NESTED:
  24607. + nt_str = "nn";
  24608. + break;
  24609. + case NDS32_NESTED_READY:
  24610. + nt_str = "nr";
  24611. + break;
  24612. + case NDS32_CRITICAL:
  24613. + /* The critical isr is not performed by two-level handler. */
  24614. + nt_str = "";
  24615. + break;
  24616. + }
  24617. +
  24618. + /* Now we can create first level handler name. */
  24619. + snprintf (first_level_handler_name, sizeof (first_level_handler_name),
  24620. + "_nds32_%s_%s_%s", c_str, sr_str, nt_str);
  24621. +
  24622. + /* Prepare vector section and symbol name. */
  24623. + snprintf (section_name, sizeof (section_name),
  24624. + ".nds32_vector.%02d", vector_id);
  24625. + snprintf (symbol_name, sizeof (symbol_name),
  24626. + "_nds32_vector_%02d", vector_id);
  24627. +
  24628. +
  24629. + /* Everything is ready. We can start emit vector section content. */
  24630. + nds32_emit_section_head_template (section_name, symbol_name,
  24631. + floor_log2 (nds32_isr_vector_size), false);
  24632. +
  24633. + /* First we check if it is a critical isr.
  24634. + If so, jump to user handler directly; otherwise, the instructions
  24635. + in the vector section may be different according to the vector size. */
  24636. + if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL)
  24637. + {
  24638. + /* This block is for critical isr. Jump to user handler directly. */
  24639. + fprintf (asm_out_file, "\tj\t%s ! jump to user handler directly\n",
  24640. + nds32_isr_vectors[vector_id].func_name);
  24641. + }
  24642. + else if (nds32_isr_vector_size == 4)
  24643. + {
  24644. + /* This block is for 4-byte vector size.
  24645. + Hardware $VID support is necessary and only one instruction
  24646. + is needed in vector section. */
  24647. + fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
  24648. + first_level_handler_name);
  24649. + }
  24650. + else
  24651. + {
  24652. + /* This block is for 16-byte vector size.
  24653. + There is NO hardware $VID so that we need several instructions
  24654. + such as pushing GPRs and preparing software vid at vector section.
  24655. + For pushing GPRs, there are four variations for
  24656. + 16-byte vector content and we have to handle each combination.
  24657. + For preparing software vid, note that the vid need to
  24658. + be substracted vector_number_offset. */
  24659. + if (TARGET_REDUCED_REGS)
  24660. + {
  24661. + if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
  24662. + {
  24663. + /* Case of reduced set registers and save_all attribute. */
  24664. + fprintf (asm_out_file, "\t! reduced set regs + save_all\n");
  24665. + fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0xf\n");
  24666. + fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r10, 0x0\n");
  24667. +
  24668. + }
  24669. + else
  24670. + {
  24671. + /* Case of reduced set registers and partial_save attribute. */
  24672. + fprintf (asm_out_file, "\t! reduced set regs + partial_save\n");
  24673. + fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0x2\n");
  24674. + fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
  24675. + }
  24676. + }
  24677. + else
  24678. + {
  24679. + if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
  24680. + {
  24681. + /* Case of full set registers and save_all attribute. */
  24682. + fprintf (asm_out_file, "\t! full set regs + save_all\n");
  24683. + fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r27, 0xf\n");
  24684. + }
  24685. + else
  24686. + {
  24687. + /* Case of full set registers and partial_save attribute. */
  24688. + fprintf (asm_out_file, "\t! full set regs + partial_save\n");
  24689. + fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r27, 0x2\n");
  24690. + fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
  24691. + }
  24692. + }
  24693. +
  24694. + fprintf (asm_out_file, "\tmovi\t$r0, %d ! preparing software vid\n",
  24695. + vector_id - vector_number_offset);
  24696. + fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
  24697. + first_level_handler_name);
  24698. + }
  24699. +
  24700. + nds32_emit_section_tail_template (symbol_name);
  24701. +}
  24702. +
  24703. +/* Function to emit isr reset handler content.
  24704. + Including all jmptbl/vector references, jmptbl section,
  24705. + vector section, nmi handler section, and warm handler section. */
  24706. +static void
  24707. +nds32_emit_isr_reset_content (void)
  24708. +{
  24709. + unsigned int i;
  24710. + unsigned int total_n_vectors;
  24711. + char reset_handler_name[100];
  24712. + char section_name[100];
  24713. + char symbol_name[100];
  24714. +
  24715. + total_n_vectors = nds32_isr_vectors[0].total_n_vectors;
  24716. +
  24717. + fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n");
  24718. +
  24719. + /* Create references in .rodata according to total number of vectors. */
  24720. + fprintf (asm_out_file, "\t.section\t.rodata\n");
  24721. + fprintf (asm_out_file, "\t.align\t2\n");
  24722. +
  24723. + /* Emit jmptbl references. */
  24724. + fprintf (asm_out_file, "\t ! references to jmptbl section entries\n");
  24725. + for (i = 0; i < total_n_vectors; i++)
  24726. + fprintf (asm_out_file, "\t.word\t_nds32_jmptbl_%02d\n", i);
  24727. +
  24728. + /* Emit vector references. */
  24729. + fprintf (asm_out_file, "\t ! references to vector section entries\n");
  24730. + for (i = 0; i < total_n_vectors; i++)
  24731. + fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d\n", i);
  24732. +
  24733. + /* Emit jmptbl_00 section. */
  24734. + snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00");
  24735. + snprintf (symbol_name, sizeof (symbol_name), "_nds32_jmptbl_00");
  24736. +
  24737. + fprintf (asm_out_file, "\t! ....................................\n");
  24738. + nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  24739. + fprintf (asm_out_file, "\t.word\t%s\n",
  24740. + nds32_isr_vectors[0].func_name);
  24741. + nds32_emit_section_tail_template (symbol_name);
  24742. +
  24743. + /* Emit vector_00 section. */
  24744. + snprintf (section_name, sizeof (section_name), ".nds32_vector.00");
  24745. + snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00");
  24746. + snprintf (reset_handler_name, sizeof (reset_handler_name),
  24747. + "_nds32_reset");
  24748. +
  24749. + fprintf (asm_out_file, "\t! ....................................\n");
  24750. + nds32_emit_section_head_template (section_name, symbol_name,
  24751. + floor_log2 (nds32_isr_vector_size), false);
  24752. + fprintf (asm_out_file, "\tj\t%s ! jump to reset handler\n",
  24753. + reset_handler_name);
  24754. + nds32_emit_section_tail_template (symbol_name);
  24755. +
  24756. + /* Emit nmi handler section. */
  24757. + snprintf (section_name, sizeof (section_name), ".nds32_nmih");
  24758. + snprintf (symbol_name, sizeof (symbol_name), "_nds32_nmih");
  24759. +
  24760. + fprintf (asm_out_file, "\t! ....................................\n");
  24761. + nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  24762. + fprintf (asm_out_file, "\t.word\t%s\n",
  24763. + (strlen (nds32_isr_vectors[0].nmi_name) == 0)
  24764. + ? "0"
  24765. + : nds32_isr_vectors[0].nmi_name);
  24766. + nds32_emit_section_tail_template (symbol_name);
  24767. +
  24768. + /* Emit warm handler section. */
  24769. + snprintf (section_name, sizeof (section_name), ".nds32_wrh");
  24770. + snprintf (symbol_name, sizeof (symbol_name), "_nds32_wrh");
  24771. +
  24772. + fprintf (asm_out_file, "\t! ....................................\n");
  24773. + nds32_emit_section_head_template (section_name, symbol_name, 2, true);
  24774. + fprintf (asm_out_file, "\t.word\t%s\n",
  24775. + (strlen (nds32_isr_vectors[0].warm_name) == 0)
  24776. + ? "0"
  24777. + : nds32_isr_vectors[0].warm_name);
  24778. + nds32_emit_section_tail_template (symbol_name);
  24779. +
  24780. + fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - END !\n");
  24781. +}
  24782. +
  24783. +/* Function for nds32_merge_decl_attributes() and nds32_insert_attributes()
  24784. + to check if there are any conflict isr-specific attributes being set.
  24785. + We need to check:
  24786. + 1. Only 'save_all' or 'partial_save' in the attributes.
  24787. + 2. Only 'nested', 'not_nested', or 'nested_ready' in the attributes.
  24788. + 3. Only 'interrupt', 'exception', or 'reset' in the attributes. */
  24789. +void
  24790. +nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
  24791. +{
  24792. + int save_all_p, partial_save_p;
  24793. + int nested_p, not_nested_p, nested_ready_p, critical_p;
  24794. + int intr_p, excp_p, reset_p;
  24795. +
  24796. + /* Initialize variables. */
  24797. + save_all_p = partial_save_p = 0;
  24798. + nested_p = not_nested_p = nested_ready_p = critical_p = 0;
  24799. + intr_p = excp_p = reset_p = 0;
  24800. +
  24801. + /* We must check at MOST one attribute to set save-reg. */
  24802. + if (lookup_attribute ("save_all", func_attrs))
  24803. + save_all_p = 1;
  24804. + if (lookup_attribute ("partial_save", func_attrs))
  24805. + partial_save_p = 1;
  24806. +
  24807. + if ((save_all_p + partial_save_p) > 1)
  24808. + error ("multiple save reg attributes to function %qD", func_decl);
  24809. +
  24810. + /* We must check at MOST one attribute to set nested-type. */
  24811. + if (lookup_attribute ("nested", func_attrs))
  24812. + nested_p = 1;
  24813. + if (lookup_attribute ("not_nested", func_attrs))
  24814. + not_nested_p = 1;
  24815. + if (lookup_attribute ("nested_ready", func_attrs))
  24816. + nested_ready_p = 1;
  24817. + if (lookup_attribute ("critical", func_attrs))
  24818. + critical_p = 1;
  24819. +
  24820. + if ((nested_p + not_nested_p + nested_ready_p + critical_p) > 1)
  24821. + error ("multiple nested types attributes to function %qD", func_decl);
  24822. +
  24823. + /* We must check at MOST one attribute to
  24824. + set interrupt/exception/reset. */
  24825. + if (lookup_attribute ("interrupt", func_attrs))
  24826. + intr_p = 1;
  24827. + if (lookup_attribute ("exception", func_attrs))
  24828. + excp_p = 1;
  24829. + if (lookup_attribute ("reset", func_attrs))
  24830. + reset_p = 1;
  24831. +
  24832. + if ((intr_p + excp_p + reset_p) > 1)
  24833. + error ("multiple interrupt attributes to function %qD", func_decl);
  24834. +
  24835. + /* Do not allow isr attributes under linux toolchain. */
  24836. + if (TARGET_LINUX_ABI && intr_p)
  24837. + error ("cannot use interrupt attributes to function %qD "
  24838. + "under linux toolchain", func_decl);
  24839. + if (TARGET_LINUX_ABI && excp_p)
  24840. + error ("cannot use exception attributes to function %qD "
  24841. + "under linux toolchain", func_decl);
  24842. + if (TARGET_LINUX_ABI && reset_p)
  24843. + error ("cannot use reset attributes to function %qD "
  24844. + "under linux toolchain", func_decl);
  24845. +}
  24846. +
  24847. +/* Function to construct isr vectors information array.
  24848. + We DO NOT HAVE TO check if the attributes are valid
  24849. + because those works are supposed to be done on
  24850. + nds32_merge_decl_attributes() and nds32_insert_attributes(). */
  24851. +void
  24852. +nds32_construct_isr_vectors_information (tree func_attrs,
  24853. + const char *func_name)
  24854. +{
  24855. + tree save_all, partial_save;
  24856. + tree nested, not_nested, nested_ready, critical;
  24857. + tree intr, excp, reset;
  24858. +
  24859. + save_all = lookup_attribute ("save_all", func_attrs);
  24860. + partial_save = lookup_attribute ("partial_save", func_attrs);
  24861. +
  24862. + nested = lookup_attribute ("nested", func_attrs);
  24863. + not_nested = lookup_attribute ("not_nested", func_attrs);
  24864. + nested_ready = lookup_attribute ("nested_ready", func_attrs);
  24865. + critical = lookup_attribute ("critical", func_attrs);
  24866. +
  24867. + intr = lookup_attribute ("interrupt", func_attrs);
  24868. + excp = lookup_attribute ("exception", func_attrs);
  24869. + reset = lookup_attribute ("reset", func_attrs);
  24870. +
  24871. + /* If there is no interrupt/exception/reset, we can return immediately. */
  24872. + if (!intr && !excp && !reset)
  24873. + return;
  24874. +
  24875. + /* ------------------------------------------------------------- */
  24876. + /* FIXME:
  24877. + FOR BACKWARD COMPATIBILITY, we need to support following patterns:
  24878. +
  24879. + __attribute__((interrupt("XXX;YYY;id=ZZZ")))
  24880. + __attribute__((exception("XXX;YYY;id=ZZZ")))
  24881. + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
  24882. +
  24883. + If interrupt/exception/reset appears and its argument is a
  24884. + STRING_CST, we will parse string with some auxiliary functions
  24885. + which set necessary isr information in the nds32_isr_vectors[] array.
  24886. + After that, we can return immediately to avoid new-syntax isr
  24887. + information construction. */
  24888. + if (intr != NULL_TREE
  24889. + && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST)
  24890. + {
  24891. + tree string_arg = TREE_VALUE (TREE_VALUE (intr));
  24892. + nds32_interrupt_attribute_parse_string (TREE_STRING_POINTER (string_arg),
  24893. + func_name);
  24894. + return;
  24895. + }
  24896. + if (excp != NULL_TREE
  24897. + && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST)
  24898. + {
  24899. + tree string_arg = TREE_VALUE (TREE_VALUE (excp));
  24900. + nds32_exception_attribute_parse_string (TREE_STRING_POINTER (string_arg),
  24901. + func_name);
  24902. + return;
  24903. + }
  24904. + if (reset != NULL_TREE
  24905. + && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST)
  24906. + {
  24907. + tree string_arg = TREE_VALUE (TREE_VALUE (reset));
  24908. + nds32_reset_attribute_parse_string (TREE_STRING_POINTER (string_arg),
  24909. + func_name);
  24910. + return;
  24911. + }
  24912. + /* ------------------------------------------------------------- */
  24913. +
  24914. + /* If we are here, either we have interrupt/exception,
  24915. + or reset attribute. */
  24916. + if (intr || excp)
  24917. + {
  24918. + tree id_list;
  24919. +
  24920. + /* Prepare id list so that we can traverse and set vector id. */
  24921. + id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp));
  24922. +
  24923. + while (id_list)
  24924. + {
  24925. + tree id;
  24926. + int vector_id;
  24927. + unsigned int vector_number_offset;
  24928. +
  24929. + /* The way to handle interrupt or exception is the same,
  24930. + we just need to take care of actual vector number.
  24931. + For interrupt(0..63), the actual vector number is (9..72).
  24932. + For exception(1..8), the actual vector number is (1..8). */
  24933. + vector_number_offset = (intr) ? (9) : (0);
  24934. +
  24935. + /* Pick up each vector id value. */
  24936. + id = TREE_VALUE (id_list);
  24937. + /* Add vector_number_offset to get actual vector number. */
  24938. + vector_id = TREE_INT_CST_LOW (id) + vector_number_offset;
  24939. +
  24940. + /* Enable corresponding vector and set function name. */
  24941. + nds32_isr_vectors[vector_id].category = (intr)
  24942. + ? (NDS32_ISR_INTERRUPT)
  24943. + : (NDS32_ISR_EXCEPTION);
  24944. + strcpy (nds32_isr_vectors[vector_id].func_name, func_name);
  24945. +
  24946. + /* Set register saving scheme. */
  24947. + if (save_all)
  24948. + nds32_isr_vectors[vector_id].save_reg = NDS32_SAVE_ALL;
  24949. + else if (partial_save)
  24950. + nds32_isr_vectors[vector_id].save_reg = NDS32_PARTIAL_SAVE;
  24951. +
  24952. + /* Set nested type. */
  24953. + if (nested)
  24954. + nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED;
  24955. + else if (not_nested)
  24956. + nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED;
  24957. + else if (nested_ready)
  24958. + nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY;
  24959. + else if (critical)
  24960. + nds32_isr_vectors[vector_id].nested_type = NDS32_CRITICAL;
  24961. +
  24962. + /* Advance to next id. */
  24963. + id_list = TREE_CHAIN (id_list);
  24964. + }
  24965. + }
  24966. + else
  24967. + {
  24968. + tree id_list;
  24969. + tree id;
  24970. + tree nmi, warm;
  24971. +
  24972. + /* Deal with reset attribute. Its vector number is always 0. */
  24973. + nds32_isr_vectors[0].category = NDS32_ISR_RESET;
  24974. +
  24975. + /* Prepare id_list and identify id value so that
  24976. + we can set total number of vectors. */
  24977. + id_list = TREE_VALUE (reset);
  24978. + id = TREE_VALUE (id_list);
  24979. +
  24980. + /* The total vectors = interrupt + exception numbers + reset.
  24981. + There are 8 exception and 1 reset in nds32 architecture. */
  24982. + nds32_isr_vectors[0].total_n_vectors = TREE_INT_CST_LOW (id) + 8 + 1;
  24983. + strcpy (nds32_isr_vectors[0].func_name, func_name);
  24984. +
  24985. + /* Retrieve nmi and warm function. */
  24986. + nmi = lookup_attribute ("nmi", func_attrs);
  24987. + warm = lookup_attribute ("warm", func_attrs);
  24988. +
  24989. + if (nmi != NULL_TREE)
  24990. + {
  24991. + tree nmi_func_list;
  24992. + tree nmi_func;
  24993. +
  24994. + nmi_func_list = TREE_VALUE (nmi);
  24995. + nmi_func = TREE_VALUE (nmi_func_list);
  24996. +
  24997. + /* Record nmi function name. */
  24998. + strcpy (nds32_isr_vectors[0].nmi_name,
  24999. + IDENTIFIER_POINTER (nmi_func));
  25000. + }
  25001. +
  25002. + if (warm != NULL_TREE)
  25003. + {
  25004. + tree warm_func_list;
  25005. + tree warm_func;
  25006. +
  25007. + warm_func_list = TREE_VALUE (warm);
  25008. + warm_func = TREE_VALUE (warm_func_list);
  25009. +
  25010. + /* Record warm function name. */
  25011. + strcpy (nds32_isr_vectors[0].warm_name,
  25012. + IDENTIFIER_POINTER (warm_func));
  25013. + }
  25014. + }
  25015. +}
  25016. +
  25017. +void
  25018. +nds32_asm_file_start_for_isr (void)
  25019. +{
  25020. + int i;
  25021. +
  25022. + /* Initialize isr vector information array before compiling functions. */
  25023. + for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
  25024. + {
  25025. + nds32_isr_vectors[i].category = NDS32_ISR_NONE;
  25026. + strcpy (nds32_isr_vectors[i].func_name, "");
  25027. + nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE;
  25028. + nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED;
  25029. + nds32_isr_vectors[i].total_n_vectors = 0;
  25030. + strcpy (nds32_isr_vectors[i].nmi_name, "");
  25031. + strcpy (nds32_isr_vectors[i].warm_name, "");
  25032. + }
  25033. +}
  25034. +
  25035. +void nds32_asm_file_end_for_isr (void)
  25036. +{
  25037. + int i;
  25038. +
  25039. + /* If all the vectors are NDS32_ISR_NONE, we can return immediately. */
  25040. + for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
  25041. + if (nds32_isr_vectors[i].category != NDS32_ISR_NONE)
  25042. + break;
  25043. +
  25044. + if (i == NDS32_N_ISR_VECTORS)
  25045. + return;
  25046. +
  25047. + /* At least one vector is NOT NDS32_ISR_NONE,
  25048. + we should output isr vector information. */
  25049. + fprintf (asm_out_file, "\t! ------------------------------------\n");
  25050. + fprintf (asm_out_file, "\t! The isr vector information:\n");
  25051. + fprintf (asm_out_file, "\t! ------------------------------------\n");
  25052. +
  25053. + /* Check reset handler first. Its vector number is always 0. */
  25054. + if (nds32_isr_vectors[0].category == NDS32_ISR_RESET)
  25055. + {
  25056. + nds32_emit_isr_reset_content ();
  25057. + fprintf (asm_out_file, "\t! ------------------------------------\n");
  25058. + }
  25059. +
  25060. + /* Check other vectors, starting from vector number 1. */
  25061. + for (i = 1; i < NDS32_N_ISR_VECTORS; i++)
  25062. + {
  25063. + if (nds32_isr_vectors[i].category == NDS32_ISR_INTERRUPT
  25064. + || nds32_isr_vectors[i].category == NDS32_ISR_EXCEPTION)
  25065. + {
  25066. + /* Found one vector which is interupt or exception.
  25067. + Output its jmptbl and vector section content. */
  25068. + fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i);
  25069. + fprintf (asm_out_file, "\t! ------------------------------------\n");
  25070. + nds32_emit_isr_jmptbl_section (i);
  25071. + fprintf (asm_out_file, "\t! ....................................\n");
  25072. + nds32_emit_isr_vector_section (i);
  25073. + fprintf (asm_out_file, "\t! ------------------------------------\n");
  25074. + }
  25075. + }
  25076. +}
  25077. +
  25078. +/* Return true if FUNC is a isr function. */
  25079. +bool
  25080. +nds32_isr_function_p (tree func)
  25081. +{
  25082. + tree t_intr;
  25083. + tree t_excp;
  25084. + tree t_reset;
  25085. +
  25086. + tree attrs;
  25087. +
  25088. + if (TREE_CODE (func) != FUNCTION_DECL)
  25089. + abort ();
  25090. +
  25091. + attrs = DECL_ATTRIBUTES (func);
  25092. +
  25093. + t_intr = lookup_attribute ("interrupt", attrs);
  25094. + t_excp = lookup_attribute ("exception", attrs);
  25095. + t_reset = lookup_attribute ("reset", attrs);
  25096. +
  25097. + return ((t_intr != NULL_TREE)
  25098. + || (t_excp != NULL_TREE)
  25099. + || (t_reset != NULL_TREE));
  25100. +}
  25101. +
  25102. +/* Return true if FUNC is a isr function with critical attribute. */
  25103. +bool
  25104. +nds32_isr_function_critical_p (tree func)
  25105. +{
  25106. + tree t_intr;
  25107. + tree t_excp;
  25108. + tree t_critical;
  25109. +
  25110. + tree attrs;
  25111. +
  25112. + if (TREE_CODE (func) != FUNCTION_DECL)
  25113. + abort ();
  25114. +
  25115. + attrs = DECL_ATTRIBUTES (func);
  25116. +
  25117. + t_intr = lookup_attribute ("interrupt", attrs);
  25118. + t_excp = lookup_attribute ("exception", attrs);
  25119. +
  25120. + t_critical = lookup_attribute ("critical", attrs);
  25121. +
  25122. + /* If both interrupt and exception attribute does not appear,
  25123. + we can return false immediately. */
  25124. + if ((t_intr == NULL_TREE) && (t_excp == NULL_TREE))
  25125. + return false;
  25126. +
  25127. + /* Here we can guarantee either interrupt or ecxception attribute
  25128. + does exist, so further check critical attribute.
  25129. + If it also appears, we can return true. */
  25130. + if (t_critical != NULL_TREE)
  25131. + return true;
  25132. +
  25133. + /* ------------------------------------------------------------- */
  25134. + /* FIXME:
  25135. + FOR BACKWARD COMPATIBILITY, we need to handle string type.
  25136. + If the string 'critical' appears in the interrupt/exception
  25137. + string argument, we can return true. */
  25138. + if (t_intr != NULL_TREE || t_excp != NULL_TREE)
  25139. + {
  25140. + char target_str[100];
  25141. + char *critical_str;
  25142. + tree t_check;
  25143. + tree string_arg;
  25144. +
  25145. + t_check = t_intr ? t_intr : t_excp;
  25146. + if (TREE_CODE (TREE_VALUE (TREE_VALUE (t_check))) == STRING_CST)
  25147. + {
  25148. + string_arg = TREE_VALUE (TREE_VALUE (t_check));
  25149. + strcpy (target_str, TREE_STRING_POINTER (string_arg));
  25150. + critical_str = strstr (target_str, "critical");
  25151. +
  25152. + /* Found 'critical' string, so return true. */
  25153. + if (critical_str)
  25154. + return true;
  25155. + }
  25156. + }
  25157. + /* ------------------------------------------------------------- */
  25158. +
  25159. + /* Other cases, this isr function is not critical type. */
  25160. + return false;
  25161. +}
  25162. +
  25163. +/* ------------------------------------------------------------- */
  25164. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32_isr.h gcc-4.9.4/gcc/config/nds32/nds32_isr.h
  25165. --- gcc-4.9.4.orig/gcc/config/nds32/nds32_isr.h 1970-01-01 01:00:00.000000000 +0100
  25166. +++ gcc-4.9.4/gcc/config/nds32/nds32_isr.h 2016-08-08 20:37:45.594273497 +0200
  25167. @@ -0,0 +1,526 @@
  25168. +/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
  25169. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  25170. + Contributed by Andes Technology Corporation.
  25171. +
  25172. + This file is part of GCC.
  25173. +
  25174. + GCC is free software; you can redistribute it and/or modify it
  25175. + under the terms of the GNU General Public License as published
  25176. + by the Free Software Foundation; either version 3, or (at your
  25177. + option) any later version.
  25178. +
  25179. + GCC is distributed in the hope that it will be useful, but WITHOUT
  25180. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  25181. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  25182. + License for more details.
  25183. +
  25184. + Under Section 7 of GPL version 3, you are granted additional
  25185. + permissions described in the GCC Runtime Library Exception, version
  25186. + 3.1, as published by the Free Software Foundation.
  25187. +
  25188. + You should have received a copy of the GNU General Public License and
  25189. + a copy of the GCC Runtime Library Exception along with this program;
  25190. + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  25191. + <http://www.gnu.org/licenses/>. */
  25192. +
  25193. +#ifndef _NDS32_ISR_H
  25194. +#define _NDS32_ISR_H
  25195. +
  25196. +/* Attribute of a interrupt or exception handler:
  25197. +
  25198. + NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit.
  25199. + NDS32_NESTED : This handler is interruptible. This is not suitable
  25200. + exception handler.
  25201. + NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do
  25202. + some work if nested is wanted
  25203. + NDS32_CRITICAL : This handler is critical ISR, which means it is small
  25204. + and efficient. */
  25205. +#define NDS32_READY_NESTED 0
  25206. +#define NDS32_NESTED 1
  25207. +#define NDS32_NOT_NESTED 2
  25208. +#define NDS32_CRITICAL 3
  25209. +
  25210. +/* Attribute of a interrupt or exception handler:
  25211. +
  25212. + NDS32_SAVE_ALL_REGS : Save all registers in a table.
  25213. + NDS32_SAVE_PARTIAL_REGS: Save partial registers. */
  25214. +#define NDS32_SAVE_CALLER_REGS 0
  25215. +#define NDS32_SAVE_ALL_REGS 1
  25216. +
  25217. +/* There are two version of Register table for interrupt and exception handler,
  25218. + one for 16-register CPU the other for 32-register CPU. These structures are
  25219. + used for context switching or system call handling. The address of this
  25220. + data can be get from the input argument of the handler functions.
  25221. +
  25222. + For system call handling, r0 to r5 are used to pass arguments. If more
  25223. + arguments are used they are put into the stack and its starting address is
  25224. + in sp. Return value of system call can be put into r0 and r1 upon exit from
  25225. + system call handler. System call ID is in a system register and it can be
  25226. + fetched via intrinsic function. For more information please read ABI and
  25227. + other related documents.
  25228. +
  25229. + For context switching, at least 2 values need to saved in kernel. One is
  25230. + IPC and the other is the stack address of current task. Use intrinsic
  25231. + function to get IPC and the input argument of the handler functions + 8 to
  25232. + get stack address of current task. To do context switching, you replace
  25233. + new_sp with the stack address of new task and replace IPC system register
  25234. + with IPC of new task, then, just return from handler. The context switching
  25235. + will happen. */
  25236. +
  25237. +/* Register table for exception handler; 32-register version. */
  25238. +typedef struct
  25239. +{
  25240. + int r0;
  25241. + int r1;
  25242. + int r2;
  25243. + int r3;
  25244. + int r4;
  25245. + int r5;
  25246. + int r6;
  25247. + int r7;
  25248. + int r8;
  25249. + int r9;
  25250. + int r10;
  25251. + int r11;
  25252. + int r12;
  25253. + int r13;
  25254. + int r14;
  25255. + int r15;
  25256. + int r16;
  25257. + int r17;
  25258. + int r18;
  25259. + int r19;
  25260. + int r20;
  25261. + int r21;
  25262. + int r22;
  25263. + int r23;
  25264. + int r24;
  25265. + int r25;
  25266. + int r26;
  25267. + int r27;
  25268. + int fp;
  25269. + int gp;
  25270. + int lp;
  25271. + int sp;
  25272. +} NDS32_GPR32;
  25273. +
  25274. +/* Register table for exception handler; 16-register version. */
  25275. +typedef struct
  25276. +{
  25277. + int r0;
  25278. + int r1;
  25279. + int r2;
  25280. + int r3;
  25281. + int r4;
  25282. + int r5;
  25283. + int r6;
  25284. + int r7;
  25285. + int r8;
  25286. + int r9;
  25287. + int r10;
  25288. + int r15;
  25289. + int fp;
  25290. + int gp;
  25291. + int lp;
  25292. + int sp;
  25293. +} NDS32_GPR16;
  25294. +
  25295. +
  25296. +/* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to
  25297. + access register table. */
  25298. +typedef struct
  25299. +{
  25300. + union
  25301. + {
  25302. + int reg_a[32] ;
  25303. + NDS32_GPR32 reg_s ;
  25304. + } u ;
  25305. +} NDS32_REG32_TAB;
  25306. +
  25307. +typedef struct
  25308. +{
  25309. + union
  25310. + {
  25311. + int reg_a[16] ;
  25312. + NDS32_GPR16 reg_s ;
  25313. + } u ;
  25314. +} NDS32_REG16_TAB;
  25315. +
  25316. +typedef struct
  25317. +{
  25318. + int d0lo;
  25319. + int d0hi;
  25320. + int d1lo;
  25321. + int d1hi;
  25322. +} NDS32_DX_TAB;
  25323. +
  25324. +typedef struct
  25325. +{
  25326. +#ifdef __NDS32_EB__
  25327. + float fsr0;
  25328. + float fsr1;
  25329. + float fsr2;
  25330. + float fsr3;
  25331. + float fsr4;
  25332. + float fsr5;
  25333. + float fsr6;
  25334. + float fsr7;
  25335. +#else
  25336. + float fsr1;
  25337. + float fsr0;
  25338. + float fsr3;
  25339. + float fsr2;
  25340. + float fsr5;
  25341. + float fsr4;
  25342. + float fsr7;
  25343. + float fsr6;
  25344. +#endif
  25345. +} NDS32_FSR8;
  25346. +
  25347. +typedef struct
  25348. +{
  25349. + double dsr0;
  25350. + double dsr1;
  25351. + double dsr2;
  25352. + double dsr3;
  25353. +} NDS32_DSR4;
  25354. +
  25355. +typedef struct
  25356. +{
  25357. +#ifdef __NDS32_EB__
  25358. + float fsr0;
  25359. + float fsr1;
  25360. + float fsr2;
  25361. + float fsr3;
  25362. + float fsr4;
  25363. + float fsr5;
  25364. + float fsr6;
  25365. + float fsr7;
  25366. + float fsr8;
  25367. + float fsr9;
  25368. + float fsr10;
  25369. + float fsr11;
  25370. + float fsr12;
  25371. + float fsr13;
  25372. + float fsr14;
  25373. + float fsr15;
  25374. +#else
  25375. + float fsr1;
  25376. + float fsr0;
  25377. + float fsr3;
  25378. + float fsr2;
  25379. + float fsr5;
  25380. + float fsr4;
  25381. + float fsr7;
  25382. + float fsr6;
  25383. + float fsr9;
  25384. + float fsr8;
  25385. + float fsr11;
  25386. + float fsr10;
  25387. + float fsr13;
  25388. + float fsr12;
  25389. + float fsr15;
  25390. + float fsr14;
  25391. +#endif
  25392. +} NDS32_FSR16;
  25393. +
  25394. +typedef struct
  25395. +{
  25396. + double dsr0;
  25397. + double dsr1;
  25398. + double dsr2;
  25399. + double dsr3;
  25400. + double dsr4;
  25401. + double dsr5;
  25402. + double dsr6;
  25403. + double dsr7;
  25404. +} NDS32_DSR8;
  25405. +
  25406. +typedef struct
  25407. +{
  25408. +#ifdef __NDS32_EB__
  25409. + float fsr0;
  25410. + float fsr1;
  25411. + float fsr2;
  25412. + float fsr3;
  25413. + float fsr4;
  25414. + float fsr5;
  25415. + float fsr6;
  25416. + float fsr7;
  25417. + float fsr8;
  25418. + float fsr9;
  25419. + float fsr10;
  25420. + float fsr11;
  25421. + float fsr12;
  25422. + float fsr13;
  25423. + float fsr14;
  25424. + float fsr15;
  25425. + float fsr16;
  25426. + float fsr17;
  25427. + float fsr18;
  25428. + float fsr19;
  25429. + float fsr20;
  25430. + float fsr21;
  25431. + float fsr22;
  25432. + float fsr23;
  25433. + float fsr24;
  25434. + float fsr25;
  25435. + float fsr26;
  25436. + float fsr27;
  25437. + float fsr28;
  25438. + float fsr29;
  25439. + float fsr30;
  25440. + float fsr31;
  25441. +#else
  25442. + float fsr1;
  25443. + float fsr0;
  25444. + float fsr3;
  25445. + float fsr2;
  25446. + float fsr5;
  25447. + float fsr4;
  25448. + float fsr7;
  25449. + float fsr6;
  25450. + float fsr9;
  25451. + float fsr8;
  25452. + float fsr11;
  25453. + float fsr10;
  25454. + float fsr13;
  25455. + float fsr12;
  25456. + float fsr15;
  25457. + float fsr14;
  25458. + float fsr17;
  25459. + float fsr16;
  25460. + float fsr19;
  25461. + float fsr18;
  25462. + float fsr21;
  25463. + float fsr20;
  25464. + float fsr23;
  25465. + float fsr22;
  25466. + float fsr25;
  25467. + float fsr24;
  25468. + float fsr27;
  25469. + float fsr26;
  25470. + float fsr29;
  25471. + float fsr28;
  25472. + float fsr31;
  25473. + float fsr30;
  25474. +#endif
  25475. +} NDS32_FSR32;
  25476. +
  25477. +typedef struct
  25478. +{
  25479. + double dsr0;
  25480. + double dsr1;
  25481. + double dsr2;
  25482. + double dsr3;
  25483. + double dsr4;
  25484. + double dsr5;
  25485. + double dsr6;
  25486. + double dsr7;
  25487. + double dsr8;
  25488. + double dsr9;
  25489. + double dsr10;
  25490. + double dsr11;
  25491. + double dsr12;
  25492. + double dsr13;
  25493. + double dsr14;
  25494. + double dsr15;
  25495. +} NDS32_DSR16;
  25496. +
  25497. +typedef struct
  25498. +{
  25499. + double dsr0;
  25500. + double dsr1;
  25501. + double dsr2;
  25502. + double dsr3;
  25503. + double dsr4;
  25504. + double dsr5;
  25505. + double dsr6;
  25506. + double dsr7;
  25507. + double dsr8;
  25508. + double dsr9;
  25509. + double dsr10;
  25510. + double dsr11;
  25511. + double dsr12;
  25512. + double dsr13;
  25513. + double dsr14;
  25514. + double dsr15;
  25515. + double dsr16;
  25516. + double dsr17;
  25517. + double dsr18;
  25518. + double dsr19;
  25519. + double dsr20;
  25520. + double dsr21;
  25521. + double dsr22;
  25522. + double dsr23;
  25523. + double dsr24;
  25524. + double dsr25;
  25525. + double dsr26;
  25526. + double dsr27;
  25527. + double dsr28;
  25528. + double dsr29;
  25529. + double dsr30;
  25530. + double dsr31;
  25531. +} NDS32_DSR32;
  25532. +
  25533. +typedef struct
  25534. +{
  25535. + union
  25536. + {
  25537. + NDS32_FSR8 fsr_s ;
  25538. + NDS32_DSR4 dsr_s ;
  25539. + } u ;
  25540. +} NDS32_FPU8_TAB;
  25541. +
  25542. +typedef struct
  25543. +{
  25544. + union
  25545. + {
  25546. + NDS32_FSR16 fsr_s ;
  25547. + NDS32_DSR8 dsr_s ;
  25548. + } u ;
  25549. +} NDS32_FPU16_TAB;
  25550. +
  25551. +typedef struct
  25552. +{
  25553. + union
  25554. + {
  25555. + NDS32_FSR32 fsr_s ;
  25556. + NDS32_DSR16 dsr_s ;
  25557. + } u ;
  25558. +} NDS32_FPU32_TAB;
  25559. +
  25560. +typedef struct
  25561. +{
  25562. + union
  25563. + {
  25564. + NDS32_FSR32 fsr_s ;
  25565. + NDS32_DSR32 dsr_s ;
  25566. + } u ;
  25567. +} NDS32_FPU64_TAB;
  25568. +
  25569. +typedef struct
  25570. +{
  25571. + int ipc;
  25572. + int ipsw;
  25573. +#if defined(NDS32_EXT_FPU_CONFIG_0)
  25574. + NDS32_FPU8_TAB fpr;
  25575. +#elif defined(NDS32_EXT_FPU_CONFIG_1)
  25576. + NDS32_FPU16_TAB fpr;
  25577. +#elif defined(NDS32_EXT_FPU_CONFIG_2)
  25578. + NDS32_FPU32_TAB fpr;
  25579. +#elif defined(NDS32_EXT_FPU_CONFIG_3)
  25580. + NDS32_FPU64_TAB fpr;
  25581. +#endif
  25582. +#if __NDS32_DX_REGS__
  25583. + NDS32_DX_TAB dxr;
  25584. +#endif
  25585. +#if __NDS32_EXT_IFC__
  25586. + int ifc_lp;
  25587. + int filler;
  25588. +#endif
  25589. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  25590. + NDS32_REG16_TAB gpr;
  25591. +#else
  25592. + NDS32_REG32_TAB gpr;
  25593. +#endif
  25594. +} NDS32_CONTEXT;
  25595. +
  25596. +/* Predefined Vector Definition.
  25597. +
  25598. + For IVIC Mode: 9 to 14 are for hardware interrupt
  25599. + and 15 is for software interrupt.
  25600. + For EVIC Mode: 9 to 72 are for hardware interrupt
  25601. + and software interrupt can be routed to any one of them.
  25602. +
  25603. + You may want to define your hardware interrupts in the following way
  25604. + for easy maintainance.
  25605. +
  25606. + IVIC mode:
  25607. + #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1
  25608. + #define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3
  25609. + EVIC mode:
  25610. + #define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2
  25611. + #define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */
  25612. +#define NDS32_VECTOR_RESET 0
  25613. +#define NDS32_VECTOR_TLB_FILL 1
  25614. +#define NDS32_VECTOR_PTE_NOT_PRESENT 2
  25615. +#define NDS32_VECTOR_TLB_MISC 3
  25616. +#define NDS32_VECTOR_TLB_VLPT_MISS 4
  25617. +#define NDS32_VECTOR_MACHINE_ERROR 5
  25618. +#define NDS32_VECTOR_DEBUG_RELATED 6
  25619. +#define NDS32_VECTOR_GENERAL_EXCEPTION 7
  25620. +#define NDS32_VECTOR_SYSCALL 8
  25621. +#define NDS32_VECTOR_INTERRUPT_HW0 9
  25622. +#define NDS32_VECTOR_INTERRUPT_HW1 10
  25623. +#define NDS32_VECTOR_INTERRUPT_HW2 11
  25624. +#define NDS32_VECTOR_INTERRUPT_HW3 12
  25625. +#define NDS32_VECTOR_INTERRUPT_HW4 13
  25626. +#define NDS32_VECTOR_INTERRUPT_HW5 14
  25627. +#define NDS32_VECTOR_INTERRUPT_HW6 15
  25628. +#define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */
  25629. +#define NDS32_VECTOR_INTERRUPT_HW7 16
  25630. +#define NDS32_VECTOR_INTERRUPT_HW8 17
  25631. +#define NDS32_VECTOR_INTERRUPT_HW9 18
  25632. +#define NDS32_VECTOR_INTERRUPT_HW10 19
  25633. +#define NDS32_VECTOR_INTERRUPT_HW11 20
  25634. +#define NDS32_VECTOR_INTERRUPT_HW12 21
  25635. +#define NDS32_VECTOR_INTERRUPT_HW13 22
  25636. +#define NDS32_VECTOR_INTERRUPT_HW14 23
  25637. +#define NDS32_VECTOR_INTERRUPT_HW15 24
  25638. +#define NDS32_VECTOR_INTERRUPT_HW16 25
  25639. +#define NDS32_VECTOR_INTERRUPT_HW17 26
  25640. +#define NDS32_VECTOR_INTERRUPT_HW18 27
  25641. +#define NDS32_VECTOR_INTERRUPT_HW19 28
  25642. +#define NDS32_VECTOR_INTERRUPT_HW20 29
  25643. +#define NDS32_VECTOR_INTERRUPT_HW21 30
  25644. +#define NDS32_VECTOR_INTERRUPT_HW22 31
  25645. +#define NDS32_VECTOR_INTERRUPT_HW23 32
  25646. +#define NDS32_VECTOR_INTERRUPT_HW24 33
  25647. +#define NDS32_VECTOR_INTERRUPT_HW25 34
  25648. +#define NDS32_VECTOR_INTERRUPT_HW26 35
  25649. +#define NDS32_VECTOR_INTERRUPT_HW27 36
  25650. +#define NDS32_VECTOR_INTERRUPT_HW28 37
  25651. +#define NDS32_VECTOR_INTERRUPT_HW29 38
  25652. +#define NDS32_VECTOR_INTERRUPT_HW30 39
  25653. +#define NDS32_VECTOR_INTERRUPT_HW31 40
  25654. +#define NDS32_VECTOR_INTERRUPT_HW32 41
  25655. +#define NDS32_VECTOR_INTERRUPT_HW33 42
  25656. +#define NDS32_VECTOR_INTERRUPT_HW34 43
  25657. +#define NDS32_VECTOR_INTERRUPT_HW35 44
  25658. +#define NDS32_VECTOR_INTERRUPT_HW36 45
  25659. +#define NDS32_VECTOR_INTERRUPT_HW37 46
  25660. +#define NDS32_VECTOR_INTERRUPT_HW38 47
  25661. +#define NDS32_VECTOR_INTERRUPT_HW39 48
  25662. +#define NDS32_VECTOR_INTERRUPT_HW40 49
  25663. +#define NDS32_VECTOR_INTERRUPT_HW41 50
  25664. +#define NDS32_VECTOR_INTERRUPT_HW42 51
  25665. +#define NDS32_VECTOR_INTERRUPT_HW43 52
  25666. +#define NDS32_VECTOR_INTERRUPT_HW44 53
  25667. +#define NDS32_VECTOR_INTERRUPT_HW45 54
  25668. +#define NDS32_VECTOR_INTERRUPT_HW46 55
  25669. +#define NDS32_VECTOR_INTERRUPT_HW47 56
  25670. +#define NDS32_VECTOR_INTERRUPT_HW48 57
  25671. +#define NDS32_VECTOR_INTERRUPT_HW49 58
  25672. +#define NDS32_VECTOR_INTERRUPT_HW50 59
  25673. +#define NDS32_VECTOR_INTERRUPT_HW51 60
  25674. +#define NDS32_VECTOR_INTERRUPT_HW52 61
  25675. +#define NDS32_VECTOR_INTERRUPT_HW53 62
  25676. +#define NDS32_VECTOR_INTERRUPT_HW54 63
  25677. +#define NDS32_VECTOR_INTERRUPT_HW55 64
  25678. +#define NDS32_VECTOR_INTERRUPT_HW56 65
  25679. +#define NDS32_VECTOR_INTERRUPT_HW57 66
  25680. +#define NDS32_VECTOR_INTERRUPT_HW58 67
  25681. +#define NDS32_VECTOR_INTERRUPT_HW59 68
  25682. +#define NDS32_VECTOR_INTERRUPT_HW60 69
  25683. +#define NDS32_VECTOR_INTERRUPT_HW61 70
  25684. +#define NDS32_VECTOR_INTERRUPT_HW62 71
  25685. +#define NDS32_VECTOR_INTERRUPT_HW63 72
  25686. +
  25687. +#define NDS32ATTR_RESET(option) __attribute__((reset(option)))
  25688. +#define NDS32ATTR_EXCEPT(type) __attribute__((exception(type)))
  25689. +#define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type)))
  25690. +#define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type)))
  25691. +#define NDS32ATTR_ISR(type) __attribute__((interrupt(type)))
  25692. +
  25693. +#endif /* nds32_isr.h */
  25694. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-linux.opt gcc-4.9.4/gcc/config/nds32/nds32-linux.opt
  25695. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-linux.opt 1970-01-01 01:00:00.000000000 +0100
  25696. +++ gcc-4.9.4/gcc/config/nds32/nds32-linux.opt 2016-08-08 20:37:45.506270091 +0200
  25697. @@ -0,0 +1,16 @@
  25698. +mcmodel=
  25699. +Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE)
  25700. +Specify the address generation strategy for code model.
  25701. +
  25702. +Enum
  25703. +Name(nds32_cmodel_type) Type(enum nds32_cmodel_type)
  25704. +Known cmodel types (for use with the -mcmodel= option):
  25705. +
  25706. +EnumValue
  25707. +Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL)
  25708. +
  25709. +EnumValue
  25710. +Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM)
  25711. +
  25712. +EnumValue
  25713. +Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE)
  25714. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-load-store-opt.c gcc-4.9.4/gcc/config/nds32/nds32-load-store-opt.c
  25715. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-load-store-opt.c 1970-01-01 01:00:00.000000000 +0100
  25716. +++ gcc-4.9.4/gcc/config/nds32/nds32-load-store-opt.c 2016-08-08 20:37:45.506270091 +0200
  25717. @@ -0,0 +1,820 @@
  25718. +/* load-store-opt pass of Andes NDS32 cpu for GNU compiler
  25719. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  25720. + Contributed by Andes Technology Corporation.
  25721. +
  25722. + This file is part of GCC.
  25723. +
  25724. + GCC is free software; you can redistribute it and/or modify it
  25725. + under the terms of the GNU General Public License as published
  25726. + by the Free Software Foundation; either version 3, or (at your
  25727. + option) any later version.
  25728. +
  25729. + GCC is distributed in the hope that it will be useful, but WITHOUT
  25730. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  25731. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  25732. + License for more details.
  25733. +
  25734. + You should have received a copy of the GNU General Public License
  25735. + along with GCC; see the file COPYING3. If not see
  25736. + <http://www.gnu.org/licenses/>. */
  25737. +
  25738. +
  25739. +#include "config.h"
  25740. +#include "system.h"
  25741. +#include "coretypes.h"
  25742. +#include "tm.h"
  25743. +#include "tree.h"
  25744. +#include "rtl.h"
  25745. +#include "regs.h"
  25746. +#include "hard-reg-set.h"
  25747. +#include "insn-config.h" /* Required by recog.h. */
  25748. +#include "conditions.h"
  25749. +#include "output.h"
  25750. +#include "insn-attr.h" /* For DFA state_t. */
  25751. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  25752. +#include "reload.h" /* For push_reload (). */
  25753. +#include "flags.h"
  25754. +#include "function.h"
  25755. +#include "expr.h"
  25756. +#include "recog.h"
  25757. +#include "diagnostic-core.h"
  25758. +#include "df.h"
  25759. +#include "tm_p.h"
  25760. +#include "tm-constrs.h"
  25761. +#include "target.h"
  25762. +#include "target-def.h"
  25763. +#include "langhooks.h" /* For add_builtin_function (). */
  25764. +#include "ggc.h"
  25765. +#include "tree-pass.h"
  25766. +#include "target-globals.h"
  25767. +#include "ira-int.h"
  25768. +#include "nds32-load-store-opt.h"
  25769. +#include <set>
  25770. +
  25771. +#define NDS32_GPR_NUM 32
  25772. +
  25773. +static new_base_reg_info_t gen_new_base (rtx,
  25774. + offset_info_t,
  25775. + unsigned,
  25776. + HOST_WIDE_INT,
  25777. + HOST_WIDE_INT);
  25778. +
  25779. +static bool debug_live_reg = false;
  25780. +
  25781. +static const load_store_optimize_pass *load_store_optimizes[] =
  25782. +{
  25783. + /* allow_regclass, new_base_regclass,
  25784. + offset_lower_bound, offset_upper_bound,
  25785. + load_only_p, name */
  25786. + new load_store_optimize_pass (
  25787. + LOW_REGS, LOW_REGS,
  25788. + 0, (32-4),
  25789. + false, "lswi333"),
  25790. + new load_store_optimize_pass (
  25791. + LOW_REGS, FRAME_POINTER_REG,
  25792. + 0, (512-4),
  25793. + false, "lswi37"),
  25794. + new load_store_optimize_pass (
  25795. + MIDDLE_REGS, GENERAL_REGS,
  25796. + 0, 0,
  25797. + false, "lswi450"),
  25798. + new load_store_optimize_pass (
  25799. + MIDDLE_REGS, R8_REG,
  25800. + -128, -4,
  25801. + true, "lwi45fe")
  25802. +};
  25803. +
  25804. +static const int N_LOAD_STORE_OPT_TYPE = sizeof (load_store_optimizes)
  25805. + / sizeof (load_store_optimize_pass*);
  25806. +
  25807. +load_store_optimize_pass
  25808. +::load_store_optimize_pass (enum reg_class allow_regclass,
  25809. + enum reg_class new_base_regclass,
  25810. + HOST_WIDE_INT offset_lower_bound,
  25811. + HOST_WIDE_INT offset_upper_bound,
  25812. + bool load_only_p,
  25813. + const char *name)
  25814. + : m_allow_regclass (allow_regclass),
  25815. + m_new_base_regclass (new_base_regclass),
  25816. + m_offset_lower_bound (offset_lower_bound),
  25817. + m_offset_upper_bound (offset_upper_bound),
  25818. + m_load_only_p (load_only_p),
  25819. + m_name (name)
  25820. +{
  25821. + gcc_assert (offset_lower_bound <= offset_upper_bound);
  25822. +}
  25823. +
  25824. +int
  25825. +load_store_optimize_pass::calc_gain (HARD_REG_SET *available_regset,
  25826. + offset_info_t offset_info,
  25827. + load_store_infos_t *load_store_info) const
  25828. +{
  25829. + int extra_cost = 0;
  25830. + int gain = 0;
  25831. + unsigned i;
  25832. + unsigned chain_size;
  25833. + unsigned new_base_regnum;
  25834. + HOST_WIDE_INT allow_range = m_offset_upper_bound - m_offset_lower_bound;
  25835. + new_base_regnum = find_available_reg (available_regset, m_new_base_regclass);
  25836. + chain_size = load_store_info->length ();
  25837. +
  25838. + if (new_base_regnum == INVALID_REGNUM)
  25839. + {
  25840. + if (dump_file)
  25841. + fprintf (dump_file,
  25842. + "%s have no avariable register, so give up try %s\n",
  25843. + reg_class_names[m_new_base_regclass],
  25844. + m_name);
  25845. + return 0;
  25846. + }
  25847. + else if (dump_file)
  25848. + fprintf (dump_file,
  25849. + "%s is avariable, get %s, try %s, chain size = %u\n",
  25850. + reg_class_names[m_new_base_regclass],
  25851. + reg_names[new_base_regnum],
  25852. + m_name,
  25853. + chain_size);
  25854. +
  25855. + HOST_WIDE_INT range = offset_info.max_offset - offset_info.min_offset;
  25856. +
  25857. + if (range > allow_range)
  25858. + {
  25859. + /* TODO: We can perform load-store opt for only part of load store. */
  25860. + if (dump_file)
  25861. + fprintf (dump_file,
  25862. + "range is too large for %s"
  25863. + " (range = " HOST_WIDE_INT_PRINT_DEC ", "
  25864. + "allow_range = " HOST_WIDE_INT_PRINT_DEC ")\n",
  25865. + m_name, range, allow_range);
  25866. + return 0;
  25867. + }
  25868. +
  25869. + if (offset_info.min_offset >= m_offset_lower_bound
  25870. + && offset_info.max_offset <= m_offset_upper_bound)
  25871. + {
  25872. + /* mov55. */
  25873. + extra_cost = 2;
  25874. + }
  25875. + else
  25876. + {
  25877. + if (satisfies_constraint_Is15 (GEN_INT (offset_info.min_offset
  25878. + - m_offset_lower_bound)))
  25879. + {
  25880. + /* add. */
  25881. + extra_cost = 4;
  25882. + }
  25883. + else
  25884. + {
  25885. + /* TODO: Try m_offset_upper_bound instead of m_offset_lower_bound
  25886. + again. */
  25887. + /* add45 + movi. */
  25888. + if (satisfies_constraint_Is20 (GEN_INT (offset_info.min_offset
  25889. + - m_offset_lower_bound)))
  25890. + extra_cost = 6;
  25891. + else
  25892. + return -1; /* Give up if this constant is too large. */
  25893. + }
  25894. + }
  25895. +
  25896. + for (i = 0; i < chain_size; ++i)
  25897. + {
  25898. + if (m_load_only_p && !(*load_store_info)[i].load_p)
  25899. + continue;
  25900. +
  25901. + if (in_reg_class_p ((*load_store_info)[i].reg, m_allow_regclass))
  25902. + gain += 2;
  25903. + }
  25904. +
  25905. + if (dump_file)
  25906. + fprintf (dump_file,
  25907. + "%s: gain = %d extra_cost = %d\n",
  25908. + m_name, gain, extra_cost);
  25909. +
  25910. + return gain - extra_cost;
  25911. +}
  25912. +
  25913. +
  25914. +void
  25915. +load_store_optimize_pass::do_optimize (
  25916. + HARD_REG_SET *available_regset,
  25917. + offset_info_t offset_info,
  25918. + load_store_infos_t *load_store_info) const
  25919. +{
  25920. + new_base_reg_info_t new_base_reg_info;
  25921. + rtx load_store_insn;
  25922. + unsigned new_base_regnum;
  25923. +
  25924. + new_base_regnum = find_available_reg (available_regset, m_new_base_regclass);
  25925. + gcc_assert (new_base_regnum != INVALID_REGNUM);
  25926. +
  25927. + new_base_reg_info =
  25928. + gen_new_base ((*load_store_info)[0].base_reg,
  25929. + offset_info,
  25930. + new_base_regnum,
  25931. + m_offset_lower_bound, m_offset_upper_bound);
  25932. + unsigned i;
  25933. + rtx insn;
  25934. + insn = emit_insn_before (new_base_reg_info.set_insns[0],
  25935. + (*load_store_info)[0].insn);
  25936. + if (new_base_reg_info.n_set_insns > 1)
  25937. + {
  25938. + gcc_assert (new_base_reg_info.n_set_insns == 2);
  25939. + emit_insn_before (new_base_reg_info.set_insns[1], insn);
  25940. + }
  25941. +
  25942. + for (i = 0; i < load_store_info->length (); ++i)
  25943. + {
  25944. + if (m_load_only_p && !(*load_store_info)[i].load_p)
  25945. + continue;
  25946. +
  25947. + if (!in_reg_class_p ((*load_store_info)[i].reg, m_allow_regclass))
  25948. + continue;
  25949. +
  25950. + HOST_WIDE_INT offset = (*load_store_info)[i].offset;
  25951. +
  25952. + if (new_base_reg_info.need_adjust_offset_p)
  25953. + offset = offset + new_base_reg_info.adjust_offset;
  25954. +
  25955. + load_store_insn =
  25956. + gen_reg_plus_imm_load_store ((*load_store_info)[i].reg,
  25957. + new_base_reg_info.reg,
  25958. + offset,
  25959. + (*load_store_info)[i].load_p,
  25960. + (*load_store_info)[i].mem);
  25961. +
  25962. + emit_insn_before (load_store_insn, (*load_store_info)[i].insn);
  25963. +
  25964. + delete_insn ((*load_store_info)[i].insn);
  25965. + }
  25966. +
  25967. + /* Recompute it CFG, to update BB_END() instruction. */
  25968. + compute_bb_for_insn ();
  25969. +}
  25970. +
  25971. +static new_base_reg_info_t
  25972. +gen_new_base (rtx original_base_reg,
  25973. + offset_info_t offset_info,
  25974. + unsigned new_base_regno,
  25975. + HOST_WIDE_INT offset_lower,
  25976. + HOST_WIDE_INT offset_upper)
  25977. +{
  25978. + new_base_reg_info_t new_base_reg_info;
  25979. +
  25980. + new_base_reg_info.reg = gen_rtx_REG (Pmode, new_base_regno);
  25981. +
  25982. + /* Setup register info. */
  25983. + ORIGINAL_REGNO (new_base_reg_info.reg) = ORIGINAL_REGNO (original_base_reg);
  25984. + REG_ATTRS (new_base_reg_info.reg) = REG_ATTRS (original_base_reg);
  25985. +
  25986. + if (offset_info.max_offset <= offset_upper
  25987. + && offset_info.min_offset >= offset_lower)
  25988. + {
  25989. + new_base_reg_info.set_insns[0] = gen_movsi (new_base_reg_info.reg,
  25990. + original_base_reg);
  25991. + new_base_reg_info.n_set_insns = 1;
  25992. + new_base_reg_info.need_adjust_offset_p = false;
  25993. + new_base_reg_info.adjust_offset = 0;
  25994. + }
  25995. + else
  25996. + {
  25997. + /* For example:
  25998. + lwi45.fe allow -4 ~ -128 range:
  25999. + offset_lower = #-4
  26000. + offset_upper = #-128
  26001. +
  26002. + lwi $r2, [$r12 + #10]
  26003. + ->
  26004. + addi $r8, $r12, #14 ! $r8 = $r12 + #10 - offset_lower
  26005. + ! = $r12 + #10 - #-4
  26006. + ! = $r12 + #14
  26007. + lwi45.fe $r2, [$r8 - #4] ! [$r8 - #4]
  26008. + ! = [$r12 + #14 - #4]
  26009. + ! = [$r12 + #10]
  26010. + */
  26011. + new_base_reg_info.adjust_offset =
  26012. + -(offset_info.min_offset - offset_lower);
  26013. +
  26014. + rtx offset = GEN_INT (-new_base_reg_info.adjust_offset);
  26015. +
  26016. +
  26017. + if (satisfies_constraint_Is15 (offset))
  26018. + {
  26019. + new_base_reg_info.set_insns[0] =
  26020. + gen_addsi3(new_base_reg_info.reg,
  26021. + original_base_reg,
  26022. + offset);
  26023. +
  26024. + new_base_reg_info.n_set_insns = 1;
  26025. + }
  26026. + else
  26027. + {
  26028. + if (!satisfies_constraint_Is20 (offset))
  26029. + gcc_unreachable ();
  26030. +
  26031. + new_base_reg_info.set_insns[1] =
  26032. + gen_rtx_SET (VOIDmode,
  26033. + new_base_reg_info.reg,
  26034. + GEN_INT (-new_base_reg_info.adjust_offset));
  26035. +
  26036. + new_base_reg_info.set_insns[0] =
  26037. + gen_addsi3 (new_base_reg_info.reg,
  26038. + new_base_reg_info.reg,
  26039. + original_base_reg);
  26040. +
  26041. + new_base_reg_info.n_set_insns = 2;
  26042. + }
  26043. +
  26044. + new_base_reg_info.need_adjust_offset_p = true;
  26045. + }
  26046. +
  26047. + return new_base_reg_info;
  26048. +}
  26049. +
  26050. +static bool
  26051. +nds32_4byte_load_store_reg_plus_offset (
  26052. + rtx insn,
  26053. + load_store_info_t *load_store_info)
  26054. +{
  26055. + if (!INSN_P (insn))
  26056. + return false;
  26057. +
  26058. + rtx pattern = PATTERN (insn);
  26059. + rtx mem = NULL_RTX;
  26060. + rtx reg = NULL_RTX;
  26061. + rtx base_reg = NULL_RTX;
  26062. + rtx addr;
  26063. + HOST_WIDE_INT offset = 0;
  26064. + bool load_p = false;
  26065. +
  26066. + if (GET_CODE (pattern) != SET)
  26067. + return false;
  26068. +
  26069. + if (MEM_P (SET_SRC (pattern)))
  26070. + {
  26071. + mem = SET_SRC (pattern);
  26072. + reg = SET_DEST (pattern);
  26073. + load_p = true;
  26074. + }
  26075. +
  26076. + if (MEM_P (SET_DEST (pattern)))
  26077. + {
  26078. + mem = SET_DEST (pattern);
  26079. + reg = SET_SRC (pattern);
  26080. + load_p = false;
  26081. + }
  26082. +
  26083. + if (mem == NULL_RTX || reg == NULL_RTX || !REG_P (reg))
  26084. + return false;
  26085. +
  26086. + gcc_assert (REG_P (reg));
  26087. +
  26088. + addr = XEXP (mem, 0);
  26089. +
  26090. + /* We only care about [reg] and [reg+const]. */
  26091. + if (REG_P (addr))
  26092. + {
  26093. + base_reg = addr;
  26094. + offset = 0;
  26095. + }
  26096. + else if (GET_CODE (addr) == PLUS
  26097. + && CONST_INT_P (XEXP (addr, 1)))
  26098. + {
  26099. + base_reg = XEXP (addr, 0);
  26100. + offset = INTVAL (XEXP (addr, 1));
  26101. + if (!REG_P (base_reg))
  26102. + return false;
  26103. + }
  26104. + else
  26105. + return false;
  26106. +
  26107. + /* At least need MIDDLE_REGS. */
  26108. + if (!in_reg_class_p (reg, MIDDLE_REGS))
  26109. + return false;
  26110. +
  26111. + /* lwi450/swi450 */
  26112. + if (offset == 0)
  26113. + return false;
  26114. +
  26115. + if (in_reg_class_p (reg, LOW_REGS))
  26116. + {
  26117. + /* lwi37.sp/swi37.sp/lwi37/swi37 */
  26118. + if ((REGNO (base_reg) == SP_REGNUM
  26119. + || REGNO (base_reg) == FP_REGNUM)
  26120. + && (offset >= 0 && offset < 512 && (offset % 4 == 0)))
  26121. + return false;
  26122. +
  26123. + /* lwi333/swi333 */
  26124. + if (in_reg_class_p (base_reg, LOW_REGS)
  26125. + && (offset >= 0 && offset < 32 && (offset % 4 == 0)))
  26126. + return false;
  26127. + }
  26128. +
  26129. + if (load_store_info)
  26130. + {
  26131. + load_store_info->load_p = load_p;
  26132. + load_store_info->offset = offset;
  26133. + load_store_info->reg = reg;
  26134. + load_store_info->base_reg = base_reg;
  26135. + load_store_info->insn = insn;
  26136. + load_store_info->mem = mem;
  26137. + }
  26138. +
  26139. + if (GET_MODE (reg) != SImode)
  26140. + return false;
  26141. +
  26142. + return true;
  26143. +}
  26144. +
  26145. +static bool
  26146. +nds32_4byte_load_store_reg_plus_offset_p (rtx insn)
  26147. +{
  26148. + return nds32_4byte_load_store_reg_plus_offset (insn, NULL);
  26149. +}
  26150. +
  26151. +static bool
  26152. +nds32_load_store_opt_profitable_p (basic_block bb)
  26153. +{
  26154. + int condidate = 0;
  26155. + int threshold = 2;
  26156. + rtx insn;
  26157. +
  26158. + if (dump_file)
  26159. + fprintf (dump_file, "scan bb %d\n", bb->index);
  26160. +
  26161. + FOR_BB_INSNS (bb, insn)
  26162. + {
  26163. + if (nds32_4byte_load_store_reg_plus_offset_p (insn))
  26164. + condidate++;
  26165. + }
  26166. +
  26167. + if (dump_file)
  26168. + fprintf (dump_file, " condidate = %d\n", condidate);
  26169. +
  26170. + return condidate >= threshold;
  26171. +}
  26172. +
  26173. +static void
  26174. +nds32_live_regs (basic_block bb, rtx first, rtx last, bitmap *live)
  26175. +{
  26176. + df_ref *def_rec;
  26177. + rtx insn;
  26178. + bitmap_copy (*live, DF_LR_IN (bb));
  26179. + df_simulate_initialize_forwards (bb, *live);
  26180. + rtx first_insn = BB_HEAD (bb);
  26181. +
  26182. + for (insn = first_insn; insn != first; insn = NEXT_INSN (insn))
  26183. + df_simulate_one_insn_forwards (bb, insn, *live);
  26184. +
  26185. + if (dump_file && debug_live_reg)
  26186. + {
  26187. + fprintf (dump_file, "scan live regs:\nfrom:\n");
  26188. + print_rtl_single (dump_file, first);
  26189. +
  26190. + fprintf (dump_file, "to:\n");
  26191. + print_rtl_single (dump_file, last);
  26192. +
  26193. + fprintf (dump_file, "bb lr in:\n");
  26194. + dump_bitmap (dump_file, DF_LR_IN (bb));
  26195. +
  26196. + fprintf (dump_file, "init:\n");
  26197. + dump_bitmap (dump_file, *live);
  26198. + }
  26199. +
  26200. + for (insn = first; insn != last; insn = NEXT_INSN (insn))
  26201. + {
  26202. + if (!INSN_P (insn))
  26203. + continue;
  26204. +
  26205. + for (def_rec = DF_INSN_DEFS (insn);
  26206. + *def_rec; def_rec++)
  26207. + bitmap_set_bit (*live, DF_REF_REGNO (*def_rec));
  26208. +
  26209. + if (dump_file && debug_live_reg)
  26210. + {
  26211. + fprintf (dump_file, "scaning:\n");
  26212. + print_rtl_single (dump_file, insn);
  26213. + dump_bitmap (dump_file, *live);
  26214. + }
  26215. + }
  26216. +
  26217. + gcc_assert (INSN_P (insn));
  26218. +
  26219. + for (def_rec = DF_INSN_DEFS (insn);
  26220. + *def_rec; def_rec++)
  26221. + bitmap_set_bit (*live, DF_REF_REGNO (*def_rec));
  26222. +
  26223. + if (dump_file && debug_live_reg)
  26224. + {
  26225. + fprintf (dump_file, "scaning:\n");
  26226. + print_rtl_single (dump_file, last);
  26227. + dump_bitmap (dump_file, *live);
  26228. + }
  26229. +}
  26230. +
  26231. +static void
  26232. +print_hard_reg_set (FILE *file, const char *prefix, HARD_REG_SET set)
  26233. +{
  26234. + int i;
  26235. + bool first = true;
  26236. + fprintf (file, "%s{ ", prefix);
  26237. +
  26238. + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
  26239. + {
  26240. + if (TEST_HARD_REG_BIT (set, i))
  26241. + {
  26242. + if (first)
  26243. + {
  26244. + fprintf (file, "%s", reg_names[i]);
  26245. + first = false;
  26246. + }
  26247. + else
  26248. + fprintf (file, ", %s", reg_names[i]);
  26249. + }
  26250. + }
  26251. + fprintf (file, "}\n");
  26252. +}
  26253. +
  26254. +static offset_info_t
  26255. +nds32_get_offset_info (auto_vec<load_store_info_t, 64> *load_store_info)
  26256. +{
  26257. + unsigned i;
  26258. + std::set<HOST_WIDE_INT> offsets;
  26259. + offset_info_t offset_info;
  26260. + offset_info.max_offset = 0;
  26261. + offset_info.min_offset = 0;
  26262. + offset_info.num_offset = 0;
  26263. +
  26264. + if (load_store_info->length () == 0)
  26265. + return offset_info;
  26266. +
  26267. + offset_info.max_offset = (*load_store_info)[0].offset;
  26268. + offset_info.min_offset = (*load_store_info)[0].offset;
  26269. + offsets.insert ((*load_store_info)[0].offset);
  26270. +
  26271. + for (i = 1; i < load_store_info->length (); i++)
  26272. + {
  26273. + HOST_WIDE_INT offset = (*load_store_info)[i].offset;
  26274. + offset_info.max_offset = MAX (offset_info.max_offset, offset);
  26275. + offset_info.min_offset = MIN (offset_info.min_offset, offset);
  26276. + offsets.insert (offset);
  26277. + }
  26278. +
  26279. + offset_info.num_offset = offsets.size ();
  26280. +
  26281. + return offset_info;
  26282. +}
  26283. +
  26284. +static void
  26285. +nds32_get_available_reg_set (basic_block bb,
  26286. + rtx first,
  26287. + rtx last,
  26288. + HARD_REG_SET *available_regset)
  26289. +{
  26290. + bitmap live;
  26291. + HARD_REG_SET live_regset;
  26292. + unsigned i;
  26293. + live = BITMAP_ALLOC (&reg_obstack);
  26294. +
  26295. + nds32_live_regs (bb, first, last, &live);
  26296. +
  26297. + REG_SET_TO_HARD_REG_SET (live_regset, live);
  26298. +
  26299. + /* Reverse available_regset. */
  26300. + COMPL_HARD_REG_SET (*available_regset, live_regset);
  26301. +
  26302. + /* We only care $r0-$r31, so mask $r0-$r31. */
  26303. + AND_HARD_REG_SET (*available_regset, reg_class_contents[GENERAL_REGS]);
  26304. +
  26305. + /* Fixed register also not available. */
  26306. + for (i = NDS32_FIRST_GPR_REGNUM; i <= NDS32_LAST_GPR_REGNUM; ++i)
  26307. + {
  26308. + if (fixed_regs[i])
  26309. + CLEAR_HARD_REG_BIT (*available_regset, i);
  26310. + }
  26311. +
  26312. + BITMAP_FREE (live);
  26313. +}
  26314. +
  26315. +static void
  26316. +nds32_do_load_store_opt (basic_block bb)
  26317. +{
  26318. + rtx insn;
  26319. + load_store_info_t load_store_info;
  26320. + auto_vec<load_store_info_t, 64> load_store_infos[NDS32_GPR_NUM];
  26321. + HARD_REG_SET available_regset;
  26322. + int i;
  26323. + unsigned j;
  26324. + unsigned regno;
  26325. + unsigned polluting;
  26326. + df_ref *def_rec;
  26327. + /* Dirty mean a register is define again after
  26328. + first load/store instruction.
  26329. + For example:
  26330. +
  26331. + lwi $r2, [$r3 + #0x100]
  26332. + mov $r3, $r4 ! $r3 is dirty after this instruction.
  26333. + lwi $r1, [$r3 + #0x120] ! so this load can't chain with prev load.
  26334. + */
  26335. + bool dirty[NDS32_GPR_NUM];
  26336. +
  26337. + if (dump_file)
  26338. + fprintf (dump_file, "try load store opt for bb %d\n", bb->index);
  26339. +
  26340. + for (i = 0; i < NDS32_GPR_NUM; ++i)
  26341. + dirty[i] = false;
  26342. +
  26343. + FOR_BB_INSNS (bb, insn)
  26344. + {
  26345. + if (!INSN_P (insn))
  26346. + continue;
  26347. +
  26348. + polluting = INVALID_REGNUM;
  26349. +
  26350. + /* Set def reg is dirty if chain is not empty. */
  26351. + for (def_rec = DF_INSN_DEFS (insn);
  26352. + *def_rec; def_rec++)
  26353. + {
  26354. + regno = DF_REF_REGNO (*def_rec);
  26355. +
  26356. + if (!NDS32_IS_GPR_REGNUM (regno))
  26357. + continue;
  26358. +
  26359. + if (!load_store_infos[regno].is_empty ())
  26360. + {
  26361. + /* Set pulluting here because the source register
  26362. + may be the same one. */
  26363. + if (dirty[regno] == false)
  26364. + polluting = regno;
  26365. +
  26366. + dirty[regno] = true;
  26367. + }
  26368. + }
  26369. +
  26370. + /* Set all caller-save register is dirty if chain is not empty. */
  26371. + if (CALL_P (insn))
  26372. + {
  26373. + for (i = 0; i < NDS32_GPR_NUM; ++i)
  26374. + {
  26375. + if (call_used_regs[i] && !load_store_infos[i].is_empty ())
  26376. + dirty[i] = true;
  26377. + }
  26378. + }
  26379. +
  26380. + if (nds32_4byte_load_store_reg_plus_offset (insn, &load_store_info))
  26381. + {
  26382. + regno = REGNO (load_store_info.base_reg);
  26383. + gcc_assert (NDS32_IS_GPR_REGNUM (regno));
  26384. +
  26385. + /* Don't add to chain if this reg is dirty. */
  26386. + if (dirty[regno] && polluting != regno)
  26387. + break;
  26388. +
  26389. + /* If the register is first time to be used and be polluted
  26390. + right away, we don't push it. */
  26391. + if (regno == REGNO (load_store_info.reg) && load_store_info.load_p
  26392. + && dirty[regno] == false)
  26393. + continue;
  26394. +
  26395. + load_store_infos[regno].safe_push (load_store_info);
  26396. + }
  26397. + }
  26398. + for (i = 0; i < NDS32_GPR_NUM; ++i)
  26399. + {
  26400. + if (load_store_infos[i].length () <= 1)
  26401. + {
  26402. + if (dump_file && load_store_infos[i].length () == 1)
  26403. + fprintf (dump_file,
  26404. + "Skip Chain for $r%d since chain size only 1\n",
  26405. + i);
  26406. + continue;
  26407. + }
  26408. +
  26409. + if (dump_file)
  26410. + {
  26411. + fprintf (dump_file,
  26412. + "Chain for $r%d: (size = %u)\n",
  26413. + i, load_store_infos[i].length ());
  26414. +
  26415. + for (j = 0; j < load_store_infos[i].length (); ++j)
  26416. + {
  26417. + fprintf (dump_file,
  26418. + "regno = %d base_regno = %d "
  26419. + "offset = " HOST_WIDE_INT_PRINT_DEC " "
  26420. + "load_p = %d UID = %u\n",
  26421. + REGNO (load_store_infos[i][j].reg),
  26422. + REGNO (load_store_infos[i][j].base_reg),
  26423. + load_store_infos[i][j].offset,
  26424. + load_store_infos[i][j].load_p,
  26425. + INSN_UID (load_store_infos[i][j].insn));
  26426. + }
  26427. + }
  26428. +
  26429. + nds32_get_available_reg_set (bb,
  26430. + load_store_infos[i][0].insn,
  26431. + load_store_infos[i].last ().insn,
  26432. + &available_regset);
  26433. +
  26434. + if (dump_file)
  26435. + {
  26436. + print_hard_reg_set (dump_file, "", available_regset);
  26437. + }
  26438. +
  26439. + offset_info_t offset_info = nds32_get_offset_info (&load_store_infos[i]);
  26440. + if (dump_file)
  26441. + {
  26442. + fprintf (dump_file,
  26443. + "max offset = " HOST_WIDE_INT_PRINT_DEC "\n"
  26444. + "min offset = " HOST_WIDE_INT_PRINT_DEC "\n"
  26445. + "num offset = %d\n",
  26446. + offset_info.max_offset,
  26447. + offset_info.min_offset,
  26448. + offset_info.num_offset);
  26449. + }
  26450. +
  26451. + int gain;
  26452. + int best_gain = 0;
  26453. + const load_store_optimize_pass *best_load_store_optimize_pass = NULL;
  26454. +
  26455. + for (j = 0; j < N_LOAD_STORE_OPT_TYPE; ++j)
  26456. + {
  26457. + gain = load_store_optimizes[j]->calc_gain (&available_regset,
  26458. + offset_info,
  26459. + &load_store_infos[i]);
  26460. +
  26461. + if (dump_file)
  26462. + fprintf (dump_file, "%s gain = %d\n",
  26463. + load_store_optimizes[j]->name (), gain);
  26464. +
  26465. + if (gain > best_gain)
  26466. + {
  26467. + best_gain = gain;
  26468. + best_load_store_optimize_pass = load_store_optimizes[j];
  26469. + }
  26470. + }
  26471. +
  26472. + if (best_load_store_optimize_pass)
  26473. + {
  26474. + if (dump_file)
  26475. + fprintf (dump_file, "%s is most profit, optimize it!\n",
  26476. + best_load_store_optimize_pass->name ());
  26477. +
  26478. + best_load_store_optimize_pass->do_optimize (&available_regset,
  26479. + offset_info,
  26480. + &load_store_infos[i]);
  26481. +
  26482. + df_insn_rescan_all ();
  26483. + }
  26484. +
  26485. + }
  26486. +}
  26487. +
  26488. +static unsigned int
  26489. +nds32_load_store_opt (void)
  26490. +{
  26491. + basic_block bb;
  26492. +
  26493. + df_set_flags (DF_LR_RUN_DCE);
  26494. + df_note_add_problem ();
  26495. + df_analyze ();
  26496. +
  26497. + FOR_EACH_BB_FN (bb, cfun)
  26498. + {
  26499. + if (nds32_load_store_opt_profitable_p (bb))
  26500. + nds32_do_load_store_opt (bb);
  26501. + }
  26502. +
  26503. + return 1;
  26504. +}
  26505. +
  26506. +const pass_data pass_data_nds32_load_store_opt =
  26507. +{
  26508. + RTL_PASS, /* type */
  26509. + "load_store_opt", /* name */
  26510. + OPTGROUP_NONE, /* optinfo_flags */
  26511. + true, /* has_gate */
  26512. + true, /* has_execute */
  26513. + TV_MACH_DEP, /* tv_id */
  26514. + 0, /* properties_required */
  26515. + 0, /* properties_provided */
  26516. + 0, /* properties_destroyed */
  26517. + 0, /* todo_flags_start */
  26518. + ( TODO_df_finish | TODO_verify_rtl_sharing), /* todo_flags_finish */
  26519. +};
  26520. +
  26521. +class pass_nds32_load_store_opt : public rtl_opt_pass
  26522. +{
  26523. +public:
  26524. + pass_nds32_load_store_opt (gcc::context *ctxt)
  26525. + : rtl_opt_pass (pass_data_nds32_load_store_opt, ctxt)
  26526. + {}
  26527. +
  26528. + /* opt_pass methods: */
  26529. + bool gate () { return TARGET_16_BIT && TARGET_LOAD_STORE_OPT; }
  26530. + unsigned int execute () { return nds32_load_store_opt (); }
  26531. +};
  26532. +
  26533. +rtl_opt_pass *
  26534. +make_pass_nds32_load_store_opt (gcc::context *ctxt)
  26535. +{
  26536. + return new pass_nds32_load_store_opt (ctxt);
  26537. +}
  26538. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-load-store-opt.h gcc-4.9.4/gcc/config/nds32/nds32-load-store-opt.h
  26539. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-load-store-opt.h 1970-01-01 01:00:00.000000000 +0100
  26540. +++ gcc-4.9.4/gcc/config/nds32/nds32-load-store-opt.h 2016-08-08 20:37:45.506270091 +0200
  26541. @@ -0,0 +1,128 @@
  26542. +/* Prototypes for load-store-opt of Andes NDS32 cpu for GNU compiler
  26543. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  26544. + Contributed by Andes Technology Corporation.
  26545. +
  26546. + This file is part of GCC.
  26547. +
  26548. + GCC is free software; you can redistribute it and/or modify it
  26549. + under the terms of the GNU General Public License as published
  26550. + by the Free Software Foundation; either version 3, or (at your
  26551. + option) any later version.
  26552. +
  26553. + GCC is distributed in the hope that it will be useful, but WITHOUT
  26554. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  26555. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  26556. + License for more details.
  26557. +
  26558. + You should have received a copy of the GNU General Public License
  26559. + along with GCC; see the file COPYING3. If not see
  26560. + <http://www.gnu.org/licenses/>. */
  26561. +
  26562. +#ifndef NDS32_LOAD_STORE_OPT_H
  26563. +#define NDS32_LOAD_STORE_OPT_H
  26564. +
  26565. +/* Define the type of a set of hard registers. */
  26566. +
  26567. +typedef struct {
  26568. + rtx reg;
  26569. + rtx base_reg;
  26570. + rtx offset;
  26571. + HOST_WIDE_INT shift;
  26572. + bool load_p;
  26573. + rtx insn;
  26574. +} rr_load_store_info_t;
  26575. +
  26576. +typedef struct {
  26577. + rtx reg;
  26578. + rtx base_reg;
  26579. + HOST_WIDE_INT offset;
  26580. + bool load_p;
  26581. + rtx insn;
  26582. + rtx mem;
  26583. +} load_store_info_t;
  26584. +
  26585. +typedef struct {
  26586. + HOST_WIDE_INT max_offset;
  26587. + HOST_WIDE_INT min_offset;
  26588. + /* How many different offset. */
  26589. + int num_offset;
  26590. +} offset_info_t;
  26591. +
  26592. +typedef struct {
  26593. + rtx set_insns[2];
  26594. + int n_set_insns;
  26595. + rtx reg;
  26596. + bool need_adjust_offset_p;
  26597. + HOST_WIDE_INT adjust_offset;
  26598. +} new_base_reg_info_t;
  26599. +
  26600. +typedef auto_vec<load_store_info_t, 64> load_store_infos_t;
  26601. +
  26602. +class load_store_optimize_pass
  26603. +{
  26604. +public:
  26605. + load_store_optimize_pass (enum reg_class,
  26606. + enum reg_class,
  26607. + HOST_WIDE_INT,
  26608. + HOST_WIDE_INT,
  26609. + bool,
  26610. + const char *);
  26611. + const char *name () const { return m_name; };
  26612. + int calc_gain (HARD_REG_SET *,
  26613. + offset_info_t,
  26614. + load_store_infos_t *) const;
  26615. + void do_optimize (HARD_REG_SET *,
  26616. + offset_info_t,
  26617. + load_store_infos_t *) const;
  26618. +private:
  26619. + enum reg_class m_allow_regclass;
  26620. + enum reg_class m_new_base_regclass;
  26621. + HOST_WIDE_INT m_offset_lower_bound;
  26622. + HOST_WIDE_INT m_offset_upper_bound;
  26623. + bool m_load_only_p;
  26624. + const char *m_name;
  26625. +};
  26626. +
  26627. +static inline bool
  26628. +in_reg_class_p (unsigned regno, enum reg_class clazz)
  26629. +{
  26630. + return TEST_HARD_REG_BIT (reg_class_contents[clazz], regno);
  26631. +}
  26632. +
  26633. +static inline bool
  26634. +in_reg_class_p (rtx reg, enum reg_class clazz)
  26635. +{
  26636. + gcc_assert (REG_P (reg));
  26637. + return in_reg_class_p (REGNO (reg), clazz);
  26638. +}
  26639. +
  26640. +static inline rtx
  26641. +gen_reg_plus_imm_load_store (rtx reg, rtx base_reg,
  26642. + HOST_WIDE_INT offset, bool load_p, rtx oldmem)
  26643. +{
  26644. + rtx addr = plus_constant(Pmode, base_reg, offset);
  26645. + rtx mem = gen_rtx_MEM (SImode, addr);
  26646. + MEM_COPY_ATTRIBUTES (mem, oldmem);
  26647. + if (load_p)
  26648. + return gen_movsi (reg, mem);
  26649. + else
  26650. + return gen_movsi (mem, reg);
  26651. +}
  26652. +
  26653. +static inline unsigned
  26654. +find_available_reg (HARD_REG_SET *available_regset, enum reg_class clazz)
  26655. +{
  26656. + hard_reg_set_iterator hrsi;
  26657. + unsigned regno;
  26658. + EXECUTE_IF_SET_IN_HARD_REG_SET (reg_class_contents[clazz], 0, regno, hrsi)
  26659. + {
  26660. + /* Caller-save register or callee-save register but it's ever live. */
  26661. + if (TEST_HARD_REG_BIT (*available_regset, regno)
  26662. + && (call_used_regs[regno] || df_regs_ever_live_p (regno)))
  26663. + return regno;
  26664. + }
  26665. +
  26666. + return INVALID_REGNUM;
  26667. +}
  26668. +
  26669. +#endif /* ! NDS32_LOAD_STORE_OPT_H */
  26670. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32.md gcc-4.9.4/gcc/config/nds32/nds32.md
  26671. --- gcc-4.9.4.orig/gcc/config/nds32/nds32.md 2014-01-02 23:23:26.000000000 +0100
  26672. +++ gcc-4.9.4/gcc/config/nds32/nds32.md 2016-08-08 20:37:45.590273343 +0200
  26673. @@ -1,5 +1,5 @@
  26674. ;; Machine description of Andes NDS32 cpu for GNU compiler
  26675. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  26676. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  26677. ;; Contributed by Andes Technology Corporation.
  26678. ;;
  26679. ;; This file is part of GCC.
  26680. @@ -46,58 +46,140 @@
  26681. ;; Include DImode/DFmode operations.
  26682. (include "nds32-doubleword.md")
  26683. +;; Include floating-point patterns.
  26684. +(include "nds32-fpu.md")
  26685. +
  26686. ;; Include peephole patterns.
  26687. (include "nds32-peephole2.md")
  26688. +;; ------------------------------------------------------------------------
  26689. +
  26690. +;; CPU pipeline model.
  26691. +(define_attr "pipeline_model" "n7,n8,e8,n9,n13,simple"
  26692. + (const
  26693. + (cond [(match_test "nds32_cpu_option == CPU_N7") (const_string "n7")
  26694. + (match_test "nds32_cpu_option == CPU_N8") (const_string "n8")
  26695. + (match_test "nds32_cpu_option == CPU_E8") (const_string "e8")
  26696. + (match_test "nds32_cpu_option == CPU_N9") (const_string "n9")
  26697. + (match_test "nds32_cpu_option == CPU_N10") (const_string "n9")
  26698. + (match_test "nds32_cpu_option == CPU_N12") (const_string "n13")
  26699. + (match_test "nds32_cpu_option == CPU_N13") (const_string "n13")
  26700. + (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")]
  26701. + (const_string "n9"))))
  26702. +
  26703. ;; Insn type, it is used to default other attribute values.
  26704. (define_attr "type"
  26705. - "unknown,move,load,store,alu,compare,branch,call,misc"
  26706. + "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,pbsad,pbsada,mul,mac,div,branch,mmu,misc"
  26707. (const_string "unknown"))
  26708. -
  26709. ;; Length, in bytes, default is 4-bytes.
  26710. (define_attr "length" "" (const_int 4))
  26711. +;; Indicate the amount of micro instructions.
  26712. +(define_attr "combo"
  26713. + "0,1,2,3,4,5,6,7,8,9,10,12"
  26714. + (const_string "1"))
  26715. +
  26716. +;; Insn in which feature set, it is used to enable/disable insn alternatives.
  26717. +;; v1 : Baseline Instructions
  26718. +;; v2 : Baseline Version 2 Instructions
  26719. +;; v3m : Baseline Version 3m Instructions
  26720. +;; v3 : Baseline Version 3 Instructions
  26721. +;; pe1 : Performance Extension Instructions
  26722. +;; pe2 : Performance Extension Version 2 Instructions
  26723. +;; se : String Extension instructions
  26724. +(define_attr "feature"
  26725. + "v1,v2,v3m,v3,pe1,pe2,se,fpu"
  26726. + (const_string "v1"))
  26727. +;; Because linker relaxation only can reduce size, gcc has to forbid some
  26728. +;; 2-byte insntruction patterns which may be tagged relax hint.
  26729. +(define_attr "relaxable"
  26730. + "yes,no"
  26731. + (const_string "yes"))
  26732. ;; Enabled, which is used to enable/disable insn alternatives.
  26733. ;; Note that we use length and TARGET_16_BIT here as criteria.
  26734. -;; If the instruction pattern already check TARGET_16_BIT to
  26735. -;; determine the length by itself, its enabled attribute should be
  26736. -;; always 1 to avoid the conflict with the settings here.
  26737. -(define_attr "enabled" ""
  26738. - (cond [(and (eq_attr "length" "2")
  26739. - (match_test "!TARGET_16_BIT"))
  26740. - (const_int 0)]
  26741. - (const_int 1)))
  26742. +;; If the instruction pattern already check TARGET_16_BIT to determine
  26743. +;; the length by itself, its enabled attribute should be customized to
  26744. +;; avoid the conflict between length attribute and this default setting.
  26745. +(define_attr "enabled" "no,yes"
  26746. + (if_then_else
  26747. + (ior (and (eq_attr "length" "2") (match_test "!TARGET_16_BIT"))
  26748. + (and (eq_attr "relaxable" "no") (match_test "TARGET_LINUX_ABI")))
  26749. + (const_string "no")
  26750. + (cond [(eq_attr "feature" "v1") (const_string "yes")
  26751. + (eq_attr "feature" "v2") (if_then_else (match_test "TARGET_ISA_V2 || TARGET_ISA_V3 || TARGET_ISA_V3M")
  26752. + (const_string "yes")
  26753. + (const_string "no"))
  26754. + (eq_attr "feature" "v3") (if_then_else (match_test "TARGET_ISA_V3")
  26755. + (const_string "yes")
  26756. + (const_string "no"))
  26757. + (eq_attr "feature" "v3m") (if_then_else (match_test "TARGET_ISA_V3 || TARGET_ISA_V3M")
  26758. + (const_string "yes")
  26759. + (const_string "no"))
  26760. + (eq_attr "feature" "pe1") (if_then_else (match_test "TARGET_EXT_PERF")
  26761. + (const_string "yes")
  26762. + (const_string "no"))
  26763. + (eq_attr "feature" "pe2") (if_then_else (match_test "TARGET_EXT_PERF2")
  26764. + (const_string "yes")
  26765. + (const_string "no"))
  26766. + (eq_attr "feature" "se") (if_then_else (match_test "TARGET_EXT_STRING")
  26767. + (const_string "yes")
  26768. + (const_string "no"))
  26769. + (eq_attr "feature" "fpu") (if_then_else (match_test "TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE")
  26770. + (const_string "yes")
  26771. + (const_string "no"))]
  26772. + (const_string "yes"))))
  26773. ;; ----------------------------------------------------------------------------
  26774. +(include "nds32-dspext.md")
  26775. ;; Move instructions.
  26776. ;; For QImode and HImode, the immediate value can be fit in imm20s.
  26777. ;; So there is no need to split rtx for QI and HI patterns.
  26778. -(define_expand "movqi"
  26779. - [(set (match_operand:QI 0 "general_operand" "")
  26780. - (match_operand:QI 1 "general_operand" ""))]
  26781. +(define_expand "mov<mode>"
  26782. + [(set (match_operand:QIHI 0 "general_operand" "")
  26783. + (match_operand:QIHI 1 "general_operand" ""))]
  26784. ""
  26785. {
  26786. /* Need to force register if mem <- !reg. */
  26787. if (MEM_P (operands[0]) && !REG_P (operands[1]))
  26788. - operands[1] = force_reg (QImode, operands[1]);
  26789. + operands[1] = force_reg (<MODE>mode, operands[1]);
  26790. +
  26791. + if (MEM_P (operands[1]) && optimize > 0)
  26792. + {
  26793. + rtx reg = gen_reg_rtx (SImode);
  26794. +
  26795. + emit_insn (gen_zero_extend<mode>si2 (reg, operands[1]));
  26796. + operands[1] = gen_lowpart (<MODE>mode, reg);
  26797. + }
  26798. })
  26799. -(define_expand "movhi"
  26800. - [(set (match_operand:HI 0 "general_operand" "")
  26801. - (match_operand:HI 1 "general_operand" ""))]
  26802. +(define_expand "movmisalign<mode>"
  26803. + [(set (match_operand:SIDI 0 "general_operand" "")
  26804. + (match_operand:SIDI 1 "general_operand" ""))]
  26805. ""
  26806. {
  26807. - /* Need to force register if mem <- !reg. */
  26808. + rtx addr;
  26809. if (MEM_P (operands[0]) && !REG_P (operands[1]))
  26810. - operands[1] = force_reg (HImode, operands[1]);
  26811. + operands[1] = force_reg (<MODE>mode, operands[1]);
  26812. +
  26813. + if (MEM_P (operands[0]))
  26814. + {
  26815. + addr = force_reg (Pmode, XEXP (operands[0], 0));
  26816. + emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
  26817. + }
  26818. + else
  26819. + {
  26820. + addr = force_reg (Pmode, XEXP (operands[1], 0));
  26821. + emit_insn (gen_unaligned_load<mode> (operands[0], addr));
  26822. + }
  26823. + DONE;
  26824. })
  26825. (define_expand "movsi"
  26826. @@ -130,12 +212,27 @@
  26827. low12_int));
  26828. DONE;
  26829. }
  26830. +
  26831. + if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1]))
  26832. + {
  26833. + if (nds32_tls_referenced_p (operands [1]))
  26834. + {
  26835. + nds32_expand_tls_move (operands);
  26836. + DONE;
  26837. + }
  26838. + else if (flag_pic)
  26839. + {
  26840. + nds32_expand_pic_move (operands);
  26841. + DONE;
  26842. + }
  26843. + }
  26844. })
  26845. (define_insn "*mov<mode>"
  26846. - [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m, l, l, l, d, r, d, r, r, r")
  26847. - (match_operand:QIHISI 1 "nds32_move_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45, m, Ip05, Is05, Is20, Ihig"))]
  26848. - ""
  26849. + [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q, A")
  26850. + (match_operand:QIHISI 1 "nds32_move_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, Ip05, Is05, Is20, Ihig, *f, r, *f, Q, *f, r"))]
  26851. + "register_operand(operands[0], <MODE>mode)
  26852. + || register_operand(operands[1], <MODE>mode)"
  26853. {
  26854. switch (which_alternative)
  26855. {
  26856. @@ -154,37 +251,55 @@
  26857. case 8:
  26858. case 9:
  26859. case 10:
  26860. - return nds32_output_16bit_load (operands, <byte>);
  26861. case 11:
  26862. - return nds32_output_32bit_load (operands, <byte>);
  26863. + return nds32_output_16bit_load (operands, <byte>);
  26864. case 12:
  26865. - return "movpi45\t%0, %1";
  26866. + return nds32_output_32bit_load (operands, <byte>);
  26867. case 13:
  26868. - return "movi55\t%0, %1";
  26869. + return "movpi45\t%0, %1";
  26870. case 14:
  26871. - return "movi\t%0, %1";
  26872. + return "movi55\t%0, %1";
  26873. case 15:
  26874. + return "movi\t%0, %1";
  26875. + case 16:
  26876. return "sethi\t%0, hi20(%1)";
  26877. + case 17:
  26878. + if (TARGET_FPU_SINGLE)
  26879. + return "fcpyss\t%0, %1, %1";
  26880. + else
  26881. + return "#";
  26882. + case 18:
  26883. + return "fmtsr\t%1, %0";
  26884. + case 19:
  26885. + return "fmfsr\t%0, %1";
  26886. + case 20:
  26887. + return nds32_output_float_load (operands);
  26888. + case 21:
  26889. + return nds32_output_float_store (operands);
  26890. + case 22:
  26891. + return "mtusr\t%1, %0";
  26892. default:
  26893. gcc_unreachable ();
  26894. }
  26895. }
  26896. - [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
  26897. - (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 4, 2, 2, 4, 4")])
  26898. + [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,unknown,unknown,unknown,unknown,unknown,alu")
  26899. + (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4, 4")
  26900. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu, v1")
  26901. + (set_attr "relaxable" "yes,yes, no, no, yes, no, yes, no, no, yes, no, yes, yes,yes,yes,yes,yes, yes, yes, yes, yes, yes,yes")])
  26902. ;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
  26903. ;; are able to match such instruction template.
  26904. (define_insn "*move_addr"
  26905. - [(set (match_operand:SI 0 "register_operand" "=l, r")
  26906. - (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))]
  26907. + [(set (match_operand:SI 0 "nds32_general_register_operand" "=l, r")
  26908. + (match_operand:SI 1 "nds32_nonunspec_symbolic_operand" " i, i"))]
  26909. ""
  26910. "la\t%0, %1"
  26911. - [(set_attr "type" "move")
  26912. + [(set_attr "type" "alu")
  26913. (set_attr "length" "8")])
  26914. -(define_insn "*sethi"
  26915. +(define_insn "sethi"
  26916. [(set (match_operand:SI 0 "register_operand" "=r")
  26917. (high:SI (match_operand:SI 1 "nds32_symbolic_operand" " i")))]
  26918. ""
  26919. @@ -193,7 +308,7 @@
  26920. (set_attr "length" "4")])
  26921. -(define_insn "*lo_sum"
  26922. +(define_insn "lo_sum"
  26923. [(set (match_operand:SI 0 "register_operand" "=r")
  26924. (lo_sum:SI (match_operand:SI 1 "register_operand" " r")
  26925. (match_operand:SI 2 "nds32_symbolic_operand" " i")))]
  26926. @@ -208,8 +323,8 @@
  26927. ;; Zero extension instructions.
  26928. (define_insn "zero_extend<mode>si2"
  26929. - [(set (match_operand:SI 0 "register_operand" "=l, r, l, *r")
  26930. - (zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33, m")))]
  26931. + [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l, *r")
  26932. + (zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33, m")))]
  26933. ""
  26934. {
  26935. switch (which_alternative)
  26936. @@ -234,8 +349,8 @@
  26937. ;; Sign extension instructions.
  26938. (define_insn "extend<mode>si2"
  26939. - [(set (match_operand:SI 0 "register_operand" "=l, r, r")
  26940. - (sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
  26941. + [(set (match_operand:SI 0 "register_operand" "=$l, r, r")
  26942. + (sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
  26943. ""
  26944. {
  26945. switch (which_alternative)
  26946. @@ -245,7 +360,7 @@
  26947. case 1:
  26948. return "se<size>\t%0, %1";
  26949. case 2:
  26950. - return nds32_output_32bit_load_s (operands, <byte>);
  26951. + return nds32_output_32bit_load_se (operands, <byte>);
  26952. default:
  26953. gcc_unreachable ();
  26954. @@ -259,22 +374,22 @@
  26955. ;; Arithmetic instructions.
  26956. -(define_insn "add<mode>3"
  26957. - [(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
  26958. - (plus:QIHISI (match_operand:QIHISI 1 "register_operand" " 0, l, 0, l, %0, l, 0, k, r, r")
  26959. - (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))]
  26960. +(define_insn "addsi3"
  26961. + [(set (match_operand:SI 0 "register_operand" "=$ d,$ l,$ d,$ l,$ d,$l,$ k,$ l, r, r")
  26962. + (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
  26963. + (match_operand:SI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, IU06, Is15, r")))]
  26964. ""
  26965. {
  26966. switch (which_alternative)
  26967. {
  26968. case 0:
  26969. /* addi Rt4,Rt4,-x ==> subi45 Rt4,x
  26970. - where 0 <= x <= 31 */
  26971. + where 0 <= x <= 31 */
  26972. operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
  26973. return "subi45\t%0, %2";
  26974. case 1:
  26975. /* addi Rt3,Ra3,-x ==> subi333 Rt3,Ra3,x
  26976. - where 0 <= x <= 7 */
  26977. + where 0 <= x <= 7 */
  26978. operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
  26979. return "subi333\t%0, %1, %2";
  26980. case 2:
  26981. @@ -298,19 +413,21 @@
  26982. gcc_unreachable ();
  26983. }
  26984. }
  26985. - [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
  26986. - (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")])
  26987. -
  26988. -(define_insn "sub<mode>3"
  26989. - [(set (match_operand:QIHISI 0 "register_operand" "=d, l, r, r")
  26990. - (minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
  26991. - (match_operand:QIHISI 2 "register_operand" " r, l, r, r")))]
  26992. + [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
  26993. + (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")
  26994. + (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")
  26995. + (set_attr "relaxable" "yes,yes,yes,yes, no,yes,yes,yes,yes,yes")])
  26996. +
  26997. +(define_insn "subsi3"
  26998. + [(set (match_operand:SI 0 "register_operand" "=$d, $l, r, r")
  26999. + (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
  27000. + (match_operand:SI 2 "register_operand" " r, l, r, r")))]
  27001. ""
  27002. "@
  27003. - sub45\t%0, %2
  27004. - sub333\t%0, %1, %2
  27005. - subri\t%0, %2, %1
  27006. - sub\t%0, %1, %2"
  27007. + sub45\t%0, %2
  27008. + sub333\t%0, %1, %2
  27009. + subri\t%0, %2, %1
  27010. + sub\t%0, %1, %2"
  27011. [(set_attr "type" "alu,alu,alu,alu")
  27012. (set_attr "length" " 2, 2, 4, 4")])
  27013. @@ -320,10 +437,10 @@
  27014. ;; and needs to ensure it is exact_log2 value.
  27015. (define_insn "*add_slli"
  27016. [(set (match_operand:SI 0 "register_operand" "=r")
  27017. - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
  27018. + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
  27019. (match_operand:SI 2 "immediate_operand" " i"))
  27020. (match_operand:SI 3 "register_operand" " r")))]
  27021. - "TARGET_ISA_V3
  27022. + "TARGET_ISA_V3 && optimize_size
  27023. && (exact_log2 (INTVAL (operands[2])) != -1)
  27024. && (exact_log2 (INTVAL (operands[2])) <= 31)"
  27025. {
  27026. @@ -333,18 +450,20 @@
  27027. return "add_slli\t%0, %3, %1, %2";
  27028. }
  27029. - [(set_attr "type" "alu")
  27030. - (set_attr "length" "4")])
  27031. + [(set_attr "type" "alu_shift")
  27032. + (set_attr "combo" "2")
  27033. + (set_attr "length" "4")])
  27034. (define_insn "*add_srli"
  27035. - [(set (match_operand:SI 0 "register_operand" "= r")
  27036. - (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27037. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27038. - (match_operand:SI 3 "register_operand" " r")))]
  27039. - "TARGET_ISA_V3"
  27040. + [(set (match_operand:SI 0 "register_operand" "= r")
  27041. + (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27042. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27043. + (match_operand:SI 3 "register_operand" " r")))]
  27044. + "TARGET_ISA_V3 && optimize_size"
  27045. "add_srli\t%0, %3, %1, %2"
  27046. - [(set_attr "type" "alu")
  27047. - (set_attr "length" "4")])
  27048. + [(set_attr "type" "alu_shift")
  27049. + (set_attr "combo" "2")
  27050. + (set_attr "length" "4")])
  27051. ;; GCC intends to simplify (minus (reg) (ashift ...))
  27052. @@ -355,7 +474,7 @@
  27053. (minus:SI (match_operand:SI 1 "register_operand" " r")
  27054. (mult:SI (match_operand:SI 2 "register_operand" " r")
  27055. (match_operand:SI 3 "immediate_operand" " i"))))]
  27056. - "TARGET_ISA_V3
  27057. + "TARGET_ISA_V3 && optimize_size
  27058. && (exact_log2 (INTVAL (operands[3])) != -1)
  27059. && (exact_log2 (INTVAL (operands[3])) <= 31)"
  27060. {
  27061. @@ -365,32 +484,35 @@
  27062. return "sub_slli\t%0, %1, %2, %3";
  27063. }
  27064. - [(set_attr "type" "alu")
  27065. - (set_attr "length" "4")])
  27066. + [(set_attr "type" "alu_shift")
  27067. + (set_attr "combo" "2")
  27068. + (set_attr "length" "4")])
  27069. (define_insn "*sub_srli"
  27070. - [(set (match_operand:SI 0 "register_operand" "= r")
  27071. - (minus:SI (match_operand:SI 1 "register_operand" " r")
  27072. - (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
  27073. - (match_operand:SI 3 "immediate_operand" " Iu05"))))]
  27074. - "TARGET_ISA_V3"
  27075. + [(set (match_operand:SI 0 "register_operand" "= r")
  27076. + (minus:SI (match_operand:SI 1 "register_operand" " r")
  27077. + (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
  27078. + (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))]
  27079. + "TARGET_ISA_V3 && optimize_size"
  27080. "sub_srli\t%0, %1, %2, %3"
  27081. - [(set_attr "type" "alu")
  27082. - (set_attr "length" "4")])
  27083. + [(set_attr "type" "alu_shift")
  27084. + (set_attr "combo" "2")
  27085. + (set_attr "length" "4")])
  27086. ;; Multiplication instructions.
  27087. (define_insn "mulsi3"
  27088. - [(set (match_operand:SI 0 "register_operand" "= w, r")
  27089. - (mult:SI (match_operand:SI 1 "register_operand" " %0, r")
  27090. - (match_operand:SI 2 "register_operand" " w, r")))]
  27091. + [(set (match_operand:SI 0 "register_operand" "=$l, r")
  27092. + (mult:SI (match_operand:SI 1 "register_operand" "% 0, r")
  27093. + (match_operand:SI 2 "register_operand" " l, r")))]
  27094. ""
  27095. "@
  27096. - mul33\t%0, %2
  27097. - mul\t%0, %1, %2"
  27098. - [(set_attr "type" "alu,alu")
  27099. - (set_attr "length" " 2, 4")])
  27100. + mul33\t%0, %2
  27101. + mul\t%0, %1, %2"
  27102. + [(set_attr "type" "mul,mul")
  27103. + (set_attr "length" " 2, 4")
  27104. + (set_attr "feature" "v3m, v1")])
  27105. (define_insn "mulsidi3"
  27106. [(set (match_operand:DI 0 "register_operand" "=r")
  27107. @@ -398,7 +520,7 @@
  27108. (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
  27109. "TARGET_ISA_V2 || TARGET_ISA_V3"
  27110. "mulsr64\t%0, %1, %2"
  27111. - [(set_attr "type" "alu")
  27112. + [(set_attr "type" "mul")
  27113. (set_attr "length" "4")])
  27114. (define_insn "umulsidi3"
  27115. @@ -407,7 +529,7 @@
  27116. (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
  27117. "TARGET_ISA_V2 || TARGET_ISA_V3"
  27118. "mulr64\t%0, %1, %2"
  27119. - [(set_attr "type" "alu")
  27120. + [(set_attr "type" "mul")
  27121. (set_attr "length" "4")])
  27122. @@ -415,32 +537,32 @@
  27123. (define_insn "*maddr32_0"
  27124. [(set (match_operand:SI 0 "register_operand" "=r")
  27125. - (plus:SI (match_operand:SI 3 "register_operand" " 0")
  27126. - (mult:SI (match_operand:SI 1 "register_operand" " r")
  27127. - (match_operand:SI 2 "register_operand" " r"))))]
  27128. + (plus:SI (match_operand:SI 3 "register_operand" " 0")
  27129. + (mult:SI (match_operand:SI 1 "register_operand" " r")
  27130. + (match_operand:SI 2 "register_operand" " r"))))]
  27131. ""
  27132. "maddr32\t%0, %1, %2"
  27133. - [(set_attr "type" "alu")
  27134. + [(set_attr "type" "mac")
  27135. (set_attr "length" "4")])
  27136. (define_insn "*maddr32_1"
  27137. [(set (match_operand:SI 0 "register_operand" "=r")
  27138. - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
  27139. - (match_operand:SI 2 "register_operand" " r"))
  27140. - (match_operand:SI 3 "register_operand" " 0")))]
  27141. + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
  27142. + (match_operand:SI 2 "register_operand" " r"))
  27143. + (match_operand:SI 3 "register_operand" " 0")))]
  27144. ""
  27145. "maddr32\t%0, %1, %2"
  27146. - [(set_attr "type" "alu")
  27147. + [(set_attr "type" "mac")
  27148. (set_attr "length" "4")])
  27149. (define_insn "*msubr32"
  27150. [(set (match_operand:SI 0 "register_operand" "=r")
  27151. - (minus:SI (match_operand:SI 3 "register_operand" " 0")
  27152. - (mult:SI (match_operand:SI 1 "register_operand" " r")
  27153. - (match_operand:SI 2 "register_operand" " r"))))]
  27154. + (minus:SI (match_operand:SI 3 "register_operand" " 0")
  27155. + (mult:SI (match_operand:SI 1 "register_operand" " r")
  27156. + (match_operand:SI 2 "register_operand" " r"))))]
  27157. ""
  27158. "msubr32\t%0, %1, %2"
  27159. - [(set_attr "type" "alu")
  27160. + [(set_attr "type" "mac")
  27161. (set_attr "length" "4")])
  27162. @@ -448,26 +570,46 @@
  27163. (define_insn "divmodsi4"
  27164. [(set (match_operand:SI 0 "register_operand" "=r")
  27165. - (div:SI (match_operand:SI 1 "register_operand" " r")
  27166. - (match_operand:SI 2 "register_operand" " r")))
  27167. + (div:SI (match_operand:SI 1 "register_operand" " r")
  27168. + (match_operand:SI 2 "register_operand" " r")))
  27169. (set (match_operand:SI 3 "register_operand" "=r")
  27170. - (mod:SI (match_dup 1) (match_dup 2)))]
  27171. + (mod:SI (match_dup 1) (match_dup 2)))]
  27172. ""
  27173. "divsr\t%0, %3, %1, %2"
  27174. - [(set_attr "type" "alu")
  27175. + [(set_attr "type" "div")
  27176. (set_attr "length" "4")])
  27177. (define_insn "udivmodsi4"
  27178. [(set (match_operand:SI 0 "register_operand" "=r")
  27179. - (udiv:SI (match_operand:SI 1 "register_operand" " r")
  27180. - (match_operand:SI 2 "register_operand" " r")))
  27181. + (udiv:SI (match_operand:SI 1 "register_operand" " r")
  27182. + (match_operand:SI 2 "register_operand" " r")))
  27183. (set (match_operand:SI 3 "register_operand" "=r")
  27184. - (umod:SI (match_dup 1) (match_dup 2)))]
  27185. + (umod:SI (match_dup 1) (match_dup 2)))]
  27186. ""
  27187. "divr\t%0, %3, %1, %2"
  27188. - [(set_attr "type" "alu")
  27189. + [(set_attr "type" "div")
  27190. + (set_attr "length" "4")])
  27191. +
  27192. +;; divsr/divr will keep quotient only when quotient and remainder is the same
  27193. +;; register in our ISA spec, it's can reduce 1 register presure if we don't
  27194. +;; want remainder.
  27195. +(define_insn "divsi4"
  27196. + [(set (match_operand:SI 0 "register_operand" "=r")
  27197. + (div:SI (match_operand:SI 1 "register_operand" " r")
  27198. + (match_operand:SI 2 "register_operand" " r")))]
  27199. + ""
  27200. + "divsr\t%0, %0, %1, %2"
  27201. + [(set_attr "type" "div")
  27202. (set_attr "length" "4")])
  27203. +(define_insn "udivsi4"
  27204. + [(set (match_operand:SI 0 "register_operand" "=r")
  27205. + (udiv:SI (match_operand:SI 1 "register_operand" " r")
  27206. + (match_operand:SI 2 "register_operand" " r")))]
  27207. + ""
  27208. + "divr\t%0, %0, %1, %2"
  27209. + [(set_attr "type" "div")
  27210. + (set_attr "length" "4")])
  27211. ;; ----------------------------------------------------------------------------
  27212. @@ -488,14 +630,28 @@
  27213. (set_attr "length" "4")]
  27214. )
  27215. -(define_insn "andsi3"
  27216. - [(set (match_operand:SI 0 "register_operand" "= w, r, l, l, l, l, l, l, r, r, r, r, r")
  27217. - (and:SI (match_operand:SI 1 "register_operand" " %0, r, l, l, l, l, 0, 0, r, r, r, r, r")
  27218. - (match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
  27219. +(define_expand "andsi3"
  27220. + [(set (match_operand:SI 0 "register_operand" "")
  27221. + (and:SI (match_operand:SI 1 "register_operand" "")
  27222. + (match_operand:SI 2 "nds32_reg_constant_operand" "")))]
  27223. + ""
  27224. +{
  27225. + if (CONST_INT_P (operands[2])
  27226. + && !nds32_and_operand (operands[2], SImode))
  27227. + {
  27228. + nds32_expand_constant (SImode, INTVAL (operands[2]),
  27229. + operands[0], operands[1]);
  27230. + DONE;
  27231. + }
  27232. +})
  27233. +
  27234. +(define_insn "*andsi3"
  27235. + [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l,$ l,$ l,$ l,$ l,$ l, r, r, r, r, r")
  27236. + (and:SI (match_operand:SI 1 "register_operand" "% 0, r, l, l, l, l, 0, 0, r, r, r, r, r")
  27237. + (match_operand:SI 2 "nds32_and_operand" " l, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
  27238. ""
  27239. {
  27240. HOST_WIDE_INT mask = INTVAL (operands[2]);
  27241. - int zero_position;
  27242. /* 16-bit andi instructions:
  27243. andi Rt3,Ra3,0xff -> zeb33 Rt3,Ra3
  27244. @@ -520,8 +676,7 @@
  27245. case 5:
  27246. return "x11b33\t%0, %1";
  27247. case 6:
  27248. - operands[2] = GEN_INT (floor_log2 (mask));
  27249. - return "bmski33\t%0, %2";
  27250. + return "bmski33\t%0, %B2";
  27251. case 7:
  27252. operands[2] = GEN_INT (floor_log2 (mask + 1) - 1);
  27253. return "fexti33\t%0, %2";
  27254. @@ -535,47 +690,35 @@
  27255. operands[2] = GEN_INT (~mask);
  27256. return "bitci\t%0, %1, %2";
  27257. case 12:
  27258. - /* If we reach this alternative,
  27259. - it must pass the nds32_can_use_bclr_p() test,
  27260. - so that we can guarantee there is only one 0-bit
  27261. - within the immediate value. */
  27262. - for (zero_position = 31; zero_position >= 0; zero_position--)
  27263. - {
  27264. - if ((INTVAL (operands[2]) & (1 << zero_position)) == 0)
  27265. - {
  27266. - /* Found the 0-bit position. */
  27267. - operands[2] = GEN_INT (zero_position);
  27268. - break;
  27269. - }
  27270. - }
  27271. - return "bclr\t%0, %1, %2";
  27272. + return "bclr\t%0, %1, %b2";
  27273. default:
  27274. gcc_unreachable ();
  27275. }
  27276. }
  27277. - [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
  27278. - (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")])
  27279. + [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
  27280. + (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")
  27281. + (set_attr "feature" "v3m, v1, v1, v1, v1, v1,v3m,v3m, v1, v1, v1, v3,pe1")])
  27282. (define_insn "*and_slli"
  27283. - [(set (match_operand:SI 0 "register_operand" "= r")
  27284. - (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
  27285. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27286. - (match_operand:SI 3 "register_operand" " r")))]
  27287. - "TARGET_ISA_V3"
  27288. + [(set (match_operand:SI 0 "register_operand" "= r")
  27289. + (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
  27290. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27291. + (match_operand:SI 3 "register_operand" " r")))]
  27292. + "TARGET_ISA_V3 && optimize_size"
  27293. "and_slli\t%0, %3, %1, %2"
  27294. - [(set_attr "type" "alu")
  27295. - (set_attr "length" "4")])
  27296. + [(set_attr "type" "alu_shift")
  27297. + (set_attr "length" "4")])
  27298. (define_insn "*and_srli"
  27299. - [(set (match_operand:SI 0 "register_operand" "= r")
  27300. - (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27301. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27302. - (match_operand:SI 3 "register_operand" " r")))]
  27303. - "TARGET_ISA_V3"
  27304. + [(set (match_operand:SI 0 "register_operand" "= r")
  27305. + (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27306. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27307. + (match_operand:SI 3 "register_operand" " r")))]
  27308. + "TARGET_ISA_V3 && optimize_size"
  27309. "and_srli\t%0, %3, %1, %2"
  27310. - [(set_attr "type" "alu")
  27311. - (set_attr "length" "4")])
  27312. + [(set_attr "type" "alu_shift")
  27313. + (set_attr "length" "4")])
  27314. ;; ----------------------------------------------------------------------------
  27315. @@ -584,58 +727,50 @@
  27316. ;; For V3/V3M ISA, we have 'or33' instruction.
  27317. ;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
  27318. -(define_insn "iorsi3"
  27319. - [(set (match_operand:SI 0 "register_operand" "= w, r, r, r")
  27320. - (ior:SI (match_operand:SI 1 "register_operand" " %0, r, r, r")
  27321. - (match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))]
  27322. +
  27323. +(define_expand "iorsi3"
  27324. + [(set (match_operand:SI 0 "register_operand" "")
  27325. + (ior:SI (match_operand:SI 1 "register_operand" "")
  27326. + (match_operand:SI 2 "general_operand" "")))]
  27327. ""
  27328. {
  27329. - int one_position;
  27330. -
  27331. - switch (which_alternative)
  27332. - {
  27333. - case 0:
  27334. - return "or33\t%0, %2";
  27335. - case 1:
  27336. - return "or\t%0, %1, %2";
  27337. - case 2:
  27338. - return "ori\t%0, %1, %2";
  27339. - case 3:
  27340. - /* If we reach this alternative,
  27341. - it must pass the nds32_can_use_bset_p() test,
  27342. - so that we can guarantee there is only one 1-bit
  27343. - within the immediate value. */
  27344. - /* Use exact_log2() to search the 1-bit position. */
  27345. - one_position = exact_log2 (INTVAL (operands[2]));
  27346. - operands[2] = GEN_INT (one_position);
  27347. - return "bset\t%0, %1, %2";
  27348. + if (!nds32_ior_operand (operands[2], SImode))
  27349. + operands[2] = force_reg (SImode, operands[2]);
  27350. +})
  27351. - default:
  27352. - gcc_unreachable ();
  27353. - }
  27354. -}
  27355. - [(set_attr "type" "alu,alu,alu,alu")
  27356. - (set_attr "length" " 2, 4, 4, 4")])
  27357. +(define_insn "*iorsi3"
  27358. + [(set (match_operand:SI 0 "register_operand" "=l, r, r, r")
  27359. + (ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
  27360. + (match_operand:SI 2 "nds32_ior_operand" " l, r, Iu15, Ie15")))]
  27361. + ""
  27362. + "@
  27363. + or33\t%0, %2
  27364. + or\t%0, %1, %2
  27365. + ori\t%0, %1, %2
  27366. + bset\t%0, %1, %B2"
  27367. + [(set_attr "type" "alu,alu,alu,alu")
  27368. + (set_attr "length" " 2, 4, 4, 4")
  27369. + (set_attr "feature" "v3m, v1, v1,pe1")])
  27370. (define_insn "*or_slli"
  27371. - [(set (match_operand:SI 0 "register_operand" "= r")
  27372. - (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
  27373. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27374. - (match_operand:SI 3 "register_operand" " r")))]
  27375. - "TARGET_ISA_V3"
  27376. + [(set (match_operand:SI 0 "register_operand" "= r")
  27377. + (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
  27378. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27379. + (match_operand:SI 3 "register_operand" " r")))]
  27380. + "TARGET_ISA_V3 && optimize_size"
  27381. "or_slli\t%0, %3, %1, %2"
  27382. - [(set_attr "type" "alu")
  27383. - (set_attr "length" "4")])
  27384. + [(set_attr "type" "alu_shift")
  27385. + (set_attr "length" "4")])
  27386. (define_insn "*or_srli"
  27387. - [(set (match_operand:SI 0 "register_operand" "= r")
  27388. - (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27389. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27390. - (match_operand:SI 3 "register_operand" " r")))]
  27391. - "TARGET_ISA_V3"
  27392. + [(set (match_operand:SI 0 "register_operand" "= r")
  27393. + (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27394. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27395. + (match_operand:SI 3 "register_operand" " r")))]
  27396. + "TARGET_ISA_V3 && optimize_size"
  27397. "or_srli\t%0, %3, %1, %2"
  27398. - [(set_attr "type" "alu")
  27399. - (set_attr "length" "4")])
  27400. + [(set_attr "type" "alu_shift")
  27401. + (set_attr "length" "4")])
  27402. ;; ----------------------------------------------------------------------------
  27403. @@ -644,69 +779,61 @@
  27404. ;; For V3/V3M ISA, we have 'xor33' instruction.
  27405. ;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
  27406. -(define_insn "xorsi3"
  27407. - [(set (match_operand:SI 0 "register_operand" "= w, r, r, r")
  27408. - (xor:SI (match_operand:SI 1 "register_operand" " %0, r, r, r")
  27409. - (match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))]
  27410. +
  27411. +(define_expand "xorsi3"
  27412. + [(set (match_operand:SI 0 "register_operand" "")
  27413. + (xor:SI (match_operand:SI 1 "register_operand" "")
  27414. + (match_operand:SI 2 "general_operand" "")))]
  27415. ""
  27416. {
  27417. - int one_position;
  27418. -
  27419. - switch (which_alternative)
  27420. - {
  27421. - case 0:
  27422. - return "xor33\t%0, %2";
  27423. - case 1:
  27424. - return "xor\t%0, %1, %2";
  27425. - case 2:
  27426. - return "xori\t%0, %1, %2";
  27427. - case 3:
  27428. - /* If we reach this alternative,
  27429. - it must pass the nds32_can_use_btgl_p() test,
  27430. - so that we can guarantee there is only one 1-bit
  27431. - within the immediate value. */
  27432. - /* Use exact_log2() to search the 1-bit position. */
  27433. - one_position = exact_log2 (INTVAL (operands[2]));
  27434. - operands[2] = GEN_INT (one_position);
  27435. - return "btgl\t%0, %1, %2";
  27436. + if (!nds32_xor_operand (operands[2], SImode))
  27437. + operands[2] = force_reg (SImode, operands[2]);
  27438. +})
  27439. - default:
  27440. - gcc_unreachable ();
  27441. - }
  27442. -}
  27443. - [(set_attr "type" "alu,alu,alu,alu")
  27444. - (set_attr "length" " 2, 4, 4, 4")])
  27445. +(define_insn "*xorsi3"
  27446. + [(set (match_operand:SI 0 "register_operand" "=$l, r, r, r")
  27447. + (xor:SI (match_operand:SI 1 "register_operand" "% 0, r, r, r")
  27448. + (match_operand:SI 2 "nds32_xor_operand" " l, r, Iu15, It15")))]
  27449. + ""
  27450. + "@
  27451. + xor33\t%0, %2
  27452. + xor\t%0, %1, %2
  27453. + xori\t%0, %1, %2
  27454. + btgl\t%0, %1, %B2"
  27455. + [(set_attr "type" "alu,alu,alu,alu")
  27456. + (set_attr "length" " 2, 4, 4, 4")
  27457. + (set_attr "feature" "v3m, v1, v1,pe1")])
  27458. (define_insn "*xor_slli"
  27459. [(set (match_operand:SI 0 "register_operand" "= r")
  27460. (xor:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
  27461. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27462. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27463. (match_operand:SI 3 "register_operand" " r")))]
  27464. - "TARGET_ISA_V3"
  27465. + "TARGET_ISA_V3 && optimize_size"
  27466. "xor_slli\t%0, %3, %1, %2"
  27467. - [(set_attr "type" "alu")
  27468. - (set_attr "length" "4")])
  27469. + [(set_attr "type" "alu_shift")
  27470. + (set_attr "length" "4")])
  27471. (define_insn "*xor_srli"
  27472. - [(set (match_operand:SI 0 "register_operand" "= r")
  27473. - (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27474. - (match_operand:SI 2 "immediate_operand" " Iu05"))
  27475. - (match_operand:SI 3 "register_operand" " r")))]
  27476. - "TARGET_ISA_V3"
  27477. + [(set (match_operand:SI 0 "register_operand" "= r")
  27478. + (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
  27479. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
  27480. + (match_operand:SI 3 "register_operand" " r")))]
  27481. + "TARGET_ISA_V3 && optimize_size"
  27482. "xor_srli\t%0, %3, %1, %2"
  27483. - [(set_attr "type" "alu")
  27484. - (set_attr "length" "4")])
  27485. + [(set_attr "type" "alu_shift")
  27486. + (set_attr "length" "4")])
  27487. ;; Rotate Right Instructions.
  27488. -(define_insn "rotrsi3"
  27489. - [(set (match_operand:SI 0 "register_operand" "= r, r")
  27490. - (rotatert:SI (match_operand:SI 1 "register_operand" " r, r")
  27491. - (match_operand:SI 2 "nonmemory_operand" " Iu05, r")))]
  27492. +(define_insn "*rotrsi3"
  27493. + [(set (match_operand:SI 0 "register_operand" "= r, r")
  27494. + (rotatert:SI (match_operand:SI 1 "register_operand" " r, r")
  27495. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))]
  27496. ""
  27497. "@
  27498. - rotri\t%0, %1, %2
  27499. - rotr\t%0, %1, %2"
  27500. + rotri\t%0, %1, %2
  27501. + rotr\t%0, %1, %2"
  27502. [(set_attr "type" "alu,alu")
  27503. (set_attr "length" " 4, 4")])
  27504. @@ -720,14 +847,95 @@
  27505. ;; And for V2 ISA, there is NO 'neg33' instruction.
  27506. ;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
  27507. (define_insn "negsi2"
  27508. - [(set (match_operand:SI 0 "register_operand" "=w, r")
  27509. - (neg:SI (match_operand:SI 1 "register_operand" " w, r")))]
  27510. + [(set (match_operand:SI 0 "register_operand" "=$l, r")
  27511. + (neg:SI (match_operand:SI 1 "register_operand" " l, r")))]
  27512. ""
  27513. "@
  27514. neg33\t%0, %1
  27515. subri\t%0, %1, 0"
  27516. - [(set_attr "type" "alu,alu")
  27517. - (set_attr "length" " 2, 4")])
  27518. + [(set_attr "type" "alu,alu")
  27519. + (set_attr "length" " 2, 4")
  27520. + (set_attr "feature" "v3m, v1")])
  27521. +
  27522. +(define_expand "negsf2"
  27523. + [(set (match_operand:SF 0 "register_operand" "")
  27524. + (neg:SF (match_operand:SF 1 "register_operand" "")))]
  27525. + ""
  27526. +{
  27527. + if (!TARGET_FPU_SINGLE && !TARGET_EXT_PERF)
  27528. + {
  27529. + rtx new_dst = simplify_gen_subreg (SImode, operands[0], SFmode, 0);
  27530. + rtx new_src = simplify_gen_subreg (SImode, operands[1], SFmode, 0);
  27531. +
  27532. + emit_insn (gen_xorsi3 (new_dst,
  27533. + new_src,
  27534. + gen_int_mode (0x80000000, SImode)));
  27535. +
  27536. + DONE;
  27537. + }
  27538. +})
  27539. +
  27540. +(define_expand "negdf2"
  27541. + [(set (match_operand:DF 0 "register_operand" "")
  27542. + (neg:DF (match_operand:DF 1 "register_operand" "")))]
  27543. + ""
  27544. +{
  27545. +})
  27546. +
  27547. +(define_insn_and_split "soft_negdf2"
  27548. + [(set (match_operand:DF 0 "register_operand" "")
  27549. + (neg:DF (match_operand:DF 1 "register_operand" "")))]
  27550. + "!TARGET_FPU_DOUBLE"
  27551. + "#"
  27552. + "!TARGET_FPU_DOUBLE"
  27553. + [(const_int 1)]
  27554. +{
  27555. + rtx src = operands[1];
  27556. + rtx dst = operands[0];
  27557. + rtx ori_dst = operands[0];
  27558. +
  27559. + bool need_extra_move_for_dst_p;
  27560. + /* FPU register can't change mode to SI directly, so we need create a
  27561. + tmp register to handle it, and FPU register can't do `xor` or btgl. */
  27562. + if (HARD_REGISTER_P (src)
  27563. + && TEST_HARD_REG_BIT (reg_class_contents[FP_REGS], REGNO (src)))
  27564. + {
  27565. + rtx tmp = gen_reg_rtx (DFmode);
  27566. + emit_move_insn (tmp, src);
  27567. + src = tmp;
  27568. + }
  27569. +
  27570. + if (HARD_REGISTER_P (dst)
  27571. + && TEST_HARD_REG_BIT (reg_class_contents[FP_REGS], REGNO (dst)))
  27572. + {
  27573. + need_extra_move_for_dst_p = true;
  27574. + rtx tmp = gen_reg_rtx (DFmode);
  27575. + dst = tmp;
  27576. + }
  27577. +
  27578. + rtx dst_high_part = simplify_gen_subreg (
  27579. + SImode, dst,
  27580. + DFmode, subreg_highpart_offset (SImode, DFmode));
  27581. + rtx dst_low_part = simplify_gen_subreg (
  27582. + SImode, dst,
  27583. + DFmode, subreg_lowpart_offset (SImode, DFmode));
  27584. + rtx src_high_part = simplify_gen_subreg (
  27585. + SImode, src,
  27586. + DFmode, subreg_highpart_offset (SImode, DFmode));
  27587. + rtx src_low_part = simplify_gen_subreg (
  27588. + SImode, src,
  27589. + DFmode, subreg_lowpart_offset (SImode, DFmode));
  27590. +
  27591. + emit_insn (gen_xorsi3 (dst_high_part,
  27592. + src_high_part,
  27593. + gen_int_mode (0x80000000, SImode)));
  27594. + emit_move_insn (dst_low_part, src_low_part);
  27595. +
  27596. + if (need_extra_move_for_dst_p)
  27597. + emit_move_insn (ori_dst, dst);
  27598. +
  27599. + DONE;
  27600. +})
  27601. ;; ----------------------------------------------------------------------------
  27602. @@ -737,53 +945,67 @@
  27603. ;; For V3/V3M ISA, we have 'not33' instruction.
  27604. ;; So we can identify 'not Rt3,Ra3' case and set its length to be 2.
  27605. (define_insn "one_cmplsi2"
  27606. - [(set (match_operand:SI 0 "register_operand" "=w, r")
  27607. - (not:SI (match_operand:SI 1 "register_operand" " w, r")))]
  27608. + [(set (match_operand:SI 0 "register_operand" "=$l, r")
  27609. + (not:SI (match_operand:SI 1 "register_operand" " l, r")))]
  27610. ""
  27611. "@
  27612. not33\t%0, %1
  27613. nor\t%0, %1, %1"
  27614. - [(set_attr "type" "alu,alu")
  27615. - (set_attr "length" " 2, 4")])
  27616. + [(set_attr "type" "alu,alu")
  27617. + (set_attr "length" " 2, 4")
  27618. + (set_attr "feature" "v3m, v1")])
  27619. ;; ----------------------------------------------------------------------------
  27620. ;; Shift instructions.
  27621. -(define_insn "ashlsi3"
  27622. - [(set (match_operand:SI 0 "register_operand" "= l, r, r")
  27623. - (ashift:SI (match_operand:SI 1 "register_operand" " l, r, r")
  27624. - (match_operand:SI 2 "nonmemory_operand" " Iu03, Iu05, r")))]
  27625. +(define_expand "<shift>si3"
  27626. + [(set (match_operand:SI 0 "register_operand" "")
  27627. + (shift_rotate:SI (match_operand:SI 1 "register_operand" "")
  27628. + (match_operand:SI 2 "nds32_rimm5u_operand" "")))]
  27629. + ""
  27630. +{
  27631. + if (operands[2] == const0_rtx)
  27632. + {
  27633. + emit_move_insn (operands[0], operands[1]);
  27634. + DONE;
  27635. + }
  27636. +})
  27637. +
  27638. +(define_insn "*ashlsi3"
  27639. + [(set (match_operand:SI 0 "register_operand" "=$ l, r, r")
  27640. + (ashift:SI (match_operand:SI 1 "register_operand" " l, r, r")
  27641. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu03, Iu05, r")))]
  27642. ""
  27643. "@
  27644. - slli333\t%0, %1, %2
  27645. - slli\t%0, %1, %2
  27646. - sll\t%0, %1, %2"
  27647. + slli333\t%0, %1, %2
  27648. + slli\t%0, %1, %2
  27649. + sll\t%0, %1, %2"
  27650. [(set_attr "type" "alu,alu,alu")
  27651. (set_attr "length" " 2, 4, 4")])
  27652. -(define_insn "ashrsi3"
  27653. - [(set (match_operand:SI 0 "register_operand" "= d, r, r")
  27654. - (ashiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
  27655. - (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
  27656. +(define_insn "*ashrsi3"
  27657. + [(set (match_operand:SI 0 "register_operand" "=$ d, r, r")
  27658. + (ashiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
  27659. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
  27660. ""
  27661. "@
  27662. - srai45\t%0, %2
  27663. - srai\t%0, %1, %2
  27664. - sra\t%0, %1, %2"
  27665. + srai45\t%0, %2
  27666. + srai\t%0, %1, %2
  27667. + sra\t%0, %1, %2"
  27668. [(set_attr "type" "alu,alu,alu")
  27669. (set_attr "length" " 2, 4, 4")])
  27670. -(define_insn "lshrsi3"
  27671. - [(set (match_operand:SI 0 "register_operand" "= d, r, r")
  27672. - (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
  27673. - (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
  27674. +(define_insn "*lshrsi3"
  27675. + [(set (match_operand:SI 0 "register_operand" "=$ d, r, r")
  27676. + (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
  27677. + (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
  27678. ""
  27679. "@
  27680. - srli45\t%0, %2
  27681. - srli\t%0, %1, %2
  27682. - srl\t%0, %1, %2"
  27683. + srli45\t%0, %2
  27684. + srli\t%0, %1, %2
  27685. + srl\t%0, %1, %2"
  27686. [(set_attr "type" "alu,alu,alu")
  27687. (set_attr "length" " 2, 4, 4")])
  27688. @@ -794,149 +1016,65 @@
  27689. ;; Conditional Move patterns
  27690. ;; ----------------------------------------------------------------------------
  27691. -(define_expand "movsicc"
  27692. - [(set (match_operand:SI 0 "register_operand" "")
  27693. - (if_then_else:SI (match_operand 1 "comparison_operator" "")
  27694. - (match_operand:SI 2 "register_operand" "")
  27695. - (match_operand:SI 3 "register_operand" "")))]
  27696. - "TARGET_CMOV"
  27697. +(define_expand "mov<mode>cc"
  27698. + [(set (match_operand:QIHISI 0 "register_operand" "")
  27699. + (if_then_else:QIHISI (match_operand 1 "nds32_movecc_comparison_operator" "")
  27700. + (match_operand:QIHISI 2 "register_operand" "")
  27701. + (match_operand:QIHISI 3 "register_operand" "")))]
  27702. + "TARGET_CMOV && !optimize_size"
  27703. {
  27704. - if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
  27705. - && GET_MODE (XEXP (operands[1], 0)) == SImode
  27706. - && XEXP (operands[1], 1) == const0_rtx)
  27707. - {
  27708. - /* If the operands[1] rtx is already (eq X 0) or (ne X 0),
  27709. - we have gcc generate original template rtx. */
  27710. - goto create_template;
  27711. - }
  27712. - else
  27713. + enum nds32_expand_result_type result = nds32_expand_movcc (operands);
  27714. + switch (result)
  27715. {
  27716. - /* Since there is only 'slt'(Set when Less Than) instruction for
  27717. - comparison in Andes ISA, the major strategy we use here is to
  27718. - convert conditional move into 'LT + EQ' or 'LT + NE' rtx combination.
  27719. - We design constraints properly so that the reload phase will assist
  27720. - to make one source operand to use same register as result operand.
  27721. - Then we can use cmovz/cmovn to catch the other source operand
  27722. - which has different register. */
  27723. - enum rtx_code code = GET_CODE (operands[1]);
  27724. - enum rtx_code new_code = code;
  27725. - rtx cmp_op0 = XEXP (operands[1], 0);
  27726. - rtx cmp_op1 = XEXP (operands[1], 1);
  27727. - rtx tmp;
  27728. - int reverse = 0;
  27729. -
  27730. - /* Main Goal: Use 'LT + EQ' or 'LT + NE' to target "then" part
  27731. - Strategy : Reverse condition and swap comparison operands
  27732. -
  27733. - For example:
  27734. -
  27735. - a <= b ? P : Q (LE or LEU)
  27736. - --> a > b ? Q : P (reverse condition)
  27737. - --> b < a ? Q : P (swap comparison operands to achieve 'LT/LTU')
  27738. -
  27739. - a >= b ? P : Q (GE or GEU)
  27740. - --> a < b ? Q : P (reverse condition to achieve 'LT/LTU')
  27741. -
  27742. - a < b ? P : Q (LT or LTU)
  27743. - --> (NO NEED TO CHANGE, it is already 'LT/LTU')
  27744. -
  27745. - a > b ? P : Q (GT or GTU)
  27746. - --> b < a ? P : Q (swap comparison operands to achieve 'LT/LTU') */
  27747. - switch (code)
  27748. - {
  27749. - case NE:
  27750. - /* (a != b ? P : Q)
  27751. - can be expressed as
  27752. - (a == b ? Q : P)
  27753. - so, fall through to reverse condition */
  27754. - case GE: case GEU: case LE: case LEU:
  27755. - new_code = reverse_condition (code);
  27756. - reverse = 1;
  27757. - break;
  27758. - case EQ: case GT: case GTU: case LT: case LTU:
  27759. - /* no need to reverse condition */
  27760. - break;
  27761. - default:
  27762. - FAIL;
  27763. - }
  27764. -
  27765. - /* For '>' comparison operator, we swap operands
  27766. - so that we can have 'LT/LTU' operator. */
  27767. - if (new_code == GT || new_code == GTU)
  27768. - {
  27769. - tmp = cmp_op0;
  27770. - cmp_op0 = cmp_op1;
  27771. - cmp_op1 = tmp;
  27772. -
  27773. - new_code = swap_condition (new_code);
  27774. - }
  27775. -
  27776. - /* Use a temporary register to store slt/slts result. */
  27777. - tmp = gen_reg_rtx (SImode);
  27778. -
  27779. - /* Split EQ and NE because we don't have direct comparison of EQ and NE.
  27780. - If we don't split it, the conditional move transformation will fail
  27781. - when producing (SET A (EQ B C)) or (SET A (NE B C)). */
  27782. - if (new_code == EQ)
  27783. - {
  27784. - emit_insn (gen_xorsi3 (tmp, cmp_op0, cmp_op1));
  27785. - emit_insn (gen_slt_compare (tmp, tmp, GEN_INT (1)));
  27786. - }
  27787. - else if (new_code == NE)
  27788. - {
  27789. - emit_insn (gen_xorsi3 (tmp, cmp_op0, cmp_op1));
  27790. - emit_insn (gen_slt_compare (tmp, GEN_INT (0), tmp));
  27791. - }
  27792. - else
  27793. - /* This emit_insn will create corresponding 'slt/slts' insturction. */
  27794. - emit_insn (gen_rtx_SET (VOIDmode, tmp,
  27795. - gen_rtx_fmt_ee (new_code, SImode,
  27796. - cmp_op0, cmp_op1)));
  27797. -
  27798. - /* Change comparison semantic into (eq X 0) or (ne X 0) behavior
  27799. - so that cmovz or cmovn will be matched later.
  27800. -
  27801. - For reverse condition cases, we want to create a semantic that:
  27802. - (eq X 0) --> pick up "else" part
  27803. - For normal cases, we want to create a semantic that:
  27804. - (ne X 0) --> pick up "then" part
  27805. -
  27806. - Later we will have cmovz/cmovn instruction pattern to
  27807. - match corresponding behavior and output instruction. */
  27808. - operands[1] = gen_rtx_fmt_ee (reverse ? EQ : NE,
  27809. - VOIDmode, tmp, const0_rtx);
  27810. + case EXPAND_DONE:
  27811. + DONE;
  27812. + break;
  27813. + case EXPAND_FAIL:
  27814. + FAIL;
  27815. + break;
  27816. + case EXPAND_CREATE_TEMPLATE:
  27817. + break;
  27818. + default:
  27819. + gcc_unreachable ();
  27820. }
  27821. -
  27822. -create_template:
  27823. - do {} while(0); /* dummy line */
  27824. })
  27825. -(define_insn "cmovz"
  27826. - [(set (match_operand:SI 0 "register_operand" "=r, r")
  27827. - (if_then_else:SI (eq (match_operand:SI 1 "register_operand" " r, r")
  27828. +(define_insn "cmovz<mode>"
  27829. + [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
  27830. + (if_then_else:QIHISI (eq (match_operand:SI 1 "register_operand" " r, r")
  27831. (const_int 0))
  27832. - (match_operand:SI 2 "register_operand" " r, 0")
  27833. - (match_operand:SI 3 "register_operand" " 0, r")))]
  27834. + (match_operand:QIHISI 2 "register_operand" " r, 0")
  27835. + (match_operand:QIHISI 3 "register_operand" " 0, r")))]
  27836. "TARGET_CMOV"
  27837. "@
  27838. cmovz\t%0, %2, %1
  27839. cmovn\t%0, %3, %1"
  27840. - [(set_attr "type" "move")
  27841. + [(set_attr "type" "alu")
  27842. (set_attr "length" "4")])
  27843. -(define_insn "cmovn"
  27844. - [(set (match_operand:SI 0 "register_operand" "=r, r")
  27845. - (if_then_else:SI (ne (match_operand:SI 1 "register_operand" " r, r")
  27846. +(define_insn "cmovn<mode>"
  27847. + [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
  27848. + (if_then_else:QIHISI (ne (match_operand:SI 1 "register_operand" " r, r")
  27849. (const_int 0))
  27850. - (match_operand:SI 2 "register_operand" " r, 0")
  27851. - (match_operand:SI 3 "register_operand" " 0, r")))]
  27852. + (match_operand:QIHISI 2 "register_operand" " r, 0")
  27853. + (match_operand:QIHISI 3 "register_operand" " 0, r")))]
  27854. "TARGET_CMOV"
  27855. "@
  27856. cmovn\t%0, %2, %1
  27857. cmovz\t%0, %3, %1"
  27858. - [(set_attr "type" "move")
  27859. + [(set_attr "type" "alu")
  27860. (set_attr "length" "4")])
  27861. +;; A hotfix to help RTL combiner to merge a cmovn insn and a zero_extend insn.
  27862. +;; It should be removed once after we change the expansion form of the cmovn.
  27863. +(define_insn "*cmovn_simplified_<mode>"
  27864. + [(set (match_operand:QIHISI 0 "register_operand" "=r")
  27865. + (if_then_else:QIHISI (match_operand:SI 1 "register_operand" "r")
  27866. + (match_operand:QIHISI 2 "register_operand" "r")
  27867. + (match_operand:QIHISI 3 "register_operand" "0")))]
  27868. + ""
  27869. + "cmovn\t%0, %2, %1"
  27870. + [(set_attr "type" "alu")])
  27871. ;; ----------------------------------------------------------------------------
  27872. ;; Conditional Branch patterns
  27873. @@ -951,573 +1089,188 @@
  27874. (pc)))]
  27875. ""
  27876. {
  27877. - rtx tmp_reg;
  27878. - enum rtx_code code;
  27879. -
  27880. - code = GET_CODE (operands[0]);
  27881. -
  27882. - /* If operands[2] is (const_int 0),
  27883. - we can use beqz,bnez,bgtz,bgez,bltz,or blez instructions.
  27884. - So we have gcc generate original template rtx. */
  27885. - if (GET_CODE (operands[2]) == CONST_INT)
  27886. - if (INTVAL (operands[2]) == 0)
  27887. - if ((code != GTU)
  27888. - && (code != GEU)
  27889. - && (code != LTU)
  27890. - && (code != LEU))
  27891. - goto create_template;
  27892. -
  27893. - /* For other comparison, NDS32 ISA only has slt (Set-on-Less-Than)
  27894. - behavior for the comparison, we might need to generate other
  27895. - rtx patterns to achieve same semantic. */
  27896. - switch (code)
  27897. - {
  27898. - case GT:
  27899. - case GTU:
  27900. - if (GET_CODE (operands[2]) == CONST_INT)
  27901. - {
  27902. - /* GT reg_A, const_int => !(LT reg_A, const_int + 1) */
  27903. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  27904. -
  27905. - /* We want to plus 1 into the integer value
  27906. - of operands[2] to create 'slt' instruction.
  27907. - This caculation is performed on the host machine,
  27908. - which may be 64-bit integer.
  27909. - So the meaning of caculation result may be
  27910. - different from the 32-bit nds32 target.
  27911. -
  27912. - For example:
  27913. - 0x7fffffff + 0x1 -> 0x80000000,
  27914. - this value is POSITIVE on 64-bit machine,
  27915. - but the expected value on 32-bit nds32 target
  27916. - should be NEGATIVE value.
  27917. -
  27918. - Hence, instead of using GEN_INT(), we use gen_int_mode() to
  27919. - explicitly create SImode constant rtx. */
  27920. - operands[2] = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
  27921. -
  27922. - if (code == GT)
  27923. - {
  27924. - /* GT, use slts instruction */
  27925. - emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  27926. - }
  27927. - else
  27928. - {
  27929. - /* GTU, use slt instruction */
  27930. - emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  27931. - }
  27932. -
  27933. - PUT_CODE (operands[0], EQ);
  27934. - operands[1] = tmp_reg;
  27935. - operands[2] = const0_rtx;
  27936. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  27937. - operands[2], operands[3]));
  27938. -
  27939. - DONE;
  27940. - }
  27941. - else
  27942. - {
  27943. - /* GT reg_A, reg_B => LT reg_B, reg_A */
  27944. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  27945. -
  27946. - if (code == GT)
  27947. - {
  27948. - /* GT, use slts instruction */
  27949. - emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
  27950. - }
  27951. - else
  27952. - {
  27953. - /* GTU, use slt instruction */
  27954. - emit_insn (gen_slt_compare (tmp_reg, operands[2], operands[1]));
  27955. - }
  27956. -
  27957. - PUT_CODE (operands[0], NE);
  27958. - operands[1] = tmp_reg;
  27959. - operands[2] = const0_rtx;
  27960. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  27961. - operands[2], operands[3]));
  27962. -
  27963. - DONE;
  27964. - }
  27965. -
  27966. - case GE:
  27967. - case GEU:
  27968. - /* GE reg_A, reg_B => !(LT reg_A, reg_B) */
  27969. - /* GE reg_A, const_int => !(LT reg_A, const_int) */
  27970. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  27971. -
  27972. - if (code == GE)
  27973. - {
  27974. - /* GE, use slts instruction */
  27975. - emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  27976. - }
  27977. - else
  27978. - {
  27979. - /* GEU, use slt instruction */
  27980. - emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  27981. - }
  27982. -
  27983. - PUT_CODE (operands[0], EQ);
  27984. - operands[1] = tmp_reg;
  27985. - operands[2] = const0_rtx;
  27986. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  27987. - operands[2], operands[3]));
  27988. -
  27989. - DONE;
  27990. -
  27991. - case LT:
  27992. - case LTU:
  27993. - /* LT reg_A, reg_B => LT reg_A, reg_B */
  27994. - /* LT reg_A, const_int => LT reg_A, const_int */
  27995. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  27996. -
  27997. - if (code == LT)
  27998. - {
  27999. - /* LT, use slts instruction */
  28000. - emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  28001. - }
  28002. - else
  28003. - {
  28004. - /* LTU, use slt instruction */
  28005. - emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  28006. - }
  28007. -
  28008. - PUT_CODE (operands[0], NE);
  28009. - operands[1] = tmp_reg;
  28010. - operands[2] = const0_rtx;
  28011. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  28012. - operands[2], operands[3]));
  28013. -
  28014. + enum nds32_expand_result_type result = nds32_expand_cbranch (operands);
  28015. + switch (result)
  28016. + {
  28017. + case EXPAND_DONE:
  28018. DONE;
  28019. -
  28020. - case LE:
  28021. - case LEU:
  28022. - if (GET_CODE (operands[2]) == CONST_INT)
  28023. - {
  28024. - /* LE reg_A, const_int => LT reg_A, const_int + 1 */
  28025. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  28026. -
  28027. - /* Note that (le:SI X INT_MAX) is not the same as (lt:SI X INT_MIN).
  28028. - We better have an assert here in case GCC does not properly
  28029. - optimize it away. The INT_MAX here is 0x7fffffff for target. */
  28030. - gcc_assert (code != LE || INTVAL (operands[2]) != 0x7fffffff);
  28031. - operands[2] = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
  28032. -
  28033. - if (code == LE)
  28034. - {
  28035. - /* LE, use slts instruction */
  28036. - emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  28037. - }
  28038. - else
  28039. - {
  28040. - /* LEU, use slt instruction */
  28041. - emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  28042. - }
  28043. -
  28044. - PUT_CODE (operands[0], NE);
  28045. - operands[1] = tmp_reg;
  28046. - operands[2] = const0_rtx;
  28047. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  28048. - operands[2], operands[3]));
  28049. -
  28050. - DONE;
  28051. - }
  28052. - else
  28053. - {
  28054. - /* LE reg_A, reg_B => !(LT reg_B, reg_A) */
  28055. - tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  28056. -
  28057. - if (code == LE)
  28058. - {
  28059. - /* LE, use slts instruction */
  28060. - emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
  28061. - }
  28062. - else
  28063. - {
  28064. - /* LEU, use slt instruction */
  28065. - emit_insn (gen_slt_compare (tmp_reg, operands[2], operands[1]));
  28066. - }
  28067. -
  28068. - PUT_CODE (operands[0], EQ);
  28069. - operands[1] = tmp_reg;
  28070. - operands[2] = const0_rtx;
  28071. - emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  28072. - operands[2], operands[3]));
  28073. -
  28074. - DONE;
  28075. - }
  28076. -
  28077. - case EQ:
  28078. - case NE:
  28079. - /* NDS32 ISA has various form for eq/ne behavior no matter
  28080. - what kind of the operand is.
  28081. - So just generate original template rtx. */
  28082. - goto create_template;
  28083. -
  28084. - default:
  28085. + break;
  28086. + case EXPAND_FAIL:
  28087. FAIL;
  28088. + break;
  28089. + case EXPAND_CREATE_TEMPLATE:
  28090. + break;
  28091. + default:
  28092. + gcc_unreachable ();
  28093. }
  28094. -
  28095. -create_template:
  28096. - do {} while(0); /* dummy line */
  28097. })
  28098. -(define_insn "*cbranchsi4_equality_zero"
  28099. +(define_insn "cbranchsi4_equality_zero"
  28100. [(set (pc)
  28101. (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
  28102. - [(match_operand:SI 1 "register_operand" "t, l, r")
  28103. + [(match_operand:SI 1 "register_operand" "$t,$l, r")
  28104. (const_int 0)])
  28105. (label_ref (match_operand 2 "" ""))
  28106. (pc)))]
  28107. ""
  28108. {
  28109. - enum rtx_code code;
  28110. -
  28111. - code = GET_CODE (operands[0]);
  28112. -
  28113. - /* This zero-comparison conditional branch has two forms:
  28114. - 32-bit instruction => beqz/bnez imm16s << 1
  28115. - 16-bit instruction => beqzs8/bnezs8/beqz38/bnez38 imm8s << 1
  28116. -
  28117. - For 32-bit case,
  28118. - we assume it is always reachable. (but check range -65500 ~ 65500)
  28119. -
  28120. - For 16-bit case,
  28121. - it must satisfy { 255 >= (label - pc) >= -256 } condition.
  28122. - However, since the $pc for nds32 is at the beginning of the instruction,
  28123. - we should leave some length space for current insn.
  28124. - So we use range -250 ~ 250. */
  28125. -
  28126. - switch (get_attr_length (insn))
  28127. - {
  28128. - case 2:
  28129. - if (which_alternative == 0)
  28130. - {
  28131. - /* constraint: t */
  28132. - return (code == EQ) ? "beqzs8\t%2" : "bnezs8\t%2";
  28133. - }
  28134. - else if (which_alternative == 1)
  28135. - {
  28136. - /* constraint: l */
  28137. - return (code == EQ) ? "beqz38\t%1, %2" : "bnez38\t%1, %2";
  28138. - }
  28139. - else
  28140. - {
  28141. - /* constraint: r */
  28142. - /* For which_alternative==2, it should not be here. */
  28143. - gcc_unreachable ();
  28144. - }
  28145. - case 4:
  28146. - /* including constraints: t, l, and r */
  28147. - return (code == EQ) ? "beqz\t%1, %2" : "bnez\t%1, %2";
  28148. - case 6:
  28149. - if (which_alternative == 0)
  28150. - {
  28151. - /* constraint: t */
  28152. - if (code == EQ)
  28153. - {
  28154. - /* beqzs8 .L0
  28155. - =>
  28156. - bnezs8 .LCB0
  28157. - j .L0
  28158. - .LCB0:
  28159. - */
  28160. - return "bnezs8\t.LCB%=\;j\t%2\n.LCB%=:";
  28161. - }
  28162. - else
  28163. - {
  28164. - /* bnezs8 .L0
  28165. - =>
  28166. - beqzs8 .LCB0
  28167. - j .L0
  28168. - .LCB0:
  28169. - */
  28170. - return "beqzs8\t.LCB%=\;j\t%2\n.LCB%=:";
  28171. - }
  28172. - }
  28173. - else if (which_alternative == 1)
  28174. - {
  28175. - /* constraint: l */
  28176. - if (code == EQ)
  28177. - {
  28178. - /* beqz38 $r0, .L0
  28179. - =>
  28180. - bnez38 $r0, .LCB0
  28181. - j .L0
  28182. - .LCB0:
  28183. - */
  28184. - return "bnez38\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28185. - }
  28186. - else
  28187. - {
  28188. - /* bnez38 $r0, .L0
  28189. - =>
  28190. - beqz38 $r0, .LCB0
  28191. - j .L0
  28192. - .LCB0:
  28193. - */
  28194. - return "beqz38\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28195. - }
  28196. - }
  28197. - else
  28198. - {
  28199. - /* constraint: r */
  28200. - /* For which_alternative==2, it should not be here. */
  28201. - gcc_unreachable ();
  28202. - }
  28203. - case 8:
  28204. - /* constraint: t, l, r. */
  28205. - if (code == EQ)
  28206. - {
  28207. - /* beqz $r8, .L0
  28208. - =>
  28209. - bnez $r8, .LCB0
  28210. - j .L0
  28211. - .LCB0:
  28212. - */
  28213. - return "bnez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28214. - }
  28215. - else
  28216. - {
  28217. - /* bnez $r8, .L0
  28218. - =>
  28219. - beqz $r8, .LCB0
  28220. - j .L0
  28221. - .LCB0:
  28222. - */
  28223. - return "beqz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28224. - }
  28225. - default:
  28226. - gcc_unreachable ();
  28227. - }
  28228. -}
  28229. - [(set_attr "type" "branch")
  28230. - (set_attr "enabled" "1")
  28231. - (set_attr_alternative "length"
  28232. - [
  28233. - ;; Alternative 0
  28234. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
  28235. - (le (minus (match_dup 2) (pc)) (const_int 250)))
  28236. - (if_then_else (match_test "TARGET_16_BIT")
  28237. - (const_int 2)
  28238. - (const_int 4))
  28239. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28240. - (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28241. - (const_int 4)
  28242. - (if_then_else (match_test "TARGET_16_BIT")
  28243. - (const_int 6)
  28244. - (const_int 8))))
  28245. - ;; Alternative 1
  28246. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
  28247. - (le (minus (match_dup 2) (pc)) (const_int 250)))
  28248. - (if_then_else (match_test "TARGET_16_BIT")
  28249. - (const_int 2)
  28250. - (const_int 4))
  28251. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28252. - (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28253. - (const_int 4)
  28254. - (if_then_else (match_test "TARGET_16_BIT")
  28255. - (const_int 6)
  28256. - (const_int 8))))
  28257. - ;; Alternative 2
  28258. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28259. - (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28260. - (const_int 4)
  28261. - (const_int 8))
  28262. - ])])
  28263. + return nds32_output_cbranchsi4_equality_zero (insn, operands);
  28264. +}
  28265. + [(set_attr "type" "branch")
  28266. + (set_attr_alternative "enabled"
  28267. + [
  28268. + ;; Alternative 0
  28269. + (if_then_else (match_test "TARGET_16_BIT")
  28270. + (const_string "yes")
  28271. + (const_string "no"))
  28272. + ;; Alternative 1
  28273. + (if_then_else (match_test "TARGET_16_BIT")
  28274. + (const_string "yes")
  28275. + (const_string "no"))
  28276. + ;; Alternative 2
  28277. + (const_string "yes")
  28278. + ])
  28279. + (set_attr_alternative "length"
  28280. + [
  28281. + ;; Alternative 0
  28282. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28283. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
  28284. + (le (minus (match_dup 2) (pc)) (const_int 250)))
  28285. + (if_then_else (match_test "TARGET_16_BIT")
  28286. + (const_int 2)
  28287. + (const_int 4))
  28288. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28289. + (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28290. + (const_int 4)
  28291. + (if_then_else (match_test "TARGET_16_BIT")
  28292. + (const_int 8)
  28293. + (const_int 10))))
  28294. + (const_int 10))
  28295. + ;; Alternative 1
  28296. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28297. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
  28298. + (le (minus (match_dup 2) (pc)) (const_int 250)))
  28299. + (if_then_else (match_test "TARGET_16_BIT")
  28300. + (const_int 2)
  28301. + (const_int 4))
  28302. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28303. + (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28304. + (const_int 4)
  28305. + (if_then_else (match_test "TARGET_16_BIT")
  28306. + (const_int 8)
  28307. + (const_int 10))))
  28308. + (const_int 10))
  28309. + ;; Alternative 2
  28310. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28311. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28312. + (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28313. + (const_int 4)
  28314. + (const_int 10))
  28315. + (const_int 10))
  28316. + ])])
  28317. ;; This pattern is dedicated to V2 ISA,
  28318. ;; because V2 DOES NOT HAVE beqc/bnec instruction.
  28319. -(define_insn "*cbranchsi4_equality_reg"
  28320. +(define_insn "cbranchsi4_equality_reg"
  28321. [(set (pc)
  28322. (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
  28323. - [(match_operand:SI 1 "register_operand" "r")
  28324. - (match_operand:SI 2 "nds32_reg_constant_operand" "r")])
  28325. + [(match_operand:SI 1 "register_operand" "$v, r")
  28326. + (match_operand:SI 2 "register_operand" " l, r")])
  28327. (label_ref (match_operand 3 "" ""))
  28328. (pc)))]
  28329. "TARGET_ISA_V2"
  28330. {
  28331. - enum rtx_code code;
  28332. -
  28333. - code = GET_CODE (operands[0]);
  28334. -
  28335. - /* This register-comparison conditional branch has one form:
  28336. - 32-bit instruction => beq/bne imm14s << 1
  28337. -
  28338. - For 32-bit case,
  28339. - we assume it is always reachable. (but check range -16350 ~ 16350). */
  28340. -
  28341. - switch (code)
  28342. - {
  28343. - case EQ:
  28344. - /* r, r */
  28345. - switch (get_attr_length (insn))
  28346. - {
  28347. - case 4:
  28348. - return "beq\t%1, %2, %3";
  28349. - case 8:
  28350. - /* beq $r0, $r1, .L0
  28351. - =>
  28352. - bne $r0, $r1, .LCB0
  28353. - j .L0
  28354. - .LCB0:
  28355. - */
  28356. - return "bne\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28357. - default:
  28358. - gcc_unreachable ();
  28359. - }
  28360. -
  28361. - case NE:
  28362. - /* r, r */
  28363. - switch (get_attr_length (insn))
  28364. - {
  28365. - case 4:
  28366. - return "bne\t%1, %2, %3";
  28367. - case 8:
  28368. - /* bne $r0, $r1, .L0
  28369. - =>
  28370. - beq $r0, $r1, .LCB0
  28371. - j .L0
  28372. - .LCB0:
  28373. - */
  28374. - return "beq\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28375. - default:
  28376. - gcc_unreachable ();
  28377. - }
  28378. -
  28379. - default:
  28380. - gcc_unreachable ();
  28381. - }
  28382. + return nds32_output_cbranchsi4_equality_reg (insn, operands);
  28383. }
  28384. [(set_attr "type" "branch")
  28385. - (set (attr "length")
  28386. - (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
  28387. - (le (minus (match_dup 3) (pc)) (const_int 16350)))
  28388. - (const_int 4)
  28389. - (const_int 8)))])
  28390. + (set_attr_alternative "enabled"
  28391. + [
  28392. + ;; Alternative 0
  28393. + (if_then_else (match_test "TARGET_16_BIT")
  28394. + (const_string "yes")
  28395. + (const_string "no"))
  28396. + ;; Alternative 1
  28397. + (const_string "yes")
  28398. + ])
  28399. + (set_attr_alternative "length"
  28400. + [
  28401. + ;; Alternative 0
  28402. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28403. + (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
  28404. + (le (minus (match_dup 3) (pc)) (const_int 250)))
  28405. + (const_int 2)
  28406. + (if_then_else (and (ge (minus (match_dup 3) (pc))
  28407. + (const_int -16350))
  28408. + (le (minus (match_dup 3) (pc))
  28409. + (const_int 16350)))
  28410. + (const_int 4)
  28411. + (const_int 8)))
  28412. + (const_int 8))
  28413. + ;; Alternative 1
  28414. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28415. + (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
  28416. + (le (minus (match_dup 3) (pc)) (const_int 16350)))
  28417. + (const_int 4)
  28418. + (const_int 10))
  28419. + (const_int 10))
  28420. + ])])
  28421. ;; This pattern is dedicated to V3/V3M,
  28422. ;; because V3/V3M DO HAVE beqc/bnec instruction.
  28423. -(define_insn "*cbranchsi4_equality_reg_or_const_int"
  28424. +(define_insn "cbranchsi4_equality_reg_or_const_int"
  28425. [(set (pc)
  28426. (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
  28427. - [(match_operand:SI 1 "register_operand" "r, r")
  28428. - (match_operand:SI 2 "nds32_reg_constant_operand" "r, Is11")])
  28429. + [(match_operand:SI 1 "register_operand" "$v, r, r")
  28430. + (match_operand:SI 2 "nds32_rimm11s_operand" " l, r, Is11")])
  28431. (label_ref (match_operand 3 "" ""))
  28432. (pc)))]
  28433. "TARGET_ISA_V3 || TARGET_ISA_V3M"
  28434. {
  28435. - enum rtx_code code;
  28436. -
  28437. - code = GET_CODE (operands[0]);
  28438. -
  28439. - /* This register-comparison conditional branch has one form:
  28440. - 32-bit instruction => beq/bne imm14s << 1
  28441. - 32-bit instruction => beqc/bnec imm8s << 1
  28442. -
  28443. - For 32-bit case, we assume it is always reachable.
  28444. - (but check range -16350 ~ 16350 and -250 ~ 250). */
  28445. -
  28446. - switch (code)
  28447. - {
  28448. - case EQ:
  28449. - if (which_alternative == 0)
  28450. - {
  28451. - /* r, r */
  28452. - switch (get_attr_length (insn))
  28453. - {
  28454. - case 4:
  28455. - return "beq\t%1, %2, %3";
  28456. - case 8:
  28457. - /* beq $r0, $r1, .L0
  28458. - =>
  28459. - bne $r0, $r1, .LCB0
  28460. - j .L0
  28461. - .LCB0:
  28462. - */
  28463. - return "bne\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28464. - default:
  28465. - gcc_unreachable ();
  28466. - }
  28467. - }
  28468. - else
  28469. - {
  28470. - /* r, Is11 */
  28471. - switch (get_attr_length (insn))
  28472. - {
  28473. - case 4:
  28474. - return "beqc\t%1, %2, %3";
  28475. - case 8:
  28476. - /* beqc $r0, constant, .L0
  28477. - =>
  28478. - bnec $r0, constant, .LCB0
  28479. - j .L0
  28480. - .LCB0:
  28481. - */
  28482. - return "bnec\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28483. - default:
  28484. - gcc_unreachable ();
  28485. - }
  28486. - }
  28487. - case NE:
  28488. - if (which_alternative == 0)
  28489. - {
  28490. - /* r, r */
  28491. - switch (get_attr_length (insn))
  28492. - {
  28493. - case 4:
  28494. - return "bne\t%1, %2, %3";
  28495. - case 8:
  28496. - /* bne $r0, $r1, .L0
  28497. - =>
  28498. - beq $r0, $r1, .LCB0
  28499. - j .L0
  28500. - .LCB0:
  28501. - */
  28502. - return "beq\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28503. - default:
  28504. - gcc_unreachable ();
  28505. - }
  28506. - }
  28507. - else
  28508. - {
  28509. - /* r, Is11 */
  28510. - switch (get_attr_length (insn))
  28511. - {
  28512. - case 4:
  28513. - return "bnec\t%1, %2, %3";
  28514. - case 8:
  28515. - /* bnec $r0, constant, .L0
  28516. - =>
  28517. - beqc $r0, constant, .LCB0
  28518. - j .L0
  28519. - .LCB0:
  28520. - */
  28521. - return "beqc\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
  28522. - default:
  28523. - gcc_unreachable ();
  28524. - }
  28525. - }
  28526. - default:
  28527. - gcc_unreachable ();
  28528. - }
  28529. + return nds32_output_cbranchsi4_equality_reg_or_const_int (insn, operands);
  28530. }
  28531. [(set_attr "type" "branch")
  28532. + (set_attr_alternative "enabled"
  28533. + [
  28534. + ;; Alternative 0
  28535. + (if_then_else (match_test "TARGET_16_BIT")
  28536. + (const_string "yes")
  28537. + (const_string "no"))
  28538. + ;; Alternative 1
  28539. + (const_string "yes")
  28540. + ;; Alternative 2
  28541. + (const_string "yes")
  28542. + ])
  28543. (set_attr_alternative "length"
  28544. [
  28545. ;; Alternative 0
  28546. - (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
  28547. - (le (minus (match_dup 3) (pc)) (const_int 16350)))
  28548. - (const_int 4)
  28549. - (const_int 8))
  28550. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28551. + (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
  28552. + (le (minus (match_dup 3) (pc)) (const_int 250)))
  28553. + (const_int 2)
  28554. + (if_then_else (and (ge (minus (match_dup 3) (pc))
  28555. + (const_int -16350))
  28556. + (le (minus (match_dup 3) (pc))
  28557. + (const_int 16350)))
  28558. + (const_int 4)
  28559. + (const_int 8)))
  28560. + (const_int 8))
  28561. ;; Alternative 1
  28562. - (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
  28563. - (le (minus (match_dup 3) (pc)) (const_int 250)))
  28564. - (const_int 4)
  28565. - (const_int 8))
  28566. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28567. + (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
  28568. + (le (minus (match_dup 3) (pc)) (const_int 16350)))
  28569. + (const_int 4)
  28570. + (const_int 10))
  28571. + (const_int 10))
  28572. + ;; Alternative 2
  28573. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28574. + (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
  28575. + (le (minus (match_dup 3) (pc)) (const_int 250)))
  28576. + (const_int 4)
  28577. + (const_int 10))
  28578. + (const_int 10))
  28579. ])])
  28580. @@ -1530,80 +1283,16 @@
  28581. (pc)))]
  28582. ""
  28583. {
  28584. - enum rtx_code code;
  28585. -
  28586. - code = GET_CODE (operands[0]);
  28587. -
  28588. - /* This zero-greater-less-comparison conditional branch has one form:
  28589. - 32-bit instruction => bgtz/bgez/bltz/blez imm16s << 1
  28590. -
  28591. - For 32-bit case, we assume it is always reachable.
  28592. - (but check range -65500 ~ 65500). */
  28593. -
  28594. - if (get_attr_length (insn) == 8)
  28595. - {
  28596. - /* The branch target is too far to simply use one
  28597. - bgtz/bgez/bltz/blez instruction.
  28598. - We need to reverse condition and use 'j' to jump to the target. */
  28599. - switch (code)
  28600. - {
  28601. - case GT:
  28602. - /* bgtz $r8, .L0
  28603. - =>
  28604. - blez $r8, .LCB0
  28605. - j .L0
  28606. - .LCB0:
  28607. - */
  28608. - return "blez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28609. - case GE:
  28610. - /* bgez $r8, .L0
  28611. - =>
  28612. - bltz $r8, .LCB0
  28613. - j .L0
  28614. - .LCB0:
  28615. - */
  28616. - return "bltz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28617. - case LT:
  28618. - /* bltz $r8, .L0
  28619. - =>
  28620. - bgez $r8, .LCB0
  28621. - j .L0
  28622. - .LCB0:
  28623. - */
  28624. - return "bgez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28625. - case LE:
  28626. - /* blez $r8, .L0
  28627. - =>
  28628. - bgtz $r8, .LCB0
  28629. - j .L0
  28630. - .LCB0:
  28631. - */
  28632. - return "bgtz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
  28633. - default:
  28634. - gcc_unreachable ();
  28635. - }
  28636. - }
  28637. -
  28638. - switch (code)
  28639. - {
  28640. - case GT:
  28641. - return "bgtz\t%1, %2";
  28642. - case GE:
  28643. - return "bgez\t%1, %2";
  28644. - case LT:
  28645. - return "bltz\t%1, %2";
  28646. - case LE:
  28647. - return "blez\t%1, %2";
  28648. - default:
  28649. - gcc_unreachable ();
  28650. - }
  28651. + return nds32_output_cbranchsi4_greater_less_zero (insn, operands);
  28652. }
  28653. [(set_attr "type" "branch")
  28654. (set (attr "length")
  28655. - (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28656. - (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28657. - (const_int 4)
  28658. - (const_int 8)))])
  28659. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28660. + (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
  28661. + (le (minus (match_dup 2) (pc)) (const_int 65500)))
  28662. + (const_int 4)
  28663. + (const_int 10))
  28664. + (const_int 10)))])
  28665. (define_expand "cstoresi4"
  28666. @@ -1613,237 +1302,85 @@
  28667. (match_operand:SI 3 "nonmemory_operand" "")]))]
  28668. ""
  28669. {
  28670. - rtx tmp_reg;
  28671. - enum rtx_code code;
  28672. -
  28673. - code = GET_CODE (operands[1]);
  28674. -
  28675. - switch (code)
  28676. + enum nds32_expand_result_type result = nds32_expand_cstore (operands);
  28677. + switch (result)
  28678. {
  28679. - case EQ:
  28680. - if (GET_CODE (operands[3]) == CONST_INT)
  28681. - {
  28682. - /* reg_R = (reg_A == const_int_B)
  28683. - --> addi reg_C, reg_A, -const_int_B
  28684. - slti reg_R, reg_C, const_int_1 */
  28685. - tmp_reg = gen_reg_rtx (SImode);
  28686. - operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
  28687. - /* If the integer value is not in the range of imm15s,
  28688. - we need to force register first because our addsi3 pattern
  28689. - only accept nds32_rimm15s_operand predicate. */
  28690. - if (!satisfies_constraint_Is15 (operands[3]))
  28691. - operands[3] = force_reg (SImode, operands[3]);
  28692. - emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
  28693. - emit_insn (gen_slt_compare (operands[0], tmp_reg, const1_rtx));
  28694. -
  28695. - DONE;
  28696. - }
  28697. - else
  28698. - {
  28699. - /* reg_R = (reg_A == reg_B)
  28700. - --> xor reg_C, reg_A, reg_B
  28701. - slti reg_R, reg_C, const_int_1 */
  28702. - tmp_reg = gen_reg_rtx (SImode);
  28703. - emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
  28704. - emit_insn (gen_slt_compare (operands[0], tmp_reg, const1_rtx));
  28705. -
  28706. - DONE;
  28707. - }
  28708. -
  28709. - case NE:
  28710. - if (GET_CODE (operands[3]) == CONST_INT)
  28711. - {
  28712. - /* reg_R = (reg_A != const_int_B)
  28713. - --> addi reg_C, reg_A, -const_int_B
  28714. - slti reg_R, const_int_0, reg_C */
  28715. - tmp_reg = gen_reg_rtx (SImode);
  28716. - operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
  28717. - /* If the integer value is not in the range of imm15s,
  28718. - we need to force register first because our addsi3 pattern
  28719. - only accept nds32_rimm15s_operand predicate. */
  28720. - if (!satisfies_constraint_Is15 (operands[3]))
  28721. - operands[3] = force_reg (SImode, operands[3]);
  28722. - emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
  28723. - emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
  28724. -
  28725. - DONE;
  28726. - }
  28727. - else
  28728. - {
  28729. - /* reg_R = (reg_A != reg_B)
  28730. - --> xor reg_C, reg_A, reg_B
  28731. - slti reg_R, const_int_0, reg_C */
  28732. - tmp_reg = gen_reg_rtx (SImode);
  28733. - emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
  28734. - emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
  28735. -
  28736. - DONE;
  28737. - }
  28738. -
  28739. - case GT:
  28740. - case GTU:
  28741. - /* reg_R = (reg_A > reg_B) --> slt reg_R, reg_B, reg_A */
  28742. - /* reg_R = (reg_A > const_int_B) --> slt reg_R, const_int_B, reg_A */
  28743. - if (code == GT)
  28744. - {
  28745. - /* GT, use slts instruction */
  28746. - emit_insn (gen_slts_compare (operands[0], operands[3], operands[2]));
  28747. - }
  28748. - else
  28749. - {
  28750. - /* GTU, use slt instruction */
  28751. - emit_insn (gen_slt_compare (operands[0], operands[3], operands[2]));
  28752. - }
  28753. -
  28754. - DONE;
  28755. -
  28756. - case GE:
  28757. - case GEU:
  28758. - if (GET_CODE (operands[3]) == CONST_INT)
  28759. - {
  28760. - /* reg_R = (reg_A >= const_int_B)
  28761. - --> movi reg_C, const_int_B - 1
  28762. - slt reg_R, reg_C, reg_A */
  28763. - tmp_reg = gen_reg_rtx (SImode);
  28764. -
  28765. - emit_insn (gen_movsi (tmp_reg,
  28766. - gen_int_mode (INTVAL (operands[3]) - 1,
  28767. - SImode)));
  28768. - if (code == GE)
  28769. - {
  28770. - /* GE, use slts instruction */
  28771. - emit_insn (gen_slts_compare (operands[0], tmp_reg, operands[2]));
  28772. - }
  28773. - else
  28774. - {
  28775. - /* GEU, use slt instruction */
  28776. - emit_insn (gen_slt_compare (operands[0], tmp_reg, operands[2]));
  28777. - }
  28778. -
  28779. - DONE;
  28780. - }
  28781. - else
  28782. - {
  28783. - /* reg_R = (reg_A >= reg_B)
  28784. - --> slt reg_R, reg_A, reg_B
  28785. - xori reg_R, reg_R, const_int_1 */
  28786. - if (code == GE)
  28787. - {
  28788. - /* GE, use slts instruction */
  28789. - emit_insn (gen_slts_compare (operands[0],
  28790. - operands[2], operands[3]));
  28791. - }
  28792. - else
  28793. - {
  28794. - /* GEU, use slt instruction */
  28795. - emit_insn (gen_slt_compare (operands[0],
  28796. - operands[2], operands[3]));
  28797. - }
  28798. -
  28799. - /* perform 'not' behavior */
  28800. - emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  28801. -
  28802. - DONE;
  28803. - }
  28804. -
  28805. - case LT:
  28806. - case LTU:
  28807. - /* reg_R = (reg_A < reg_B) --> slt reg_R, reg_A, reg_B */
  28808. - /* reg_R = (reg_A < const_int_B) --> slt reg_R, reg_A, const_int_B */
  28809. - if (code == LT)
  28810. - {
  28811. - /* LT, use slts instruction */
  28812. - emit_insn (gen_slts_compare (operands[0], operands[2], operands[3]));
  28813. - }
  28814. - else
  28815. - {
  28816. - /* LTU, use slt instruction */
  28817. - emit_insn (gen_slt_compare (operands[0], operands[2], operands[3]));
  28818. - }
  28819. -
  28820. + case EXPAND_DONE:
  28821. DONE;
  28822. -
  28823. - case LE:
  28824. - case LEU:
  28825. - if (GET_CODE (operands[3]) == CONST_INT)
  28826. - {
  28827. - /* reg_R = (reg_A <= const_int_B)
  28828. - --> movi reg_C, const_int_B + 1
  28829. - slt reg_R, reg_A, reg_C */
  28830. - tmp_reg = gen_reg_rtx (SImode);
  28831. -
  28832. - emit_insn (gen_movsi (tmp_reg,
  28833. - gen_int_mode (INTVAL (operands[3]) + 1,
  28834. - SImode)));
  28835. - if (code == LE)
  28836. - {
  28837. - /* LE, use slts instruction */
  28838. - emit_insn (gen_slts_compare (operands[0], operands[2], tmp_reg));
  28839. - }
  28840. - else
  28841. - {
  28842. - /* LEU, use slt instruction */
  28843. - emit_insn (gen_slt_compare (operands[0], operands[2], tmp_reg));
  28844. - }
  28845. -
  28846. - DONE;
  28847. - }
  28848. - else
  28849. - {
  28850. - /* reg_R = (reg_A <= reg_B) --> slt reg_R, reg_B, reg_A
  28851. - xori reg_R, reg_R, const_int_1 */
  28852. - if (code == LE)
  28853. - {
  28854. - /* LE, use slts instruction */
  28855. - emit_insn (gen_slts_compare (operands[0],
  28856. - operands[3], operands[2]));
  28857. - }
  28858. - else
  28859. - {
  28860. - /* LEU, use slt instruction */
  28861. - emit_insn (gen_slt_compare (operands[0],
  28862. - operands[3], operands[2]));
  28863. - }
  28864. -
  28865. - /* perform 'not' behavior */
  28866. - emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  28867. -
  28868. - DONE;
  28869. - }
  28870. -
  28871. -
  28872. + break;
  28873. + case EXPAND_FAIL:
  28874. + FAIL;
  28875. + break;
  28876. + case EXPAND_CREATE_TEMPLATE:
  28877. + break;
  28878. default:
  28879. gcc_unreachable ();
  28880. }
  28881. })
  28882. -(define_insn "slts_compare"
  28883. - [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
  28884. - (lt:SI (match_operand:SI 1 "nonmemory_operand" " d, d, r, r")
  28885. - (match_operand:SI 2 "nonmemory_operand" " r, Iu05, r, Is15")))]
  28886. +(define_expand "slts_compare"
  28887. + [(set (match_operand:SI 0 "register_operand" "")
  28888. + (lt:SI (match_operand:SI 1 "general_operand" "")
  28889. + (match_operand:SI 2 "general_operand" "")))]
  28890. + ""
  28891. +{
  28892. + if (!REG_P (operands[1]))
  28893. + operands[1] = force_reg (SImode, operands[1]);
  28894. +
  28895. + if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
  28896. + operands[2] = force_reg (SImode, operands[2]);
  28897. +})
  28898. +
  28899. +(define_insn "slts_compare_impl"
  28900. + [(set (match_operand:SI 0 "register_operand" "=$t,$ t, r, r")
  28901. + (lt:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
  28902. + (match_operand:SI 2 "nds32_rimm15s_operand" " r, Iu05, r, Is15")))]
  28903. ""
  28904. "@
  28905. slts45\t%1, %2
  28906. sltsi45\t%1, %2
  28907. slts\t%0, %1, %2
  28908. sltsi\t%0, %1, %2"
  28909. - [(set_attr "type" "compare,compare,compare,compare")
  28910. - (set_attr "length" " 2, 2, 4, 4")])
  28911. + [(set_attr "type" "alu, alu, alu, alu")
  28912. + (set_attr "length" " 2, 2, 4, 4")])
  28913. +
  28914. +(define_insn "slt_eq0"
  28915. + [(set (match_operand:SI 0 "register_operand" "=$t, r")
  28916. + (eq:SI (match_operand:SI 1 "register_operand" " d, r")
  28917. + (const_int 0)))]
  28918. + ""
  28919. + "@
  28920. + slti45\t%1, 1
  28921. + slti\t%0, %1, 1"
  28922. + [(set_attr "type" "alu, alu")
  28923. + (set_attr "length" " 2, 4")])
  28924. +
  28925. +(define_expand "slt_compare"
  28926. + [(set (match_operand:SI 0 "register_operand" "")
  28927. + (ltu:SI (match_operand:SI 1 "general_operand" "")
  28928. + (match_operand:SI 2 "general_operand" "")))]
  28929. + ""
  28930. +{
  28931. + if (!REG_P (operands[1]))
  28932. + operands[1] = force_reg (SImode, operands[1]);
  28933. -(define_insn "slt_compare"
  28934. - [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
  28935. - (ltu:SI (match_operand:SI 1 "nonmemory_operand" " d, d, r, r")
  28936. - (match_operand:SI 2 "nonmemory_operand" " r, Iu05, r, Is15")))]
  28937. + if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
  28938. + operands[2] = force_reg (SImode, operands[2]);
  28939. +})
  28940. +
  28941. +(define_insn "slt_compare_impl"
  28942. + [(set (match_operand:SI 0 "register_operand" "=$t,$ t, r, r")
  28943. + (ltu:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
  28944. + (match_operand:SI 2 "nds32_rimm15s_operand" " r, Iu05, r, Is15")))]
  28945. ""
  28946. "@
  28947. slt45\t%1, %2
  28948. slti45\t%1, %2
  28949. slt\t%0, %1, %2
  28950. slti\t%0, %1, %2"
  28951. - [(set_attr "type" "compare,compare,compare,compare")
  28952. - (set_attr "length" " 2, 2, 4, 4")])
  28953. -
  28954. + [(set_attr "type" "alu, alu, alu, alu")
  28955. + (set_attr "length" " 2, 2, 4, 4")])
  28956. ;; ----------------------------------------------------------------------------
  28957. @@ -1875,12 +1412,14 @@
  28958. }
  28959. }
  28960. [(set_attr "type" "branch")
  28961. - (set_attr "enabled" "1")
  28962. + (set_attr "enabled" "yes")
  28963. (set (attr "length")
  28964. - (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
  28965. - (le (minus (match_dup 0) (pc)) (const_int 250)))
  28966. - (if_then_else (match_test "TARGET_16_BIT")
  28967. - (const_int 2)
  28968. + (if_then_else (match_test "!find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)")
  28969. + (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
  28970. + (le (minus (match_dup 0) (pc)) (const_int 250)))
  28971. + (if_then_else (match_test "TARGET_16_BIT")
  28972. + (const_int 2)
  28973. + (const_int 4))
  28974. (const_int 4))
  28975. (const_int 4)))])
  28976. @@ -1888,11 +1427,24 @@
  28977. [(set (pc) (match_operand:SI 0 "register_operand" "r, r"))]
  28978. ""
  28979. "@
  28980. - jr5\t%0
  28981. - jr\t%0"
  28982. + jr5\t%0
  28983. + jr\t%0"
  28984. [(set_attr "type" "branch,branch")
  28985. (set_attr "length" " 2, 4")])
  28986. +(define_insn "*cond_indirect_jump"
  28987. + [(cond_exec (ne (match_operand:SI 0 "register_operand" "r")
  28988. + (const_int 0))
  28989. + (set (pc) (match_operand:SI 1 "register_operand" "0")))]
  28990. + ""
  28991. + "jrnez\t%0"
  28992. + [(set_attr "type" "branch")
  28993. + (set_attr "length" "4")])
  28994. +
  28995. +;; ----------------------------------------------------------------------------
  28996. +
  28997. +;; Normal call patterns.
  28998. +
  28999. ;; Subroutine call instruction returning no value.
  29000. ;; operands[0]: It should be a mem RTX whose address is
  29001. ;; the the address of the function.
  29002. @@ -1902,31 +1454,126 @@
  29003. (define_expand "call"
  29004. [(parallel [(call (match_operand 0 "memory_operand" "")
  29005. (match_operand 1))
  29006. - (clobber (reg:SI LP_REGNUM))])]
  29007. - ""
  29008. + (clobber (reg:SI LP_REGNUM))
  29009. + (clobber (reg:SI TA_REGNUM))])]
  29010. ""
  29011. + "nds32_expand_call_address (&operands[0]);"
  29012. )
  29013. -(define_insn "*call_register"
  29014. +(define_insn "call_register_align"
  29015. [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
  29016. (match_operand 1))
  29017. - (clobber (reg:SI LP_REGNUM))])]
  29018. - ""
  29019. - "@
  29020. - jral5\t%0
  29021. - jral\t%0"
  29022. - [(set_attr "type" "branch,branch")
  29023. - (set_attr "length" " 2, 4")])
  29024. + (clobber (reg:SI LP_REGNUM))
  29025. + (clobber (reg:SI TA_REGNUM))])]
  29026. + "NDS32_ALIGN_P ()"
  29027. +{
  29028. + rtx next_insn = next_active_insn (insn);
  29029. + bool align_p = !(next_insn && get_attr_length (next_insn) == 2);
  29030. + switch (which_alternative)
  29031. + {
  29032. + case 0:
  29033. + if (align_p)
  29034. + return "jral5\t%0\;.align 2";
  29035. + else
  29036. + return "jral5\t%0";
  29037. + case 1:
  29038. + if (align_p)
  29039. + return "jral\t%0\;.align 2";
  29040. + else
  29041. + return "jral\t%0";
  29042. + default:
  29043. + gcc_unreachable ();
  29044. + }
  29045. +}
  29046. + [(set_attr "type" "branch,branch")
  29047. + (set_attr "length" " 2, 4")
  29048. + (set_attr "relaxable" " no, yes")])
  29049. -(define_insn "*call_immediate"
  29050. - [(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
  29051. +(define_insn "call_register"
  29052. + [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
  29053. (match_operand 1))
  29054. - (clobber (reg:SI LP_REGNUM))])]
  29055. - ""
  29056. - "jal\t%0"
  29057. + (clobber (reg:SI LP_REGNUM))
  29058. + (clobber (reg:SI TA_REGNUM))])]
  29059. + "!NDS32_ALIGN_P ()"
  29060. + "@
  29061. + jral5\t%0
  29062. + jral\t%0"
  29063. + [(set_attr "type" "branch,branch")
  29064. + (set_attr "length" " 2, 4")
  29065. + (set_attr "relaxable" " no, yes")])
  29066. +
  29067. +(define_insn "*cond_call_register"
  29068. + [(cond_exec (ne (match_operand:SI 0 "register_operand" "r")
  29069. + (const_int 0))
  29070. + (parallel [(call (mem (match_operand:SI 1 "register_operand" "0"))
  29071. + (match_operand 2))
  29072. + (clobber (reg:SI LP_REGNUM))
  29073. + (clobber (reg:SI TA_REGNUM))]))]
  29074. + "TARGET_ISA_V3"
  29075. + "jralnez\t%0"
  29076. [(set_attr "type" "branch")
  29077. (set_attr "length" "4")])
  29078. +(define_insn "call_immediate_align"
  29079. + [(parallel [(call (mem (match_operand:SI 0 "nds32_symbolic_operand" "i"))
  29080. + (match_operand 1))
  29081. + (clobber (reg:SI LP_REGNUM))
  29082. + (clobber (reg:SI TA_REGNUM))])]
  29083. + "NDS32_ALIGN_P ()"
  29084. +{
  29085. + rtx next_insn = next_active_insn (insn);
  29086. + bool align_p = next_insn && get_attr_length (next_insn) != 2;
  29087. +
  29088. + return nds32_output_call (insn, operands, "bal\t%0", "jal\t%0", align_p);
  29089. +}
  29090. + [(set_attr "type" "branch")
  29091. + (set (attr "length")
  29092. + (if_then_else (match_test "flag_pic")
  29093. + (const_int 16)
  29094. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29095. + (const_int 12)
  29096. + (const_int 4))))])
  29097. +
  29098. +(define_insn "call_immediate"
  29099. + [(parallel [(call (mem (match_operand:SI 0 "nds32_symbolic_operand" "i"))
  29100. + (match_operand 1))
  29101. + (clobber (reg:SI LP_REGNUM))
  29102. + (clobber (reg:SI TA_REGNUM))])]
  29103. + "!NDS32_ALIGN_P ()"
  29104. +{
  29105. + return nds32_output_call (insn, operands, "bal\t%0", "jal\t%0", false);
  29106. +}
  29107. + [(set_attr "type" "branch")
  29108. + (set (attr "length")
  29109. + (if_then_else (match_test "flag_pic")
  29110. + (const_int 16)
  29111. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29112. + (const_int 12)
  29113. + (const_int 4))))])
  29114. +
  29115. +
  29116. +(define_insn "*cond_call_immediate"
  29117. + [(cond_exec (match_operator 0 "nds32_conditional_call_comparison_operator"
  29118. + [(match_operand:SI 1 "register_operand" "r")
  29119. + (const_int 0)])
  29120. + (parallel [(call (mem (match_operand:SI 2 "nds32_symbolic_operand" "i"))
  29121. + (match_operand 3))
  29122. + (clobber (reg:SI LP_REGNUM))
  29123. + (clobber (reg:SI TA_REGNUM))]))]
  29124. + "!flag_pic && !TARGET_CMODEL_LARGE"
  29125. +{
  29126. + switch (GET_CODE (operands[0]))
  29127. + {
  29128. + case LT:
  29129. + return "bltzal\t%1, %2";
  29130. + case GE:
  29131. + return "bgezal\t%1, %2";
  29132. + default:
  29133. + gcc_unreachable ();
  29134. + }
  29135. +}
  29136. + [(set_attr "type" "branch")
  29137. + (set_attr "length" "4")])
  29138. ;; Subroutine call instruction returning a value.
  29139. ;; operands[0]: It is the hard regiser in which the value is returned.
  29140. @@ -1938,58 +1585,319 @@
  29141. [(parallel [(set (match_operand 0)
  29142. (call (match_operand 1 "memory_operand" "")
  29143. (match_operand 2)))
  29144. - (clobber (reg:SI LP_REGNUM))])]
  29145. - ""
  29146. + (clobber (reg:SI LP_REGNUM))
  29147. + (clobber (reg:SI TA_REGNUM))])]
  29148. ""
  29149. + "nds32_expand_call_address (&operands[1]);"
  29150. )
  29151. -(define_insn "*call_value_register"
  29152. +(define_insn "call_value_register_align"
  29153. + [(parallel [(set (match_operand 0)
  29154. + (call (mem (match_operand:SI 1 "register_operand" "r, r"))
  29155. + (match_operand 2)))
  29156. + (clobber (reg:SI LP_REGNUM))
  29157. + (clobber (reg:SI TA_REGNUM))])]
  29158. + "NDS32_ALIGN_P ()"
  29159. +{
  29160. + rtx next_insn = next_active_insn (insn);
  29161. + bool align_p = !(next_insn && get_attr_length (next_insn) == 2);
  29162. + switch (which_alternative)
  29163. + {
  29164. + case 0:
  29165. + if (align_p)
  29166. + return "jral5\t%1\;.align 2";
  29167. + else
  29168. + return "jral5\t%1";
  29169. + case 1:
  29170. + if (align_p)
  29171. + return "jral\t%1\;.align 2";
  29172. + else
  29173. + return "jral\t%1";
  29174. + default:
  29175. + gcc_unreachable ();
  29176. + }
  29177. +}
  29178. + [(set_attr "type" "branch,branch")
  29179. + (set_attr "length" " 2, 4")
  29180. + (set_attr "relaxable" " no, yes")])
  29181. +
  29182. +(define_insn "call_value_register"
  29183. [(parallel [(set (match_operand 0)
  29184. (call (mem (match_operand:SI 1 "register_operand" "r, r"))
  29185. (match_operand 2)))
  29186. - (clobber (reg:SI LP_REGNUM))])]
  29187. + (clobber (reg:SI LP_REGNUM))
  29188. + (clobber (reg:SI TA_REGNUM))])]
  29189. + "!NDS32_ALIGN_P ()"
  29190. + "@
  29191. + jral5\t%1
  29192. + jral\t%1"
  29193. + [(set_attr "type" "branch,branch")
  29194. + (set_attr "length" " 2, 4")
  29195. + (set_attr "relaxable" " no, yes")])
  29196. +
  29197. +(define_insn "*cond_call_value_register"
  29198. + [(cond_exec (ne (match_operand:SI 0 "register_operand" "r")
  29199. + (const_int 0))
  29200. + (parallel [(set (match_operand 1)
  29201. + (call (mem (match_operand:SI 2 "register_operand" "0"))
  29202. + (match_operand 3)))
  29203. + (clobber (reg:SI LP_REGNUM))
  29204. + (clobber (reg:SI TA_REGNUM))]))]
  29205. + "TARGET_ISA_V3"
  29206. + "jralnez\t%0"
  29207. + [(set_attr "type" "branch")
  29208. + (set_attr "length" "4")])
  29209. +
  29210. +(define_insn "call_value_immediate_align"
  29211. + [(parallel [(set (match_operand 0)
  29212. + (call (mem (match_operand:SI 1 "nds32_symbolic_operand" "i"))
  29213. + (match_operand 2)))
  29214. + (clobber (reg:SI LP_REGNUM))
  29215. + (clobber (reg:SI TA_REGNUM))])]
  29216. + "NDS32_ALIGN_P ()"
  29217. +{
  29218. + rtx next_insn = next_active_insn (insn);
  29219. + bool align_p = next_insn && get_attr_length (next_insn) != 2;
  29220. +
  29221. + return nds32_output_call (insn, operands, "bal\t%1", "jal\t%1", align_p);
  29222. +}
  29223. + [(set_attr "type" "branch")
  29224. + (set (attr "length")
  29225. + (if_then_else (match_test "flag_pic")
  29226. + (const_int 16)
  29227. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29228. + (const_int 12)
  29229. + (const_int 4))))])
  29230. +
  29231. +(define_insn "call_value_immediate"
  29232. + [(parallel [(set (match_operand 0)
  29233. + (call (mem (match_operand:SI 1 "nds32_symbolic_operand" "i"))
  29234. + (match_operand 2)))
  29235. + (clobber (reg:SI LP_REGNUM))
  29236. + (clobber (reg:SI TA_REGNUM))])]
  29237. + "!NDS32_ALIGN_P ()"
  29238. +{
  29239. + return nds32_output_call (insn, operands, "bal\t%1", "jal\t%1", false);
  29240. +}
  29241. + [(set_attr "type" "branch")
  29242. + (set (attr "length")
  29243. + (if_then_else (match_test "flag_pic")
  29244. + (const_int 16)
  29245. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29246. + (const_int 12)
  29247. + (const_int 4))))])
  29248. +
  29249. +
  29250. +(define_insn "*cond_call_value_immediate"
  29251. + [(cond_exec (match_operator 0 "nds32_conditional_call_comparison_operator"
  29252. + [(match_operand:SI 1 "register_operand" "r")
  29253. + (const_int 0)])
  29254. + (parallel [(set (match_operand 2)
  29255. + (call (mem (match_operand:SI 3 "nds32_symbolic_operand" "i"))
  29256. + (match_operand 4)))
  29257. + (clobber (reg:SI LP_REGNUM))
  29258. + (clobber (reg:SI TA_REGNUM))]))]
  29259. + "!flag_pic && !TARGET_CMODEL_LARGE"
  29260. +{
  29261. + switch (GET_CODE (operands[0]))
  29262. + {
  29263. + case LT:
  29264. + return "bltzal\t%1, %3";
  29265. + case GE:
  29266. + return "bgezal\t%1, %3";
  29267. + default:
  29268. + gcc_unreachable ();
  29269. + }
  29270. +}
  29271. + [(set_attr "type" "branch")
  29272. + (set_attr "length" "4")])
  29273. +
  29274. +;; Call subroutine returning any type.
  29275. +
  29276. +(define_expand "untyped_call"
  29277. + [(parallel [(call (match_operand 0 "" "")
  29278. + (const_int 0))
  29279. + (match_operand 1 "" "")
  29280. + (match_operand 2 "" "")])]
  29281. + ""
  29282. +{
  29283. + int i;
  29284. +
  29285. + emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
  29286. +
  29287. + for (i = 0; i < XVECLEN (operands[2], 0); i++)
  29288. + {
  29289. + rtx set = XVECEXP (operands[2], 0, i);
  29290. + emit_move_insn (SET_DEST (set), SET_SRC (set));
  29291. + }
  29292. +
  29293. + /* The optimizer does not know that the call sets the function value
  29294. + registers we stored in the result block. We avoid problems by
  29295. + claiming that all hard registers are used and clobbered at this
  29296. + point. */
  29297. + emit_insn (gen_blockage ());
  29298. + DONE;
  29299. +})
  29300. +
  29301. +;; ----------------------------------------------------------------------------
  29302. +
  29303. +;; The sibcall patterns.
  29304. +
  29305. +;; sibcall
  29306. +;; sibcall_register
  29307. +;; sibcall_immediate
  29308. +
  29309. +(define_expand "sibcall"
  29310. + [(parallel [(call (match_operand 0 "memory_operand" "")
  29311. + (const_int 0))
  29312. + (clobber (reg:SI TA_REGNUM))
  29313. + (return)])]
  29314. + ""
  29315. + "nds32_expand_call_address (&operands[0]);"
  29316. +)
  29317. +
  29318. +(define_insn "*sibcall_register"
  29319. + [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
  29320. + (match_operand 1))
  29321. + (clobber (reg:SI TA_REGNUM))
  29322. + (return)])]
  29323. ""
  29324. "@
  29325. - jral5\t%1
  29326. - jral\t%1"
  29327. - [(set_attr "type" "branch,branch")
  29328. - (set_attr "length" " 2, 4")])
  29329. + jr5\t%0
  29330. + jr\t%0"
  29331. + [(set_attr "type" "branch,branch")
  29332. + (set_attr "length" " 2, 4")
  29333. + (set_attr "relaxable" " no, yes")])
  29334. +
  29335. +(define_insn "*sibcall_immediate"
  29336. + [(parallel [(call (mem (match_operand:SI 0 "nds32_symbolic_operand" "i"))
  29337. + (match_operand 1))
  29338. + (clobber (reg:SI TA_REGNUM))
  29339. + (return)])]
  29340. + ""
  29341. +{
  29342. + if (TARGET_CMODEL_LARGE)
  29343. + return "b\t%0";
  29344. + else
  29345. + return "j\t%0";
  29346. +}
  29347. + [(set_attr "type" "branch")
  29348. + (set (attr "length")
  29349. + (if_then_else (match_test "flag_pic")
  29350. + (const_int 16)
  29351. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29352. + (const_int 12)
  29353. + (const_int 4))))])
  29354. +
  29355. +;; sibcall_value
  29356. +;; sibcall_value_register
  29357. +;; sibcall_value_immediate
  29358. +
  29359. +(define_expand "sibcall_value"
  29360. + [(parallel [(set (match_operand 0)
  29361. + (call (match_operand 1 "memory_operand" "")
  29362. + (const_int 0)))
  29363. + (clobber (reg:SI TA_REGNUM))
  29364. + (return)])]
  29365. + ""
  29366. + "nds32_expand_call_address (&operands[1]);"
  29367. +)
  29368. -(define_insn "*call_value_immediate"
  29369. +(define_insn "*sibcall_value_register"
  29370. [(parallel [(set (match_operand 0)
  29371. - (call (mem (match_operand:SI 1 "immediate_operand" "i"))
  29372. + (call (mem (match_operand:SI 1 "register_operand" "r, r"))
  29373. (match_operand 2)))
  29374. - (clobber (reg:SI LP_REGNUM))])]
  29375. + (clobber (reg:SI TA_REGNUM))
  29376. + (return)])]
  29377. ""
  29378. - "jal\t%1"
  29379. + "@
  29380. + jr5\t%1
  29381. + jr\t%1"
  29382. + [(set_attr "type" "branch,branch")
  29383. + (set_attr "length" " 2, 4")
  29384. + (set_attr "relaxable" " no, yes")])
  29385. +
  29386. +(define_insn "*sibcall_value_immediate"
  29387. + [(parallel [(set (match_operand 0)
  29388. + (call (mem (match_operand:SI 1 "nds32_symbolic_operand" "i"))
  29389. + (match_operand 2)))
  29390. + (clobber (reg:SI TA_REGNUM))
  29391. + (return)])]
  29392. + ""
  29393. +{
  29394. + if (TARGET_CMODEL_LARGE)
  29395. + return "b\t%1";
  29396. + else
  29397. + return "j\t%1";
  29398. +}
  29399. [(set_attr "type" "branch")
  29400. - (set_attr "length" "4")])
  29401. + (set (attr "length")
  29402. + (if_then_else (match_test "flag_pic")
  29403. + (const_int 16)
  29404. + (if_then_else (match_test "TARGET_CMODEL_LARGE")
  29405. + (const_int 12)
  29406. + (const_int 4))))])
  29407. +;; ----------------------------------------------------------------------------
  29408. -;; prologue and epilogue.
  29409. +;; The prologue and epilogue.
  29410. (define_expand "prologue" [(const_int 0)]
  29411. ""
  29412. {
  29413. - /* Note that only under V3/V3M ISA, we could use v3push prologue. */
  29414. - if (TARGET_V3PUSH)
  29415. + /* Note that only under V3/V3M ISA, we could use v3push prologue.
  29416. + In addition, we need to check if v3push is indeed available. */
  29417. + if (NDS32_V3PUSH_AVAILABLE_P)
  29418. nds32_expand_prologue_v3push ();
  29419. else
  29420. nds32_expand_prologue ();
  29421. +
  29422. + /* If cfun->machine->fp_as_gp_p is true, we can generate special
  29423. + directive to guide linker doing fp-as-gp optimization.
  29424. + However, for a naked function, which means
  29425. + it should not have prologue/epilogue,
  29426. + using fp-as-gp still requires saving $fp by push/pop behavior and
  29427. + there is no benefit to use fp-as-gp on such small function.
  29428. + So we need to make sure this function is NOT naked as well. */
  29429. + if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p)
  29430. + emit_insn (gen_omit_fp_begin (gen_rtx_REG (SImode, FP_REGNUM)));
  29431. +
  29432. DONE;
  29433. })
  29434. (define_expand "epilogue" [(const_int 0)]
  29435. ""
  29436. {
  29437. - /* Note that only under V3/V3M ISA, we could use v3pop epilogue. */
  29438. - if (TARGET_V3PUSH)
  29439. - nds32_expand_epilogue_v3pop ();
  29440. + /* If cfun->machine->fp_as_gp_p is true, we can generate special
  29441. + directive to guide linker doing fp-as-gp optimization.
  29442. + However, for a naked function, which means
  29443. + it should not have prologue/epilogue,
  29444. + using fp-as-gp still requires saving $fp by push/pop behavior and
  29445. + there is no benefit to use fp-as-gp on such small function.
  29446. + So we need to make sure this function is NOT naked as well. */
  29447. + if (cfun->machine->fp_as_gp_p && !cfun->machine->naked_p)
  29448. + emit_insn (gen_omit_fp_end (gen_rtx_REG (SImode, FP_REGNUM)));
  29449. +
  29450. + /* Note that only under V3/V3M ISA, we could use v3pop epilogue.
  29451. + In addition, we need to check if v3push is indeed available. */
  29452. + if (NDS32_V3PUSH_AVAILABLE_P)
  29453. + nds32_expand_epilogue_v3pop (false);
  29454. else
  29455. - nds32_expand_epilogue ();
  29456. + nds32_expand_epilogue (false);
  29457. +
  29458. DONE;
  29459. })
  29460. +(define_expand "sibcall_epilogue" [(const_int 0)]
  29461. + ""
  29462. +{
  29463. + /* Pass true to indicate that this is sibcall epilogue and
  29464. + exit from a function without the final branch back to the
  29465. + calling function. */
  29466. + nds32_expand_epilogue (true);
  29467. +
  29468. + DONE;
  29469. +})
  29470. ;; nop instruction.
  29471. @@ -2003,7 +1911,7 @@
  29472. return "nop";
  29473. }
  29474. [(set_attr "type" "misc")
  29475. - (set_attr "enabled" "1")
  29476. + (set_attr "enabled" "yes")
  29477. (set (attr "length")
  29478. (if_then_else (match_test "TARGET_16_BIT")
  29479. (const_int 2)
  29480. @@ -2025,12 +1933,13 @@
  29481. ])]
  29482. ""
  29483. {
  29484. - return nds32_output_stack_push ();
  29485. + return nds32_output_stack_push (operands[0]);
  29486. }
  29487. - [(set_attr "type" "misc")
  29488. - (set_attr "enabled" "1")
  29489. + [(set_attr "type" "store_multiple")
  29490. + (set_attr "combo" "12")
  29491. + (set_attr "enabled" "yes")
  29492. (set (attr "length")
  29493. - (if_then_else (match_test "TARGET_V3PUSH")
  29494. + (if_then_else (match_test "NDS32_V3PUSH_AVAILABLE_P")
  29495. (const_int 2)
  29496. (const_int 4)))])
  29497. @@ -2045,41 +1954,82 @@
  29498. ])]
  29499. ""
  29500. {
  29501. - return nds32_output_stack_pop ();
  29502. + return nds32_output_stack_pop (operands[0]);
  29503. }
  29504. - [(set_attr "type" "misc")
  29505. - (set_attr "enabled" "1")
  29506. + [(set_attr "type" "load_multiple")
  29507. + (set_attr "combo" "12")
  29508. + (set_attr "enabled" "yes")
  29509. (set (attr "length")
  29510. - (if_then_else (match_test "TARGET_V3PUSH")
  29511. + (if_then_else (match_test "NDS32_V3PUSH_AVAILABLE_P")
  29512. (const_int 2)
  29513. (const_int 4)))])
  29514. ;; ----------------------------------------------------------------------------
  29515. -;; unspec operation patterns
  29516. +;; Return operation patterns
  29517. ;; ----------------------------------------------------------------------------
  29518. -;; In nds32 target, the 'ret5' instuction is actually 'jr5 $lp'.
  29519. -;; This pattern is designed to distinguish function return
  29520. -;; from general indirect_jump pattern so that we can directly
  29521. -;; generate 'ret5' for readability.
  29522. +;; Use this pattern to expand a return instruction
  29523. +;; with simple_return rtx if no epilogue is required.
  29524. +(define_expand "return"
  29525. + [(parallel [(return)
  29526. + (clobber (reg:SI FP_REGNUM))])]
  29527. + "nds32_can_use_return_insn ()"
  29528. +{
  29529. + /* Emit as the simple return. */
  29530. + if (!cfun->machine->fp_as_gp_p
  29531. + && cfun->machine->naked_p
  29532. + && (cfun->machine->va_args_size == 0))
  29533. + {
  29534. + emit_jump_insn (gen_return_internal ());
  29535. + DONE;
  29536. + }
  29537. +})
  29538. -(define_insn "unspec_volatile_func_return"
  29539. - [(set (pc)
  29540. - (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_FUNC_RETURN))]
  29541. +;; This pattern is expanded only by the shrink-wrapping optimization
  29542. +;; on paths where the function prologue has not been executed.
  29543. +;; However, such optimization may reorder the prologue/epilogue blocks
  29544. +;; together with basic blocks within function body.
  29545. +;; So we must disable this pattern if we have already decided
  29546. +;; to perform fp_as_gp optimization, which requires prologue to be
  29547. +;; first block and epilogue to be last block.
  29548. +(define_expand "simple_return"
  29549. + [(simple_return)]
  29550. + "!cfun->machine->fp_as_gp_p"
  29551. + ""
  29552. +)
  29553. +
  29554. +(define_insn "*nds32_return"
  29555. + [(parallel [(return)
  29556. + (clobber (reg:SI FP_REGNUM))])]
  29557. + ""
  29558. +{
  29559. + return nds32_output_return ();
  29560. +}
  29561. + [(set_attr "type" "branch")
  29562. + (set_attr "enabled" "yes")
  29563. + (set_attr "length" "4")])
  29564. +
  29565. +(define_insn "return_internal"
  29566. + [(simple_return)]
  29567. ""
  29568. {
  29569. + if (nds32_isr_function_critical_p (current_function_decl))
  29570. + return "iret";
  29571. +
  29572. if (TARGET_16_BIT)
  29573. return "ret5";
  29574. else
  29575. return "ret";
  29576. }
  29577. - [(set_attr "type" "misc")
  29578. - (set_attr "enabled" "1")
  29579. + [(set_attr "type" "branch")
  29580. + (set_attr "enabled" "yes")
  29581. (set (attr "length")
  29582. - (if_then_else (match_test "TARGET_16_BIT")
  29583. - (const_int 2)
  29584. - (const_int 4)))])
  29585. + (if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)")
  29586. + (const_int 4)
  29587. + (if_then_else (match_test "TARGET_16_BIT")
  29588. + (const_int 2)
  29589. + (const_int 4))))])
  29590. ;; ----------------------------------------------------------------------------
  29591. @@ -2114,6 +2064,7 @@
  29592. {
  29593. rtx add_tmp;
  29594. rtx reg, test;
  29595. + rtx tmp_reg;
  29596. /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */
  29597. if (operands[1] != const0_rtx)
  29598. @@ -2122,8 +2073,8 @@
  29599. add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
  29600. /* If the integer value is not in the range of imm15s,
  29601. - we need to force register first because our addsi3 pattern
  29602. - only accept nds32_rimm15s_operand predicate. */
  29603. + we need to force register first because our addsi3 pattern
  29604. + only accept nds32_rimm15s_operand predicate. */
  29605. add_tmp = force_reg (SImode, add_tmp);
  29606. emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
  29607. @@ -2135,11 +2086,14 @@
  29608. emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
  29609. operands[4]));
  29610. - operands[5] = gen_reg_rtx (SImode);
  29611. - /* Step C, D, E, and F, using another temporary register operands[5]. */
  29612. + tmp_reg = gen_reg_rtx (SImode);
  29613. + /* Step C, D, E, and F, using another temporary register tmp_reg. */
  29614. + if (flag_pic)
  29615. + emit_use (pic_offset_table_rtx);
  29616. +
  29617. emit_jump_insn (gen_casesi_internal (operands[0],
  29618. operands[3],
  29619. - operands[5]));
  29620. + tmp_reg));
  29621. DONE;
  29622. })
  29623. @@ -2166,7 +2120,7 @@
  29624. (const_int 4))
  29625. (label_ref (match_operand 1 "" "")))))
  29626. (use (label_ref (match_dup 1)))
  29627. - (clobber (match_operand:SI 2 "register_operand" ""))
  29628. + (clobber (match_operand:SI 2 "register_operand" "=r"))
  29629. (clobber (reg:SI TA_REGNUM))])]
  29630. ""
  29631. {
  29632. @@ -2175,17 +2129,34 @@
  29633. else
  29634. return nds32_output_casesi (operands);
  29635. }
  29636. - [(set_attr "length" "20")
  29637. - (set_attr "type" "alu")])
  29638. + [(set_attr "type" "branch")
  29639. + (set (attr "length")
  29640. + (if_then_else (match_test "flag_pic")
  29641. + (const_int 28)
  29642. + (const_int 20)))])
  29643. ;; ----------------------------------------------------------------------------
  29644. ;; Performance Extension
  29645. +; If -fwrapv option is issued, GCC expects there will be
  29646. +; signed overflow situation. So the ABS(INT_MIN) is still INT_MIN
  29647. +; (e.g. ABS(0x80000000)=0x80000000).
  29648. +; However, the hardware ABS instruction of nds32 target
  29649. +; always performs saturation: abs 0x80000000 -> 0x7fffffff.
  29650. +; So that we can only enable abssi2 pattern if flag_wrapv is NOT presented.
  29651. +(define_insn "abssi2"
  29652. + [(set (match_operand:SI 0 "register_operand" "=r")
  29653. + (abs:SI (match_operand:SI 1 "register_operand" " r")))]
  29654. + "TARGET_EXT_PERF && TARGET_HW_ABS && !flag_wrapv"
  29655. + "abs\t%0, %1"
  29656. + [(set_attr "type" "alu")
  29657. + (set_attr "length" "4")])
  29658. +
  29659. (define_insn "clzsi2"
  29660. [(set (match_operand:SI 0 "register_operand" "=r")
  29661. (clz:SI (match_operand:SI 1 "register_operand" " r")))]
  29662. - "TARGET_PERF_EXT"
  29663. + "TARGET_EXT_PERF"
  29664. "clz\t%0, %1"
  29665. [(set_attr "type" "alu")
  29666. (set_attr "length" "4")])
  29667. @@ -2194,28 +2165,436 @@
  29668. [(set (match_operand:SI 0 "register_operand" "=r")
  29669. (smax:SI (match_operand:SI 1 "register_operand" " r")
  29670. (match_operand:SI 2 "register_operand" " r")))]
  29671. - "TARGET_PERF_EXT"
  29672. + "TARGET_EXT_PERF"
  29673. "max\t%0, %1, %2"
  29674. [(set_attr "type" "alu")
  29675. (set_attr "length" "4")])
  29676. +(define_expand "uminqi3"
  29677. + [(set (match_operand:QI 0 "register_operand" "")
  29678. + (umin:QI (match_operand:QI 1 "register_operand" "")
  29679. + (match_operand:QI 2 "register_operand" "")))]
  29680. + "TARGET_EXT_PERF"
  29681. +{
  29682. + rtx tmpop[3];
  29683. + tmpop[0] = gen_reg_rtx (SImode);
  29684. + tmpop[1] = gen_reg_rtx (SImode);
  29685. + tmpop[2] = gen_reg_rtx (SImode);
  29686. +
  29687. + emit_insn (gen_zero_extendqisi2 (tmpop[1], operands[1]));
  29688. + emit_insn (gen_zero_extendqisi2 (tmpop[2], operands[2]));
  29689. + emit_insn (gen_sminsi3 (tmpop[0], tmpop[1], tmpop[2]));
  29690. + convert_move (operands[0], tmpop[0], false);
  29691. + DONE;
  29692. +})
  29693. +
  29694. +(define_expand "sminqi3"
  29695. + [(set (match_operand:QI 0 "register_operand" "")
  29696. + (smin:QI (match_operand:QI 1 "register_operand" "")
  29697. + (match_operand:QI 2 "register_operand" "")))]
  29698. + "TARGET_EXT_PERF"
  29699. +{
  29700. + rtx tmpop[3];
  29701. + tmpop[0] = gen_reg_rtx (SImode);
  29702. + tmpop[1] = gen_reg_rtx (SImode);
  29703. + tmpop[2] = gen_reg_rtx (SImode);
  29704. +
  29705. + emit_insn (gen_extendqisi2 (tmpop[1], operands[1]));
  29706. + emit_insn (gen_extendqisi2 (tmpop[2], operands[2]));
  29707. + emit_insn (gen_sminsi3 (tmpop[0], tmpop[1], tmpop[2]));
  29708. + convert_move (operands[0], tmpop[0], false);
  29709. + DONE;
  29710. +})
  29711. +
  29712. +(define_expand "uminhi3"
  29713. + [(set (match_operand:HI 0 "register_operand" "")
  29714. + (umin:HI (match_operand:HI 1 "register_operand" "")
  29715. + (match_operand:HI 2 "register_operand" "")))]
  29716. + "TARGET_EXT_PERF"
  29717. +{
  29718. + rtx tmpop[3];
  29719. + tmpop[0] = gen_reg_rtx (SImode);
  29720. + tmpop[1] = gen_reg_rtx (SImode);
  29721. + tmpop[2] = gen_reg_rtx (SImode);
  29722. +
  29723. + emit_insn (gen_zero_extendhisi2 (tmpop[1], operands[1]));
  29724. + emit_insn (gen_zero_extendhisi2 (tmpop[2], operands[2]));
  29725. + emit_insn (gen_sminsi3 (tmpop[0], tmpop[1], tmpop[2]));
  29726. + convert_move (operands[0], tmpop[0], false);
  29727. + DONE;
  29728. +})
  29729. +
  29730. +(define_expand "sminhi3"
  29731. + [(set (match_operand:HI 0 "register_operand" "")
  29732. + (smin:HI (match_operand:HI 1 "register_operand" "")
  29733. + (match_operand:HI 2 "register_operand" "")))]
  29734. + "TARGET_EXT_PERF"
  29735. +{
  29736. + rtx tmpop[3];
  29737. + tmpop[0] = gen_reg_rtx (SImode);
  29738. + tmpop[1] = gen_reg_rtx (SImode);
  29739. + tmpop[2] = gen_reg_rtx (SImode);
  29740. +
  29741. + emit_insn (gen_extendhisi2 (tmpop[1], operands[1]));
  29742. + emit_insn (gen_extendhisi2 (tmpop[2], operands[2]));
  29743. + emit_insn (gen_sminsi3 (tmpop[0], tmpop[1], tmpop[2]));
  29744. + convert_move (operands[0], tmpop[0], false);
  29745. + DONE;
  29746. +})
  29747. +
  29748. (define_insn "sminsi3"
  29749. [(set (match_operand:SI 0 "register_operand" "=r")
  29750. (smin:SI (match_operand:SI 1 "register_operand" " r")
  29751. (match_operand:SI 2 "register_operand" " r")))]
  29752. - "TARGET_PERF_EXT"
  29753. + "TARGET_EXT_PERF"
  29754. "min\t%0, %1, %2"
  29755. [(set_attr "type" "alu")
  29756. (set_attr "length" "4")])
  29757. (define_insn "*btst"
  29758. - [(set (match_operand:SI 0 "register_operand" "= r")
  29759. - (zero_extract:SI (match_operand:SI 1 "register_operand" " r")
  29760. + [(set (match_operand:SI 0 "register_operand" "= r")
  29761. + (zero_extract:SI (match_operand:SI 1 "register_operand" " r")
  29762. (const_int 1)
  29763. - (match_operand:SI 2 "immediate_operand" " Iu05")))]
  29764. - "TARGET_PERF_EXT"
  29765. + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")))]
  29766. + "TARGET_EXT_PERF"
  29767. "btst\t%0, %1, %2"
  29768. [(set_attr "type" "alu")
  29769. (set_attr "length" "4")])
  29770. ;; ----------------------------------------------------------------------------
  29771. +
  29772. +;; Pseudo NOPs
  29773. +
  29774. +;; Structural hazards NOP
  29775. +(define_insn "nop_res_dep"
  29776. + [(unspec [(match_operand 0 "const_int_operand" "i")] UNSPEC_VOLATILE_RES_DEP)]
  29777. + ""
  29778. + "! structural dependency (%0 cycles)"
  29779. + [(set_attr "length" "0")]
  29780. +)
  29781. +
  29782. +;; Data hazards NOP
  29783. +(define_insn "nop_data_dep"
  29784. + [(unspec [(match_operand 0 "const_int_operand" "i")] UNSPEC_VOLATILE_DATA_DEP)]
  29785. + ""
  29786. + "! data dependency (%0 cycles)"
  29787. + [(set_attr "length" "0")]
  29788. +)
  29789. +
  29790. +(define_insn "relax_group"
  29791. + [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)]
  29792. + ""
  29793. + ".relax_hint %0"
  29794. + [(set_attr "length" "0")]
  29795. +)
  29796. +
  29797. +(define_insn "innermost_loop_begin"
  29798. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_INNERMOST_LOOP_BEGIN)]
  29799. + ""
  29800. + ".innermost_loop_begin"
  29801. + [(set_attr "length" "0")]
  29802. +)
  29803. +
  29804. +(define_insn "innermost_loop_end"
  29805. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_INNERMOST_LOOP_END)]
  29806. + ""
  29807. + ".innermost_loop_end"
  29808. + [(set_attr "length" "0")]
  29809. +)
  29810. +
  29811. +(define_insn "no_ifc_begin"
  29812. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NO_IFC_BEGIN)]
  29813. + ""
  29814. + ".no_ifc_begin"
  29815. + [(set_attr "length" "0")]
  29816. +)
  29817. +
  29818. +(define_insn "no_ifc_end"
  29819. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NO_IFC_END)]
  29820. + ""
  29821. + ".no_ifc_end"
  29822. + [(set_attr "length" "0")]
  29823. +)
  29824. +
  29825. +(define_insn "no_ex9_begin"
  29826. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NO_EX9_BEGIN)]
  29827. + ""
  29828. + ".no_ex9_begin"
  29829. + [(set_attr "length" "0")]
  29830. +)
  29831. +
  29832. +(define_insn "no_ex9_end"
  29833. + [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NO_EX9_END)]
  29834. + ""
  29835. + ".no_ex9_end"
  29836. + [(set_attr "length" "0")]
  29837. +)
  29838. +
  29839. +;; Output .omit_fp_begin for fp-as-gp optimization.
  29840. +;; Also we have to set $fp register.
  29841. +(define_insn "omit_fp_begin"
  29842. + [(set (match_operand:SI 0 "register_operand" "=x")
  29843. + (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_OMIT_FP_BEGIN))]
  29844. + ""
  29845. + "! -----\;.omit_fp_begin\;la\t$fp,_FP_BASE_\;! -----"
  29846. + [(set_attr "length" "8")]
  29847. +)
  29848. +
  29849. +;; Output .omit_fp_end for fp-as-gp optimization.
  29850. +;; Claim that we have to use $fp register.
  29851. +(define_insn "omit_fp_end"
  29852. + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "x")] UNSPEC_VOLATILE_OMIT_FP_END)]
  29853. + ""
  29854. + "! -----\;.omit_fp_end\;! -----"
  29855. + [(set_attr "length" "0")]
  29856. +)
  29857. +
  29858. +(define_insn "pop25return"
  29859. + [(return)
  29860. + (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)]
  29861. + ""
  29862. + "! return for pop 25"
  29863. + [(set_attr "length" "0")]
  29864. +)
  29865. +
  29866. +;; Add pc
  29867. +(define_insn "add_pc"
  29868. + [(set (match_operand:SI 0 "register_operand" "=r")
  29869. + (plus:SI (match_operand:SI 1 "register_operand" "0")
  29870. + (pc)))]
  29871. + "TARGET_LINUX_ABI || flag_pic"
  29872. + "add5.pc\t%0"
  29873. + [(set_attr "type" "alu")
  29874. + (set_attr "length" "4")]
  29875. +)
  29876. +
  29877. +(define_expand "bswapsi2"
  29878. + [(set (match_operand:SI 0 "register_operand" "=r")
  29879. + (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
  29880. + ""
  29881. +{
  29882. + emit_insn (gen_unspec_wsbh (operands[0], operands[1]));
  29883. + emit_insn (gen_rotrsi3 (operands[0], operands[0], GEN_INT (16)));
  29884. + DONE;
  29885. +})
  29886. +
  29887. +(define_insn "bswaphi2"
  29888. + [(set (match_operand:HI 0 "register_operand" "=r")
  29889. + (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
  29890. + ""
  29891. + "wsbh\t%0, %1"
  29892. + [(set_attr "type" "alu")
  29893. + (set_attr "length" "4")]
  29894. +)
  29895. +
  29896. +;; Hardware loop
  29897. +
  29898. +; operand 0 is the loop count pseudo register
  29899. +; operand 1 is the label to jump to at the top of the loop
  29900. +(define_expand "doloop_end"
  29901. + [(parallel [(set (pc) (if_then_else
  29902. + (ne (match_operand:SI 0 "" "")
  29903. + (const_int 1))
  29904. + (label_ref (match_operand 1 "" ""))
  29905. + (pc)))
  29906. + (set (match_dup 0)
  29907. + (plus:SI (match_dup 0)
  29908. + (const_int -1)))
  29909. + (unspec [(const_int 0)] UNSPEC_LOOP_END)
  29910. + (clobber (match_dup 2))])] ; match_scratch
  29911. + "NDS32_HW_LOOP_P ()"
  29912. +{
  29913. + /* The loop optimizer doesn't check the predicates... */
  29914. + if (GET_MODE (operands[0]) != SImode)
  29915. + FAIL;
  29916. + operands[2] = gen_rtx_SCRATCH (SImode);
  29917. +})
  29918. +
  29919. +(define_insn "loop_end"
  29920. + [(set (pc)
  29921. + (if_then_else (ne (match_operand:SI 3 "nonimmediate_operand" "0, 0, *r")
  29922. + (const_int 1))
  29923. + (label_ref (match_operand 1 "" ""))
  29924. + (pc)))
  29925. + (set (match_operand:SI 0 "nonimmediate_operand" "=r, m, m")
  29926. + (plus:SI (match_dup 3)
  29927. + (const_int -1)))
  29928. + (unspec [(const_int 0)] UNSPEC_LOOP_END)
  29929. + (clobber (match_scratch:SI 2 "=X, &r, &r"))]
  29930. + "NDS32_HW_LOOP_P ()"
  29931. + "#"
  29932. + [(set_attr "length" "12, 12, 12")])
  29933. +
  29934. +(define_split
  29935. + [(set (pc)
  29936. + (if_then_else (ne (match_operand:SI 3 "nonimmediate_operand" "")
  29937. + (const_int 1))
  29938. + (label_ref (match_operand 1 "" ""))
  29939. + (pc)))
  29940. + (set (match_operand:SI 0 "memory_operand" "")
  29941. + (plus:SI (match_dup 3)
  29942. + (const_int -1)))
  29943. + (unspec [(const_int 0)] UNSPEC_LOOP_END)
  29944. + (clobber (match_scratch:SI 2 ""))]
  29945. + "NDS32_HW_LOOP_P ()"
  29946. + [(set (match_dup 2) (plus:SI (match_dup 3) (const_int -1)))
  29947. + (set (match_dup 0) (match_dup 2))
  29948. + (set (pc)
  29949. + (if_then_else (ne (match_dup 2) (const_int 0))
  29950. + (label_ref (match_dup 1))
  29951. + (pc)))]
  29952. +{
  29953. + if (!REG_P (operands[3]))
  29954. + {
  29955. + emit_move_insn (operands[2], operands[3]);
  29956. + operands[3] = operands[2];
  29957. + }
  29958. +})
  29959. +
  29960. +(define_insn "mtlbi_hint"
  29961. + [(set (reg:SI LB_REGNUM)
  29962. + (match_operand:SI 0 "nds32_label_operand" "i"))
  29963. + (unspec [(match_operand 1 "const_int_operand" "i")] UNSPEC_LOOP_END)]
  29964. + "NDS32_HW_LOOP_P ()"
  29965. + "mtlbi\t%0"
  29966. + [(set_attr "length" "4")])
  29967. +
  29968. +(define_insn "mtlbi"
  29969. + [(set (reg:SI LB_REGNUM)
  29970. + (match_operand:SI 0 "nds32_label_operand" "i"))]
  29971. + "NDS32_HW_LOOP_P ()"
  29972. + "mtlbi\t%0"
  29973. + [(set_attr "length" "4")])
  29974. +
  29975. +(define_insn "mtlei"
  29976. + [(set (reg:SI LE_REGNUM)
  29977. + (match_operand:SI 0 "nds32_label_operand" "i"))]
  29978. + "NDS32_HW_LOOP_P ()"
  29979. + "mtlei\t%0"
  29980. + [(set_attr "length" "4")])
  29981. +
  29982. +(define_insn "init_lc"
  29983. + [(set (reg:SI LC_REGNUM)
  29984. + (match_operand:SI 0 "register_operand" "r"))
  29985. + (unspec [(match_operand 1 "const_int_operand" "i")] UNSPEC_LOOP_END)]
  29986. + "NDS32_HW_LOOP_P ()"
  29987. + "mtusr\t%0, LC"
  29988. + [(set_attr "length" "4")])
  29989. +
  29990. +; After replace hwloop, use this is pattern to get right CFG
  29991. +(define_insn "hwloop_cfg"
  29992. + [(set (pc)
  29993. + (if_then_else (ne (reg:SI LC_REGNUM)
  29994. + (const_int 1))
  29995. + (match_operand:SI 1 "nds32_label_operand" "i")
  29996. + (pc)))
  29997. + (set (reg:SI LC_REGNUM)
  29998. + (plus:SI (reg:SI LC_REGNUM)
  29999. + (const_int -1)))
  30000. + (use (reg:SI LB_REGNUM))
  30001. + (use (reg:SI LE_REGNUM))
  30002. + (use (reg:SI LC_REGNUM))
  30003. + (unspec [(match_operand 0 "const_int_operand" "i")] UNSPEC_LOOP_END)]
  30004. + "TARGET_HWLOOP"
  30005. + ""
  30006. + [(set_attr "length" "0")])
  30007. +;; ----------------------------------------------------------------------------
  30008. +
  30009. +;; Patterns for exception handling
  30010. +
  30011. +(define_expand "eh_return"
  30012. + [(use (match_operand 0 "general_operand"))]
  30013. + ""
  30014. +{
  30015. + emit_insn (gen_nds32_eh_return (operands[0]));
  30016. + DONE;
  30017. +})
  30018. +
  30019. +(define_insn_and_split "nds32_eh_return"
  30020. + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_EH_RETURN)]
  30021. + ""
  30022. + "#"
  30023. + "reload_completed"
  30024. + [(const_int 0)]
  30025. +{
  30026. + rtx place;
  30027. + rtx addr;
  30028. +
  30029. + /* The operands[0] is the handler address. We need to assign it
  30030. + to return address rtx so that we can jump to exception handler
  30031. + when returning from current function. */
  30032. +
  30033. + if (cfun->machine->lp_size == 0)
  30034. + {
  30035. + /* If $lp is not saved in the stack frame, we can take $lp directly. */
  30036. + place = gen_rtx_REG (SImode, LP_REGNUM);
  30037. + }
  30038. + else
  30039. + {
  30040. + /* Otherwise, we need to locate the stack slot of return address.
  30041. + The return address is generally saved in [$fp-4] location.
  30042. + However, DSE (dead store elimination) does not detect an alias
  30043. + between [$fp-x] and [$sp+y]. This can result in a store to save
  30044. + $lp introduced by builtin_eh_return() being incorrectly deleted
  30045. + if it is based on $fp. The solution we take here is to compute
  30046. + the offset relative to stack pointer and then use $sp to access
  30047. + location so that the alias can be detected.
  30048. + FIXME: What if the immediate value "offset" is too large to be
  30049. + fit in a single addi instruction? */
  30050. + HOST_WIDE_INT offset;
  30051. +
  30052. + offset = (cfun->machine->fp_size
  30053. + + cfun->machine->gp_size
  30054. + + cfun->machine->lp_size
  30055. + + cfun->machine->callee_saved_gpr_regs_size
  30056. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  30057. + + cfun->machine->callee_saved_fpr_regs_size
  30058. + + cfun->machine->eh_return_data_regs_size
  30059. + + cfun->machine->local_size
  30060. + + cfun->machine->out_args_size);
  30061. +
  30062. + addr = plus_constant (Pmode, stack_pointer_rtx, offset - 4);
  30063. + place = gen_frame_mem (SImode, addr);
  30064. + }
  30065. +
  30066. + emit_move_insn (place, operands[0]);
  30067. + DONE;
  30068. +})
  30069. +
  30070. +;; ----------------------------------------------------------------------------
  30071. +
  30072. +;; Patterns for TLS.
  30073. +
  30074. +(define_insn "tls_desc"
  30075. + [(set (reg:SI 0)
  30076. + (call (unspec_volatile:SI [(match_operand:SI 0 "nds32_symbolic_operand" "i")] UNSPEC_TLS_DESC)
  30077. + (const_int 1)))
  30078. + (use (unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP))
  30079. + (use (reg:SI GP_REGNUM))
  30080. + (clobber (reg:SI LP_REGNUM))
  30081. + (clobber (reg:SI TA_REGNUM))]
  30082. + ""
  30083. + {
  30084. + return nds32_output_tls_desc (operands);
  30085. + }
  30086. + [(set_attr "length" "20")
  30087. + (set_attr "type" "branch")]
  30088. +)
  30089. +
  30090. +
  30091. +(define_insn "tls_ie"
  30092. + [(set (match_operand:SI 0 "register_operand" "=r")
  30093. + (unspec:SI [(match_operand:SI 1 "nds32_symbolic_operand" "i")] UNSPEC_TLS_IE))
  30094. + (use (unspec [(match_operand:SI 2 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP))
  30095. + (use (reg:SI GP_REGNUM))]
  30096. + ""
  30097. + {
  30098. + return nds32_output_tls_ie (operands);
  30099. + }
  30100. + [(set (attr "length") (if_then_else (match_test "flag_pic")
  30101. + (const_int 12)
  30102. + (const_int 8)))
  30103. + (set_attr "type" "misc")]
  30104. +)
  30105. +
  30106. +;; ----------------------------------------------------------------------------
  30107. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-md-auxiliary.c gcc-4.9.4/gcc/config/nds32/nds32-md-auxiliary.c
  30108. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-md-auxiliary.c 1970-01-01 01:00:00.000000000 +0100
  30109. +++ gcc-4.9.4/gcc/config/nds32/nds32-md-auxiliary.c 2016-08-08 20:37:45.506270091 +0200
  30110. @@ -0,0 +1,3772 @@
  30111. +/* Auxiliary functions for output asm template or expand rtl
  30112. + pattern of Andes NDS32 cpu for GNU compiler
  30113. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  30114. + Contributed by Andes Technology Corporation.
  30115. +
  30116. + This file is part of GCC.
  30117. +
  30118. + GCC is free software; you can redistribute it and/or modify it
  30119. + under the terms of the GNU General Public License as published
  30120. + by the Free Software Foundation; either version 3, or (at your
  30121. + option) any later version.
  30122. +
  30123. + GCC is distributed in the hope that it will be useful, but WITHOUT
  30124. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  30125. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  30126. + License for more details.
  30127. +
  30128. + You should have received a copy of the GNU General Public License
  30129. + along with GCC; see the file COPYING3. If not see
  30130. + <http://www.gnu.org/licenses/>. */
  30131. +
  30132. +/* ------------------------------------------------------------------------ */
  30133. +
  30134. +#include "config.h"
  30135. +#include "system.h"
  30136. +#include "coretypes.h"
  30137. +#include "tm.h"
  30138. +#include "tree.h"
  30139. +#include "rtl.h"
  30140. +#include "regs.h"
  30141. +#include "hard-reg-set.h"
  30142. +#include "insn-config.h" /* Required by recog.h. */
  30143. +#include "conditions.h"
  30144. +#include "output.h"
  30145. +#include "insn-attr.h" /* For DFA state_t. */
  30146. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  30147. +#include "reload.h" /* For push_reload(). */
  30148. +#include "flags.h"
  30149. +#include "function.h"
  30150. +#include "expr.h"
  30151. +#include "recog.h"
  30152. +#include "diagnostic-core.h"
  30153. +#include "df.h"
  30154. +#include "tm_p.h"
  30155. +#include "tm-constrs.h"
  30156. +#include "optabs.h" /* For GEN_FCN. */
  30157. +#include "target.h"
  30158. +#include "target-def.h"
  30159. +#include "langhooks.h" /* For add_builtin_function(). */
  30160. +#include "ggc.h"
  30161. +
  30162. +/* ------------------------------------------------------------------------ */
  30163. +
  30164. +/* This file is divided into three parts:
  30165. +
  30166. + PART 1: Auxiliary static function definitions.
  30167. +
  30168. + PART 2: Auxiliary function for expand RTL pattern.
  30169. +
  30170. + PART 3: Auxiliary function for output asm template. */
  30171. +
  30172. +/* ------------------------------------------------------------------------ */
  30173. +
  30174. +/* PART 1: Auxiliary static function definitions. */
  30175. +
  30176. +static int
  30177. +nds32_regno_to_enable4 (unsigned regno)
  30178. +{
  30179. + switch (regno)
  30180. + {
  30181. + case 28: /* $r28/fp */
  30182. + return 0x8;
  30183. + case 29: /* $r29/gp */
  30184. + return 0x4;
  30185. + case 30: /* $r30/lp */
  30186. + return 0x2;
  30187. + case 31: /* $r31/sp */
  30188. + return 0x1;
  30189. + default:
  30190. + gcc_unreachable ();
  30191. + }
  30192. +}
  30193. +
  30194. +/* A helper function to return character based on byte size. */
  30195. +static char
  30196. +nds32_byte_to_size (int byte)
  30197. +{
  30198. + switch (byte)
  30199. + {
  30200. + case 4:
  30201. + return 'w';
  30202. + case 2:
  30203. + return 'h';
  30204. + case 1:
  30205. + return 'b';
  30206. + default:
  30207. + /* Normally it should not be here. */
  30208. + gcc_unreachable ();
  30209. + }
  30210. +}
  30211. +
  30212. +static int
  30213. +nds32_inverse_cond_code (int code)
  30214. +{
  30215. + switch (code)
  30216. + {
  30217. + case NE:
  30218. + return EQ;
  30219. + case EQ:
  30220. + return NE;
  30221. + case GT:
  30222. + return LE;
  30223. + case LE:
  30224. + return GT;
  30225. + case GE:
  30226. + return LT;
  30227. + case LT:
  30228. + return GE;
  30229. + default:
  30230. + gcc_unreachable ();
  30231. + }
  30232. +}
  30233. +
  30234. +static const char *
  30235. +nds32_cond_code_str (int code)
  30236. +{
  30237. + switch (code)
  30238. + {
  30239. + case NE:
  30240. + return "ne";
  30241. + case EQ:
  30242. + return "eq";
  30243. + case GT:
  30244. + return "gt";
  30245. + case LE:
  30246. + return "le";
  30247. + case GE:
  30248. + return "ge";
  30249. + case LT:
  30250. + return "lt";
  30251. + default:
  30252. + gcc_unreachable ();
  30253. + }
  30254. +}
  30255. +
  30256. +static void
  30257. +output_cond_branch (int code, const char *suffix, bool r5_p,
  30258. + bool long_jump_p, rtx *operands)
  30259. +{
  30260. + char pattern[256];
  30261. + const char *cond_code;
  30262. + bool align_p = NDS32_ALIGN_P ();
  30263. + const char *align = align_p ? "\t.align\t2\n" : "";
  30264. +
  30265. + if (r5_p && REGNO (operands[2]) == 5 && TARGET_16_BIT)
  30266. + {
  30267. + /* This is special case for beqs38 and bnes38,
  30268. + second operand 2 can't be $r5 and it's almost meanless,
  30269. + however it may occur after copy propgation. */
  30270. + if (code == EQ)
  30271. + {
  30272. + /* $r5 == $r5 always taken! */
  30273. + if (long_jump_p)
  30274. + snprintf (pattern, sizeof (pattern),
  30275. + "j\t%%3");
  30276. + else
  30277. + snprintf (pattern, sizeof (pattern),
  30278. + "j8\t%%3");
  30279. + }
  30280. + else
  30281. + /* Don't output anything since $r5 != $r5 never taken! */
  30282. + pattern[0] = '\0';
  30283. + }
  30284. + else if (long_jump_p)
  30285. + {
  30286. + int inverse_code = nds32_inverse_cond_code (code);
  30287. + cond_code = nds32_cond_code_str (inverse_code);
  30288. +
  30289. + /* b<cond><suffix> $r0, $r1, .L0
  30290. + =>
  30291. + b<inverse_cond><suffix> $r0, $r1, .LCB0
  30292. + j .L0
  30293. + .LCB0:
  30294. +
  30295. + or
  30296. +
  30297. + b<cond><suffix> $r0, $r1, .L0
  30298. + =>
  30299. + b<inverse_cond><suffix> $r0, $r1, .LCB0
  30300. + j .L0
  30301. + .LCB0:
  30302. + */
  30303. + if (r5_p && TARGET_16_BIT)
  30304. + {
  30305. + snprintf (pattern, sizeof (pattern),
  30306. + "b%ss38\t %%2, .LCB%%=\n\tj\t%%3\n%s.LCB%%=:",
  30307. + cond_code, align);
  30308. + }
  30309. + else
  30310. + {
  30311. + snprintf (pattern, sizeof (pattern),
  30312. + "b%s%s\t%%1, %%2, .LCB%%=\n\tj\t%%3\n%s.LCB%%=:",
  30313. + cond_code, suffix, align);
  30314. + }
  30315. + }
  30316. + else
  30317. + {
  30318. + cond_code = nds32_cond_code_str (code);
  30319. + if (r5_p && TARGET_16_BIT)
  30320. + {
  30321. + /* b<cond>s38 $r1, .L0 */
  30322. + snprintf (pattern, sizeof (pattern),
  30323. + "b%ss38\t %%2, %%3", cond_code);
  30324. + }
  30325. + else
  30326. + {
  30327. + /* b<cond><suffix> $r0, $r1, .L0 */
  30328. + snprintf (pattern, sizeof (pattern),
  30329. + "b%s%s\t%%1, %%2, %%3", cond_code, suffix);
  30330. + }
  30331. + }
  30332. +
  30333. + output_asm_insn (pattern, operands);
  30334. +}
  30335. +
  30336. +static void
  30337. +output_cond_branch_compare_zero (int code, const char *suffix,
  30338. + bool long_jump_p, rtx *operands,
  30339. + bool ta_implied_p)
  30340. +{
  30341. + char pattern[256];
  30342. + const char *cond_code;
  30343. + bool align_p = NDS32_ALIGN_P ();
  30344. + const char *align = align_p ? "\t.align\t2\n" : "";
  30345. + if (long_jump_p)
  30346. + {
  30347. + int inverse_code = nds32_inverse_cond_code (code);
  30348. + cond_code = nds32_cond_code_str (inverse_code);
  30349. +
  30350. + if (ta_implied_p && TARGET_16_BIT)
  30351. + {
  30352. + /* b<cond>z<suffix> .L0
  30353. + =>
  30354. + b<inverse_cond>z<suffix> .LCB0
  30355. + j .L0
  30356. + .LCB0:
  30357. + */
  30358. + snprintf (pattern, sizeof (pattern),
  30359. + "b%sz%s\t.LCB%%=\n\tj\t%%2\n%s.LCB%%=:",
  30360. + cond_code, suffix, align);
  30361. + }
  30362. + else
  30363. + {
  30364. + /* b<cond>z<suffix> $r0, .L0
  30365. + =>
  30366. + b<inverse_cond>z<suffix> $r0, .LCB0
  30367. + j .L0
  30368. + .LCB0:
  30369. + */
  30370. + snprintf (pattern, sizeof (pattern),
  30371. + "b%sz%s\t%%1, .LCB%%=\n\tj\t%%2\n%s.LCB%%=:",
  30372. + cond_code, suffix, align);
  30373. + }
  30374. + }
  30375. + else
  30376. + {
  30377. + cond_code = nds32_cond_code_str (code);
  30378. + if (ta_implied_p && TARGET_16_BIT)
  30379. + {
  30380. + /* b<cond>z<suffix> .L0 */
  30381. + snprintf (pattern, sizeof (pattern),
  30382. + "b%sz%s\t%%2", cond_code, suffix);
  30383. + }
  30384. + else
  30385. + {
  30386. + /* b<cond>z<suffix> $r0, .L0 */
  30387. + snprintf (pattern, sizeof (pattern),
  30388. + "b%sz%s\t%%1, %%2", cond_code, suffix);
  30389. + }
  30390. + }
  30391. +
  30392. + output_asm_insn (pattern, operands);
  30393. +}
  30394. +
  30395. +static void
  30396. +nds32_split_shiftrtdi3 (rtx dst, rtx src, rtx shiftamount, bool logic_shift_p)
  30397. +{
  30398. + rtx src_high_part;
  30399. + rtx dst_high_part, dst_low_part;
  30400. +
  30401. + dst_high_part = nds32_di_high_part_subreg (dst);
  30402. + src_high_part = nds32_di_high_part_subreg (src);
  30403. + dst_low_part = nds32_di_low_part_subreg (dst);
  30404. +
  30405. + if (CONST_INT_P (shiftamount))
  30406. + {
  30407. + if (INTVAL (shiftamount) < 32)
  30408. + {
  30409. + if (logic_shift_p)
  30410. + {
  30411. + emit_insn (gen_uwext (dst_low_part, src,
  30412. + shiftamount));
  30413. + emit_insn (gen_lshrsi3 (dst_high_part, src_high_part,
  30414. + shiftamount));
  30415. + }
  30416. + else
  30417. + {
  30418. + emit_insn (gen_wext (dst_low_part, src,
  30419. + shiftamount));
  30420. + emit_insn (gen_ashrsi3 (dst_high_part, src_high_part,
  30421. + shiftamount));
  30422. + }
  30423. + }
  30424. + else
  30425. + {
  30426. + rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode);
  30427. +
  30428. + if (logic_shift_p)
  30429. + {
  30430. + emit_insn (gen_lshrsi3 (dst_low_part, src_high_part,
  30431. + new_shift_amout));
  30432. + emit_move_insn (dst_high_part, const0_rtx);
  30433. + }
  30434. + else
  30435. + {
  30436. + emit_insn (gen_ashrsi3 (dst_low_part, src_high_part,
  30437. + new_shift_amout));
  30438. + emit_insn (gen_ashrsi3 (dst_high_part, src_high_part,
  30439. + GEN_INT (31)));
  30440. + }
  30441. + }
  30442. + }
  30443. + else
  30444. + {
  30445. + rtx dst_low_part_l32, dst_high_part_l32;
  30446. + rtx dst_low_part_g32, dst_high_part_g32;
  30447. + rtx new_shift_amout, select_reg;
  30448. + dst_low_part_l32 = gen_reg_rtx (SImode);
  30449. + dst_high_part_l32 = gen_reg_rtx (SImode);
  30450. + dst_low_part_g32 = gen_reg_rtx (SImode);
  30451. + dst_high_part_g32 = gen_reg_rtx (SImode);
  30452. + new_shift_amout = gen_reg_rtx (SImode);
  30453. + select_reg = gen_reg_rtx (SImode);
  30454. +
  30455. + if (logic_shift_p)
  30456. + {
  30457. + /*
  30458. + if (shiftamount < 32)
  30459. + dst_low_part = wext (src, shiftamount)
  30460. + dst_high_part = src_high_part >> shiftamount
  30461. + else
  30462. + dst_low_part = src_high_part >> (shiftamount & 0x1f)
  30463. + dst_high_part = 0
  30464. + */
  30465. + emit_insn (gen_uwext (dst_low_part_l32, src, shiftamount));
  30466. + emit_insn (gen_lshrsi3 (dst_high_part_l32, src_high_part,
  30467. + shiftamount));
  30468. +
  30469. + emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f)));
  30470. + emit_insn (gen_lshrsi3 (dst_low_part_g32, src_high_part,
  30471. + new_shift_amout));
  30472. + emit_move_insn (dst_high_part_g32, const0_rtx);
  30473. + }
  30474. + else
  30475. + {
  30476. + /*
  30477. + if (shiftamount < 32)
  30478. + dst_low_part = wext (src, shiftamount)
  30479. + dst_high_part = src_high_part >> shiftamount
  30480. + else
  30481. + dst_low_part = src_high_part >> (shiftamount & 0x1f)
  30482. + # shift 31 for sign extend
  30483. + dst_high_part = src_high_part >> 31
  30484. + */
  30485. + emit_insn (gen_wext (dst_low_part_l32, src, shiftamount));
  30486. + emit_insn (gen_ashrsi3 (dst_high_part_l32, src_high_part,
  30487. + shiftamount));
  30488. +
  30489. + emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f)));
  30490. + emit_insn (gen_ashrsi3 (dst_low_part_g32, src_high_part,
  30491. + new_shift_amout));
  30492. + emit_insn (gen_ashrsi3 (dst_high_part_g32, src_high_part,
  30493. + GEN_INT (31)));
  30494. + }
  30495. +
  30496. + emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32)));
  30497. +
  30498. + emit_insn (gen_cmovnsi (dst_low_part, select_reg,
  30499. + dst_low_part_l32, dst_low_part_g32));
  30500. + emit_insn (gen_cmovnsi (dst_high_part, select_reg,
  30501. + dst_high_part_l32, dst_high_part_g32));
  30502. + }
  30503. +}
  30504. +
  30505. +/* ------------------------------------------------------------------------ */
  30506. +
  30507. +/* PART 2: Auxiliary function for expand RTL pattern. */
  30508. +
  30509. +enum nds32_expand_result_type
  30510. +nds32_expand_cbranch (rtx *operands)
  30511. +{
  30512. + rtx tmp_reg;
  30513. + enum rtx_code code;
  30514. +
  30515. + code = GET_CODE (operands[0]);
  30516. +
  30517. + /* If operands[2] is (const_int 0),
  30518. + we can use beqz,bnez,bgtz,bgez,bltz,or blez instructions.
  30519. + So we have gcc generate original template rtx. */
  30520. + if (GET_CODE (operands[2]) == CONST_INT)
  30521. + if (INTVAL (operands[2]) == 0)
  30522. + if ((code != GTU)
  30523. + && (code != GEU)
  30524. + && (code != LTU)
  30525. + && (code != LEU))
  30526. + return EXPAND_CREATE_TEMPLATE;
  30527. +
  30528. + /* For other comparison, NDS32 ISA only has slt (Set-on-Less-Than)
  30529. + behavior for the comparison, we might need to generate other
  30530. + rtx patterns to achieve same semantic. */
  30531. + switch (code)
  30532. + {
  30533. + case GT:
  30534. + case GTU:
  30535. + if (GET_CODE (operands[2]) == CONST_INT)
  30536. + {
  30537. + /* GT reg_A, const_int => !(LT reg_A, const_int + 1) */
  30538. + if (optimize_size || optimize == 0)
  30539. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30540. + else
  30541. + tmp_reg = gen_reg_rtx (SImode);
  30542. +
  30543. + /* We want to plus 1 into the integer value
  30544. + of operands[2] to create 'slt' instruction.
  30545. + This caculation is performed on the host machine,
  30546. + which may be 64-bit integer.
  30547. + So the meaning of caculation result may be
  30548. + different from the 32-bit nds32 target.
  30549. +
  30550. + For example:
  30551. + 0x7fffffff + 0x1 -> 0x80000000,
  30552. + this value is POSITIVE on 64-bit machine,
  30553. + but the expected value on 32-bit nds32 target
  30554. + should be NEGATIVE value.
  30555. +
  30556. + Hence, instead of using GEN_INT(), we use gen_int_mode() to
  30557. + explicitly create SImode constant rtx. */
  30558. + enum rtx_code cmp_code;
  30559. +
  30560. + rtx plus1 = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
  30561. + if (satisfies_constraint_Is15 (plus1))
  30562. + {
  30563. + operands[2] = plus1;
  30564. + cmp_code = EQ;
  30565. + if (code == GT)
  30566. + {
  30567. + /* GT, use slts instruction */
  30568. + emit_insn (
  30569. + gen_slts_compare (tmp_reg, operands[1], operands[2]));
  30570. + }
  30571. + else
  30572. + {
  30573. + /* GTU, use slt instruction */
  30574. + emit_insn (
  30575. + gen_slt_compare (tmp_reg, operands[1], operands[2]));
  30576. + }
  30577. + }
  30578. + else
  30579. + {
  30580. + cmp_code = NE;
  30581. + if (code == GT)
  30582. + {
  30583. + /* GT, use slts instruction */
  30584. + emit_insn (
  30585. + gen_slts_compare (tmp_reg, operands[2], operands[1]));
  30586. + }
  30587. + else
  30588. + {
  30589. + /* GTU, use slt instruction */
  30590. + emit_insn (
  30591. + gen_slt_compare (tmp_reg, operands[2], operands[1]));
  30592. + }
  30593. + }
  30594. +
  30595. + PUT_CODE (operands[0], cmp_code);
  30596. + operands[1] = tmp_reg;
  30597. + operands[2] = const0_rtx;
  30598. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30599. + operands[2], operands[3]));
  30600. +
  30601. + return EXPAND_DONE;
  30602. + }
  30603. + else
  30604. + {
  30605. + /* GT reg_A, reg_B => LT reg_B, reg_A */
  30606. + if (optimize_size || optimize == 0)
  30607. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30608. + else
  30609. + tmp_reg = gen_reg_rtx (SImode);
  30610. +
  30611. + if (code == GT)
  30612. + {
  30613. + /* GT, use slts instruction */
  30614. + emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
  30615. + }
  30616. + else
  30617. + {
  30618. + /* GTU, use slt instruction */
  30619. + emit_insn (gen_slt_compare (tmp_reg, operands[2], operands[1]));
  30620. + }
  30621. +
  30622. + PUT_CODE (operands[0], NE);
  30623. + operands[1] = tmp_reg;
  30624. + operands[2] = const0_rtx;
  30625. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30626. + operands[2], operands[3]));
  30627. +
  30628. + return EXPAND_DONE;
  30629. + }
  30630. +
  30631. + case GE:
  30632. + case GEU:
  30633. + /* GE reg_A, reg_B => !(LT reg_A, reg_B) */
  30634. + /* GE reg_A, const_int => !(LT reg_A, const_int) */
  30635. + if (optimize_size || optimize == 0)
  30636. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30637. + else
  30638. + tmp_reg = gen_reg_rtx (SImode);
  30639. +
  30640. + if (code == GE)
  30641. + {
  30642. + /* GE, use slts instruction */
  30643. + emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  30644. + }
  30645. + else
  30646. + {
  30647. + /* GEU, use slt instruction */
  30648. + emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  30649. + }
  30650. +
  30651. + PUT_CODE (operands[0], EQ);
  30652. + operands[1] = tmp_reg;
  30653. + operands[2] = const0_rtx;
  30654. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30655. + operands[2], operands[3]));
  30656. +
  30657. + return EXPAND_DONE;
  30658. +
  30659. + case LT:
  30660. + case LTU:
  30661. + /* LT reg_A, reg_B => LT reg_A, reg_B */
  30662. + /* LT reg_A, const_int => LT reg_A, const_int */
  30663. + if (optimize_size || optimize == 0)
  30664. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30665. + else
  30666. + tmp_reg = gen_reg_rtx (SImode);
  30667. +
  30668. + if (code == LT)
  30669. + {
  30670. + /* LT, use slts instruction */
  30671. + emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
  30672. + }
  30673. + else
  30674. + {
  30675. + /* LTU, use slt instruction */
  30676. + emit_insn (gen_slt_compare (tmp_reg, operands[1], operands[2]));
  30677. + }
  30678. +
  30679. + PUT_CODE (operands[0], NE);
  30680. + operands[1] = tmp_reg;
  30681. + operands[2] = const0_rtx;
  30682. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30683. + operands[2], operands[3]));
  30684. +
  30685. + return EXPAND_DONE;
  30686. +
  30687. + case LE:
  30688. + case LEU:
  30689. + if (GET_CODE (operands[2]) == CONST_INT)
  30690. + {
  30691. + /* LE reg_A, const_int => LT reg_A, const_int + 1 */
  30692. + if (optimize_size || optimize == 0)
  30693. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30694. + else
  30695. + tmp_reg = gen_reg_rtx (SImode);
  30696. +
  30697. + enum rtx_code cmp_code;
  30698. + /* Note that (le:SI X INT_MAX) is not the same as (lt:SI X INT_MIN).
  30699. + We better have an assert here in case GCC does not properly
  30700. + optimize it away. The INT_MAX here is 0x7fffffff for target. */
  30701. + rtx plus1 = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
  30702. + if (satisfies_constraint_Is15 (plus1))
  30703. + {
  30704. + operands[2] = plus1;
  30705. + cmp_code = NE;
  30706. + if (code == LE)
  30707. + {
  30708. + /* LE, use slts instruction */
  30709. + emit_insn (
  30710. + gen_slts_compare (tmp_reg, operands[1], operands[2]));
  30711. + }
  30712. + else
  30713. + {
  30714. + /* LEU, use slt instruction */
  30715. + emit_insn (
  30716. + gen_slt_compare (tmp_reg, operands[1], operands[2]));
  30717. + }
  30718. + }
  30719. + else
  30720. + {
  30721. + cmp_code = EQ;
  30722. + if (code == LE)
  30723. + {
  30724. + /* LE, use slts instruction */
  30725. + emit_insn (
  30726. + gen_slts_compare (tmp_reg, operands[2], operands[1]));
  30727. + }
  30728. + else
  30729. + {
  30730. + /* LEU, use slt instruction */
  30731. + emit_insn (
  30732. + gen_slt_compare (tmp_reg, operands[2], operands[1]));
  30733. + }
  30734. + }
  30735. +
  30736. + PUT_CODE (operands[0], cmp_code);
  30737. + operands[1] = tmp_reg;
  30738. + operands[2] = const0_rtx;
  30739. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30740. + operands[2], operands[3]));
  30741. +
  30742. + return EXPAND_DONE;
  30743. + }
  30744. + else
  30745. + {
  30746. + /* LE reg_A, reg_B => !(LT reg_B, reg_A) */
  30747. + if (optimize_size || optimize == 0)
  30748. + tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
  30749. + else
  30750. + tmp_reg = gen_reg_rtx (SImode);
  30751. +
  30752. + if (code == LE)
  30753. + {
  30754. + /* LE, use slts instruction */
  30755. + emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
  30756. + }
  30757. + else
  30758. + {
  30759. + /* LEU, use slt instruction */
  30760. + emit_insn (gen_slt_compare (tmp_reg, operands[2], operands[1]));
  30761. + }
  30762. +
  30763. + PUT_CODE (operands[0], EQ);
  30764. + operands[1] = tmp_reg;
  30765. + operands[2] = const0_rtx;
  30766. + emit_insn (gen_cbranchsi4 (operands[0], operands[1],
  30767. + operands[2], operands[3]));
  30768. +
  30769. + return EXPAND_DONE;
  30770. + }
  30771. +
  30772. + case EQ:
  30773. + case NE:
  30774. + /* NDS32 ISA has various form for eq/ne behavior no matter
  30775. + what kind of the operand is.
  30776. + So just generate original template rtx. */
  30777. +
  30778. + /* Put operands[2] into register if operands[2] is a large
  30779. + const_int or ISAv2. */
  30780. + if (GET_CODE (operands[2]) == CONST_INT
  30781. + && (!satisfies_constraint_Is11 (operands[2])
  30782. + || TARGET_ISA_V2))
  30783. + operands[2] = force_reg (SImode, operands[2]);
  30784. +
  30785. + return EXPAND_CREATE_TEMPLATE;
  30786. +
  30787. + default:
  30788. + return EXPAND_FAIL;
  30789. + }
  30790. +}
  30791. +
  30792. +enum nds32_expand_result_type
  30793. +nds32_expand_cstore (rtx *operands)
  30794. +{
  30795. + rtx tmp_reg;
  30796. + enum rtx_code code;
  30797. +
  30798. + code = GET_CODE (operands[1]);
  30799. +
  30800. + switch (code)
  30801. + {
  30802. + case EQ:
  30803. + if (GET_CODE (operands[3]) == CONST_INT)
  30804. + {
  30805. + /* reg_R = (reg_A == const_int_B)
  30806. + --> addi reg_C, reg_A, -const_int_B
  30807. + slti reg_R, reg_C, const_int_1 */
  30808. + tmp_reg = gen_reg_rtx (SImode);
  30809. + operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
  30810. + /* If the integer value is not in the range of imm15s,
  30811. + we need to force register first because our addsi3 pattern
  30812. + only accept nds32_rimm15s_operand predicate. */
  30813. + if (!satisfies_constraint_Is15 (operands[3]))
  30814. + operands[3] = force_reg (SImode, operands[3]);
  30815. + emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
  30816. + emit_insn (gen_slt_eq0 (operands[0], tmp_reg));
  30817. +
  30818. + return EXPAND_DONE;
  30819. + }
  30820. + else
  30821. + {
  30822. + /* reg_R = (reg_A == reg_B)
  30823. + --> xor reg_C, reg_A, reg_B
  30824. + slti reg_R, reg_C, const_int_1 */
  30825. + tmp_reg = gen_reg_rtx (SImode);
  30826. + emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
  30827. + emit_insn (gen_slt_eq0 (operands[0], tmp_reg));
  30828. +
  30829. + return EXPAND_DONE;
  30830. + }
  30831. +
  30832. + case NE:
  30833. + if (GET_CODE (operands[3]) == CONST_INT)
  30834. + {
  30835. + /* reg_R = (reg_A != const_int_B)
  30836. + --> addi reg_C, reg_A, -const_int_B
  30837. + slti reg_R, const_int_0, reg_C */
  30838. + tmp_reg = gen_reg_rtx (SImode);
  30839. + operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
  30840. + /* If the integer value is not in the range of imm15s,
  30841. + we need to force register first because our addsi3 pattern
  30842. + only accept nds32_rimm15s_operand predicate. */
  30843. + if (!satisfies_constraint_Is15 (operands[3]))
  30844. + operands[3] = force_reg (SImode, operands[3]);
  30845. + emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
  30846. + emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
  30847. +
  30848. + return EXPAND_DONE;
  30849. + }
  30850. + else
  30851. + {
  30852. + /* reg_R = (reg_A != reg_B)
  30853. + --> xor reg_C, reg_A, reg_B
  30854. + slti reg_R, const_int_0, reg_C */
  30855. + tmp_reg = gen_reg_rtx (SImode);
  30856. + emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
  30857. + emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
  30858. +
  30859. + return EXPAND_DONE;
  30860. + }
  30861. +
  30862. + case GT:
  30863. + case GTU:
  30864. + /* reg_R = (reg_A > reg_B) --> slt reg_R, reg_B, reg_A */
  30865. + /* reg_R = (reg_A > const_int_B) --> slt reg_R, const_int_B, reg_A */
  30866. + if (code == GT)
  30867. + {
  30868. + /* GT, use slts instruction */
  30869. + emit_insn (gen_slts_compare (operands[0], operands[3], operands[2]));
  30870. + }
  30871. + else
  30872. + {
  30873. + /* GTU, use slt instruction */
  30874. + emit_insn (gen_slt_compare (operands[0], operands[3], operands[2]));
  30875. + }
  30876. +
  30877. + return EXPAND_DONE;
  30878. +
  30879. + case GE:
  30880. + case GEU:
  30881. + if (GET_CODE (operands[3]) == CONST_INT)
  30882. + {
  30883. + /* reg_R = (reg_A >= const_int_B)
  30884. + --> movi reg_C, const_int_B - 1
  30885. + slt reg_R, reg_C, reg_A */
  30886. + tmp_reg = gen_reg_rtx (SImode);
  30887. +
  30888. + emit_insn (gen_movsi (tmp_reg,
  30889. + gen_int_mode (INTVAL (operands[3]) - 1,
  30890. + SImode)));
  30891. + if (code == GE)
  30892. + {
  30893. + /* GE, use slts instruction */
  30894. + emit_insn (gen_slts_compare (operands[0], tmp_reg, operands[2]));
  30895. + }
  30896. + else
  30897. + {
  30898. + /* GEU, use slt instruction */
  30899. + emit_insn (gen_slt_compare (operands[0], tmp_reg, operands[2]));
  30900. + }
  30901. +
  30902. + return EXPAND_DONE;
  30903. + }
  30904. + else
  30905. + {
  30906. + /* reg_R = (reg_A >= reg_B)
  30907. + --> slt reg_R, reg_A, reg_B
  30908. + xori reg_R, reg_R, const_int_1 */
  30909. + if (code == GE)
  30910. + {
  30911. + /* GE, use slts instruction */
  30912. + emit_insn (gen_slts_compare (operands[0],
  30913. + operands[2], operands[3]));
  30914. + }
  30915. + else
  30916. + {
  30917. + /* GEU, use slt instruction */
  30918. + emit_insn (gen_slt_compare (operands[0],
  30919. + operands[2], operands[3]));
  30920. + }
  30921. +
  30922. + /* perform 'not' behavior */
  30923. + emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  30924. +
  30925. + return EXPAND_DONE;
  30926. + }
  30927. +
  30928. + case LT:
  30929. + case LTU:
  30930. + /* reg_R = (reg_A < reg_B) --> slt reg_R, reg_A, reg_B */
  30931. + /* reg_R = (reg_A < const_int_B) --> slt reg_R, reg_A, const_int_B */
  30932. + if (code == LT)
  30933. + {
  30934. + /* LT, use slts instruction */
  30935. + emit_insn (gen_slts_compare (operands[0], operands[2], operands[3]));
  30936. + }
  30937. + else
  30938. + {
  30939. + /* LTU, use slt instruction */
  30940. + emit_insn (gen_slt_compare (operands[0], operands[2], operands[3]));
  30941. + }
  30942. +
  30943. + return EXPAND_DONE;
  30944. +
  30945. + case LE:
  30946. + case LEU:
  30947. + if (GET_CODE (operands[3]) == CONST_INT)
  30948. + {
  30949. + /* reg_R = (reg_A <= const_int_B)
  30950. + --> movi reg_C, const_int_B + 1
  30951. + slt reg_R, reg_A, reg_C */
  30952. + tmp_reg = gen_reg_rtx (SImode);
  30953. +
  30954. + emit_insn (gen_movsi (tmp_reg,
  30955. + gen_int_mode (INTVAL (operands[3]) + 1,
  30956. + SImode)));
  30957. + if (code == LE)
  30958. + {
  30959. + /* LE, use slts instruction */
  30960. + emit_insn (gen_slts_compare (operands[0], operands[2], tmp_reg));
  30961. + }
  30962. + else
  30963. + {
  30964. + /* LEU, use slt instruction */
  30965. + emit_insn (gen_slt_compare (operands[0], operands[2], tmp_reg));
  30966. + }
  30967. +
  30968. + return EXPAND_DONE;
  30969. + }
  30970. + else
  30971. + {
  30972. + /* reg_R = (reg_A <= reg_B) --> slt reg_R, reg_B, reg_A
  30973. + xori reg_R, reg_R, const_int_1 */
  30974. + if (code == LE)
  30975. + {
  30976. + /* LE, use slts instruction */
  30977. + emit_insn (gen_slts_compare (operands[0],
  30978. + operands[3], operands[2]));
  30979. + }
  30980. + else
  30981. + {
  30982. + /* LEU, use slt instruction */
  30983. + emit_insn (gen_slt_compare (operands[0],
  30984. + operands[3], operands[2]));
  30985. + }
  30986. +
  30987. + /* perform 'not' behavior */
  30988. + emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  30989. +
  30990. + return EXPAND_DONE;
  30991. + }
  30992. +
  30993. +
  30994. + default:
  30995. + gcc_unreachable ();
  30996. + }
  30997. +}
  30998. +
  30999. +void
  31000. +nds32_expand_float_cbranch (rtx *operands)
  31001. +{
  31002. + enum rtx_code code = GET_CODE (operands[0]);
  31003. + enum rtx_code new_code = code;
  31004. + rtx cmp_op0 = operands[1];
  31005. + rtx cmp_op1 = operands[2];
  31006. + rtx tmp_reg;
  31007. + rtx tmp;
  31008. +
  31009. + int reverse = 0;
  31010. +
  31011. + /* Main Goal: Use compare instruction + branch instruction.
  31012. +
  31013. + For example:
  31014. + GT, GE: swap condition and swap operands and generate
  31015. + compare instruction(LT, LE) + branch not equal instruction.
  31016. +
  31017. + UNORDERED, LT, LE, EQ: no need to change and generate
  31018. + compare instruction(UNORDERED, LT, LE, EQ) + branch not equal instruction.
  31019. +
  31020. + ORDERED, NE: reverse condition and generate
  31021. + compare instruction(EQ) + branch equal instruction. */
  31022. +
  31023. + switch (code)
  31024. + {
  31025. + case GT:
  31026. + case GE:
  31027. + tmp = cmp_op0;
  31028. + cmp_op0 = cmp_op1;
  31029. + cmp_op1 = tmp;
  31030. + new_code = swap_condition (new_code);
  31031. + break;
  31032. + case UNORDERED:
  31033. + case LT:
  31034. + case LE:
  31035. + case EQ:
  31036. + break;
  31037. + case ORDERED:
  31038. + case NE:
  31039. + new_code = reverse_condition (new_code);
  31040. + reverse = 1;
  31041. + break;
  31042. + case UNGT:
  31043. + case UNGE:
  31044. + new_code = reverse_condition_maybe_unordered (new_code);
  31045. + reverse = 1;
  31046. + break;
  31047. + case UNLT:
  31048. + case UNLE:
  31049. + new_code = reverse_condition_maybe_unordered (new_code);
  31050. + tmp = cmp_op0;
  31051. + cmp_op0 = cmp_op1;
  31052. + cmp_op1 = tmp;
  31053. + new_code = swap_condition (new_code);
  31054. + reverse = 1;
  31055. + break;
  31056. + default:
  31057. + return;
  31058. + }
  31059. +
  31060. + tmp_reg = gen_reg_rtx (SImode);
  31061. + emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
  31062. + gen_rtx_fmt_ee (new_code, SImode,
  31063. + cmp_op0, cmp_op1)));
  31064. +
  31065. + PUT_CODE (operands[0], reverse ? EQ : NE);
  31066. + emit_insn (gen_cbranchsi4 (operands[0], tmp_reg,
  31067. + const0_rtx, operands[3]));
  31068. +}
  31069. +
  31070. +void
  31071. +nds32_expand_float_cstore (rtx *operands)
  31072. +{
  31073. + enum rtx_code code = GET_CODE (operands[1]);
  31074. + enum rtx_code new_code = code;
  31075. + enum machine_mode mode = GET_MODE (operands[2]);
  31076. +
  31077. + rtx cmp_op0 = operands[2];
  31078. + rtx cmp_op1 = operands[3];
  31079. + rtx tmp;
  31080. +
  31081. + /* Main Goal: Use compare instruction to store value.
  31082. +
  31083. + For example:
  31084. + GT, GE: swap condition and swap operands.
  31085. + reg_R = (reg_A > reg_B) --> fcmplt reg_R, reg_B, reg_A
  31086. + reg_R = (reg_A >= reg_B) --> fcmple reg_R, reg_B, reg_A
  31087. +
  31088. + LT, LE, EQ: no need to change, it is already LT, LE, EQ.
  31089. + reg_R = (reg_A < reg_B) --> fcmplt reg_R, reg_A, reg_B
  31090. + reg_R = (reg_A <= reg_B) --> fcmple reg_R, reg_A, reg_B
  31091. + reg_R = (reg_A == reg_B) --> fcmpeq reg_R, reg_A, reg_B
  31092. +
  31093. + ORDERED: reverse condition and using xor insturction to achieve 'ORDERED'.
  31094. + reg_R = (reg_A != reg_B) --> fcmpun reg_R, reg_A, reg_B
  31095. + xor reg_R, reg_R, const1_rtx
  31096. +
  31097. + NE: reverse condition and using xor insturction to achieve 'NE'.
  31098. + reg_R = (reg_A != reg_B) --> fcmpeq reg_R, reg_A, reg_B
  31099. + xor reg_R, reg_R, const1_rtx */
  31100. + switch (code)
  31101. + {
  31102. + case GT:
  31103. + case GE:
  31104. + tmp = cmp_op0;
  31105. + cmp_op0 = cmp_op1;
  31106. + cmp_op1 =tmp;
  31107. + new_code = swap_condition (new_code);
  31108. + break;
  31109. + case UNORDERED:
  31110. + case LT:
  31111. + case LE:
  31112. + case EQ:
  31113. + break;
  31114. + case ORDERED:
  31115. + if (mode == SFmode)
  31116. + emit_insn (gen_cmpsf_un (operands[0], cmp_op0, cmp_op1));
  31117. + else
  31118. + emit_insn (gen_cmpdf_un (operands[0], cmp_op0, cmp_op1));
  31119. +
  31120. + emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  31121. + return;
  31122. + case NE:
  31123. + if (mode == SFmode)
  31124. + emit_insn (gen_cmpsf_eq (operands[0], cmp_op0, cmp_op1));
  31125. + else
  31126. + emit_insn (gen_cmpdf_eq (operands[0], cmp_op0, cmp_op1));
  31127. +
  31128. + emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
  31129. + return;
  31130. + default:
  31131. + return;
  31132. + }
  31133. +
  31134. + emit_insn (gen_rtx_SET (VOIDmode, operands[0],
  31135. + gen_rtx_fmt_ee (new_code, SImode,
  31136. + cmp_op0, cmp_op1)));
  31137. +}
  31138. +
  31139. +enum nds32_expand_result_type
  31140. +nds32_expand_movcc (rtx *operands)
  31141. +{
  31142. + enum rtx_code code = GET_CODE (operands[1]);
  31143. + enum rtx_code new_code = code;
  31144. + enum machine_mode cmp0_mode = GET_MODE (XEXP (operands[1], 0));
  31145. + rtx cmp_op0 = XEXP (operands[1], 0);
  31146. + rtx cmp_op1 = XEXP (operands[1], 1);
  31147. + rtx tmp;
  31148. +
  31149. + if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
  31150. + && XEXP (operands[1], 1) == const0_rtx)
  31151. + {
  31152. + /* If the operands[1] rtx is already (eq X 0) or (ne X 0),
  31153. + we have gcc generate original template rtx. */
  31154. + return EXPAND_CREATE_TEMPLATE;
  31155. + }
  31156. + else if ((TARGET_FPU_SINGLE && cmp0_mode == SFmode)
  31157. + || (TARGET_FPU_DOUBLE && cmp0_mode == DFmode))
  31158. + {
  31159. + nds32_expand_float_movcc (operands);
  31160. + }
  31161. + else
  31162. + {
  31163. + /* Since there is only 'slt'(Set when Less Than) instruction for
  31164. + comparison in Andes ISA, the major strategy we use here is to
  31165. + convert conditional move into 'LT + EQ' or 'LT + NE' rtx combination.
  31166. + We design constraints properly so that the reload phase will assist
  31167. + to make one source operand to use same register as result operand.
  31168. + Then we can use cmovz/cmovn to catch the other source operand
  31169. + which has different register. */
  31170. + int reverse = 0;
  31171. +
  31172. + /* Main Goal: Use 'LT + EQ' or 'LT + NE' to target "then" part
  31173. + Strategy : Reverse condition and swap comparison operands
  31174. +
  31175. + For example:
  31176. +
  31177. + a <= b ? P : Q (LE or LEU)
  31178. + --> a > b ? Q : P (reverse condition)
  31179. + --> b < a ? Q : P (swap comparison operands to achieve 'LT/LTU')
  31180. +
  31181. + a >= b ? P : Q (GE or GEU)
  31182. + --> a < b ? Q : P (reverse condition to achieve 'LT/LTU')
  31183. +
  31184. + a < b ? P : Q (LT or LTU)
  31185. + --> (NO NEED TO CHANGE, it is already 'LT/LTU')
  31186. +
  31187. + a > b ? P : Q (GT or GTU)
  31188. + --> b < a ? P : Q (swap comparison operands to achieve 'LT/LTU') */
  31189. + switch (code)
  31190. + {
  31191. + case GE: case GEU: case LE: case LEU:
  31192. + new_code = reverse_condition (code);
  31193. + reverse = 1;
  31194. + break;
  31195. + case EQ:
  31196. + case NE:
  31197. + /* no need to reverse condition */
  31198. + break;
  31199. + default:
  31200. + return EXPAND_FAIL;
  31201. + }
  31202. +
  31203. + /* For '>' comparison operator, we swap operands
  31204. + so that we can have 'LT/LTU' operator. */
  31205. + if (new_code == GT || new_code == GTU)
  31206. + {
  31207. + tmp = cmp_op0;
  31208. + cmp_op0 = cmp_op1;
  31209. + cmp_op1 = tmp;
  31210. +
  31211. + new_code = swap_condition (new_code);
  31212. + }
  31213. +
  31214. + /* Use a temporary register to store slt/slts result. */
  31215. + tmp = gen_reg_rtx (SImode);
  31216. +
  31217. + if (new_code == EQ || new_code == NE)
  31218. + {
  31219. + emit_insn (gen_xorsi3 (tmp, cmp_op0, cmp_op1));
  31220. + /* tmp == 0 if cmp_op0 == cmp_op1. */
  31221. + operands[1] = gen_rtx_fmt_ee (new_code, VOIDmode, tmp, const0_rtx);
  31222. + }
  31223. + else
  31224. + {
  31225. + /* This emit_insn will create corresponding 'slt/slts'
  31226. + insturction. */
  31227. + if (new_code == LT)
  31228. + emit_insn (gen_slts_compare (tmp, cmp_op0, cmp_op1));
  31229. + else if (new_code == LTU)
  31230. + emit_insn (gen_slt_compare (tmp, cmp_op0, cmp_op1));
  31231. + else
  31232. + gcc_unreachable ();
  31233. +
  31234. + /* Change comparison semantic into (eq X 0) or (ne X 0) behavior
  31235. + so that cmovz or cmovn will be matched later.
  31236. +
  31237. + For reverse condition cases, we want to create a semantic that:
  31238. + (eq X 0) --> pick up "else" part
  31239. + For normal cases, we want to create a semantic that:
  31240. + (ne X 0) --> pick up "then" part
  31241. +
  31242. + Later we will have cmovz/cmovn instruction pattern to
  31243. + match corresponding behavior and output instruction. */
  31244. + operands[1] = gen_rtx_fmt_ee (reverse ? EQ : NE,
  31245. + VOIDmode, tmp, const0_rtx);
  31246. + }
  31247. + }
  31248. + return EXPAND_CREATE_TEMPLATE;
  31249. +}
  31250. +
  31251. +void
  31252. +nds32_expand_float_movcc (rtx *operands)
  31253. +{
  31254. + if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
  31255. + && GET_MODE (XEXP (operands[1], 0)) == SImode
  31256. + && XEXP (operands[1], 1) == const0_rtx)
  31257. + {
  31258. + /* If the operands[1] rtx is already (eq X 0) or (ne X 0),
  31259. + we have gcc generate original template rtx. */
  31260. + return;
  31261. + }
  31262. + else
  31263. + {
  31264. + enum rtx_code code = GET_CODE (operands[1]);
  31265. + enum rtx_code new_code = code;
  31266. + enum machine_mode cmp0_mode = GET_MODE (XEXP (operands[1], 0));
  31267. + enum machine_mode cmp1_mode = GET_MODE (XEXP (operands[1], 1));
  31268. + rtx cmp_op0 = XEXP (operands[1], 0);
  31269. + rtx cmp_op1 = XEXP (operands[1], 1);
  31270. + rtx tmp;
  31271. +
  31272. + /* Compare instruction Operations: (cmp_op0 condition cmp_op1) ? 1 : 0,
  31273. + when result is 1, and 'reverse' be set 1 for fcmovzs instructuin. */
  31274. + int reverse = 0;
  31275. +
  31276. + /* Main Goal: Use cmpare instruction + conditional move instruction.
  31277. + Strategy : swap condition and swap comparison operands.
  31278. +
  31279. + For example:
  31280. + a > b ? P : Q (GT)
  31281. + --> a < b ? Q : P (swap condition)
  31282. + --> b < a ? Q : P (swap comparison operands to achieve 'GT')
  31283. +
  31284. + a >= b ? P : Q (GE)
  31285. + --> a <= b ? Q : P (swap condition)
  31286. + --> b <= a ? Q : P (swap comparison operands to achieve 'GE')
  31287. +
  31288. + a < b ? P : Q (LT)
  31289. + --> (NO NEED TO CHANGE, it is already 'LT')
  31290. +
  31291. + a >= b ? P : Q (LE)
  31292. + --> (NO NEED TO CHANGE, it is already 'LE')
  31293. +
  31294. + a == b ? P : Q (EQ)
  31295. + --> (NO NEED TO CHANGE, it is already 'EQ') */
  31296. +
  31297. + switch (code)
  31298. + {
  31299. + case GT:
  31300. + case GE:
  31301. + tmp = cmp_op0;
  31302. + cmp_op0 = cmp_op1;
  31303. + cmp_op1 =tmp;
  31304. + new_code = swap_condition (new_code);
  31305. + break;
  31306. + case UNORDERED:
  31307. + case LT:
  31308. + case LE:
  31309. + case EQ:
  31310. + break;
  31311. + case ORDERED:
  31312. + case NE:
  31313. + reverse = 1;
  31314. + new_code = reverse_condition (new_code);
  31315. + break;
  31316. + case UNGT:
  31317. + case UNGE:
  31318. + new_code = reverse_condition_maybe_unordered (new_code);
  31319. + reverse = 1;
  31320. + break;
  31321. + case UNLT:
  31322. + case UNLE:
  31323. + new_code = reverse_condition_maybe_unordered (new_code);
  31324. + tmp = cmp_op0;
  31325. + cmp_op0 = cmp_op1;
  31326. + cmp_op1 = tmp;
  31327. + new_code = swap_condition (new_code);
  31328. + reverse = 1;
  31329. + break;
  31330. + default:
  31331. + return;
  31332. + }
  31333. +
  31334. + /* Use a temporary register to store fcmpxxs result. */
  31335. + tmp = gen_reg_rtx (SImode);
  31336. +
  31337. + /* Create float compare instruction for SFmode and DFmode,
  31338. + other MODE using cstoresi create compare instruction. */
  31339. + if ((cmp0_mode == DFmode || cmp0_mode == SFmode)
  31340. + && (cmp1_mode == DFmode || cmp1_mode == SFmode))
  31341. + {
  31342. + /* This emit_insn create corresponding float compare instruction */
  31343. + emit_insn (gen_rtx_SET (VOIDmode, tmp,
  31344. + gen_rtx_fmt_ee (new_code, SImode,
  31345. + cmp_op0, cmp_op1)));
  31346. + }
  31347. + else
  31348. + {
  31349. + /* This emit_insn using cstoresi create corresponding
  31350. + compare instruction */
  31351. + PUT_CODE (operands[1], new_code);
  31352. + emit_insn (gen_cstoresi4 (tmp, operands[1],
  31353. + cmp_op0, cmp_op1));
  31354. + }
  31355. + /* operands[1] crete corresponding condition move instruction
  31356. + for fcmovzs and fcmovns. */
  31357. + operands[1] = gen_rtx_fmt_ee (reverse ? EQ : NE,
  31358. + VOIDmode, tmp, const0_rtx);
  31359. + }
  31360. +}
  31361. +
  31362. +void
  31363. +nds32_emit_push_fpr_callee_saved (int base_offset)
  31364. +{
  31365. + rtx fpu_insn;
  31366. + rtx reg, mem;
  31367. + unsigned int regno = cfun->machine->callee_saved_first_fpr_regno;
  31368. + unsigned int last_fpr = cfun->machine->callee_saved_last_fpr_regno;
  31369. +
  31370. + while (regno <= last_fpr)
  31371. + {
  31372. + /* Handling two registers, using fsdi instruction. */
  31373. + reg = gen_rtx_REG (DFmode, regno);
  31374. + mem = gen_frame_mem (DFmode, plus_constant (Pmode,
  31375. + stack_pointer_rtx,
  31376. + base_offset));
  31377. + base_offset += 8;
  31378. + regno += 2;
  31379. + fpu_insn = emit_move_insn (mem, reg);
  31380. + RTX_FRAME_RELATED_P (fpu_insn) = 1;
  31381. + }
  31382. +}
  31383. +
  31384. +void
  31385. +nds32_emit_pop_fpr_callee_saved (int gpr_padding_size)
  31386. +{
  31387. + rtx fpu_insn;
  31388. + rtx reg, mem, addr;
  31389. + rtx dwarf, adjust_sp_rtx;
  31390. + unsigned int regno = cfun->machine->callee_saved_first_fpr_regno;
  31391. + unsigned int last_fpr = cfun->machine->callee_saved_last_fpr_regno;
  31392. + int padding = 0;
  31393. +
  31394. + while (regno <= last_fpr)
  31395. + {
  31396. + /* Handling two registers, using fldi.bi instruction. */
  31397. + if ((regno + 1) >= last_fpr)
  31398. + padding = gpr_padding_size;
  31399. +
  31400. + reg = gen_rtx_REG (DFmode, (regno));
  31401. + addr = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx,
  31402. + gen_rtx_PLUS (Pmode, stack_pointer_rtx,
  31403. + GEN_INT (8 + padding)));
  31404. + mem = gen_frame_mem (DFmode, addr);
  31405. + regno += 2;
  31406. + fpu_insn = emit_move_insn (reg, mem);
  31407. +
  31408. + adjust_sp_rtx =
  31409. + gen_rtx_SET (VOIDmode, stack_pointer_rtx,
  31410. + plus_constant (Pmode, stack_pointer_rtx,
  31411. + 8 + padding));
  31412. +
  31413. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, NULL_RTX);
  31414. + /* Tell gcc we adjust SP in this insn. */
  31415. + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx),
  31416. + dwarf);
  31417. + RTX_FRAME_RELATED_P (fpu_insn) = 1;
  31418. + REG_NOTES (fpu_insn) = dwarf;
  31419. + }
  31420. +}
  31421. +
  31422. +void
  31423. +nds32_emit_v3pop_fpr_callee_saved (int base)
  31424. +{
  31425. + int fpu_base_addr = base;
  31426. + int regno;
  31427. + rtx fpu_insn;
  31428. + rtx reg, mem;
  31429. + rtx dwarf;
  31430. +
  31431. + regno = cfun->machine->callee_saved_first_fpr_regno;
  31432. + while (regno <= cfun->machine->callee_saved_last_fpr_regno)
  31433. + {
  31434. + /* Handling two registers, using fldi instruction. */
  31435. + reg = gen_rtx_REG (DFmode, regno);
  31436. + mem = gen_frame_mem (DFmode, plus_constant (Pmode,
  31437. + stack_pointer_rtx,
  31438. + fpu_base_addr));
  31439. + fpu_base_addr += 8;
  31440. + regno += 2;
  31441. + fpu_insn = emit_move_insn (reg, mem);
  31442. + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, NULL_RTX);
  31443. + RTX_FRAME_RELATED_P (fpu_insn) = 1;
  31444. + REG_NOTES (fpu_insn) = dwarf;
  31445. + }
  31446. +}
  31447. +
  31448. +/* ------------------------------------------------------------------------ */
  31449. +
  31450. +/* PART 3: Auxiliary function for output asm template. */
  31451. +
  31452. +/* Function to generate PC relative jump table.
  31453. + Refer to nds32.md for more details.
  31454. +
  31455. + The following is the sample for the case that diff value
  31456. + can be presented in '.short' size.
  31457. +
  31458. + addi $r1, $r1, -(case_lower_bound)
  31459. + slti $ta, $r1, (case_number)
  31460. + beqz $ta, .L_skip_label
  31461. +
  31462. + la $ta, .L35 ! get jump table address
  31463. + lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry
  31464. + addi $ta, $r1, $ta
  31465. + jr5 $ta
  31466. +
  31467. + ! jump table entry
  31468. + L35:
  31469. + .short .L25-.L35
  31470. + .short .L26-.L35
  31471. + .short .L27-.L35
  31472. + .short .L28-.L35
  31473. + .short .L29-.L35
  31474. + .short .L30-.L35
  31475. + .short .L31-.L35
  31476. + .short .L32-.L35
  31477. + .short .L33-.L35
  31478. + .short .L34-.L35 */
  31479. +const char *
  31480. +nds32_output_casesi_pc_relative (rtx *operands)
  31481. +{
  31482. + enum machine_mode mode;
  31483. + rtx diff_vec;
  31484. +
  31485. + diff_vec = PATTERN (NEXT_INSN (operands[1]));
  31486. +
  31487. + gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
  31488. +
  31489. + /* Step C: "t <-- operands[1]". */
  31490. + if (flag_pic)
  31491. + {
  31492. + output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands);
  31493. + output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands);
  31494. + output_asm_insn ("add\t$ta, $ta, $gp", operands);
  31495. + }
  31496. + else
  31497. + output_asm_insn ("la\t$ta, %l1", operands);
  31498. +
  31499. + /* Get the mode of each element in the difference vector. */
  31500. + mode = GET_MODE (diff_vec);
  31501. +
  31502. + /* Step D: "z <-- (mem (plus (operands[0] << m) t))",
  31503. + where m is 0, 1, or 2 to load address-diff value from table. */
  31504. + switch (mode)
  31505. + {
  31506. + case QImode:
  31507. + output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
  31508. + break;
  31509. + case HImode:
  31510. + output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
  31511. + break;
  31512. + case SImode:
  31513. + output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
  31514. + break;
  31515. + default:
  31516. + gcc_unreachable ();
  31517. + }
  31518. +
  31519. + /* Step E: "t <-- z + t".
  31520. + Add table label_ref with address-diff value to
  31521. + obtain target case address. */
  31522. + output_asm_insn ("add\t$ta, %2, $ta", operands);
  31523. +
  31524. + /* Step F: jump to target with register t. */
  31525. + if (TARGET_16_BIT)
  31526. + return "jr5\t$ta";
  31527. + else
  31528. + return "jr\t$ta";
  31529. +}
  31530. +
  31531. +/* Function to generate normal jump table. */
  31532. +const char *
  31533. +nds32_output_casesi (rtx *operands)
  31534. +{
  31535. + /* Step C: "t <-- operands[1]". */
  31536. + if (flag_pic)
  31537. + {
  31538. + output_asm_insn ("sethi\t$ta, hi20(%l1@GOTOFF)", operands);
  31539. + output_asm_insn ("ori\t$ta, $ta, lo12(%l1@GOTOFF)", operands);
  31540. + output_asm_insn ("add\t$ta, $ta, $gp", operands);
  31541. + }
  31542. + else
  31543. + output_asm_insn ("la\t$ta, %l1", operands);
  31544. +
  31545. + /* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */
  31546. + output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
  31547. +
  31548. + /* No need to perform Step E, which is only used for
  31549. + pc relative jump table. */
  31550. +
  31551. + /* Step F: jump to target with register z. */
  31552. + if (TARGET_16_BIT)
  31553. + return "jr5\t%2";
  31554. + else
  31555. + return "jr\t%2";
  31556. +}
  31557. +
  31558. +
  31559. +/* Function to return memory format. */
  31560. +enum nds32_16bit_address_type
  31561. +nds32_mem_format (rtx op)
  31562. +{
  31563. + enum machine_mode mode_test;
  31564. + int val;
  31565. + int regno;
  31566. +
  31567. + if (!TARGET_16_BIT)
  31568. + return ADDRESS_NOT_16BIT_FORMAT;
  31569. +
  31570. + mode_test = GET_MODE (op);
  31571. +
  31572. + op = XEXP (op, 0);
  31573. +
  31574. + /* 45 format. */
  31575. + if (GET_CODE (op) == REG
  31576. + && ((mode_test == SImode) || (mode_test == SFmode)))
  31577. + return ADDRESS_REG;
  31578. +
  31579. + /* 333 format for QI/HImode. */
  31580. + if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
  31581. + return ADDRESS_LO_REG_IMM3U;
  31582. +
  31583. + /* post_inc 333 format. */
  31584. + if ((GET_CODE (op) == POST_INC)
  31585. + && ((mode_test == SImode) || (mode_test == SFmode)))
  31586. + {
  31587. + regno = REGNO(XEXP (op, 0));
  31588. +
  31589. + if (regno < 8)
  31590. + return ADDRESS_POST_INC_LO_REG_IMM3U;
  31591. + }
  31592. +
  31593. + /* post_inc 333 format. */
  31594. + if ((GET_CODE (op) == POST_MODIFY)
  31595. + && ((mode_test == SImode) || (mode_test == SFmode))
  31596. + && (REG_P (XEXP (XEXP (op, 1), 0)))
  31597. + && (CONST_INT_P (XEXP (XEXP (op, 1), 1))))
  31598. + {
  31599. + regno = REGNO (XEXP (XEXP (op, 1), 0));
  31600. + val = INTVAL (XEXP (XEXP (op, 1), 1));
  31601. + if (regno < 8 && val > 0 && val < 32)
  31602. + return ADDRESS_POST_MODIFY_LO_REG_IMM3U;
  31603. + }
  31604. +
  31605. + if ((GET_CODE (op) == PLUS)
  31606. + && (GET_CODE (XEXP (op, 0)) == REG)
  31607. + && (GET_CODE (XEXP (op, 1)) == CONST_INT))
  31608. + {
  31609. + val = INTVAL (XEXP (op, 1));
  31610. +
  31611. + regno = REGNO(XEXP (op, 0));
  31612. +
  31613. + if (regno > 8
  31614. + && regno != SP_REGNUM
  31615. + && regno != FP_REGNUM)
  31616. + return ADDRESS_NOT_16BIT_FORMAT;
  31617. +
  31618. + switch (mode_test)
  31619. + {
  31620. + case QImode:
  31621. + /* 333 format. */
  31622. + if (val >= 0 && val < 8 && regno < 8)
  31623. + return ADDRESS_LO_REG_IMM3U;
  31624. + break;
  31625. +
  31626. + case HImode:
  31627. + /* 333 format. */
  31628. + if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
  31629. + return ADDRESS_LO_REG_IMM3U;
  31630. + break;
  31631. +
  31632. + case SImode:
  31633. + case SFmode:
  31634. + case DFmode:
  31635. + /* r8 imply fe format. */
  31636. + if ((regno == 8) &&
  31637. + (val >= -128 && val <= -4 && (val % 4 == 0)))
  31638. + return ADDRESS_R8_IMM7U;
  31639. + /* fp imply 37 format. */
  31640. + if ((regno == FP_REGNUM) &&
  31641. + (val >= 0 && val < 512 && (val % 4 == 0)))
  31642. + return ADDRESS_FP_IMM7U;
  31643. + /* sp imply 37 format. */
  31644. + else if ((regno == SP_REGNUM) &&
  31645. + (val >= 0 && val < 512 && (val % 4 == 0)))
  31646. + return ADDRESS_SP_IMM7U;
  31647. + /* 333 format. */
  31648. + else if (val >= 0 && val < 32 && (val % 4 == 0) && regno < 8)
  31649. + return ADDRESS_LO_REG_IMM3U;
  31650. + break;
  31651. +
  31652. + default:
  31653. + break;
  31654. + }
  31655. + }
  31656. +
  31657. + return ADDRESS_NOT_16BIT_FORMAT;
  31658. +}
  31659. +
  31660. +/* Output 16-bit store. */
  31661. +const char *
  31662. +nds32_output_16bit_store (rtx *operands, int byte)
  31663. +{
  31664. + char pattern[100];
  31665. + char size;
  31666. + rtx code = XEXP (operands[0], 0);
  31667. +
  31668. + size = nds32_byte_to_size (byte);
  31669. +
  31670. + switch (nds32_mem_format (operands[0]))
  31671. + {
  31672. + case ADDRESS_REG:
  31673. + operands[0] = code;
  31674. + output_asm_insn ("swi450\t%1, [%0]", operands);
  31675. + break;
  31676. + case ADDRESS_LO_REG_IMM3U:
  31677. + snprintf (pattern, sizeof (pattern), "s%ci333\t%%1, %%0", size);
  31678. + output_asm_insn (pattern, operands);
  31679. + break;
  31680. + case ADDRESS_POST_INC_LO_REG_IMM3U:
  31681. + snprintf (pattern, sizeof (pattern), "swi333.bi\t%%1, %%0, 4");
  31682. + output_asm_insn (pattern, operands);
  31683. + break;
  31684. + case ADDRESS_POST_MODIFY_LO_REG_IMM3U:
  31685. + snprintf (pattern, sizeof (pattern), "swi333.bi\t%%1, %%0");
  31686. + output_asm_insn (pattern, operands);
  31687. + break;
  31688. + case ADDRESS_FP_IMM7U:
  31689. + output_asm_insn ("swi37\t%1, %0", operands);
  31690. + break;
  31691. + case ADDRESS_SP_IMM7U:
  31692. + /* Get immediate value and set back to operands[1]. */
  31693. + operands[0] = XEXP (code, 1);
  31694. + output_asm_insn ("swi37.sp\t%1, [ + (%0)]", operands);
  31695. + break;
  31696. + default:
  31697. + break;
  31698. + }
  31699. +
  31700. + return "";
  31701. +}
  31702. +
  31703. +/* Output 16-bit load. */
  31704. +const char *
  31705. +nds32_output_16bit_load (rtx *operands, int byte)
  31706. +{
  31707. + char pattern[100];
  31708. + unsigned char size;
  31709. + rtx code = XEXP (operands[1], 0);
  31710. +
  31711. + size = nds32_byte_to_size (byte);
  31712. +
  31713. + switch (nds32_mem_format (operands[1]))
  31714. + {
  31715. + case ADDRESS_REG:
  31716. + operands[1] = code;
  31717. + output_asm_insn ("lwi450\t%0, [%1]", operands);
  31718. + break;
  31719. + case ADDRESS_LO_REG_IMM3U:
  31720. + snprintf (pattern, sizeof (pattern), "l%ci333\t%%0, %%1", size);
  31721. + output_asm_insn (pattern, operands);
  31722. + break;
  31723. + case ADDRESS_POST_INC_LO_REG_IMM3U:
  31724. + snprintf (pattern, sizeof (pattern), "lwi333.bi\t%%0, %%1, 4");
  31725. + output_asm_insn (pattern, operands);
  31726. + break;
  31727. + case ADDRESS_POST_MODIFY_LO_REG_IMM3U:
  31728. + snprintf (pattern, sizeof (pattern), "lwi333.bi\t%%0, %%1");
  31729. + output_asm_insn (pattern, operands);
  31730. + break;
  31731. + case ADDRESS_R8_IMM7U:
  31732. + output_asm_insn ("lwi45.fe\t%0, %e1", operands);
  31733. + break;
  31734. + case ADDRESS_FP_IMM7U:
  31735. + output_asm_insn ("lwi37\t%0, %1", operands);
  31736. + break;
  31737. + case ADDRESS_SP_IMM7U:
  31738. + /* Get immediate value and set back to operands[0]. */
  31739. + operands[1] = XEXP (code, 1);
  31740. + output_asm_insn ("lwi37.sp\t%0, [ + (%1)]", operands);
  31741. + break;
  31742. + default:
  31743. + break;
  31744. + }
  31745. +
  31746. + return "";
  31747. +}
  31748. +
  31749. +/* Output 32-bit store. */
  31750. +const char *
  31751. +nds32_output_32bit_store (rtx *operands, int byte)
  31752. +{
  31753. + char pattern[100];
  31754. + unsigned char size;
  31755. + rtx code = XEXP (operands[0], 0);
  31756. +
  31757. + size = nds32_byte_to_size (byte);
  31758. +
  31759. + switch (GET_CODE (code))
  31760. + {
  31761. + case REG:
  31762. + /* (mem (reg X))
  31763. + => access location by using register,
  31764. + use "sbi / shi / swi" */
  31765. + snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
  31766. + break;
  31767. +
  31768. + case SYMBOL_REF:
  31769. + case CONST:
  31770. + /* (mem (symbol_ref X))
  31771. + (mem (const (...)))
  31772. + => access global variables,
  31773. + use "sbi.gp / shi.gp / swi.gp" */
  31774. + operands[0] = XEXP (operands[0], 0);
  31775. + snprintf (pattern, sizeof (pattern), "s%ci.gp\t%%1, [ + %%0]", size);
  31776. + break;
  31777. +
  31778. + case POST_INC:
  31779. + /* (mem (post_inc reg))
  31780. + => access location by using register which will be post increment,
  31781. + use "sbi.bi / shi.bi / swi.bi" */
  31782. + snprintf (pattern, sizeof (pattern),
  31783. + "s%ci.bi\t%%1, %%0, %d", size, byte);
  31784. + break;
  31785. +
  31786. + case POST_DEC:
  31787. + /* (mem (post_dec reg))
  31788. + => access location by using register which will be post decrement,
  31789. + use "sbi.bi / shi.bi / swi.bi" */
  31790. + snprintf (pattern, sizeof (pattern),
  31791. + "s%ci.bi\t%%1, %%0, -%d", size, byte);
  31792. + break;
  31793. +
  31794. + case POST_MODIFY:
  31795. + switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  31796. + {
  31797. + case REG:
  31798. + case SUBREG:
  31799. + /* (mem (post_modify (reg) (plus (reg) (reg))))
  31800. + => access location by using register which will be
  31801. + post modified with reg,
  31802. + use "sb.bi/ sh.bi / sw.bi" */
  31803. + snprintf (pattern, sizeof (pattern), "s%c.bi\t%%1, %%0", size);
  31804. + break;
  31805. + case CONST_INT:
  31806. + /* (mem (post_modify (reg) (plus (reg) (const_int))))
  31807. + => access location by using register which will be
  31808. + post modified with const_int,
  31809. + use "sbi.bi/ shi.bi / swi.bi" */
  31810. + snprintf (pattern, sizeof (pattern), "s%ci.bi\t%%1, %%0", size);
  31811. + break;
  31812. + default:
  31813. + abort ();
  31814. + }
  31815. + break;
  31816. +
  31817. + case PLUS:
  31818. + switch (GET_CODE (XEXP (code, 1)))
  31819. + {
  31820. + case REG:
  31821. + case SUBREG:
  31822. + /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  31823. + => access location by adding two registers,
  31824. + use "sb / sh / sw" */
  31825. + snprintf (pattern, sizeof (pattern), "s%c\t%%1, %%0", size);
  31826. + break;
  31827. + case CONST_INT:
  31828. + /* (mem (plus reg const_int))
  31829. + => access location by adding one register with const_int,
  31830. + use "sbi / shi / swi" */
  31831. + snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
  31832. + break;
  31833. + default:
  31834. + abort ();
  31835. + }
  31836. + break;
  31837. +
  31838. + case LO_SUM:
  31839. + operands[2] = XEXP (code, 1);
  31840. + operands[0] = XEXP (code, 0);
  31841. + snprintf (pattern, sizeof (pattern),
  31842. + "s%ci\t%%1, [%%0 + lo12(%%2)]", size);
  31843. + break;
  31844. +
  31845. + default:
  31846. + abort ();
  31847. + }
  31848. +
  31849. + output_asm_insn (pattern, operands);
  31850. + return "";
  31851. +}
  31852. +
  31853. +/* Output 32-bit load. */
  31854. +const char *
  31855. +nds32_output_32bit_load (rtx *operands, int byte)
  31856. +{
  31857. + char pattern[100];
  31858. + unsigned char size;
  31859. + rtx code;
  31860. +
  31861. + code = XEXP (operands[1], 0);
  31862. +
  31863. + size = nds32_byte_to_size (byte);
  31864. +
  31865. + switch (GET_CODE (code))
  31866. + {
  31867. + case REG:
  31868. + /* (mem (reg X))
  31869. + => access location by using register,
  31870. + use "lbi / lhi / lwi" */
  31871. + snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
  31872. + break;
  31873. +
  31874. + case SYMBOL_REF:
  31875. + case CONST:
  31876. + /* (mem (symbol_ref X))
  31877. + (mem (const (...)))
  31878. + => access global variables,
  31879. + use "lbi.gp / lhi.gp / lwi.gp" */
  31880. + operands[1] = XEXP (operands[1], 0);
  31881. + snprintf (pattern, sizeof (pattern), "l%ci.gp\t%%0, [ + %%1]", size);
  31882. + break;
  31883. +
  31884. + case POST_INC:
  31885. + /* (mem (post_inc reg))
  31886. + => access location by using register which will be post increment,
  31887. + use "lbi.bi / lhi.bi / lwi.bi" */
  31888. + snprintf (pattern, sizeof (pattern),
  31889. + "l%ci.bi\t%%0, %%1, %d", size, byte);
  31890. + break;
  31891. +
  31892. + case POST_DEC:
  31893. + /* (mem (post_dec reg))
  31894. + => access location by using register which will be post decrement,
  31895. + use "lbi.bi / lhi.bi / lwi.bi" */
  31896. + snprintf (pattern, sizeof (pattern),
  31897. + "l%ci.bi\t%%0, %%1, -%d", size, byte);
  31898. + break;
  31899. +
  31900. + case POST_MODIFY:
  31901. + switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  31902. + {
  31903. + case REG:
  31904. + case SUBREG:
  31905. + /* (mem (post_modify (reg) (plus (reg) (reg))))
  31906. + => access location by using register which will be
  31907. + post modified with reg,
  31908. + use "lb.bi/ lh.bi / lw.bi" */
  31909. + snprintf (pattern, sizeof (pattern), "l%c.bi\t%%0, %%1", size);
  31910. + break;
  31911. + case CONST_INT:
  31912. + /* (mem (post_modify (reg) (plus (reg) (const_int))))
  31913. + => access location by using register which will be
  31914. + post modified with const_int,
  31915. + use "lbi.bi/ lhi.bi / lwi.bi" */
  31916. + snprintf (pattern, sizeof (pattern), "l%ci.bi\t%%0, %%1", size);
  31917. + break;
  31918. + default:
  31919. + abort ();
  31920. + }
  31921. + break;
  31922. +
  31923. + case PLUS:
  31924. + switch (GET_CODE (XEXP (code, 1)))
  31925. + {
  31926. + case REG:
  31927. + case SUBREG:
  31928. + /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  31929. + use "lb / lh / lw" */
  31930. + snprintf (pattern, sizeof (pattern), "l%c\t%%0, %%1", size);
  31931. + break;
  31932. + case CONST_INT:
  31933. + /* (mem (plus reg const_int))
  31934. + => access location by adding one register with const_int,
  31935. + use "lbi / lhi / lwi" */
  31936. + snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
  31937. + break;
  31938. + default:
  31939. + abort ();
  31940. + }
  31941. + break;
  31942. +
  31943. + case LO_SUM:
  31944. + operands[2] = XEXP (code, 1);
  31945. + operands[1] = XEXP (code, 0);
  31946. + snprintf (pattern, sizeof (pattern),
  31947. + "l%ci\t%%0, [%%1 + lo12(%%2)]", size);
  31948. + break;
  31949. +
  31950. + default:
  31951. + abort ();
  31952. + }
  31953. +
  31954. + output_asm_insn (pattern, operands);
  31955. + return "";
  31956. +}
  31957. +
  31958. +/* Output 32-bit load with signed extension. */
  31959. +const char *
  31960. +nds32_output_32bit_load_se (rtx *operands, int byte)
  31961. +{
  31962. + char pattern[100];
  31963. + unsigned char size;
  31964. + rtx code;
  31965. +
  31966. + code = XEXP (operands[1], 0);
  31967. +
  31968. + size = nds32_byte_to_size (byte);
  31969. +
  31970. + switch (GET_CODE (code))
  31971. + {
  31972. + case REG:
  31973. + /* (mem (reg X))
  31974. + => access location by using register,
  31975. + use "lbsi / lhsi" */
  31976. + snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
  31977. + break;
  31978. +
  31979. + case SYMBOL_REF:
  31980. + case CONST:
  31981. + /* (mem (symbol_ref X))
  31982. + (mem (const (...)))
  31983. + => access global variables,
  31984. + use "lbsi.gp / lhsi.gp" */
  31985. + operands[1] = XEXP (operands[1], 0);
  31986. + snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
  31987. + break;
  31988. +
  31989. + case POST_INC:
  31990. + /* (mem (post_inc reg))
  31991. + => access location by using register which will be post increment,
  31992. + use "lbsi.bi / lhsi.bi" */
  31993. + snprintf (pattern, sizeof (pattern),
  31994. + "l%csi.bi\t%%0, %%1, %d", size, byte);
  31995. + break;
  31996. +
  31997. + case POST_DEC:
  31998. + /* (mem (post_dec reg))
  31999. + => access location by using register which will be post decrement,
  32000. + use "lbsi.bi / lhsi.bi" */
  32001. + snprintf (pattern, sizeof (pattern),
  32002. + "l%csi.bi\t%%0, %%1, -%d", size, byte);
  32003. + break;
  32004. +
  32005. + case POST_MODIFY:
  32006. + switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
  32007. + {
  32008. + case REG:
  32009. + case SUBREG:
  32010. + /* (mem (post_modify (reg) (plus (reg) (reg))))
  32011. + => access location by using register which will be
  32012. + post modified with reg,
  32013. + use "lbs.bi/ lhs.bi" */
  32014. + snprintf (pattern, sizeof (pattern), "l%cs.bi\t%%0, %%1", size);
  32015. + break;
  32016. + case CONST_INT:
  32017. + /* (mem (post_modify (reg) (plus (reg) (const_int))))
  32018. + => access location by using register which will be
  32019. + post modified with const_int,
  32020. + use "lbsi.bi/ lhsi.bi" */
  32021. + snprintf (pattern, sizeof (pattern), "l%csi.bi\t%%0, %%1", size);
  32022. + break;
  32023. + default:
  32024. + abort ();
  32025. + }
  32026. + break;
  32027. +
  32028. + case PLUS:
  32029. + switch (GET_CODE (XEXP (code, 1)))
  32030. + {
  32031. + case REG:
  32032. + case SUBREG:
  32033. + /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
  32034. + use "lbs / lhs" */
  32035. + snprintf (pattern, sizeof (pattern), "l%cs\t%%0, %%1", size);
  32036. + break;
  32037. + case CONST_INT:
  32038. + /* (mem (plus reg const_int))
  32039. + => access location by adding one register with const_int,
  32040. + use "lbsi / lhsi" */
  32041. + snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
  32042. + break;
  32043. + default:
  32044. + abort ();
  32045. + }
  32046. + break;
  32047. +
  32048. + case LO_SUM:
  32049. + operands[2] = XEXP (code, 1);
  32050. + operands[1] = XEXP (code, 0);
  32051. + snprintf (pattern, sizeof (pattern),
  32052. + "l%csi\t%%0, [%%1 + lo12(%%2)]", size);
  32053. + break;
  32054. +
  32055. + default:
  32056. + abort ();
  32057. + }
  32058. +
  32059. + output_asm_insn (pattern, operands);
  32060. + return "";
  32061. +}
  32062. +
  32063. +/* Function to output stack push operation.
  32064. + We need to deal with normal stack push multiple or stack v3push. */
  32065. +const char *
  32066. +nds32_output_stack_push (rtx par_rtx)
  32067. +{
  32068. + /* A string pattern for output_asm_insn(). */
  32069. + char pattern[100];
  32070. + /* The operands array which will be used in output_asm_insn(). */
  32071. + rtx operands[3];
  32072. + /* Pick up varargs first regno and last regno for further use. */
  32073. + int rb_va_args = cfun->machine->va_args_first_regno;
  32074. + int re_va_args = cfun->machine->va_args_last_regno;
  32075. + int last_argument_regno = NDS32_FIRST_GPR_REGNUM
  32076. + + NDS32_MAX_GPR_REGS_FOR_ARGS
  32077. + - 1;
  32078. + /* Pick up first and last eh data regno for further use. */
  32079. + int rb_eh_data = cfun->machine->eh_return_data_first_regno;
  32080. + int re_eh_data = cfun->machine->eh_return_data_last_regno;
  32081. + int first_eh_data_regno = EH_RETURN_DATA_REGNO (0);
  32082. + /* Pick up callee-saved first regno and last regno for further use. */
  32083. + int rb_callee_saved = cfun->machine->callee_saved_first_gpr_regno;
  32084. + int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
  32085. +
  32086. + /* First we need to check if we are pushing argument registers not used
  32087. + for the named arguments. If so, we have to create 'smw.adm' (push.s)
  32088. + instruction. */
  32089. + if (reg_mentioned_p (gen_rtx_REG (SImode, last_argument_regno), par_rtx))
  32090. + {
  32091. + /* Set operands[0] and operands[1]. */
  32092. + operands[0] = gen_rtx_REG (SImode, rb_va_args);
  32093. + operands[1] = gen_rtx_REG (SImode, re_va_args);
  32094. + /* Create assembly code pattern: "Rb, Re, { }". */
  32095. + snprintf (pattern, sizeof (pattern), "push.s\t%s", "%0, %1, { }");
  32096. + /* We use output_asm_insn() to output assembly code by ourself. */
  32097. + output_asm_insn (pattern, operands);
  32098. + return "";
  32099. + }
  32100. +
  32101. + /* If last_argument_regno is not mentioned in par_rtx, we can confirm that
  32102. + we do not need to push argument registers for variadic function.
  32103. + But we still need to check if we need to push exception handling
  32104. + data registers. */
  32105. + if (reg_mentioned_p (gen_rtx_REG (SImode, first_eh_data_regno), par_rtx))
  32106. + {
  32107. + /* Set operands[0] and operands[1]. */
  32108. + operands[0] = gen_rtx_REG (SImode, rb_eh_data);
  32109. + operands[1] = gen_rtx_REG (SImode, re_eh_data);
  32110. + /* Create assembly code pattern: "Rb, Re, { }". */
  32111. + snprintf (pattern, sizeof (pattern), "push.s\t%s", "%0, %1, { }");
  32112. + /* We use output_asm_insn() to output assembly code by ourself. */
  32113. + output_asm_insn (pattern, operands);
  32114. + return "";
  32115. + }
  32116. +
  32117. + /* If we step here, we are going to do v3push or multiple push operation. */
  32118. +
  32119. + /* Refer to nds32.h, where we comment when push25/pop25 are available. */
  32120. + if (NDS32_V3PUSH_AVAILABLE_P)
  32121. + {
  32122. + /* For stack v3push:
  32123. + operands[0]: Re
  32124. + operands[1]: imm8u */
  32125. +
  32126. + /* This variable is to check if 'push25 Re,imm8u' is available. */
  32127. + int sp_adjust;
  32128. +
  32129. + /* Set operands[0]. */
  32130. + operands[0] = gen_rtx_REG (SImode, re_callee_saved);
  32131. +
  32132. + /* Check if we can generate 'push25 Re,imm8u',
  32133. + otherwise, generate 'push25 Re,0'. */
  32134. + sp_adjust = cfun->machine->local_size
  32135. + + cfun->machine->out_args_size
  32136. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  32137. + + cfun->machine->callee_saved_fpr_regs_size;
  32138. + if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  32139. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
  32140. + operands[1] = GEN_INT (sp_adjust);
  32141. + else
  32142. + {
  32143. + /* Allocate callee saved fpr space. */
  32144. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  32145. + {
  32146. + sp_adjust = cfun->machine->callee_saved_area_gpr_padding_bytes
  32147. + + cfun->machine->callee_saved_fpr_regs_size;
  32148. + operands[1] = GEN_INT (sp_adjust);
  32149. + }
  32150. + else
  32151. + {
  32152. + operands[1] = GEN_INT (0);
  32153. + }
  32154. + }
  32155. +
  32156. + /* Create assembly code pattern. */
  32157. + snprintf (pattern, sizeof (pattern), "push25\t%%0, %%1");
  32158. + }
  32159. + else
  32160. + {
  32161. + /* For normal stack push multiple:
  32162. + operands[0]: Rb
  32163. + operands[1]: Re
  32164. + operands[2]: En4 */
  32165. +
  32166. + /* This variable is used to check if we only need to generate En4 field.
  32167. + As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
  32168. + int push_en4_only_p = 0;
  32169. +
  32170. + /* Set operands[0] and operands[1]. */
  32171. + operands[0] = gen_rtx_REG (SImode, rb_callee_saved);
  32172. + operands[1] = gen_rtx_REG (SImode, re_callee_saved);
  32173. +
  32174. + /* 'smw.adm $sp,[$sp],$sp,0' means push nothing. */
  32175. + if (!cfun->machine->fp_size
  32176. + && !cfun->machine->gp_size
  32177. + && !cfun->machine->lp_size
  32178. + && REGNO (operands[0]) == SP_REGNUM
  32179. + && REGNO (operands[1]) == SP_REGNUM)
  32180. + {
  32181. + /* No need to generate instruction. */
  32182. + return "";
  32183. + }
  32184. + else
  32185. + {
  32186. + /* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
  32187. + if (REGNO (operands[0]) == SP_REGNUM
  32188. + && REGNO (operands[1]) == SP_REGNUM)
  32189. + push_en4_only_p = 1;
  32190. +
  32191. + /* Create assembly code pattern.
  32192. + We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
  32193. + snprintf (pattern, sizeof (pattern),
  32194. + "push.s\t%s{%s%s%s }",
  32195. + push_en4_only_p ? "" : "%0, %1, ",
  32196. + cfun->machine->fp_size ? " $fp" : "",
  32197. + cfun->machine->gp_size ? " $gp" : "",
  32198. + cfun->machine->lp_size ? " $lp" : "");
  32199. + }
  32200. + }
  32201. +
  32202. + /* We use output_asm_insn() to output assembly code by ourself. */
  32203. + output_asm_insn (pattern, operands);
  32204. + return "";
  32205. +}
  32206. +
  32207. +/* Function to output stack pop operation.
  32208. + We need to deal with normal stack pop multiple or stack v3pop. */
  32209. +const char *
  32210. +nds32_output_stack_pop (rtx par_rtx ATTRIBUTE_UNUSED)
  32211. +{
  32212. + /* A string pattern for output_asm_insn(). */
  32213. + char pattern[100];
  32214. + /* The operands array which will be used in output_asm_insn(). */
  32215. + rtx operands[3];
  32216. + /* Pick up first and last eh data regno for further use. */
  32217. + int rb_eh_data = cfun->machine->eh_return_data_first_regno;
  32218. + int re_eh_data = cfun->machine->eh_return_data_last_regno;
  32219. + int first_eh_data_regno = EH_RETURN_DATA_REGNO (0);
  32220. + /* Pick up callee-saved first regno and last regno for further use. */
  32221. + int rb_callee_saved = cfun->machine->callee_saved_first_gpr_regno;
  32222. + int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
  32223. +
  32224. + /* We need to check if we need to push exception handling
  32225. + data registers. */
  32226. + if (reg_mentioned_p (gen_rtx_REG (SImode, first_eh_data_regno), par_rtx))
  32227. + {
  32228. + /* Set operands[0] and operands[1]. */
  32229. + operands[0] = gen_rtx_REG (SImode, rb_eh_data);
  32230. + operands[1] = gen_rtx_REG (SImode, re_eh_data);
  32231. + /* Create assembly code pattern: "Rb, Re, { }". */
  32232. + snprintf (pattern, sizeof (pattern), "pop.s\t%s", "%0, %1, { }");
  32233. + /* We use output_asm_insn() to output assembly code by ourself. */
  32234. + output_asm_insn (pattern, operands);
  32235. + return "";
  32236. + }
  32237. +
  32238. + /* If we step here, we are going to do v3pop or multiple pop operation. */
  32239. +
  32240. + /* Refer to nds32.h, where we comment when push25/pop25 are available. */
  32241. + if (NDS32_V3PUSH_AVAILABLE_P)
  32242. + {
  32243. + /* For stack v3pop:
  32244. + operands[0]: Re
  32245. + operands[1]: imm8u */
  32246. +
  32247. + /* This variable is to check if 'pop25 Re,imm8u' is available. */
  32248. + int sp_adjust;
  32249. +
  32250. + /* Set operands[0]. */
  32251. + operands[0] = gen_rtx_REG (SImode, re_callee_saved);
  32252. +
  32253. + /* Check if we can generate 'pop25 Re,imm8u',
  32254. + otherwise, generate 'pop25 Re,0'.
  32255. + We have to consider alloca issue as well.
  32256. + If the function does call alloca(), the stack pointer is not fixed.
  32257. + In that case, we cannot use 'pop25 Re,imm8u' directly.
  32258. + We have to caculate stack pointer from frame pointer
  32259. + and then use 'pop25 Re,0'. */
  32260. + sp_adjust = cfun->machine->local_size
  32261. + + cfun->machine->out_args_size
  32262. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  32263. + + cfun->machine->callee_saved_fpr_regs_size;
  32264. + if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  32265. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  32266. + && !cfun->calls_alloca)
  32267. + operands[1] = GEN_INT (sp_adjust);
  32268. + else
  32269. + {
  32270. + if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
  32271. + {
  32272. + /* If has fpr need to restore, the $sp on callee saved fpr
  32273. + position, so we need to consider gpr pading bytes and
  32274. + callee saved fpr size. */
  32275. + sp_adjust = cfun->machine->callee_saved_area_gpr_padding_bytes
  32276. + + cfun->machine->callee_saved_fpr_regs_size;
  32277. + operands[1] = GEN_INT (sp_adjust);
  32278. + }
  32279. + else
  32280. + {
  32281. + operands[1] = GEN_INT (0);
  32282. + }
  32283. + }
  32284. +
  32285. + /* Create assembly code pattern. */
  32286. + snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
  32287. + }
  32288. + else
  32289. + {
  32290. + /* For normal stack pop multiple:
  32291. + operands[0]: Rb
  32292. + operands[1]: Re
  32293. + operands[2]: En4 */
  32294. +
  32295. + /* This variable is used to check if we only need to generate En4 field.
  32296. + As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
  32297. + int pop_en4_only_p = 0;
  32298. +
  32299. + /* Set operands[0] and operands[1]. */
  32300. + operands[0] = gen_rtx_REG (SImode, rb_callee_saved);
  32301. + operands[1] = gen_rtx_REG (SImode, re_callee_saved);
  32302. +
  32303. + /* 'lmw.bim $sp,[$sp],$sp,0' means pop nothing. */
  32304. + if (!cfun->machine->fp_size
  32305. + && !cfun->machine->gp_size
  32306. + && !cfun->machine->lp_size
  32307. + && REGNO (operands[0]) == SP_REGNUM
  32308. + && REGNO (operands[1]) == SP_REGNUM)
  32309. + {
  32310. + /* No need to generate instruction. */
  32311. + return "";
  32312. + }
  32313. + else
  32314. + {
  32315. + /* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
  32316. + if (REGNO (operands[0]) == SP_REGNUM
  32317. + && REGNO (operands[1]) == SP_REGNUM)
  32318. + pop_en4_only_p = 1;
  32319. +
  32320. + /* Create assembly code pattern.
  32321. + We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
  32322. + snprintf (pattern, sizeof (pattern),
  32323. + "pop.s\t%s{%s%s%s }",
  32324. + pop_en4_only_p ? "" : "%0, %1, ",
  32325. + cfun->machine->fp_size ? " $fp" : "",
  32326. + cfun->machine->gp_size ? " $gp" : "",
  32327. + cfun->machine->lp_size ? " $lp" : "");
  32328. + }
  32329. + }
  32330. +
  32331. + /* We use output_asm_insn() to output assembly code by ourself. */
  32332. + output_asm_insn (pattern, operands);
  32333. + return "";
  32334. +}
  32335. +
  32336. +/* Function to output return operation. */
  32337. +const char *
  32338. +nds32_output_return (void)
  32339. +{
  32340. + /* A string pattern for output_asm_insn(). */
  32341. + char pattern[100];
  32342. + /* The operands array which will be used in output_asm_insn(). */
  32343. + rtx operands[2];
  32344. + /* For stack v3pop:
  32345. + operands[0]: Re
  32346. + operands[1]: imm8u */
  32347. + int re_callee_saved = cfun->machine->callee_saved_last_gpr_regno;
  32348. + int sp_adjust;
  32349. +
  32350. + /* Set operands[0]. */
  32351. + operands[0] = gen_rtx_REG (SImode, re_callee_saved);
  32352. +
  32353. + /* Check if we can generate 'pop25 Re,imm8u',
  32354. + otherwise, generate 'pop25 Re,0'.
  32355. + We have to consider alloca issue as well.
  32356. + If the function does call alloca(), the stack pointer is not fixed.
  32357. + In that case, we cannot use 'pop25 Re,imm8u' directly.
  32358. + We have to caculate stack pointer from frame pointer
  32359. + and then use 'pop25 Re,0'. */
  32360. + sp_adjust = cfun->machine->local_size
  32361. + + cfun->machine->out_args_size
  32362. + + cfun->machine->callee_saved_area_gpr_padding_bytes
  32363. + + cfun->machine->callee_saved_fpr_regs_size;
  32364. + if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
  32365. + && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
  32366. + && !cfun->calls_alloca)
  32367. + operands[1] = GEN_INT (sp_adjust);
  32368. + else
  32369. + operands[1] = GEN_INT (0);
  32370. +
  32371. + /* Create assembly code pattern. */
  32372. + snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
  32373. + /* We use output_asm_insn() to output assembly code by ourself. */
  32374. + output_asm_insn (pattern, operands);
  32375. + return "";
  32376. +}
  32377. +
  32378. +
  32379. +/* output a float load instruction */
  32380. +const char *
  32381. +nds32_output_float_load (rtx *operands)
  32382. +{
  32383. + char buff[100];
  32384. + const char *pattern;
  32385. + rtx addr, addr_op0, addr_op1;
  32386. + int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
  32387. + addr = XEXP (operands[1], 0);
  32388. + switch (GET_CODE (addr))
  32389. + {
  32390. + case REG:
  32391. + pattern = "fl%ci\t%%0, %%1";
  32392. + break;
  32393. +
  32394. + case PLUS:
  32395. + addr_op0 = XEXP (addr, 0);
  32396. + addr_op1 = XEXP (addr, 1);
  32397. +
  32398. + if (REG_P (addr_op0) && REG_P (addr_op1))
  32399. + pattern = "fl%c\t%%0, %%1";
  32400. + else if (REG_P (addr_op0) && CONST_INT_P (addr_op1))
  32401. + pattern = "fl%ci\t%%0, %%1";
  32402. + else if (GET_CODE (addr_op0) == MULT && REG_P (addr_op1)
  32403. + && REG_P (XEXP (addr_op0, 0))
  32404. + && CONST_INT_P (XEXP (addr_op0, 1)))
  32405. + pattern = "fl%c\t%%0, %%1";
  32406. + else
  32407. + gcc_unreachable ();
  32408. + break;
  32409. +
  32410. + case POST_MODIFY:
  32411. + addr_op0 = XEXP (addr, 0);
  32412. + addr_op1 = XEXP (addr, 1);
  32413. +
  32414. + if (REG_P (addr_op0) && GET_CODE (addr_op1) == PLUS
  32415. + && REG_P (XEXP (addr_op1, 1)))
  32416. + pattern = "fl%c.bi\t%%0, %%1";
  32417. + else if (REG_P (addr_op0) && GET_CODE (addr_op1) == PLUS
  32418. + && CONST_INT_P (XEXP (addr_op1, 1)))
  32419. + pattern = "fl%ci.bi\t%%0, %%1";
  32420. + else
  32421. + gcc_unreachable ();
  32422. + break;
  32423. +
  32424. + case POST_INC:
  32425. + if (REG_P (XEXP (addr, 0)))
  32426. + {
  32427. + if (dp)
  32428. + pattern = "fl%ci.bi\t%%0, %%1, 8";
  32429. + else
  32430. + pattern = "fl%ci.bi\t%%0, %%1, 4";
  32431. + }
  32432. + else
  32433. + gcc_unreachable ();
  32434. + break;
  32435. +
  32436. + case POST_DEC:
  32437. + if (REG_P (XEXP (addr, 0)))
  32438. + {
  32439. + if (dp)
  32440. + pattern = "fl%ci.bi\t%%0, %%1, -8";
  32441. + else
  32442. + pattern = "fl%ci.bi\t%%0, %%1, -4";
  32443. + }
  32444. + else
  32445. + gcc_unreachable ();
  32446. + break;
  32447. +
  32448. + default:
  32449. + gcc_unreachable ();
  32450. + }
  32451. +
  32452. + sprintf (buff, pattern, dp ? 'd' : 's');
  32453. + output_asm_insn (buff, operands);
  32454. + return "";
  32455. +}
  32456. +
  32457. +/* output a float store instruction */
  32458. +const char *
  32459. +nds32_output_float_store (rtx *operands)
  32460. +{
  32461. + char buff[100];
  32462. + const char *pattern;
  32463. + rtx addr, addr_op0, addr_op1;
  32464. + int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
  32465. + addr = XEXP (operands[0], 0);
  32466. + switch (GET_CODE (addr))
  32467. + {
  32468. + case REG:
  32469. + pattern = "fs%ci\t%%1, %%0";
  32470. + break;
  32471. +
  32472. + case PLUS:
  32473. + addr_op0 = XEXP (addr, 0);
  32474. + addr_op1 = XEXP (addr, 1);
  32475. +
  32476. + if (REG_P (addr_op0) && REG_P (addr_op1))
  32477. + pattern = "fs%c\t%%1, %%0";
  32478. + else if (REG_P (addr_op0) && CONST_INT_P (addr_op1))
  32479. + pattern = "fs%ci\t%%1, %%0";
  32480. + else if (GET_CODE (addr_op0) == MULT && REG_P (addr_op1)
  32481. + && REG_P (XEXP (addr_op0, 0))
  32482. + && CONST_INT_P (XEXP (addr_op0, 1)))
  32483. + pattern = "fs%c\t%%1, %%0";
  32484. + else
  32485. + gcc_unreachable ();
  32486. + break;
  32487. +
  32488. + case POST_MODIFY:
  32489. + addr_op0 = XEXP (addr, 0);
  32490. + addr_op1 = XEXP (addr, 1);
  32491. +
  32492. + if (REG_P (addr_op0) && GET_CODE (addr_op1) == PLUS
  32493. + && REG_P (XEXP (addr_op1, 1)))
  32494. + pattern = "fs%c.bi\t%%1, %%0";
  32495. + else if (REG_P (addr_op0) && GET_CODE (addr_op1) == PLUS
  32496. + && CONST_INT_P (XEXP (addr_op1, 1)))
  32497. + pattern = "fs%ci.bi\t%%1, %%0";
  32498. + else
  32499. + gcc_unreachable ();
  32500. + break;
  32501. +
  32502. + case POST_INC:
  32503. + if (REG_P (XEXP (addr, 0)))
  32504. + {
  32505. + if (dp)
  32506. + pattern = "fs%ci.bi\t%%1, %%0, 8";
  32507. + else
  32508. + pattern = "fs%ci.bi\t%%1, %%0, 4";
  32509. + }
  32510. + else
  32511. + gcc_unreachable ();
  32512. + break;
  32513. +
  32514. + case POST_DEC:
  32515. + if (REG_P (XEXP (addr, 0)))
  32516. + {
  32517. + if (dp)
  32518. + pattern = "fs%ci.bi\t%%1, %%0, -8";
  32519. + else
  32520. + pattern = "fs%ci.bi\t%%1, %%0, -4";
  32521. + }
  32522. + else
  32523. + gcc_unreachable ();
  32524. + break;
  32525. +
  32526. + default:
  32527. + gcc_unreachable ();
  32528. + }
  32529. +
  32530. + sprintf (buff, pattern, dp ? 'd' : 's');
  32531. + output_asm_insn (buff, operands);
  32532. + return "";
  32533. +}
  32534. +
  32535. +const char *
  32536. +nds32_output_smw_single_word (rtx *operands)
  32537. +{
  32538. + char buff[100];
  32539. + unsigned regno;
  32540. + int enable4;
  32541. + bool update_base_p;
  32542. + rtx base_addr = operands[0];
  32543. + rtx base_reg;
  32544. + rtx otherops[2];
  32545. +
  32546. + if (REG_P (XEXP (base_addr, 0)))
  32547. + {
  32548. + update_base_p = false;
  32549. + base_reg = XEXP (base_addr, 0);
  32550. + }
  32551. + else
  32552. + {
  32553. + update_base_p = true;
  32554. + base_reg = XEXP (XEXP (base_addr, 0), 0);
  32555. + }
  32556. +
  32557. + const char *update_base = update_base_p ? "m" : "";
  32558. +
  32559. + regno = REGNO (operands[1]);
  32560. +
  32561. + otherops[0] = base_reg;
  32562. + otherops[1] = operands[1];
  32563. +
  32564. + if (regno >= 28)
  32565. + {
  32566. + enable4 = nds32_regno_to_enable4 (regno);
  32567. + sprintf (buff, "smw.bi%s\t$sp, [%%0], $sp, %x", update_base, enable4);
  32568. + }
  32569. + else
  32570. + {
  32571. + sprintf (buff, "smw.bi%s\t%%1, [%%0], %%1", update_base);
  32572. + }
  32573. + output_asm_insn (buff, otherops);
  32574. + return "";
  32575. +}
  32576. +
  32577. +const char *
  32578. +nds32_output_lmw_single_word (rtx *operands)
  32579. +{
  32580. + char buff[100];
  32581. + unsigned regno;
  32582. + bool update_base_p;
  32583. + int enable4;
  32584. + rtx base_addr = operands[1];
  32585. + rtx base_reg;
  32586. + rtx otherops[2];
  32587. +
  32588. + if (REG_P (XEXP (base_addr, 0)))
  32589. + {
  32590. + update_base_p = false;
  32591. + base_reg = XEXP (base_addr, 0);
  32592. + }
  32593. + else
  32594. + {
  32595. + update_base_p = true;
  32596. + base_reg = XEXP (XEXP (base_addr, 0), 0);
  32597. + }
  32598. +
  32599. + const char *update_base = update_base_p ? "m" : "";
  32600. +
  32601. + regno = REGNO (operands[0]);
  32602. +
  32603. + otherops[0] = operands[0];
  32604. + otherops[1] = base_reg;
  32605. +
  32606. + if (regno >= 28)
  32607. + {
  32608. + enable4 = nds32_regno_to_enable4 (regno);
  32609. + sprintf (buff, "lmw.bi%s\t$sp, [%%1], $sp, %x", update_base, enable4);
  32610. + }
  32611. + else
  32612. + {
  32613. + sprintf (buff, "lmw.bi%s\t%%0, [%%1], %%0", update_base);
  32614. + }
  32615. + output_asm_insn (buff, otherops);
  32616. + return "";
  32617. +}
  32618. +
  32619. +void
  32620. +nds32_expand_unaligned_load (rtx *operands, enum machine_mode mode)
  32621. +{
  32622. + /* Initial memory offset. */
  32623. + int offset = WORDS_BIG_ENDIAN ? GET_MODE_SIZE (mode) - 1 : 0;
  32624. + int offset_adj = WORDS_BIG_ENDIAN ? -1 : 1;
  32625. + /* Initial register shift byte. */
  32626. + int shift = 0;
  32627. + /* The first load byte instruction is not the same. */
  32628. + int width = GET_MODE_SIZE (mode) - 1;
  32629. + rtx mem[2];
  32630. + rtx reg[2];
  32631. + rtx sub_reg;
  32632. + rtx temp_reg, temp_sub_reg;
  32633. + int num_reg;
  32634. +
  32635. + /* Generating a series of load byte instructions.
  32636. + The first load byte instructions and other
  32637. + load byte instructions are not the same. like:
  32638. + First:
  32639. + lbi reg0, [mem]
  32640. + zeh reg0, reg0
  32641. + Second:
  32642. + lbi temp_reg, [mem + offset]
  32643. + sll temp_reg, (8 * shift)
  32644. + ior reg0, temp_reg
  32645. +
  32646. + lbi temp_reg, [mem + (offset + 1)]
  32647. + sll temp_reg, (8 * (shift + 1))
  32648. + ior reg0, temp_reg */
  32649. +
  32650. + temp_reg = gen_reg_rtx (SImode);
  32651. + temp_sub_reg = gen_lowpart (QImode, temp_reg);
  32652. +
  32653. + if (mode == DImode)
  32654. + {
  32655. + /* Load doubleword, we need two registers to access. */
  32656. + reg[0] = simplify_gen_subreg (SImode, operands[0],
  32657. + GET_MODE (operands[0]), 0);
  32658. + reg[1] = simplify_gen_subreg (SImode, operands[0],
  32659. + GET_MODE (operands[0]), 4);
  32660. + /* A register only store 4 byte. */
  32661. + width = GET_MODE_SIZE (SImode) - 1;
  32662. + }
  32663. + else
  32664. + {
  32665. + reg[0] = operands[0];
  32666. + }
  32667. +
  32668. + for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--)
  32669. + {
  32670. + sub_reg = gen_lowpart (QImode, reg[0]);
  32671. + mem[0] = gen_rtx_MEM (QImode, plus_constant (Pmode, operands[1], offset));
  32672. +
  32673. + /* Generating the first part instructions.
  32674. + lbi reg0, [mem] */
  32675. + emit_move_insn (sub_reg, mem[0]);
  32676. +
  32677. + while (width > 0)
  32678. + {
  32679. + offset = offset + offset_adj;
  32680. + shift++;
  32681. + width--;
  32682. +
  32683. + mem[1] = gen_rtx_MEM (QImode, plus_constant (Pmode,
  32684. + operands[1],
  32685. + offset));
  32686. + /* Generating the second part instructions.
  32687. + lbi temp_reg, [mem + offset]
  32688. + sll temp_reg, (8 * shift)
  32689. + ior reg0, temp_reg */
  32690. + emit_move_insn (temp_sub_reg, mem[1]);
  32691. + emit_insn (gen_ashlsi3 (temp_reg, temp_reg,
  32692. + GEN_INT (shift * 8)));
  32693. + emit_insn (gen_iorsi3 (reg[0], reg[0], temp_reg));
  32694. + }
  32695. +
  32696. + if (mode == DImode)
  32697. + {
  32698. + /* Using the second register to load memory information. */
  32699. + reg[0] = reg[1];
  32700. + shift = 0;
  32701. + width = GET_MODE_SIZE (SImode) - 1;
  32702. + offset = offset + offset_adj;
  32703. + }
  32704. + }
  32705. +}
  32706. +
  32707. +void
  32708. +nds32_expand_unaligned_store (rtx *operands, enum machine_mode mode)
  32709. +{
  32710. + /* Initial memory offset. */
  32711. + int offset = WORDS_BIG_ENDIAN ? GET_MODE_SIZE (mode) - 1 : 0;
  32712. + int offset_adj = WORDS_BIG_ENDIAN ? -1 : 1;
  32713. + /* Initial register shift byte. */
  32714. + int shift = 0;
  32715. + /* The first load byte instruction is not the same. */
  32716. + int width = GET_MODE_SIZE (mode) - 1;
  32717. + rtx mem[2];
  32718. + rtx reg[2];
  32719. + rtx sub_reg;
  32720. + rtx temp_reg, temp_sub_reg;
  32721. + int num_reg;
  32722. +
  32723. + /* Generating a series of store byte instructions.
  32724. + The first store byte instructions and other
  32725. + load byte instructions are not the same. like:
  32726. + First:
  32727. + sbi reg0, [mem + 0]
  32728. + Second:
  32729. + srli temp_reg, reg0, (8 * shift)
  32730. + sbi temp_reg, [mem + offset] */
  32731. +
  32732. + temp_reg = gen_reg_rtx (SImode);
  32733. + temp_sub_reg = gen_lowpart (QImode, temp_reg);
  32734. +
  32735. + if (mode == DImode)
  32736. + {
  32737. + /* Load doubleword, we need two registers to access. */
  32738. + reg[0] = simplify_gen_subreg (SImode, operands[1],
  32739. + GET_MODE (operands[1]), 0);
  32740. + reg[1] = simplify_gen_subreg (SImode, operands[1],
  32741. + GET_MODE (operands[1]), 4);
  32742. + /* A register only store 4 byte. */
  32743. + width = GET_MODE_SIZE (SImode) - 1;
  32744. + }
  32745. + else
  32746. + {
  32747. + reg[0] = operands[1];
  32748. + }
  32749. +
  32750. + for (num_reg = (mode == DImode) ? 2 : 1; num_reg > 0; num_reg--)
  32751. + {
  32752. + sub_reg = gen_lowpart (QImode, reg[0]);
  32753. + mem[0] = gen_rtx_MEM (QImode, plus_constant (Pmode, operands[0], offset));
  32754. +
  32755. + /* Generating the first part instructions.
  32756. + sbi reg0, [mem + 0] */
  32757. + emit_move_insn (mem[0], sub_reg);
  32758. +
  32759. + while (width > 0)
  32760. + {
  32761. + offset = offset + offset_adj;
  32762. + shift++;
  32763. + width--;
  32764. +
  32765. + mem[1] = gen_rtx_MEM (QImode, plus_constant (Pmode,
  32766. + operands[0],
  32767. + offset));
  32768. + /* Generating the second part instructions.
  32769. + srli temp_reg, reg0, (8 * shift)
  32770. + sbi temp_reg, [mem + offset] */
  32771. + emit_insn (gen_lshrsi3 (temp_reg, reg[0],
  32772. + GEN_INT (shift * 8)));
  32773. + emit_move_insn (mem[1], temp_sub_reg);
  32774. + }
  32775. +
  32776. + if (mode == DImode)
  32777. + {
  32778. + /* Using the second register to load memory information. */
  32779. + reg[0] = reg[1];
  32780. + shift = 0;
  32781. + width = GET_MODE_SIZE (SImode) - 1;
  32782. + offset = offset + offset_adj;
  32783. + }
  32784. + }
  32785. +}
  32786. +
  32787. +/* Using multiple load/store instruction to output doubleword instruction. */
  32788. +const char *
  32789. +nds32_output_double (rtx *operands, bool load_p)
  32790. +{
  32791. + char pattern[100];
  32792. + int reg = load_p ? 0 : 1;
  32793. + int mem = load_p ? 1 : 0;
  32794. + rtx otherops[3];
  32795. + rtx addr = XEXP (operands[mem], 0);
  32796. +
  32797. + otherops[0] = gen_rtx_REG (SImode, REGNO (operands[reg]));
  32798. + otherops[1] = gen_rtx_REG (SImode, REGNO (operands[reg]) + 1);
  32799. +
  32800. + if (GET_CODE (addr) == POST_INC)
  32801. + {
  32802. + /* (mem (post_inc (reg))) */
  32803. + otherops[2] = XEXP (addr, 0);
  32804. + snprintf (pattern, sizeof (pattern),
  32805. + "%cmw.bim\t%%0, [%%2], %%1, 0", load_p ? 'l' : 's');
  32806. + }
  32807. + else
  32808. + {
  32809. + /* (mem (reg)) */
  32810. + otherops[2] = addr;
  32811. + snprintf (pattern, sizeof (pattern),
  32812. + "%cmw.bi\t%%0, [%%2], %%1, 0", load_p ? 'l' : 's');
  32813. +
  32814. + }
  32815. +
  32816. + output_asm_insn (pattern, otherops);
  32817. + return "";
  32818. +}
  32819. +
  32820. +const char *
  32821. +nds32_output_cbranchsi4_equality_zero (rtx insn, rtx *operands)
  32822. +{
  32823. + enum rtx_code code;
  32824. + bool long_jump_p = false;
  32825. +
  32826. + code = GET_CODE (operands[0]);
  32827. +
  32828. + /* This zero-comparison conditional branch has two forms:
  32829. + 32-bit instruction => beqz/bnez imm16s << 1
  32830. + 16-bit instruction => beqzs8/bnezs8/beqz38/bnez38 imm8s << 1
  32831. +
  32832. + For 32-bit case,
  32833. + we assume it is always reachable. (but check range -65500 ~ 65500)
  32834. +
  32835. + For 16-bit case,
  32836. + it must satisfy { 255 >= (label - pc) >= -256 } condition.
  32837. + However, since the $pc for nds32 is at the beginning of the instruction,
  32838. + we should leave some length space for current insn.
  32839. + So we use range -250 ~ 250. */
  32840. +
  32841. + switch (get_attr_length (insn))
  32842. + {
  32843. + case 8:
  32844. + long_jump_p = true;
  32845. + /* fall through */
  32846. + case 2:
  32847. + if (which_alternative == 0)
  32848. + {
  32849. + /* constraint: t */
  32850. + /* b<cond>zs8 .L0
  32851. + or
  32852. + b<inverse_cond>zs8 .LCB0
  32853. + j .L0
  32854. + .LCB0:
  32855. + */
  32856. + output_cond_branch_compare_zero (code, "s8", long_jump_p,
  32857. + operands, true);
  32858. + return "";
  32859. + }
  32860. + else if (which_alternative == 1)
  32861. + {
  32862. + /* constraint: l */
  32863. + /* b<cond>z38 $r0, .L0
  32864. + or
  32865. + b<inverse_cond>z38 $r0, .LCB0
  32866. + j .L0
  32867. + .LCB0:
  32868. + */
  32869. + output_cond_branch_compare_zero (code, "38", long_jump_p,
  32870. + operands, false);
  32871. + return "";
  32872. + }
  32873. + else
  32874. + {
  32875. + /* constraint: r */
  32876. + /* For which_alternative==2, it should not be here. */
  32877. + gcc_unreachable ();
  32878. + }
  32879. + case 10:
  32880. + /* including constraints: t, l, and r */
  32881. + long_jump_p = true;
  32882. + /* fall through */
  32883. + case 4:
  32884. + /* including constraints: t, l, and r */
  32885. + output_cond_branch_compare_zero (code, "", long_jump_p, operands, false);
  32886. + return "";
  32887. +
  32888. + default:
  32889. + gcc_unreachable ();
  32890. + }
  32891. +}
  32892. +
  32893. +const char *
  32894. +nds32_output_cbranchsi4_equality_reg (rtx insn, rtx *operands)
  32895. +{
  32896. + enum rtx_code code;
  32897. + bool long_jump_p, r5_p;
  32898. + int insn_length;
  32899. +
  32900. + insn_length = get_attr_length (insn);
  32901. +
  32902. + long_jump_p = (insn_length == 10 || insn_length == 8) ? true : false;
  32903. + r5_p = (insn_length == 2 || insn_length == 8) ? true : false;
  32904. +
  32905. + code = GET_CODE (operands[0]);
  32906. +
  32907. + /* This register-comparison conditional branch has one form:
  32908. + 32-bit instruction => beq/bne imm14s << 1
  32909. +
  32910. + For 32-bit case,
  32911. + we assume it is always reachable. (but check range -16350 ~ 16350). */
  32912. +
  32913. + switch (code)
  32914. + {
  32915. + case EQ:
  32916. + case NE:
  32917. + output_cond_branch (code, "", r5_p, long_jump_p, operands);
  32918. + return "";
  32919. +
  32920. + default:
  32921. + gcc_unreachable ();
  32922. + }
  32923. +}
  32924. +
  32925. +const char *
  32926. +nds32_output_cbranchsi4_equality_reg_or_const_int (rtx insn, rtx *operands)
  32927. +{
  32928. + enum rtx_code code;
  32929. + bool long_jump_p, r5_p;
  32930. + int insn_length;
  32931. +
  32932. + insn_length = get_attr_length (insn);
  32933. +
  32934. + long_jump_p = (insn_length == 10 || insn_length == 8) ? true : false;
  32935. + r5_p = (insn_length == 2 || insn_length == 8) ? true : false;
  32936. +
  32937. + code = GET_CODE (operands[0]);
  32938. +
  32939. + /* This register-comparison conditional branch has one form:
  32940. + 32-bit instruction => beq/bne imm14s << 1
  32941. + 32-bit instruction => beqc/bnec imm8s << 1
  32942. +
  32943. + For 32-bit case, we assume it is always reachable.
  32944. + (but check range -16350 ~ 16350 and -250 ~ 250). */
  32945. +
  32946. + switch (code)
  32947. + {
  32948. + case EQ:
  32949. + case NE:
  32950. + if (which_alternative == 2)
  32951. + {
  32952. + /* r, Is11 */
  32953. + /* b<cond>c */
  32954. + output_cond_branch (code, "c", r5_p, long_jump_p, operands);
  32955. + }
  32956. + else
  32957. + {
  32958. + /* r, r */
  32959. + /* v, r */
  32960. + output_cond_branch (code, "", r5_p, long_jump_p, operands);
  32961. + }
  32962. + return "";
  32963. + default:
  32964. + gcc_unreachable ();
  32965. + }
  32966. +}
  32967. +
  32968. +const char *
  32969. +nds32_output_cbranchsi4_greater_less_zero (rtx insn, rtx *operands)
  32970. +{
  32971. + enum rtx_code code;
  32972. + bool long_jump_p;
  32973. + int insn_length;
  32974. +
  32975. + insn_length = get_attr_length (insn);
  32976. +
  32977. + gcc_assert (insn_length == 4 || insn_length == 10);
  32978. +
  32979. + long_jump_p = (insn_length == 10) ? true : false;
  32980. +
  32981. + code = GET_CODE (operands[0]);
  32982. +
  32983. + /* This zero-greater-less-comparison conditional branch has one form:
  32984. + 32-bit instruction => bgtz/bgez/bltz/blez imm16s << 1
  32985. +
  32986. + For 32-bit case, we assume it is always reachable.
  32987. + (but check range -65500 ~ 65500). */
  32988. +
  32989. + switch (code)
  32990. + {
  32991. + case GT:
  32992. + case GE:
  32993. + case LT:
  32994. + case LE:
  32995. + output_cond_branch_compare_zero (code, "", long_jump_p, operands, false);
  32996. + break;
  32997. + default:
  32998. + gcc_unreachable ();
  32999. + }
  33000. + return "";
  33001. +}
  33002. +
  33003. +const char *
  33004. +nds32_output_unpkd8 (rtx output, rtx input,
  33005. + rtx high_idx_rtx, rtx low_idx_rtx,
  33006. + bool signed_p)
  33007. +{
  33008. + char pattern[100];
  33009. + rtx output_operands[2];
  33010. + HOST_WIDE_INT high_idx, low_idx;
  33011. + high_idx = INTVAL (high_idx_rtx);
  33012. + low_idx = INTVAL (low_idx_rtx);
  33013. +
  33014. + gcc_assert (high_idx >= 0 && high_idx <= 3);
  33015. + gcc_assert (low_idx >= 0 && low_idx <= 3);
  33016. +
  33017. + /* We only have 10, 20, 30 and 31. */
  33018. + if ((low_idx != 0 || high_idx == 0) &&
  33019. + !(low_idx == 1 && high_idx == 3))
  33020. + return "#";
  33021. +
  33022. + char sign_char = signed_p ? 's' : 'z';
  33023. +
  33024. + sprintf (pattern,
  33025. + "%cunpkd8" HOST_WIDE_INT_PRINT_DEC HOST_WIDE_INT_PRINT_DEC "\t%%0, %%1",
  33026. + sign_char, high_idx, low_idx);
  33027. + output_operands[0] = output;
  33028. + output_operands[1] = input;
  33029. + output_asm_insn (pattern, output_operands);
  33030. + return "";
  33031. +}
  33032. +
  33033. +const char *nds32_output_call (rtx insn, rtx *operands,
  33034. + const char *long_call, const char *call,
  33035. + bool align_p)
  33036. +{
  33037. + char pattern[100];
  33038. + bool noreturn_p;
  33039. + if (TARGET_CMODEL_LARGE)
  33040. + strcpy (pattern, long_call);
  33041. + else
  33042. + strcpy (pattern, call);
  33043. +
  33044. + if (align_p)
  33045. + strcat (pattern, "\n\t.align 2");
  33046. +
  33047. + noreturn_p = find_reg_note (insn, REG_NORETURN, NULL_RTX) != NULL_RTX;
  33048. +
  33049. + if (noreturn_p)
  33050. + {
  33051. + if (TARGET_16_BIT)
  33052. + strcat (pattern, "\n\tnop16");
  33053. + else
  33054. + strcat (pattern, "\n\tnop");
  33055. + }
  33056. +
  33057. + output_asm_insn (pattern, operands);
  33058. + return "";
  33059. +}
  33060. +
  33061. +bool
  33062. +nds32_need_split_sms_p (rtx in0_idx0, rtx in1_idx0,
  33063. + rtx in0_idx1, rtx in1_idx1)
  33064. +{
  33065. + /* smds or smdrs. */
  33066. + if (INTVAL (in0_idx0) == INTVAL (in1_idx0)
  33067. + && INTVAL (in0_idx1) == INTVAL (in1_idx1)
  33068. + && INTVAL (in0_idx0) != INTVAL (in0_idx1))
  33069. + return false;
  33070. +
  33071. + /* smxds. */
  33072. + if (INTVAL (in0_idx0) != INTVAL (in0_idx1)
  33073. + && INTVAL (in1_idx0) != INTVAL (in1_idx1))
  33074. + return false;
  33075. +
  33076. + return true;
  33077. +}
  33078. +
  33079. +const char *
  33080. +nds32_output_sms (rtx in0_idx0, rtx in1_idx0,
  33081. + rtx in0_idx1, rtx in1_idx1)
  33082. +{
  33083. + if (nds32_need_split_sms_p (in0_idx0, in1_idx0,
  33084. + in0_idx1, in1_idx1))
  33085. + return "#";
  33086. + /* out = in0[in0_idx0] * in1[in1_idx0] - in0[in0_idx1] * in1[in1_idx1] */
  33087. +
  33088. + /* smds or smdrs. */
  33089. + if (INTVAL (in0_idx0) == INTVAL (in1_idx0)
  33090. + && INTVAL (in0_idx1) == INTVAL (in1_idx1)
  33091. + && INTVAL (in0_idx0) != INTVAL (in0_idx1))
  33092. + {
  33093. + if (INTVAL (in0_idx0) == 0)
  33094. + {
  33095. + if (TARGET_BIG_ENDIAN)
  33096. + return "smds\t%0, %1, %2";
  33097. + else
  33098. + return "smdrs\t%0, %1, %2";
  33099. + }
  33100. + else
  33101. + {
  33102. + if (TARGET_BIG_ENDIAN)
  33103. + return "smdrs\t%0, %1, %2";
  33104. + else
  33105. + return "smds\t%0, %1, %2";
  33106. + }
  33107. + }
  33108. +
  33109. + if (INTVAL (in0_idx0) != INTVAL (in0_idx1)
  33110. + && INTVAL (in1_idx0) != INTVAL (in1_idx1))
  33111. + {
  33112. + if (INTVAL (in0_idx0) == 1)
  33113. + {
  33114. + if (TARGET_BIG_ENDIAN)
  33115. + return "smxds\t%0, %2, %1";
  33116. + else
  33117. + return "smxds\t%0, %1, %2";
  33118. + }
  33119. + else
  33120. + {
  33121. + if (TARGET_BIG_ENDIAN)
  33122. + return "smxds\t%0, %1, %2";
  33123. + else
  33124. + return "smxds\t%0, %2, %1";
  33125. + }
  33126. + }
  33127. +
  33128. + gcc_unreachable ();
  33129. + return "";
  33130. +}
  33131. +
  33132. +void
  33133. +nds32_split_sms (rtx out, rtx in0, rtx in1,
  33134. + rtx in0_idx0, rtx in1_idx0,
  33135. + rtx in0_idx1, rtx in1_idx1)
  33136. +{
  33137. + rtx result0 = gen_reg_rtx (SImode);
  33138. + rtx result1 = gen_reg_rtx (SImode);
  33139. + emit_insn (gen_mulhisi3v (result0, in0, in1,
  33140. + in0_idx0, in1_idx0));
  33141. + emit_insn (gen_mulhisi3v (result1, in0, in1,
  33142. + in0_idx1, in1_idx1));
  33143. + emit_insn (gen_subsi3 (out, result0, result1));
  33144. +}
  33145. +
  33146. +/* Spilt a doubleword instrucion to two single word instructions. */
  33147. +void
  33148. +nds32_spilt_doubleword (rtx *operands, bool load_p)
  33149. +{
  33150. + int reg = load_p ? 0 : 1;
  33151. + int mem = load_p ? 1 : 0;
  33152. + rtx reg_rtx = load_p ? operands[0] : operands[1];
  33153. + rtx mem_rtx = load_p ? operands[1] : operands[0];
  33154. + rtx low_part[2], high_part[2];
  33155. + rtx sub_mem = XEXP (mem_rtx, 0);
  33156. +
  33157. + /* Generate low_part and high_part register pattern.
  33158. + i.e. register pattern like:
  33159. + (reg:DI) -> (subreg:SI (reg:DI))
  33160. + (subreg:SI (reg:DI)) */
  33161. + low_part[reg] = simplify_gen_subreg (SImode, reg_rtx, GET_MODE (reg_rtx), 0);
  33162. + high_part[reg] = simplify_gen_subreg (SImode, reg_rtx, GET_MODE (reg_rtx), 4);
  33163. +
  33164. + /* Generate low_part and high_part memory pattern.
  33165. + Memory format is (post_dec) will generate:
  33166. + low_part: lwi.bi reg, [mem], 4
  33167. + high_part: lwi.bi reg, [mem], -12 */
  33168. + if (GET_CODE (sub_mem) == POST_DEC)
  33169. + {
  33170. + /* memory format is (post_dec (reg)),
  33171. + so that extract (reg) from the (post_dec (reg)) pattern. */
  33172. + sub_mem = XEXP (sub_mem, 0);
  33173. +
  33174. + /* generate low_part and high_part memory format:
  33175. + low_part: (post_modify ((reg) (plus (reg) (const 4)))
  33176. + high_part: (post_modify ((reg) (plus (reg) (const -12))) */
  33177. + low_part[mem] = gen_frame_mem (SImode,
  33178. + gen_rtx_POST_MODIFY (Pmode, sub_mem,
  33179. + gen_rtx_PLUS (Pmode,
  33180. + sub_mem,
  33181. + GEN_INT (4))));
  33182. + high_part[mem] = gen_frame_mem (SImode,
  33183. + gen_rtx_POST_MODIFY (Pmode, sub_mem,
  33184. + gen_rtx_PLUS (Pmode,
  33185. + sub_mem,
  33186. + GEN_INT (-12))));
  33187. + }
  33188. + else if (GET_CODE (sub_mem) == POST_MODIFY)
  33189. + {
  33190. + /* Memory format is (post_modify (reg) (plus (reg) (const))),
  33191. + so that extract (reg) from the post_modify pattern. */
  33192. + rtx post_mem = XEXP (sub_mem, 0);
  33193. +
  33194. + /* Extract (const) from the (post_modify (reg) (plus (reg) (const)))
  33195. + pattern. */
  33196. +
  33197. + rtx plus_op = XEXP (sub_mem, 1);
  33198. + rtx post_val = XEXP (plus_op, 1);
  33199. +
  33200. + /* Generate low_part and high_part memory format:
  33201. + low_part: (post_modify ((reg) (plus (reg) (const)))
  33202. + high_part: ((plus (reg) (const 4))) */
  33203. + low_part[mem] = gen_frame_mem (SImode,
  33204. + gen_rtx_POST_MODIFY (Pmode, post_mem,
  33205. + gen_rtx_PLUS (Pmode,
  33206. + post_mem,
  33207. + post_val)));
  33208. + high_part[mem] = gen_frame_mem (SImode, plus_constant (Pmode,
  33209. + post_mem,
  33210. + 4));
  33211. + }
  33212. + else
  33213. + {
  33214. + /* memory format: (symbol_ref), (const), (reg + const_int). */
  33215. + low_part[mem] = adjust_address (mem_rtx, SImode, 0);
  33216. + high_part[mem] = adjust_address (mem_rtx, SImode, 4);
  33217. + }
  33218. +
  33219. + /* After reload completed, we have dependent issue by low part register and
  33220. + higt part memory. i.e. we cannot split a sequence
  33221. + like:
  33222. + load $r0, [%r1]
  33223. + spilt to
  33224. + lw $r0, [%r0]
  33225. + lwi $r1, [%r0 + 4]
  33226. + swap position
  33227. + lwi $r1, [%r0 + 4]
  33228. + lw $r0, [%r0]
  33229. + For store instruction we don't have a problem.
  33230. +
  33231. + When memory format is [post_modify], we need to emit high part instruction,
  33232. + before low part instruction.
  33233. + expamle:
  33234. + load $r0, [%r2], post_val
  33235. + spilt to
  33236. + load $r1, [%r2 + 4]
  33237. + load $r0, [$r2], post_val. */
  33238. + if ((load_p && reg_overlap_mentioned_p (low_part[0], high_part[1]))
  33239. + || GET_CODE (sub_mem) == POST_MODIFY)
  33240. + {
  33241. + operands[2] = high_part[0];
  33242. + operands[3] = high_part[1];
  33243. + operands[4] = low_part[0];
  33244. + operands[5] = low_part[1];
  33245. + }
  33246. + else
  33247. + {
  33248. + operands[2] = low_part[0];
  33249. + operands[3] = low_part[1];
  33250. + operands[4] = high_part[0];
  33251. + operands[5] = high_part[1];
  33252. + }
  33253. +}
  33254. +
  33255. +void
  33256. +nds32_split_ashiftdi3 (rtx dst, rtx src, rtx shiftamount)
  33257. +{
  33258. + rtx src_high_part, src_low_part;
  33259. + rtx dst_high_part, dst_low_part;
  33260. +
  33261. + dst_high_part = nds32_di_high_part_subreg (dst);
  33262. + dst_low_part = nds32_di_low_part_subreg (dst);
  33263. +
  33264. + src_high_part = nds32_di_high_part_subreg (src);
  33265. + src_low_part = nds32_di_low_part_subreg (src);
  33266. +
  33267. + /* We need to handle shift more than 32 bit!!!! */
  33268. + if (CONST_INT_P (shiftamount))
  33269. + {
  33270. + if (INTVAL (shiftamount) < 32)
  33271. + {
  33272. + rtx ext_start;
  33273. + ext_start = gen_int_mode(32 - INTVAL (shiftamount), SImode);
  33274. +
  33275. + emit_insn (gen_wext (dst_high_part, src, ext_start));
  33276. + emit_insn (gen_ashlsi3 (dst_low_part, src_low_part, shiftamount));
  33277. + }
  33278. + else
  33279. + {
  33280. + rtx new_shift_amout = gen_int_mode(INTVAL (shiftamount) - 32, SImode);
  33281. +
  33282. + emit_insn (gen_ashlsi3 (dst_high_part, src_low_part,
  33283. + new_shift_amout));
  33284. +
  33285. + emit_move_insn (dst_low_part, GEN_INT (0));
  33286. + }
  33287. + }
  33288. + else
  33289. + {
  33290. + rtx dst_low_part_l32, dst_high_part_l32;
  33291. + rtx dst_low_part_g32, dst_high_part_g32;
  33292. + rtx new_shift_amout, select_reg;
  33293. + dst_low_part_l32 = gen_reg_rtx (SImode);
  33294. + dst_high_part_l32 = gen_reg_rtx (SImode);
  33295. + dst_low_part_g32 = gen_reg_rtx (SImode);
  33296. + dst_high_part_g32 = gen_reg_rtx (SImode);
  33297. + new_shift_amout = gen_reg_rtx (SImode);
  33298. + select_reg = gen_reg_rtx (SImode);
  33299. +
  33300. + rtx ext_start;
  33301. + ext_start = gen_reg_rtx (SImode);
  33302. +
  33303. + /*
  33304. + if (shiftamount < 32)
  33305. + dst_low_part = src_low_part << shiftamout
  33306. + dst_high_part = wext (src, 32 - shiftamount)
  33307. + # wext can't handle wext (src, 32) since it's only take rb[0:4]
  33308. + # for extract.
  33309. + dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part
  33310. + else
  33311. + dst_low_part = 0
  33312. + dst_high_part = src_low_part << shiftamount & 0x1f
  33313. + */
  33314. +
  33315. + emit_insn (gen_subsi3 (ext_start,
  33316. + gen_int_mode (32, SImode),
  33317. + shiftamount));
  33318. + emit_insn (gen_wext (dst_high_part_l32, src, ext_start));
  33319. +
  33320. + /* Handle for shiftamout == 0. */
  33321. + emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount,
  33322. + src_high_part, dst_high_part_l32));
  33323. +
  33324. + emit_insn (gen_ashlsi3 (dst_low_part_l32, src_low_part, shiftamount));
  33325. +
  33326. + emit_move_insn (dst_low_part_g32, const0_rtx);
  33327. + emit_insn (gen_andsi3 (new_shift_amout, shiftamount, GEN_INT (0x1f)));
  33328. + emit_insn (gen_ashlsi3 (dst_high_part_g32, src_low_part,
  33329. + new_shift_amout));
  33330. +
  33331. + emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32)));
  33332. +
  33333. + emit_insn (gen_cmovnsi (dst_low_part, select_reg,
  33334. + dst_low_part_l32, dst_low_part_g32));
  33335. + emit_insn (gen_cmovnsi (dst_high_part, select_reg,
  33336. + dst_high_part_l32, dst_high_part_g32));
  33337. + }
  33338. +}
  33339. +
  33340. +void
  33341. +nds32_split_ashiftrtdi3 (rtx dst, rtx src, rtx shiftamount)
  33342. +{
  33343. + nds32_split_shiftrtdi3 (dst, src, shiftamount, false);
  33344. +}
  33345. +
  33346. +void
  33347. +nds32_split_lshiftrtdi3 (rtx dst, rtx src, rtx shiftamount)
  33348. +{
  33349. + nds32_split_shiftrtdi3 (dst, src, shiftamount, true);
  33350. +}
  33351. +
  33352. +void
  33353. +nds32_split_rotatertdi3 (rtx dst, rtx src, rtx shiftamount)
  33354. +{
  33355. + rtx dst_low_part_l32, dst_high_part_l32;
  33356. + rtx dst_low_part_g32, dst_high_part_g32;
  33357. + rtx select_reg, low5bit, low5bit_inv, minus32sa;
  33358. + rtx dst_low_part_g32_tmph;
  33359. + rtx dst_low_part_g32_tmpl;
  33360. + rtx dst_high_part_l32_tmph;
  33361. + rtx dst_high_part_l32_tmpl;
  33362. +
  33363. + rtx src_low_part, src_high_part;
  33364. + rtx dst_high_part, dst_low_part;
  33365. +
  33366. + shiftamount = force_reg (SImode, shiftamount);
  33367. +
  33368. + emit_insn (gen_andsi3 (shiftamount,
  33369. + shiftamount,
  33370. + gen_int_mode (0x3f, SImode)));
  33371. +
  33372. + dst_high_part = nds32_di_high_part_subreg (dst);
  33373. + dst_low_part = nds32_di_low_part_subreg (dst);
  33374. +
  33375. + src_high_part = nds32_di_high_part_subreg (src);
  33376. + src_low_part = nds32_di_low_part_subreg (src);
  33377. +
  33378. + dst_low_part_l32 = gen_reg_rtx (SImode);
  33379. + dst_high_part_l32 = gen_reg_rtx (SImode);
  33380. + dst_low_part_g32 = gen_reg_rtx (SImode);
  33381. + dst_high_part_g32 = gen_reg_rtx (SImode);
  33382. + low5bit = gen_reg_rtx (SImode);
  33383. + low5bit_inv = gen_reg_rtx (SImode);
  33384. + minus32sa = gen_reg_rtx (SImode);
  33385. + select_reg = gen_reg_rtx (SImode);
  33386. +
  33387. + dst_low_part_g32_tmph = gen_reg_rtx (SImode);
  33388. + dst_low_part_g32_tmpl = gen_reg_rtx (SImode);
  33389. +
  33390. + dst_high_part_l32_tmph = gen_reg_rtx (SImode);
  33391. + dst_high_part_l32_tmpl = gen_reg_rtx (SImode);
  33392. +
  33393. + emit_insn (gen_slt_compare (select_reg, shiftamount, GEN_INT (32)));
  33394. +
  33395. + /* if shiftamount < 32
  33396. + dst_low_part = wext(src, shiftamount)
  33397. + else
  33398. + dst_low_part = ((src_high_part >> (shiftamount & 0x1f))
  33399. + | (src_low_part << (32 - (shiftamount & 0x1f))))
  33400. + */
  33401. + emit_insn (gen_andsi3 (low5bit, shiftamount, gen_int_mode (0x1f, SImode)));
  33402. + emit_insn (gen_subsi3 (low5bit_inv, gen_int_mode (32, SImode), low5bit));
  33403. +
  33404. + emit_insn (gen_wext (dst_low_part_l32, src, shiftamount));
  33405. +
  33406. + emit_insn (gen_lshrsi3 (dst_low_part_g32_tmpl, src_high_part, low5bit));
  33407. + emit_insn (gen_ashlsi3 (dst_low_part_g32_tmph, src_low_part, low5bit_inv));
  33408. +
  33409. + emit_insn (gen_iorsi3 (dst_low_part_g32,
  33410. + dst_low_part_g32_tmpl,
  33411. + dst_low_part_g32_tmph));
  33412. +
  33413. + emit_insn (gen_cmovnsi (dst_low_part, select_reg,
  33414. + dst_low_part_l32, dst_low_part_g32));
  33415. +
  33416. + /* if shiftamount < 32
  33417. + dst_high_part = ((src_high_part >> shiftamount)
  33418. + | (src_low_part << (32 - shiftamount)))
  33419. + dst_high_part = shiftamount == 0 ? src_high_part : dst_high_part
  33420. + else
  33421. + dst_high_part = wext(src, shiftamount & 0x1f)
  33422. + */
  33423. +
  33424. + emit_insn (gen_subsi3 (minus32sa, gen_int_mode (32, SImode), shiftamount));
  33425. +
  33426. + emit_insn (gen_lshrsi3 (dst_high_part_l32_tmpl, src_high_part, shiftamount));
  33427. + emit_insn (gen_ashlsi3 (dst_high_part_l32_tmph, src_low_part, minus32sa));
  33428. +
  33429. + emit_insn (gen_iorsi3 (dst_high_part_l32,
  33430. + dst_high_part_l32_tmpl,
  33431. + dst_high_part_l32_tmph));
  33432. +
  33433. + emit_insn (gen_cmovzsi (dst_high_part_l32, shiftamount,
  33434. + src_high_part, dst_high_part_l32));
  33435. +
  33436. + emit_insn (gen_wext (dst_high_part_g32, src, low5bit));
  33437. +
  33438. + emit_insn (gen_cmovnsi (dst_high_part, select_reg,
  33439. + dst_high_part_l32, dst_high_part_g32));
  33440. +}
  33441. +
  33442. +/* Return true if OP contains a symbol reference. */
  33443. +bool
  33444. +symbolic_reference_mentioned_p (rtx op)
  33445. +{
  33446. + const char *fmt;
  33447. + int i;
  33448. +
  33449. + if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
  33450. + return true;
  33451. +
  33452. + fmt = GET_RTX_FORMAT (GET_CODE (op));
  33453. + for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
  33454. + {
  33455. + if (fmt[i] == 'E')
  33456. + {
  33457. + int j;
  33458. +
  33459. + for (j = XVECLEN (op, i) - 1; j >= 0; j--)
  33460. + if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
  33461. + return true;
  33462. + }
  33463. +
  33464. + else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
  33465. + return true;
  33466. + }
  33467. +
  33468. + return false;
  33469. +}
  33470. +
  33471. +/* Expand PIC code for @GOTOFF and @GOT.
  33472. +
  33473. + Example for @GOTOFF:
  33474. +
  33475. + la $r0, symbol@GOTOFF
  33476. + -> sethi $ta, hi20(symbol@GOTOFF)
  33477. + ori $ta, $ta, lo12(symbol@GOTOFF)
  33478. + add $r0, $ta, $gp
  33479. +
  33480. + Example for @GOT:
  33481. +
  33482. + la $r0, symbol@GOT
  33483. + -> sethi $ta, hi20(symbol@GOT)
  33484. + ori $ta, $ta, lo12(symbol@GOT)
  33485. + lw $r0, [$ta + $gp]
  33486. +*/
  33487. +void
  33488. +nds32_expand_pic_move (rtx *operands)
  33489. +{
  33490. + rtx tmp_reg = gen_reg_rtx (SImode);
  33491. + rtx pat;
  33492. +
  33493. + if (GET_CODE (operands[1]) == LABEL_REF
  33494. + || (GET_CODE (operands[1]) == SYMBOL_REF
  33495. + && (CONSTANT_POOL_ADDRESS_P (operands[1])
  33496. + || SYMBOL_REF_LOCAL_P (operands[1]))))
  33497. + {
  33498. + pat = gen_rtx_UNSPEC (SImode,
  33499. + gen_rtvec (1, operands[1]), UNSPEC_GOTOFF);
  33500. + pat = gen_rtx_CONST (SImode, pat);
  33501. + emit_insn (gen_sethi (tmp_reg, pat));
  33502. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33503. + emit_insn (gen_addsi3 (operands[0], pic_offset_table_rtx, tmp_reg));
  33504. + emit_insn (gen_blockage ());
  33505. + }
  33506. + else if (GET_CODE (operands[1]) == SYMBOL_REF)
  33507. + {
  33508. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, operands[1]), UNSPEC_GOT);
  33509. + pat = gen_rtx_CONST (SImode, pat);
  33510. + emit_insn (gen_sethi (tmp_reg, pat));
  33511. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33512. + rtx got_addr = gen_frame_mem (SImode, gen_rtx_PLUS (Pmode,
  33513. + pic_offset_table_rtx,
  33514. + tmp_reg));
  33515. + emit_move_insn (operands[0], got_addr);
  33516. + emit_insn (gen_blockage ());
  33517. + }
  33518. + else if (GET_CODE (operands[1]) == CONST)
  33519. + {
  33520. + pat = XEXP (operands[1], 0);
  33521. + gcc_assert (GET_CODE (pat) == PLUS);
  33522. +
  33523. + rtx op0 = XEXP (pat, 0);
  33524. + rtx op1 = XEXP (pat, 1);
  33525. +
  33526. + if ((GET_CODE (op0) == LABEL_REF
  33527. + || (GET_CODE (op0) == SYMBOL_REF
  33528. + && (CONSTANT_POOL_ADDRESS_P (op0)
  33529. + || SYMBOL_REF_LOCAL_P (op0))))
  33530. + && GET_CODE (op1) == CONST_INT)
  33531. + {
  33532. + pat = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF);
  33533. + pat = gen_rtx_PLUS (Pmode, pat, op1);
  33534. + pat = gen_rtx_CONST (Pmode, pat);
  33535. + emit_insn (gen_sethi (tmp_reg, pat));
  33536. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33537. + emit_insn (gen_addsi3 (operands[0], tmp_reg, pic_offset_table_rtx));
  33538. + emit_insn (gen_blockage ());
  33539. + }
  33540. + else if (GET_CODE (op0) == SYMBOL_REF
  33541. + && GET_CODE (op1) == CONST_INT)
  33542. + {
  33543. + /* This is a constant offset from a @GOT symbol reference. */
  33544. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT);
  33545. + pat = gen_rtx_CONST (SImode, pat);
  33546. + emit_insn (gen_sethi (tmp_reg, pat));
  33547. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33548. + rtx got_addr = gen_frame_mem (SImode,
  33549. + gen_rtx_PLUS (Pmode,
  33550. + pic_offset_table_rtx,
  33551. + tmp_reg));
  33552. + emit_move_insn (operands[0], got_addr);
  33553. + if (satisfies_constraint_Is15 (op1))
  33554. + emit_insn (gen_addsi3 (operands[0], operands[0], op1));
  33555. + else
  33556. + {
  33557. + rtx tmp_reg2 = gen_reg_rtx (SImode);
  33558. + emit_insn (gen_movsi (tmp_reg2, op1));
  33559. + emit_insn (gen_addsi3 (operands[0], operands[0], tmp_reg2));
  33560. + }
  33561. + emit_insn (gen_blockage ());
  33562. + }
  33563. + else
  33564. + {
  33565. + /* Don't handle this pattern. */
  33566. + debug_rtx (operands[1]);
  33567. + gcc_unreachable ();
  33568. + }
  33569. + }
  33570. +}
  33571. +
  33572. +/* Return true if SYMBOL_REF X binds locally. */
  33573. +
  33574. +static bool
  33575. +nds32_symbol_binds_local_p (const_rtx x)
  33576. +{
  33577. + return (SYMBOL_REF_DECL (x)
  33578. + ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
  33579. + : SYMBOL_REF_LOCAL_P (x));
  33580. +}
  33581. +
  33582. +/* Expand call address PIC code for @PLT.
  33583. +
  33584. + Example for @PLT:
  33585. +
  33586. + bal symbol@PLT
  33587. + -> sethi $rt, hi20(symbol@PLT)
  33588. + ori $rt, $rt, lo12(symbol@PLT)
  33589. + add $rt, $rt, $gp
  33590. + jral $lp, $rt
  33591. +*/
  33592. +void
  33593. +nds32_expand_call_address (rtx *call_op)
  33594. +{
  33595. + rtx addr;
  33596. + gcc_assert (MEM_P (*call_op));
  33597. + addr = XEXP (*call_op, 0);
  33598. +
  33599. + /* If the function is hidden or internal, compiler will emit pseudo
  33600. + call instruction expanding in assembler. And the pattern will use
  33601. + GOT_OFFSET_TABLE. TODO: It can be expanded here but it have to be
  33602. + grouped for relax_hint. */
  33603. + if (flag_pic)
  33604. + emit_use (pic_offset_table_rtx);
  33605. +
  33606. + if (flag_pic && CONSTANT_P (addr) && !nds32_symbol_binds_local_p (addr))
  33607. + {
  33608. + rtx tmp_reg = gen_reg_rtx (SImode);
  33609. + rtx tmp2_reg = gen_reg_rtx (SImode);
  33610. + rtx pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, addr), UNSPEC_PLT);
  33611. + pat = gen_rtx_CONST (SImode, pat);
  33612. + emit_insn (gen_sethi (tmp_reg, pat));
  33613. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33614. + emit_insn (gen_addsi3 (tmp2_reg, tmp_reg, pic_offset_table_rtx));
  33615. + /* Expand jral instruction. */
  33616. + XEXP (*call_op, 0) = tmp2_reg;
  33617. + }
  33618. +}
  33619. +
  33620. +/* Return true X is a indirect call symbol. */
  33621. +bool
  33622. +nds32_indirect_call_referenced_p (rtx x)
  33623. +{
  33624. + if (GET_CODE (x) == SYMBOL_REF)
  33625. + {
  33626. + tree decl = SYMBOL_REF_DECL (x);
  33627. +
  33628. + return decl
  33629. + && (lookup_attribute("indirect_call",
  33630. + DECL_ATTRIBUTES(decl))
  33631. + != NULL);
  33632. + }
  33633. +
  33634. + return false;
  33635. +}
  33636. +
  33637. +/* Return true if X contains a thread-local symbol. */
  33638. +bool
  33639. +nds32_tls_referenced_p (rtx x)
  33640. +{
  33641. + if (!targetm.have_tls)
  33642. + return false;
  33643. +
  33644. + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
  33645. + x = XEXP (XEXP (x, 0), 0);
  33646. +
  33647. + if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
  33648. + return true;
  33649. +
  33650. + return false;
  33651. +}
  33652. +
  33653. +/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
  33654. + this (thread-local) address. */
  33655. +rtx
  33656. +nds32_legitimize_tls_address (rtx x)
  33657. +{
  33658. + rtx tmp_reg;
  33659. + rtx tp_reg = gen_rtx_REG (Pmode, TP_REGNUM);
  33660. + rtx pat, insns, ret;
  33661. +
  33662. + if (GET_CODE (x) == SYMBOL_REF)
  33663. + switch (SYMBOL_REF_TLS_MODEL (x))
  33664. + {
  33665. + case TLS_MODEL_GLOBAL_DYNAMIC:
  33666. + case TLS_MODEL_LOCAL_DYNAMIC:
  33667. + /* Emit UNSPEC_TLS_DESC rather than expand rtl directly because spill
  33668. + may destroy the define-use chain anylysis to insert relax_hint. */
  33669. + if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC)
  33670. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSGD);
  33671. + else
  33672. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLD);
  33673. +
  33674. + pat = gen_rtx_CONST (SImode, pat);
  33675. + ret = gen_rtx_REG (Pmode, 0);
  33676. + /* If we can confirm all clobber reigsters, it doesn't have to use call
  33677. + instruction. */
  33678. + insns = emit_call_insn (gen_tls_desc (pat, GEN_INT (0)));
  33679. + use_reg (&CALL_INSN_FUNCTION_USAGE (insns), pic_offset_table_rtx);
  33680. + RTL_CONST_CALL_P (insns) = 1;
  33681. + x = ret;
  33682. + break;
  33683. +
  33684. + case TLS_MODEL_INITIAL_EXEC:
  33685. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSIE);
  33686. + tmp_reg = gen_reg_rtx (SImode);
  33687. + pat = gen_rtx_CONST (SImode, pat);
  33688. + emit_insn (gen_tls_ie (tmp_reg, pat, GEN_INT (0)));
  33689. + if (flag_pic)
  33690. + emit_use (pic_offset_table_rtx);
  33691. + x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg);
  33692. + break;
  33693. +
  33694. + case TLS_MODEL_LOCAL_EXEC:
  33695. + /* Expand symbol_ref@TPOFF':
  33696. + sethi $ta, hi20(symbol_ref@TPOFF)
  33697. + ori $ta, $ta, lo12(symbol_ref@TPOFF)
  33698. + add $r0, $ta, $tp */
  33699. + tmp_reg = gen_reg_rtx (SImode);
  33700. + pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_TLSLE);
  33701. + pat = gen_rtx_CONST (SImode, pat);
  33702. + emit_insn (gen_sethi (tmp_reg, pat));
  33703. + emit_insn (gen_lo_sum (tmp_reg, tmp_reg, pat));
  33704. + x = gen_rtx_PLUS (Pmode, tmp_reg, tp_reg);
  33705. + break;
  33706. +
  33707. + default:
  33708. + gcc_unreachable ();
  33709. + }
  33710. +
  33711. + return x;
  33712. +}
  33713. +
  33714. +void
  33715. +nds32_expand_tls_move (rtx *operands)
  33716. +{
  33717. + rtx src = operands[1];
  33718. + rtx addend = NULL;
  33719. +
  33720. + if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
  33721. + {
  33722. + addend = XEXP (XEXP (src, 0), 1);
  33723. + src = XEXP (XEXP (src, 0), 0);
  33724. + }
  33725. +
  33726. + src = nds32_legitimize_tls_address (src);
  33727. +
  33728. + if (addend)
  33729. + {
  33730. + src = gen_rtx_PLUS (SImode, src, addend);
  33731. + src = force_operand (src, operands[0]);
  33732. + }
  33733. + emit_move_insn (operands[0], src);
  33734. +}
  33735. +
  33736. +void
  33737. +nds32_expand_constant (enum machine_mode mode, HOST_WIDE_INT val,
  33738. + rtx target, rtx source)
  33739. +{
  33740. + rtx temp = gen_reg_rtx (mode);
  33741. + int clear_sign_bit_copies = 0;
  33742. + int clear_zero_bit_copies = 0;
  33743. + unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
  33744. +
  33745. + /* Count number of leading zeros. */
  33746. + clear_sign_bit_copies = __builtin_clz (remainder);
  33747. + /* Count number of trailing zeros. */
  33748. + clear_zero_bit_copies = __builtin_ctz (remainder);
  33749. +
  33750. + HOST_WIDE_INT sign_shift_mask = ((0xffffffffUL
  33751. + << (32 - clear_sign_bit_copies))
  33752. + & 0xffffffffUL);
  33753. + HOST_WIDE_INT zero_shift_mask = (1 << clear_zero_bit_copies) - 1;
  33754. +
  33755. + if (clear_sign_bit_copies > 0 && clear_sign_bit_copies < 17
  33756. + && (remainder | sign_shift_mask) == 0xffffffffUL)
  33757. + {
  33758. + /* Transfer AND to two shifts, example:
  33759. + a = b & 0x7fffffff => (b << 1) >> 1 */
  33760. + rtx shift = GEN_INT (clear_sign_bit_copies);
  33761. +
  33762. + emit_insn (gen_ashlsi3 (temp, source, shift));
  33763. + emit_insn (gen_lshrsi3 (target, temp, shift));
  33764. + }
  33765. + else if (clear_zero_bit_copies > 0 && clear_sign_bit_copies < 17
  33766. + && (remainder | zero_shift_mask) == 0xffffffffUL)
  33767. + {
  33768. + /* Transfer AND to two shifts, example:
  33769. + a = b & 0xfff00000 => (b >> 20) << 20 */
  33770. + rtx shift = GEN_INT (clear_zero_bit_copies);
  33771. +
  33772. + emit_insn (gen_lshrsi3 (temp, source, shift));
  33773. + emit_insn (gen_ashlsi3 (target, temp, shift));
  33774. + }
  33775. + else
  33776. + {
  33777. + emit_move_insn (temp, GEN_INT (val));
  33778. + emit_move_insn (target, gen_rtx_fmt_ee (AND, mode, source, temp));
  33779. + }
  33780. +}
  33781. +
  33782. +/* Auxiliary functions for lwm/smw. */
  33783. +bool
  33784. +nds32_valid_smw_lwm_base_p (rtx op)
  33785. +{
  33786. + rtx base_addr;
  33787. +
  33788. + if (!MEM_P (op))
  33789. + return false;
  33790. +
  33791. + base_addr = XEXP (op, 0);
  33792. +
  33793. + if (REG_P (base_addr))
  33794. + return true;
  33795. + else
  33796. + {
  33797. + if (GET_CODE (base_addr) == POST_INC
  33798. + && REG_P (XEXP (base_addr, 0)))
  33799. + return true;
  33800. + }
  33801. +
  33802. + return false;
  33803. +}
  33804. +
  33805. +/* Auxiliary functions for manipulation DI mode. */
  33806. +rtx nds32_di_high_part_subreg(rtx reg)
  33807. +{
  33808. + unsigned high_part_offset = subreg_highpart_offset (SImode, DImode);
  33809. +
  33810. + return simplify_gen_subreg (
  33811. + SImode, reg,
  33812. + DImode, high_part_offset);
  33813. +}
  33814. +
  33815. +rtx nds32_di_low_part_subreg(rtx reg)
  33816. +{
  33817. + unsigned low_part_offset = subreg_lowpart_offset (SImode, DImode);
  33818. +
  33819. + return simplify_gen_subreg (
  33820. + SImode, reg,
  33821. + DImode, low_part_offset);
  33822. +}
  33823. +
  33824. +/* ------------------------------------------------------------------------ */
  33825. +
  33826. +/* Auxiliary function for output TLS patterns. */
  33827. +
  33828. +const char *
  33829. +nds32_output_tls_desc (rtx *operands)
  33830. +{
  33831. + char pattern[1000];
  33832. +
  33833. + if (TARGET_RELAX_HINT)
  33834. + snprintf (pattern, sizeof (pattern),
  33835. + ".relax_hint %%1\n\tsethi $r0, hi20(%%0)\n\t"
  33836. + ".relax_hint %%1\n\tori $r0, $r0, lo12(%%0)\n\t"
  33837. + ".relax_hint %%1\n\tlw $r15, [$r0 + $gp]\n\t"
  33838. + ".relax_hint %%1\n\tadd $r0, $r0, $gp\n\t"
  33839. + ".relax_hint %%1\n\tjral $r15");
  33840. + else
  33841. + snprintf (pattern, sizeof (pattern),
  33842. + "sethi $r0, hi20(%%0)\n\t"
  33843. + "ori $r0, $r0, lo12(%%0)\n\t"
  33844. + "lw $r15, [$r0 + $gp]\n\t"
  33845. + "add $r0, $r0, $gp\n\t"
  33846. + "jral $r15");
  33847. + output_asm_insn (pattern, operands);
  33848. + return "";
  33849. +}
  33850. +
  33851. +const char *
  33852. +nds32_output_tls_ie (rtx *operands)
  33853. +{
  33854. + char pattern[1000];
  33855. +
  33856. + if (flag_pic)
  33857. + {
  33858. + if (TARGET_RELAX_HINT)
  33859. + snprintf (pattern, sizeof (pattern),
  33860. + ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t"
  33861. + ".relax_hint %%2\n\tori %%0, %%0, lo12(%%1)\n\t"
  33862. + ".relax_hint %%2\n\tlw %%0, [%%0 + $gp]");
  33863. + else
  33864. + snprintf (pattern, sizeof (pattern),
  33865. + "sethi %%0, hi20(%%1)\n\t"
  33866. + "ori %%0, %%0, lo12(%%1)\n\t"
  33867. + "lw %%0, [%%0 + $gp]");
  33868. + }
  33869. + else
  33870. + {
  33871. + if (TARGET_RELAX_HINT)
  33872. + snprintf (pattern, sizeof (pattern),
  33873. + ".relax_hint %%2\n\tsethi %%0, hi20(%%1)\n\t"
  33874. + ".relax_hint %%2\n\tlwi %%0, [%%0 + lo12(%%1)]");
  33875. + else
  33876. + snprintf (pattern, sizeof (pattern),
  33877. + "sethi %%0, hi20(%%1)\n\t"
  33878. + "lwi %%0, [%%0 + lo12(%%1)]");
  33879. + }
  33880. + output_asm_insn (pattern, operands);
  33881. + return "";
  33882. +}
  33883. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-memory-manipulation.c gcc-4.9.4/gcc/config/nds32/nds32-memory-manipulation.c
  33884. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-memory-manipulation.c 1970-01-01 01:00:00.000000000 +0100
  33885. +++ gcc-4.9.4/gcc/config/nds32/nds32-memory-manipulation.c 2016-08-08 20:37:45.506270091 +0200
  33886. @@ -0,0 +1,1152 @@
  33887. +/* Auxiliary functions for expand movmem, setmem, cmpmem, load_multiple
  33888. + and store_multiple pattern of Andes NDS32 cpu for GNU compiler
  33889. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  33890. + Contributed by Andes Technology Corporation.
  33891. +
  33892. + This file is part of GCC.
  33893. +
  33894. + GCC is free software; you can redistribute it and/or modify it
  33895. + under the terms of the GNU General Public License as published
  33896. + by the Free Software Foundation; either version 3, or (at your
  33897. + option) any later version.
  33898. +
  33899. + GCC is distributed in the hope that it will be useful, but WITHOUT
  33900. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  33901. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  33902. + License for more details.
  33903. +
  33904. + You should have received a copy of the GNU General Public License
  33905. + along with GCC; see the file COPYING3. If not see
  33906. + <http://www.gnu.org/licenses/>. */
  33907. +
  33908. +/* ------------------------------------------------------------------------ */
  33909. +
  33910. +#include "config.h"
  33911. +#include "system.h"
  33912. +#include "coretypes.h"
  33913. +#include "tm.h"
  33914. +#include "tree.h"
  33915. +#include "rtl.h"
  33916. +#include "regs.h"
  33917. +#include "hard-reg-set.h"
  33918. +#include "insn-config.h" /* Required by recog.h. */
  33919. +#include "conditions.h"
  33920. +#include "output.h"
  33921. +#include "insn-attr.h" /* For DFA state_t. */
  33922. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  33923. +#include "reload.h" /* For push_reload(). */
  33924. +#include "flags.h"
  33925. +#include "function.h"
  33926. +#include "expr.h"
  33927. +#include "recog.h"
  33928. +#include "diagnostic-core.h"
  33929. +#include "df.h"
  33930. +#include "tm_p.h"
  33931. +#include "tm-constrs.h"
  33932. +#include "optabs.h" /* For GEN_FCN. */
  33933. +#include "target.h"
  33934. +#include "target-def.h"
  33935. +#include "langhooks.h" /* For add_builtin_function(). */
  33936. +#include "ggc.h"
  33937. +
  33938. +/* ------------------------------------------------------------------------ */
  33939. +
  33940. +/* This file is divided into six parts:
  33941. +
  33942. + PART 1: Auxiliary static function definitions.
  33943. +
  33944. + PART 2: Auxiliary function for expand movmem pattern.
  33945. +
  33946. + PART 3: Auxiliary function for expand setmem pattern.
  33947. +
  33948. + PART 4: Auxiliary function for expand movstr pattern.
  33949. +
  33950. + PART 5: Auxiliary function for expand strlen pattern.
  33951. +
  33952. + PART 6: Auxiliary function for expand load_multiple/store_multiple
  33953. + pattern. */
  33954. +
  33955. +/* ------------------------------------------------------------------------ */
  33956. +
  33957. +/* PART 1: Auxiliary static function definitions. */
  33958. +
  33959. +static void
  33960. +nds32_emit_load_store (rtx reg, rtx mem,
  33961. + enum machine_mode mode,
  33962. + int offset, bool load_p)
  33963. +{
  33964. + rtx new_mem;
  33965. + new_mem = adjust_address (mem, mode, offset);
  33966. + if (load_p)
  33967. + emit_move_insn (reg, new_mem);
  33968. + else
  33969. + emit_move_insn (new_mem, reg);
  33970. +}
  33971. +
  33972. +static void
  33973. +nds32_emit_post_inc_load_store (rtx reg, rtx base_reg,
  33974. + enum machine_mode mode,
  33975. + bool load_p)
  33976. +{
  33977. + gcc_assert (GET_MODE (reg) == mode);
  33978. + gcc_assert (GET_MODE (base_reg) == Pmode);
  33979. +
  33980. + /* Do not gen (set (reg) (mem (post_inc (reg)))) directly here since it may
  33981. + not recognize by gcc, so let gcc combine it at auto_inc_dec pass. */
  33982. + if (load_p)
  33983. + emit_move_insn (reg,
  33984. + gen_rtx_MEM (mode,
  33985. + base_reg));
  33986. + else
  33987. + emit_move_insn (gen_rtx_MEM (mode,
  33988. + base_reg),
  33989. + reg);
  33990. +
  33991. + emit_move_insn (base_reg,
  33992. + plus_constant(Pmode, base_reg, GET_MODE_SIZE (mode)));
  33993. +}
  33994. +
  33995. +static void
  33996. +nds32_emit_mem_move (rtx src, rtx dst,
  33997. + enum machine_mode mode,
  33998. + int addr_offset)
  33999. +{
  34000. + gcc_assert (MEM_P (src) && MEM_P (dst));
  34001. + rtx tmp_reg = gen_reg_rtx (mode);
  34002. + nds32_emit_load_store (tmp_reg, src, mode,
  34003. + addr_offset, /* load_p */ true);
  34004. + nds32_emit_load_store (tmp_reg, dst, mode,
  34005. + addr_offset, /* load_p */ false);
  34006. +}
  34007. +
  34008. +static void
  34009. +nds32_emit_mem_move_block (int base_regno, int count,
  34010. + rtx *dst_base_reg, rtx *dst_mem,
  34011. + rtx *src_base_reg, rtx *src_mem,
  34012. + bool update_base_reg_p)
  34013. +{
  34014. + rtx new_base_reg;
  34015. +
  34016. + emit_insn (nds32_expand_load_multiple (base_regno, count,
  34017. + *src_base_reg, *src_mem,
  34018. + update_base_reg_p, &new_base_reg));
  34019. + if (update_base_reg_p)
  34020. + {
  34021. + *src_base_reg = new_base_reg;
  34022. + *src_mem = gen_rtx_MEM (SImode, *src_base_reg);
  34023. + }
  34024. +
  34025. + emit_insn (nds32_expand_store_multiple (base_regno, count,
  34026. + *dst_base_reg, *dst_mem,
  34027. + update_base_reg_p, &new_base_reg));
  34028. +
  34029. + if (update_base_reg_p)
  34030. + {
  34031. + *dst_base_reg = new_base_reg;
  34032. + *dst_mem = gen_rtx_MEM (SImode, *dst_base_reg);
  34033. + }
  34034. +}
  34035. +
  34036. +/* ------------------------------------------------------------------------ */
  34037. +
  34038. +/* PART 2: Auxiliary function for expand movmem pattern. */
  34039. +
  34040. +static bool
  34041. +nds32_expand_movmemsi_loop_unknown_size (rtx dstmem, rtx srcmem,
  34042. + rtx size,
  34043. + rtx alignment)
  34044. +{
  34045. + /* Emit loop version of movmem.
  34046. +
  34047. + andi $size_least_3_bit, $size, #~7
  34048. + add $dst_end, $dst, $size
  34049. + move $dst_itr, $dst
  34050. + move $src_itr, $src
  34051. + beqz $size_least_3_bit, .Lbyte_mode_entry ! Not large enough.
  34052. + add $double_word_end, $dst, $size_least_3_bit
  34053. +
  34054. + .Ldouble_word_mode_loop:
  34055. + lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr
  34056. + smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr
  34057. + ! move will delete after register allocation
  34058. + move $src_itr, $src_itr'
  34059. + move $dst_itr, $dst_itr'
  34060. + ! Not readch upper bound. Loop.
  34061. + bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop
  34062. +
  34063. + .Lbyte_mode_entry:
  34064. + beq $dst_itr, $dst_end, .Lend_label
  34065. + .Lbyte_mode_loop:
  34066. + lbi.bi $tmp, [$src_itr], #1
  34067. + sbi.bi $tmp, [$dst_itr], #1
  34068. + ! Not readch upper bound. Loop.
  34069. + bne $dst_itr, $dst_end, .Lbyte_mode_loop
  34070. + .Lend_label:
  34071. + */
  34072. + rtx dst_base_reg, src_base_reg;
  34073. + rtx dst_itr, src_itr;
  34074. + rtx dstmem_m, srcmem_m, dst_itr_m, src_itr_m;
  34075. + rtx dst_end;
  34076. + rtx size_least_3_bit;
  34077. + rtx double_word_end;
  34078. + rtx double_word_mode_loop, byte_mode_entry, byte_mode_loop, end_label;
  34079. + rtx tmp;
  34080. + rtx mask_least_3_bit;
  34081. + int start_regno;
  34082. + bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0;
  34083. +
  34084. + if (TARGET_ISA_V3M && !align_to_4_bytes)
  34085. + return 0;
  34086. +
  34087. + if (TARGET_REDUCED_REGS)
  34088. + start_regno = 2;
  34089. + else
  34090. + start_regno = 16;
  34091. +
  34092. + dst_itr = gen_reg_rtx (Pmode);
  34093. + src_itr = gen_reg_rtx (Pmode);
  34094. + dst_end = gen_reg_rtx (Pmode);
  34095. + tmp = gen_reg_rtx (QImode);
  34096. + mask_least_3_bit = GEN_INT (~7);
  34097. +
  34098. + double_word_mode_loop = gen_label_rtx ();
  34099. + byte_mode_entry = gen_label_rtx ();
  34100. + byte_mode_loop = gen_label_rtx ();
  34101. + end_label = gen_label_rtx ();
  34102. +
  34103. + dst_base_reg = copy_to_mode_reg (Pmode, XEXP (dstmem, 0));
  34104. + src_base_reg = copy_to_mode_reg (Pmode, XEXP (srcmem, 0));
  34105. + /* andi $size_least_3_bit, $size, #~7 */
  34106. + size_least_3_bit = expand_binop (SImode, and_optab, size, mask_least_3_bit,
  34107. + NULL_RTX, 0, OPTAB_WIDEN);
  34108. + /* add $dst_end, $dst, $size */
  34109. + dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size,
  34110. + NULL_RTX, 0, OPTAB_WIDEN);
  34111. +
  34112. + /* move $dst_itr, $dst
  34113. + move $src_itr, $src */
  34114. + emit_move_insn (dst_itr, dst_base_reg);
  34115. + emit_move_insn (src_itr, src_base_reg);
  34116. +
  34117. + /* beqz $size_least_3_bit, .Lbyte_mode_entry ! Not large enough. */
  34118. + emit_cmp_and_jump_insns (size_least_3_bit, const0_rtx, EQ, NULL,
  34119. + SImode, 1, byte_mode_entry);
  34120. + /* add $double_word_end, $dst, $size_least_3_bit */
  34121. + double_word_end = expand_binop (Pmode, add_optab,
  34122. + dst_base_reg, size_least_3_bit,
  34123. + NULL_RTX, 0, OPTAB_WIDEN);
  34124. +
  34125. + /* .Ldouble_word_mode_loop: */
  34126. + emit_label (double_word_mode_loop);
  34127. + /* lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr
  34128. + smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr */
  34129. + src_itr_m = src_itr;
  34130. + dst_itr_m = dst_itr;
  34131. + srcmem_m = srcmem;
  34132. + dstmem_m = dstmem;
  34133. + nds32_emit_mem_move_block (start_regno, 2,
  34134. + &dst_itr_m, &dstmem_m,
  34135. + &src_itr_m, &srcmem_m,
  34136. + true);
  34137. + /* move $src_itr, $src_itr'
  34138. + move $dst_itr, $dst_itr' */
  34139. + emit_move_insn (dst_itr, dst_itr_m);
  34140. + emit_move_insn (src_itr, src_itr_m);
  34141. +
  34142. + /* ! Not readch upper bound. Loop.
  34143. + bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */
  34144. + emit_cmp_and_jump_insns (double_word_end, dst_itr, NE, NULL,
  34145. + Pmode, 1, double_word_mode_loop);
  34146. + /* .Lbyte_mode_entry: */
  34147. + emit_label (byte_mode_entry);
  34148. +
  34149. + /* beq $dst_itr, $dst_end, .Lend_label */
  34150. + emit_cmp_and_jump_insns (dst_itr, dst_end, EQ, NULL,
  34151. + Pmode, 1, end_label);
  34152. + /* .Lbyte_mode_loop: */
  34153. + emit_label (byte_mode_loop);
  34154. +
  34155. + emit_insn (gen_no_hwloop ());
  34156. + /* lbi.bi $tmp, [$src_itr], #1 */
  34157. + nds32_emit_post_inc_load_store (tmp, src_itr, QImode, true);
  34158. +
  34159. + /* sbi.bi $tmp, [$dst_itr], #1 */
  34160. + nds32_emit_post_inc_load_store (tmp, dst_itr, QImode, false);
  34161. + /* ! Not readch upper bound. Loop.
  34162. + bne $dst_itr, $dst_end, .Lbyte_mode_loop */
  34163. + emit_cmp_and_jump_insns (dst_itr, dst_end, NE, NULL,
  34164. + SImode, 1, byte_mode_loop);
  34165. +
  34166. + /* .Lend_label: */
  34167. + emit_label (end_label);
  34168. +
  34169. + return true;
  34170. +}
  34171. +
  34172. +static bool
  34173. +nds32_expand_movmemsi_loop_known_size (rtx dstmem, rtx srcmem,
  34174. + rtx size, rtx alignment)
  34175. +{
  34176. + return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,
  34177. + size, alignment);
  34178. +}
  34179. +
  34180. +static bool
  34181. +nds32_expand_movmemsi_loop (rtx dstmem, rtx srcmem,
  34182. + rtx size, rtx alignment)
  34183. +{
  34184. + if (CONST_INT_P (size))
  34185. + return nds32_expand_movmemsi_loop_known_size (dstmem, srcmem,
  34186. + size, alignment);
  34187. + else
  34188. + return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,
  34189. + size, alignment);
  34190. +}
  34191. +
  34192. +static bool
  34193. +nds32_expand_movmemsi_unroll (rtx dstmem, rtx srcmem,
  34194. + rtx total_bytes, rtx alignment)
  34195. +{
  34196. + rtx dst_base_reg, src_base_reg;
  34197. + rtx tmp_reg;
  34198. + int maximum_bytes;
  34199. + int maximum_bytes_per_inst;
  34200. + int maximum_regs;
  34201. + int start_regno;
  34202. + int i, inst_num;
  34203. + HOST_WIDE_INT remain_bytes, remain_words;
  34204. + bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0;
  34205. + bool align_to_2_bytes = (INTVAL (alignment) & 1) == 0;
  34206. +
  34207. + /* Because reduced-set regsiters has few registers
  34208. + (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31'
  34209. + cannot be used for register allocation),
  34210. + using 8 registers (32 bytes) for moving memory block
  34211. + may easily consume all of them.
  34212. + It makes register allocation/spilling hard to work.
  34213. + So we only allow maximum=4 registers (16 bytes) for
  34214. + moving memory block under reduced-set registers. */
  34215. + if (TARGET_REDUCED_REGS)
  34216. + {
  34217. + maximum_regs = 4;
  34218. + maximum_bytes = 64;
  34219. + start_regno = 2;
  34220. + }
  34221. + else
  34222. + {
  34223. + if (TARGET_LINUX_ABI)
  34224. + {
  34225. + /* $r25 is $tp so we use up to 8 registers if using Linux ABI. */
  34226. + maximum_regs = 8;
  34227. + maximum_bytes = 160;
  34228. + start_regno = 16;
  34229. + }
  34230. + else
  34231. + {
  34232. + maximum_regs = 10;
  34233. + maximum_bytes = 160;
  34234. + start_regno = 16;
  34235. + }
  34236. + }
  34237. + maximum_bytes_per_inst = maximum_regs * UNITS_PER_WORD;
  34238. +
  34239. + /* 1. Total_bytes is integer for sure.
  34240. + 2. Alignment is integer for sure.
  34241. + 3. Maximum 4 or 10 registers and up to 4 instructions,
  34242. + 4 * 4 * 4 = 64 bytes, 8 * 4 * 10 = 160 bytes.
  34243. + 4. The dstmem cannot be volatile memory access.
  34244. + 5. The srcmem cannot be volatile memory access.
  34245. + 6. Known shared alignment not align to 4 byte in v3m since lmw/smw *NOT*
  34246. + support unalign access with v3m configure. */
  34247. + if (GET_CODE (total_bytes) != CONST_INT
  34248. + || GET_CODE (alignment) != CONST_INT
  34249. + || INTVAL (total_bytes) > maximum_bytes
  34250. + || MEM_VOLATILE_P (dstmem)
  34251. + || MEM_VOLATILE_P (srcmem)
  34252. + || (TARGET_ISA_V3M && !align_to_4_bytes))
  34253. + return false;
  34254. +
  34255. + dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
  34256. + src_base_reg = copy_to_mode_reg (SImode, XEXP (srcmem, 0));
  34257. + remain_bytes = INTVAL (total_bytes);
  34258. +
  34259. + /* Do not update base address for last lmw/smw pair. */
  34260. + inst_num = ((INTVAL (total_bytes) + (maximum_bytes_per_inst - 1))
  34261. + / maximum_bytes_per_inst) - 1;
  34262. +
  34263. + for (i = 0; i < inst_num; i++)
  34264. + {
  34265. + nds32_emit_mem_move_block (start_regno, maximum_regs,
  34266. + &dst_base_reg, &dstmem,
  34267. + &src_base_reg, &srcmem,
  34268. + true);
  34269. + }
  34270. + remain_bytes -= maximum_bytes_per_inst * inst_num;
  34271. +
  34272. + remain_words = remain_bytes / UNITS_PER_WORD;
  34273. + remain_bytes = remain_bytes - (remain_words * UNITS_PER_WORD);
  34274. +
  34275. + if (remain_words != 0)
  34276. + {
  34277. + if (remain_bytes != 0)
  34278. + nds32_emit_mem_move_block (start_regno, remain_words,
  34279. + &dst_base_reg, &dstmem,
  34280. + &src_base_reg, &srcmem,
  34281. + true);
  34282. + else
  34283. + {
  34284. + /* Do not update address if no further byte to move. */
  34285. + if (remain_words == 1)
  34286. + {
  34287. + /* emit move instruction if align to 4 byte and only 1
  34288. + word to move. */
  34289. + if (align_to_4_bytes)
  34290. + nds32_emit_mem_move (srcmem, dstmem, SImode, 0);
  34291. + else
  34292. + {
  34293. + tmp_reg = gen_reg_rtx (SImode);
  34294. + emit_insn (
  34295. + gen_unaligned_load_w (tmp_reg,
  34296. + gen_rtx_MEM (SImode, src_base_reg)));
  34297. + emit_insn (
  34298. + gen_unaligned_store_w (gen_rtx_MEM (SImode, dst_base_reg),
  34299. + tmp_reg));
  34300. + }
  34301. + }
  34302. + else
  34303. + nds32_emit_mem_move_block (start_regno, remain_words,
  34304. + &dst_base_reg, &dstmem,
  34305. + &src_base_reg, &srcmem,
  34306. + false);
  34307. + }
  34308. + }
  34309. +
  34310. + switch (remain_bytes)
  34311. + {
  34312. + case 3:
  34313. + case 2:
  34314. + {
  34315. + if (align_to_2_bytes)
  34316. + nds32_emit_mem_move (srcmem, dstmem, HImode, 0);
  34317. + else
  34318. + {
  34319. + nds32_emit_mem_move (srcmem, dstmem, QImode, 0);
  34320. + nds32_emit_mem_move (srcmem, dstmem, QImode, 1);
  34321. + }
  34322. +
  34323. + if (remain_bytes == 3)
  34324. + nds32_emit_mem_move (srcmem, dstmem, QImode, 2);
  34325. + break;
  34326. + }
  34327. + case 1:
  34328. + nds32_emit_mem_move (srcmem, dstmem, QImode, 0);
  34329. + break;
  34330. + case 0:
  34331. + break;
  34332. + default:
  34333. + gcc_unreachable ();
  34334. + }
  34335. +
  34336. + /* Successfully create patterns, return true. */
  34337. + return true;
  34338. +}
  34339. +
  34340. +/* Function to move block memory content by
  34341. + using load_multiple and store_multiple.
  34342. + This is auxiliary extern function to help create rtx template.
  34343. + Check nds32-multiple.md file for the patterns. */
  34344. +bool
  34345. +nds32_expand_movmemsi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
  34346. +{
  34347. + if (nds32_expand_movmemsi_unroll (dstmem, srcmem, total_bytes, alignment))
  34348. + return true;
  34349. +
  34350. + if (!optimize_size && optimize > 2)
  34351. + return nds32_expand_movmemsi_loop (dstmem, srcmem, total_bytes, alignment);
  34352. +
  34353. + return false;
  34354. +}
  34355. +
  34356. +/* ------------------------------------------------------------------------ */
  34357. +
  34358. +/* PART 3: Auxiliary function for expand setmem pattern. */
  34359. +
  34360. +static rtx
  34361. +nds32_gen_dup_4_byte_to_word_value (rtx value)
  34362. +{
  34363. + rtx value4word = gen_reg_rtx (SImode);
  34364. +
  34365. + gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value));
  34366. +
  34367. + if (CONST_INT_P (value))
  34368. + {
  34369. + unsigned HOST_WIDE_INT val = UINTVAL (value) & GET_MODE_MASK(QImode);
  34370. + rtx new_val = gen_int_mode (val | (val << 8)
  34371. + | (val << 16) | (val << 24), SImode);
  34372. + /* Just calculate at here if it's constant value. */
  34373. + emit_move_insn (value4word, new_val);
  34374. + }
  34375. + else
  34376. + {
  34377. + if (NDS32_EXT_DSP_P ())
  34378. + {
  34379. + /* ! prepare word
  34380. + andi $tmp, $value, 0xff ! $tmp <- 0x000000ab
  34381. + insb $tmp, $tmp, 1 ! $tmp <- 0x0000abab
  34382. + pkbb16 $tmp6, $tmp2, $tmp2 ! $value4word <- 0xabababab */
  34383. +
  34384. + rtx tmp;
  34385. + tmp = expand_binop (SImode, and_optab, value,
  34386. + gen_int_mode (0xff, SImode),
  34387. + NULL_RTX, 0, OPTAB_WIDEN);
  34388. +
  34389. + emit_insn (
  34390. + gen_insvsi_internal (tmp, gen_int_mode (0x8, SImode), tmp));
  34391. +
  34392. + emit_insn (gen_pkbbsi_1 (value4word, tmp, tmp));
  34393. + }
  34394. + else
  34395. + {
  34396. + /* ! prepare word
  34397. + andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab
  34398. + slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00
  34399. + or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab
  34400. + slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000
  34401. + or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */
  34402. +
  34403. + rtx tmp1, tmp2, tmp3, tmp4, final_value;
  34404. + tmp1 = expand_binop (SImode, and_optab, value,
  34405. + gen_int_mode (0xff, SImode),
  34406. + NULL_RTX, 0, OPTAB_WIDEN);
  34407. + tmp2 = expand_binop (SImode, ashl_optab, tmp1,
  34408. + gen_int_mode (8, SImode),
  34409. + NULL_RTX, 0, OPTAB_WIDEN);
  34410. + tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2,
  34411. + NULL_RTX, 0, OPTAB_WIDEN);
  34412. + tmp4 = expand_binop (SImode, ashl_optab, tmp3,
  34413. + gen_int_mode (16, SImode),
  34414. + NULL_RTX, 0, OPTAB_WIDEN);
  34415. +
  34416. + final_value = expand_binop (SImode, ior_optab, tmp3, tmp4,
  34417. + NULL_RTX, 0, OPTAB_WIDEN);
  34418. + emit_move_insn (value4word, final_value);
  34419. + }
  34420. + }
  34421. +
  34422. + return value4word;
  34423. +}
  34424. +
  34425. +static rtx
  34426. +emit_setmem_word_loop (rtx itr, rtx size, rtx value)
  34427. +{
  34428. + rtx word_mode_label = gen_label_rtx ();
  34429. + rtx word_mode_end_label = gen_label_rtx ();
  34430. + rtx byte_mode_size = gen_reg_rtx (SImode);
  34431. + rtx byte_mode_size_tmp = gen_reg_rtx (SImode);
  34432. + rtx word_mode_end = gen_reg_rtx (SImode);
  34433. + rtx size_for_word = gen_reg_rtx (SImode);
  34434. +
  34435. + /* and $size_for_word, $size, #~3 */
  34436. + size_for_word = expand_binop (SImode, and_optab, size,
  34437. + gen_int_mode (~3, SImode),
  34438. + NULL_RTX, 0, OPTAB_WIDEN);
  34439. +
  34440. + emit_move_insn (byte_mode_size, size);
  34441. +
  34442. + /* beqz $size_for_word, .Lbyte_mode_entry */
  34443. + emit_cmp_and_jump_insns (size_for_word, const0_rtx, EQ, NULL,
  34444. + SImode, 1, word_mode_end_label);
  34445. + /* add $word_mode_end, $dst, $size_for_word */
  34446. + word_mode_end = expand_binop (Pmode, add_optab, itr, size_for_word,
  34447. + NULL_RTX, 0, OPTAB_WIDEN);
  34448. +
  34449. + /* andi $byte_mode_size, $size, 3 */
  34450. + byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (3),
  34451. + NULL_RTX, 0, OPTAB_WIDEN);
  34452. +
  34453. + emit_move_insn (byte_mode_size, byte_mode_size_tmp);
  34454. +
  34455. + /* .Lword_mode: */
  34456. + emit_label (word_mode_label);
  34457. + /* ! word-mode set loop
  34458. + smw.bim $value4word, [$dst_itr], $value4word, 0
  34459. + bne $word_mode_end, $dst_itr, .Lword_mode */
  34460. + emit_insn (gen_unaligned_store_update_base_w (itr,
  34461. + itr,
  34462. + value));
  34463. + emit_cmp_and_jump_insns (word_mode_end, itr, NE, NULL,
  34464. + Pmode, 1, word_mode_label);
  34465. +
  34466. + emit_label (word_mode_end_label);
  34467. +
  34468. + return byte_mode_size;
  34469. +}
  34470. +
  34471. +static rtx
  34472. +emit_setmem_byte_loop (rtx itr, rtx size, rtx value, bool need_end)
  34473. +{
  34474. + rtx end = gen_reg_rtx (Pmode);
  34475. + rtx byte_mode_label = gen_label_rtx ();
  34476. + rtx end_label = gen_label_rtx ();
  34477. +
  34478. + value = force_reg (QImode, value);
  34479. +
  34480. + if (need_end)
  34481. + end = expand_binop (Pmode, add_optab, itr, size,
  34482. + NULL_RTX, 0, OPTAB_WIDEN);
  34483. + /* beqz $byte_mode_size, .Lend
  34484. + add $byte_mode_end, $dst_itr, $byte_mode_size */
  34485. + emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL,
  34486. + SImode, 1, end_label);
  34487. +
  34488. + if (!need_end)
  34489. + end = expand_binop (Pmode, add_optab, itr, size,
  34490. + NULL_RTX, 0, OPTAB_WIDEN);
  34491. +
  34492. + /* .Lbyte_mode: */
  34493. + emit_label (byte_mode_label);
  34494. +
  34495. + emit_insn (gen_no_hwloop ());
  34496. + /* ! byte-mode set loop
  34497. + sbi.bi $value, [$dst_itr] ,1
  34498. + bne $byte_mode_end, $dst_itr, .Lbyte_mode */
  34499. + nds32_emit_post_inc_load_store (value, itr, QImode, false);
  34500. +
  34501. + emit_cmp_and_jump_insns (end, itr, NE, NULL,
  34502. + Pmode, 1, byte_mode_label);
  34503. + /* .Lend: */
  34504. + emit_label (end_label);
  34505. +
  34506. + if (need_end)
  34507. + return end;
  34508. + else
  34509. + return NULL_RTX;
  34510. +}
  34511. +
  34512. +static bool
  34513. +nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value)
  34514. +{
  34515. + rtx value4word;
  34516. + rtx value4byte;
  34517. + rtx dst;
  34518. + rtx byte_mode_size;
  34519. +
  34520. + /* Emit loop version of setmem.
  34521. + memset:
  34522. + ! prepare word
  34523. + andi $tmp1, $val, 0xff ! $tmp1 <- 0x000000ab
  34524. + slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00
  34525. + or $tmp3, $val, $tmp2 ! $tmp3 <- 0x0000abab
  34526. + slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000
  34527. + or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab
  34528. +
  34529. + and $size_for_word, $size, #-4
  34530. + beqz $size_for_word, .Lword_mode_end
  34531. +
  34532. + add $word_mode_end, $dst, $size_for_word
  34533. + andi $byte_mode_size, $size, 3
  34534. +
  34535. + .Lword_mode:
  34536. + ! word-mode set loop
  34537. + smw.bim $value4word, [$dst], $value4word, 0
  34538. + bne $word_mode_end, $dst, .Lword_mode
  34539. +
  34540. + .Lword_mode_end:
  34541. + beqz $byte_mode_size, .Lend
  34542. + add $byte_mode_end, $dst, $byte_mode_size
  34543. +
  34544. + .Lbyte_mode:
  34545. + ! byte-mode set loop
  34546. + sbi.bi $value4word, [$dst] ,1
  34547. + bne $byte_mode_end, $dst, .Lbyte_mode
  34548. + .Lend: */
  34549. +
  34550. + dst = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
  34551. +
  34552. + /* ! prepare word
  34553. + andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab
  34554. + slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00
  34555. + or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab
  34556. + slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000
  34557. + or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */
  34558. + value4word = nds32_gen_dup_4_byte_to_word_value (value);
  34559. +
  34560. + /* and $size_for_word, $size, #-4
  34561. + beqz $size_for_word, .Lword_mode_end
  34562. +
  34563. + add $word_mode_end, $dst, $size_for_word
  34564. + andi $byte_mode_size, $size, 3
  34565. +
  34566. + .Lword_mode:
  34567. + ! word-mode set loop
  34568. + smw.bim $value4word, [$dst], $value4word, 0
  34569. + bne $word_mode_end, $dst, .Lword_mode
  34570. + .Lword_mode_end: */
  34571. + byte_mode_size = emit_setmem_word_loop (dst, size, value4word);
  34572. +
  34573. + /* beqz $byte_mode_size, .Lend
  34574. + add $byte_mode_end, $dst, $byte_mode_size
  34575. +
  34576. + .Lbyte_mode:
  34577. + ! byte-mode set loop
  34578. + sbi.bi $value, [$dst] ,1
  34579. + bne $byte_mode_end, $dst, .Lbyte_mode
  34580. + .Lend: */
  34581. +
  34582. + value4byte = simplify_gen_subreg (QImode, value4word, SImode,
  34583. + subreg_lowpart_offset (QImode, SImode));
  34584. +
  34585. + emit_setmem_byte_loop (dst, byte_mode_size, value4byte, false);
  34586. +
  34587. + return true;
  34588. +}
  34589. +
  34590. +static bool
  34591. +nds32_expand_setmem_loop_v3m (rtx dstmem, rtx size, rtx value)
  34592. +{
  34593. + rtx base_reg = copy_to_mode_reg (Pmode, XEXP (dstmem, 0));
  34594. + rtx need_align_bytes = gen_reg_rtx (SImode);
  34595. + rtx last_2_bit = gen_reg_rtx (SImode);
  34596. + rtx byte_loop_base = gen_reg_rtx (SImode);
  34597. + rtx byte_loop_size = gen_reg_rtx (SImode);
  34598. + rtx remain_size = gen_reg_rtx (SImode);
  34599. + rtx new_base_reg;
  34600. + rtx value4byte, value4word;
  34601. + rtx byte_mode_size;
  34602. + rtx last_byte_loop_label = gen_label_rtx ();
  34603. +
  34604. + size = force_reg (SImode, size);
  34605. +
  34606. + value4word = nds32_gen_dup_4_byte_to_word_value (value);
  34607. + value4byte = simplify_gen_subreg (QImode, value4word, SImode, 0);
  34608. +
  34609. + emit_move_insn (byte_loop_size, size);
  34610. + emit_move_insn (byte_loop_base, base_reg);
  34611. +
  34612. + /* Jump to last byte loop if size is less than 16. */
  34613. + emit_cmp_and_jump_insns (size, gen_int_mode (16, SImode), LE, NULL,
  34614. + SImode, 1, last_byte_loop_label);
  34615. +
  34616. + /* Make sure align to 4 byte first since v3m can't unalign access. */
  34617. + emit_insn (gen_andsi3 (last_2_bit,
  34618. + base_reg,
  34619. + gen_int_mode (0x3, SImode)));
  34620. +
  34621. + emit_insn (gen_subsi3 (need_align_bytes,
  34622. + gen_int_mode (4, SImode),
  34623. + last_2_bit));
  34624. +
  34625. + /* Align to 4 byte. */
  34626. + new_base_reg = emit_setmem_byte_loop (base_reg,
  34627. + need_align_bytes,
  34628. + value4byte,
  34629. + true);
  34630. +
  34631. + /* Calculate remain size. */
  34632. + emit_insn (gen_subsi3 (remain_size, size, need_align_bytes));
  34633. +
  34634. + /* Set memory word by word. */
  34635. + byte_mode_size = emit_setmem_word_loop (new_base_reg,
  34636. + remain_size,
  34637. + value4word);
  34638. +
  34639. + emit_move_insn (byte_loop_base, new_base_reg);
  34640. + emit_move_insn (byte_loop_size, byte_mode_size);
  34641. +
  34642. + emit_label (last_byte_loop_label);
  34643. +
  34644. + /* And set memory for remain bytes. */
  34645. + emit_setmem_byte_loop (byte_loop_base, byte_loop_size, value4byte, false);
  34646. + return true;
  34647. +}
  34648. +
  34649. +static bool
  34650. +nds32_expand_setmem_unroll (rtx dstmem, rtx size, rtx value,
  34651. + rtx align ATTRIBUTE_UNUSED,
  34652. + rtx expected_align ATTRIBUTE_UNUSED,
  34653. + rtx expected_size ATTRIBUTE_UNUSED)
  34654. +{
  34655. + unsigned maximum_regs, maximum_bytes, start_regno, regno;
  34656. + rtx value4word;
  34657. + rtx dst_base_reg, new_base_reg;
  34658. + unsigned HOST_WIDE_INT remain_bytes, remain_words, prepare_regs, fill_per_smw;
  34659. + unsigned HOST_WIDE_INT real_size;
  34660. +
  34661. + if (TARGET_REDUCED_REGS)
  34662. + {
  34663. + maximum_regs = 4;
  34664. + maximum_bytes = 64;
  34665. + start_regno = 2;
  34666. + }
  34667. + else
  34668. + {
  34669. + maximum_regs = 8;
  34670. + maximum_bytes = 128;
  34671. + start_regno = 16;
  34672. + }
  34673. +
  34674. + real_size = UINTVAL (size) & GET_MODE_MASK(SImode);
  34675. +
  34676. + if (!(CONST_INT_P (size) && real_size <= maximum_bytes))
  34677. + return false;
  34678. +
  34679. + remain_bytes = real_size;
  34680. +
  34681. + gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value));
  34682. +
  34683. + value4word = nds32_gen_dup_4_byte_to_word_value (value);
  34684. +
  34685. + prepare_regs = remain_bytes / UNITS_PER_WORD;
  34686. +
  34687. + dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
  34688. +
  34689. + if (prepare_regs > maximum_regs)
  34690. + prepare_regs = maximum_regs;
  34691. +
  34692. + fill_per_smw = prepare_regs * UNITS_PER_WORD;
  34693. +
  34694. + regno = start_regno;
  34695. + switch (prepare_regs)
  34696. + {
  34697. + case 2:
  34698. + default:
  34699. + {
  34700. + rtx reg0 = gen_rtx_REG (SImode, regno);
  34701. + rtx reg1 = gen_rtx_REG (SImode, regno+1);
  34702. + unsigned last_regno = start_regno + prepare_regs - 1;
  34703. +
  34704. + emit_move_insn (reg0, value4word);
  34705. + emit_move_insn (reg1, value4word);
  34706. + rtx regd = gen_rtx_REG (DImode, regno);
  34707. + regno += 2;
  34708. +
  34709. + /* Try to utilize movd44! */
  34710. + while (regno <= last_regno)
  34711. + {
  34712. + if ((regno + 1) <=last_regno)
  34713. + {
  34714. + rtx reg = gen_rtx_REG (DImode, regno);
  34715. + emit_move_insn (reg, regd);
  34716. + regno += 2;
  34717. + }
  34718. + else
  34719. + {
  34720. + rtx reg = gen_rtx_REG (SImode, regno);
  34721. + emit_move_insn (reg, reg0);
  34722. + regno += 1;
  34723. + }
  34724. + }
  34725. + break;
  34726. + }
  34727. + case 1:
  34728. + {
  34729. + rtx reg = gen_rtx_REG (SImode, regno++);
  34730. + emit_move_insn (reg, value4word);
  34731. + }
  34732. + break;
  34733. + case 0:
  34734. + break;
  34735. + }
  34736. +
  34737. + if (fill_per_smw)
  34738. + for (;remain_bytes >= fill_per_smw;remain_bytes -= fill_per_smw)
  34739. + {
  34740. + emit_insn (nds32_expand_store_multiple (start_regno, prepare_regs,
  34741. + dst_base_reg, dstmem,
  34742. + true, &new_base_reg));
  34743. + dst_base_reg = new_base_reg;
  34744. + dstmem = gen_rtx_MEM (SImode, dst_base_reg);
  34745. + }
  34746. +
  34747. + remain_words = remain_bytes / UNITS_PER_WORD;
  34748. +
  34749. + if (remain_words)
  34750. + {
  34751. + emit_insn (nds32_expand_store_multiple (start_regno, remain_words,
  34752. + dst_base_reg, dstmem,
  34753. + true, &new_base_reg));
  34754. + dst_base_reg = new_base_reg;
  34755. + dstmem = gen_rtx_MEM (SImode, dst_base_reg);
  34756. + }
  34757. +
  34758. + remain_bytes = remain_bytes - (remain_words * UNITS_PER_WORD);
  34759. +
  34760. + if (remain_bytes)
  34761. + {
  34762. + value = simplify_gen_subreg (QImode, value4word, SImode,
  34763. + subreg_lowpart_offset(QImode, SImode));
  34764. + int offset = 0;
  34765. + for (;remain_bytes;--remain_bytes, ++offset)
  34766. + {
  34767. + nds32_emit_load_store (value, dstmem, QImode, offset, false);
  34768. + }
  34769. + }
  34770. +
  34771. + return true;
  34772. +}
  34773. +
  34774. +bool
  34775. +nds32_expand_setmem (rtx dstmem, rtx size, rtx value, rtx align,
  34776. + rtx expected_align,
  34777. + rtx expected_size)
  34778. +{
  34779. + bool align_to_4_bytes = (INTVAL (align) & 3) == 0;
  34780. +
  34781. + /* Only expand at O3 */
  34782. + if (optimize_size || optimize < 3)
  34783. + return false;
  34784. +
  34785. + if (TARGET_ISA_V3M && !align_to_4_bytes)
  34786. + return nds32_expand_setmem_loop_v3m (dstmem, size, value);
  34787. +
  34788. + if (nds32_expand_setmem_unroll (dstmem, size, value,
  34789. + align, expected_align, expected_size))
  34790. + return true;
  34791. +
  34792. + return nds32_expand_setmem_loop (dstmem, size, value);
  34793. +}
  34794. +
  34795. +/* ------------------------------------------------------------------------ */
  34796. +
  34797. +/* PART 4: Auxiliary function for expand movstr pattern. */
  34798. +
  34799. +bool
  34800. +nds32_expand_movstr (rtx dst_end_ptr,
  34801. + rtx dstmem,
  34802. + rtx srcmem)
  34803. +{
  34804. + rtx tmp;
  34805. + rtx dst_base_reg, src_base_reg;
  34806. + rtx new_dst_base_reg, new_src_base_reg;
  34807. + rtx last_non_null_char_ptr;
  34808. + rtx ffbi_result;
  34809. + rtx loop_label;
  34810. +
  34811. + if (optimize_size || optimize < 3)
  34812. + return false;
  34813. +
  34814. + tmp = gen_reg_rtx (SImode);
  34815. + ffbi_result = gen_reg_rtx (Pmode);
  34816. + new_dst_base_reg = gen_reg_rtx (Pmode);
  34817. + new_src_base_reg = gen_reg_rtx (Pmode);
  34818. + dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
  34819. + src_base_reg = copy_to_mode_reg (SImode, XEXP (srcmem, 0));
  34820. + loop_label = gen_label_rtx ();
  34821. +
  34822. + emit_label (loop_label);
  34823. + emit_insn (gen_lmwzb (new_src_base_reg, src_base_reg, tmp));
  34824. + emit_insn (gen_smwzb (new_dst_base_reg, dst_base_reg, tmp));
  34825. + emit_insn (gen_unspec_ffb (ffbi_result, tmp, const0_rtx));
  34826. +
  34827. + emit_move_insn (src_base_reg, new_src_base_reg);
  34828. + emit_move_insn (dst_base_reg, new_dst_base_reg);
  34829. +
  34830. + emit_cmp_and_jump_insns (ffbi_result, const0_rtx, EQ, NULL,
  34831. + SImode, 1, loop_label);
  34832. +
  34833. + last_non_null_char_ptr = expand_binop (Pmode, add_optab, dst_base_reg,
  34834. + ffbi_result, NULL_RTX, 0, OPTAB_WIDEN);
  34835. +
  34836. + emit_move_insn (dst_end_ptr, last_non_null_char_ptr);
  34837. +
  34838. + return true;
  34839. +}
  34840. +
  34841. +/* ------------------------------------------------------------------------ */
  34842. +
  34843. +/* PART 5: Auxiliary function for expand strlen pattern. */
  34844. +
  34845. +bool
  34846. +nds32_expand_strlen (rtx result, rtx str,
  34847. + rtx target_char, rtx align ATTRIBUTE_UNUSED)
  34848. +{
  34849. + rtx base_reg, backup_base_reg;
  34850. + rtx ffb_result;
  34851. + rtx target_char_ptr, length;
  34852. + rtx loop_label, tmp;
  34853. +
  34854. + if (optimize_size || optimize < 3)
  34855. + return false;
  34856. +
  34857. + gcc_assert (MEM_P (str));
  34858. + gcc_assert (CONST_INT_P (target_char) || REG_P (target_char));
  34859. +
  34860. + base_reg = copy_to_mode_reg (SImode, XEXP (str, 0));
  34861. + loop_label = gen_label_rtx ();
  34862. +
  34863. + ffb_result = gen_reg_rtx (Pmode);
  34864. + tmp = gen_reg_rtx (SImode);
  34865. + backup_base_reg = gen_reg_rtx (SImode);
  34866. +
  34867. + /* Emit loop version of strlen.
  34868. + move $backup_base, $base
  34869. + .Lloop:
  34870. + lmw.bim $tmp, [$base], $tmp, 0
  34871. + ffb $ffb_result, $tmp, $target_char ! is there $target_char?
  34872. + beqz $ffb_result, .Lloop
  34873. + add $last_char_ptr, $base, $ffb_result
  34874. + sub $length, $last_char_ptr, $backup_base */
  34875. +
  34876. + /* move $backup_base, $base */
  34877. + emit_move_insn (backup_base_reg, base_reg);
  34878. +
  34879. + /* .Lloop: */
  34880. + emit_label (loop_label);
  34881. + /* lmw.bim $tmp, [$base], $tmp, 0 */
  34882. + emit_insn (gen_unaligned_load_update_base_w (base_reg, tmp, base_reg));
  34883. +
  34884. + /* ffb $ffb_result, $tmp, $target_char ! is there $target_char? */
  34885. + emit_insn (gen_unspec_ffb (ffb_result, tmp, target_char));
  34886. +
  34887. + /* beqz $ffb_result, .Lloop */
  34888. + emit_cmp_and_jump_insns (ffb_result, const0_rtx, EQ, NULL,
  34889. + SImode, 1, loop_label);
  34890. +
  34891. + /* add $target_char_ptr, $base, $ffb_result */
  34892. + target_char_ptr = expand_binop (Pmode, add_optab, base_reg,
  34893. + ffb_result, NULL_RTX, 0, OPTAB_WIDEN);
  34894. +
  34895. + /* sub $length, $target_char_ptr, $backup_base */
  34896. + length = expand_binop (Pmode, sub_optab, target_char_ptr,
  34897. + backup_base_reg, NULL_RTX, 0, OPTAB_WIDEN);
  34898. +
  34899. + emit_move_insn (result, length);
  34900. +
  34901. + return true;
  34902. +}
  34903. +
  34904. +/* ------------------------------------------------------------------------ */
  34905. +
  34906. +/* PART 6: Auxiliary function for expand load_multiple/store_multiple
  34907. + pattern. */
  34908. +
  34909. +/* Functions to expand load_multiple and store_multiple.
  34910. + They are auxiliary extern functions to help create rtx template.
  34911. + Check nds32-multiple.md file for the patterns. */
  34912. +rtx
  34913. +nds32_expand_load_multiple (int base_regno, int count,
  34914. + rtx base_addr, rtx basemem,
  34915. + bool update_base_reg_p,
  34916. + rtx *update_base_reg)
  34917. +{
  34918. + int par_index;
  34919. + int offset;
  34920. + int start_idx;
  34921. + rtx result;
  34922. + rtx new_addr, mem, reg;
  34923. +
  34924. + /* Generate a unaligned load to prevent load instruction pull out from
  34925. + parallel, and then it will generate lwi, and lose unaligned acces */
  34926. + if (count == 1)
  34927. + {
  34928. + reg = gen_rtx_REG (SImode, base_regno);
  34929. + if (update_base_reg_p)
  34930. + {
  34931. + *update_base_reg = gen_reg_rtx (SImode);
  34932. + return gen_unaligned_load_update_base_w (*update_base_reg, reg, base_addr);
  34933. + }
  34934. + else
  34935. + return gen_unaligned_load_w (reg, gen_rtx_MEM (SImode, base_addr));
  34936. + }
  34937. +
  34938. + /* Create the pattern that is presented in nds32-multiple.md. */
  34939. + if (update_base_reg_p)
  34940. + {
  34941. + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
  34942. + start_idx = 1;
  34943. + }
  34944. + else
  34945. + {
  34946. + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  34947. + start_idx = 0;
  34948. + }
  34949. +
  34950. + if (update_base_reg_p)
  34951. + {
  34952. + offset = count * 4;
  34953. + new_addr = plus_constant (Pmode, base_addr, offset);
  34954. + *update_base_reg = gen_reg_rtx (SImode);
  34955. +
  34956. + XVECEXP (result, 0, 0) = gen_rtx_SET (VOIDmode,
  34957. + *update_base_reg, new_addr);
  34958. + }
  34959. +
  34960. + for (par_index = 0; par_index < count; par_index++)
  34961. + {
  34962. + offset = par_index * 4;
  34963. + /* 4-byte for loading data to each register. */
  34964. + new_addr = plus_constant (Pmode, base_addr, offset);
  34965. + mem = adjust_automodify_address_nv (basemem, SImode,
  34966. + new_addr, offset);
  34967. + reg = gen_rtx_REG (SImode, base_regno + par_index);
  34968. +
  34969. + XVECEXP (result, 0, (par_index + start_idx)) = gen_rtx_SET (VOIDmode, reg, mem);
  34970. + }
  34971. +
  34972. + return result;
  34973. +}
  34974. +
  34975. +rtx
  34976. +nds32_expand_store_multiple (int base_regno, int count,
  34977. + rtx base_addr, rtx basemem,
  34978. + bool update_base_reg_p,
  34979. + rtx *update_base_reg)
  34980. +{
  34981. + int par_index;
  34982. + int offset;
  34983. + int start_idx;
  34984. + rtx result;
  34985. + rtx new_addr, mem, reg;
  34986. +
  34987. + if (count == 1)
  34988. + {
  34989. + reg = gen_rtx_REG (SImode, base_regno);
  34990. + if (update_base_reg_p)
  34991. + {
  34992. + *update_base_reg = gen_reg_rtx (SImode);
  34993. + return gen_unaligned_store_update_base_w (*update_base_reg, base_addr, reg);
  34994. + }
  34995. + else
  34996. + return gen_unaligned_store_w (gen_rtx_MEM (SImode, base_addr), reg);
  34997. + }
  34998. +
  34999. + /* Create the pattern that is presented in nds32-multiple.md. */
  35000. +
  35001. + if (update_base_reg_p)
  35002. + {
  35003. + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
  35004. + start_idx = 1;
  35005. + }
  35006. + else
  35007. + {
  35008. + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  35009. + start_idx = 0;
  35010. + }
  35011. +
  35012. + if (update_base_reg_p)
  35013. + {
  35014. + offset = count * 4;
  35015. + new_addr = plus_constant (Pmode, base_addr, offset);
  35016. + *update_base_reg = gen_reg_rtx (SImode);
  35017. +
  35018. + XVECEXP (result, 0, 0) = gen_rtx_SET (VOIDmode,
  35019. + *update_base_reg, new_addr);
  35020. + }
  35021. +
  35022. + for (par_index = 0; par_index < count; par_index++)
  35023. + {
  35024. + offset = par_index * 4;
  35025. + /* 4-byte for storing data to memory. */
  35026. + new_addr = plus_constant (Pmode, base_addr, offset);
  35027. + mem = adjust_automodify_address_nv (basemem, SImode,
  35028. + new_addr, offset);
  35029. + reg = gen_rtx_REG (SImode, base_regno + par_index);
  35030. +
  35031. + XVECEXP (result, 0, par_index + start_idx) = gen_rtx_SET (VOIDmode, mem, reg);
  35032. + }
  35033. +
  35034. +
  35035. + return result;
  35036. +}
  35037. +
  35038. +/* ------------------------------------------------------------------------ */
  35039. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-modes.def gcc-4.9.4/gcc/config/nds32/nds32-modes.def
  35040. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-modes.def 2014-01-02 23:23:26.000000000 +0100
  35041. +++ gcc-4.9.4/gcc/config/nds32/nds32-modes.def 2016-08-08 20:37:45.506270091 +0200
  35042. @@ -1,5 +1,5 @@
  35043. /* Extra machine modes of Andes NDS32 cpu for GNU compiler
  35044. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  35045. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  35046. Contributed by Andes Technology Corporation.
  35047. This file is part of GCC.
  35048. @@ -18,4 +18,6 @@
  35049. along with GCC; see the file COPYING3. If not see
  35050. <http://www.gnu.org/licenses/>. */
  35051. -/* So far, there is no need to define any modes for nds32 target. */
  35052. +/* Vector modes. */
  35053. +VECTOR_MODES (INT, 4); /* V4QI V2HI */
  35054. +VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
  35055. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-multiple.md gcc-4.9.4/gcc/config/nds32/nds32-multiple.md
  35056. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-multiple.md 2014-01-02 23:23:26.000000000 +0100
  35057. +++ gcc-4.9.4/gcc/config/nds32/nds32-multiple.md 2016-08-08 20:37:45.510270246 +0200
  35058. @@ -1,5 +1,5 @@
  35059. ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler
  35060. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  35061. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  35062. ;; Contributed by Andes Technology Corporation.for NDS32.
  35063. ;;
  35064. ;; This file is part of GCC.
  35065. @@ -49,17 +49,19 @@
  35066. otherwise we have to FAIL this rtx generation:
  35067. 1. The number of consecutive registers must be integer.
  35068. 2. Maximum 4 or 8 registers for lmw.bi instruction
  35069. - (based on this nds32-multiple.md design).
  35070. + (based on this nds32-multiple.md design).
  35071. 3. Minimum 2 registers for lmw.bi instruction
  35072. - (based on this nds32-multiple.md design).
  35073. + (based on this nds32-multiple.md design).
  35074. 4. operands[0] must be register for sure.
  35075. 5. operands[1] must be memory for sure.
  35076. - 6. Do not cross $r15 register because it is not allocatable. */
  35077. + 6. operands[1] is not volatile memory access.
  35078. + 7. Do not cross $r15 register because it is not allocatable. */
  35079. if (GET_CODE (operands[2]) != CONST_INT
  35080. || INTVAL (operands[2]) > maximum
  35081. || INTVAL (operands[2]) < 2
  35082. || GET_CODE (operands[0]) != REG
  35083. || GET_CODE (operands[1]) != MEM
  35084. + || MEM_VOLATILE_P (operands[1])
  35085. || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
  35086. FAIL;
  35087. @@ -69,11 +71,294 @@
  35088. INTVAL (operands[2]),
  35089. force_reg (SImode,
  35090. XEXP (operands[1], 0)),
  35091. - operands[1]);
  35092. + operands[1],
  35093. + false, NULL);
  35094. })
  35095. ;; Ordinary Load Multiple.
  35096. +(define_insn "*lmw_bim_si10"
  35097. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35098. + [(set (match_operand:SI 1 "register_operand" "=r")
  35099. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40)))
  35100. + (set (match_operand:SI 3 "register_operand" "")
  35101. + (mem:SI (match_dup 2)))
  35102. + (set (match_operand:SI 4 "register_operand" "")
  35103. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35104. + (set (match_operand:SI 5 "register_operand" "")
  35105. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35106. + (set (match_operand:SI 6 "register_operand" "")
  35107. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35108. + (set (match_operand:SI 7 "register_operand" "")
  35109. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))
  35110. + (set (match_operand:SI 8 "register_operand" "")
  35111. + (mem:SI (plus:SI (match_dup 2) (const_int 20))))
  35112. + (set (match_operand:SI 9 "register_operand" "")
  35113. + (mem:SI (plus:SI (match_dup 2) (const_int 24))))
  35114. + (set (match_operand:SI 10 "register_operand" "")
  35115. + (mem:SI (plus:SI (match_dup 2) (const_int 28))))
  35116. + (set (match_operand:SI 11 "register_operand" "")
  35117. + (mem:SI (plus:SI (match_dup 2) (const_int 32))))
  35118. + (set (match_operand:SI 12 "register_operand" "")
  35119. + (mem:SI (plus:SI (match_dup 2) (const_int 36))))])]
  35120. + "(XVECLEN (operands[0], 0) == 11)"
  35121. + "lmw.bim\t%3, [%1], %12, 0x0"
  35122. + [(set_attr "type" "load_multiple")
  35123. + (set_attr "combo" "10")
  35124. + (set_attr "length" "4")]
  35125. +)
  35126. +
  35127. +(define_insn "*lmw_bim_si9"
  35128. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35129. + [(set (match_operand:SI 1 "register_operand" "=r")
  35130. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36)))
  35131. + (set (match_operand:SI 3 "register_operand" "")
  35132. + (mem:SI (match_dup 2)))
  35133. + (set (match_operand:SI 4 "register_operand" "")
  35134. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35135. + (set (match_operand:SI 5 "register_operand" "")
  35136. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35137. + (set (match_operand:SI 6 "register_operand" "")
  35138. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35139. + (set (match_operand:SI 7 "register_operand" "")
  35140. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))
  35141. + (set (match_operand:SI 8 "register_operand" "")
  35142. + (mem:SI (plus:SI (match_dup 2) (const_int 20))))
  35143. + (set (match_operand:SI 9 "register_operand" "")
  35144. + (mem:SI (plus:SI (match_dup 2) (const_int 24))))
  35145. + (set (match_operand:SI 10 "register_operand" "")
  35146. + (mem:SI (plus:SI (match_dup 2) (const_int 28))))
  35147. + (set (match_operand:SI 11 "register_operand" "")
  35148. + (mem:SI (plus:SI (match_dup 2) (const_int 32))))])]
  35149. + "(XVECLEN (operands[0], 0) == 10)"
  35150. + "lmw.bim\t%3, [%1], %11, 0x0"
  35151. + [(set_attr "type" "load_multiple")
  35152. + (set_attr "combo" "9")
  35153. + (set_attr "length" "4")]
  35154. +)
  35155. +
  35156. +(define_insn "*lmw_bim_si8"
  35157. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35158. + [(set (match_operand:SI 1 "register_operand" "=r")
  35159. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32)))
  35160. + (set (match_operand:SI 3 "register_operand" "")
  35161. + (mem:SI (match_dup 2)))
  35162. + (set (match_operand:SI 4 "register_operand" "")
  35163. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35164. + (set (match_operand:SI 5 "register_operand" "")
  35165. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35166. + (set (match_operand:SI 6 "register_operand" "")
  35167. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35168. + (set (match_operand:SI 7 "register_operand" "")
  35169. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))
  35170. + (set (match_operand:SI 8 "register_operand" "")
  35171. + (mem:SI (plus:SI (match_dup 2) (const_int 20))))
  35172. + (set (match_operand:SI 9 "register_operand" "")
  35173. + (mem:SI (plus:SI (match_dup 2) (const_int 24))))
  35174. + (set (match_operand:SI 10 "register_operand" "")
  35175. + (mem:SI (plus:SI (match_dup 2) (const_int 28))))])]
  35176. + "(XVECLEN (operands[0], 0) == 9)"
  35177. + "lmw.bim\t%3, [%1], %10, 0x0"
  35178. + [(set_attr "type" "load_multiple")
  35179. + (set_attr "combo" "8")
  35180. + (set_attr "length" "4")]
  35181. +)
  35182. +
  35183. +(define_insn "*lmw_bim_si7"
  35184. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35185. + [(set (match_operand:SI 1 "register_operand" "=r")
  35186. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28)))
  35187. + (set (match_operand:SI 3 "register_operand" "")
  35188. + (mem:SI (match_dup 2)))
  35189. + (set (match_operand:SI 4 "register_operand" "")
  35190. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35191. + (set (match_operand:SI 5 "register_operand" "")
  35192. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35193. + (set (match_operand:SI 6 "register_operand" "")
  35194. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35195. + (set (match_operand:SI 7 "register_operand" "")
  35196. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))
  35197. + (set (match_operand:SI 8 "register_operand" "")
  35198. + (mem:SI (plus:SI (match_dup 2) (const_int 20))))
  35199. + (set (match_operand:SI 9 "register_operand" "")
  35200. + (mem:SI (plus:SI (match_dup 2) (const_int 24))))])]
  35201. + "(XVECLEN (operands[0], 0) == 8)"
  35202. + "lmw.bim\t%3, [%1], %9, 0x0"
  35203. + [(set_attr "type" "load_multiple")
  35204. + (set_attr "combo" "7")
  35205. + (set_attr "length" "4")]
  35206. +)
  35207. +
  35208. +(define_insn "*lmw_bim_si6"
  35209. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35210. + [(set (match_operand:SI 1 "register_operand" "=r")
  35211. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24)))
  35212. + (set (match_operand:SI 3 "register_operand" "")
  35213. + (mem:SI (match_dup 2)))
  35214. + (set (match_operand:SI 4 "register_operand" "")
  35215. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35216. + (set (match_operand:SI 5 "register_operand" "")
  35217. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35218. + (set (match_operand:SI 6 "register_operand" "")
  35219. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35220. + (set (match_operand:SI 7 "register_operand" "")
  35221. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))
  35222. + (set (match_operand:SI 8 "register_operand" "")
  35223. + (mem:SI (plus:SI (match_dup 2) (const_int 20))))])]
  35224. + "(XVECLEN (operands[0], 0) == 7)"
  35225. + "lmw.bim\t%3, [%1], %8, 0x0"
  35226. + [(set_attr "type" "load_multiple")
  35227. + (set_attr "combo" "6")
  35228. + (set_attr "length" "4")]
  35229. +)
  35230. +
  35231. +(define_insn "*lmw_bim_si5"
  35232. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35233. + [(set (match_operand:SI 1 "register_operand" "=r")
  35234. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20)))
  35235. + (set (match_operand:SI 3 "register_operand" "")
  35236. + (mem:SI (match_dup 2)))
  35237. + (set (match_operand:SI 4 "register_operand" "")
  35238. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35239. + (set (match_operand:SI 5 "register_operand" "")
  35240. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35241. + (set (match_operand:SI 6 "register_operand" "")
  35242. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))
  35243. + (set (match_operand:SI 7 "register_operand" "")
  35244. + (mem:SI (plus:SI (match_dup 2) (const_int 16))))])]
  35245. + "(XVECLEN (operands[0], 0) == 6)"
  35246. + "lmw.bim\t%3, [%1], %7, 0x0"
  35247. + [(set_attr "type" "load_multiple")
  35248. + (set_attr "combo" "5")
  35249. + (set_attr "length" "4")]
  35250. +)
  35251. +
  35252. +(define_insn "*lmw_bim_si4"
  35253. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35254. + [(set (match_operand:SI 1 "register_operand" "=r")
  35255. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16)))
  35256. + (set (match_operand:SI 3 "register_operand" "")
  35257. + (mem:SI (match_dup 2)))
  35258. + (set (match_operand:SI 4 "register_operand" "")
  35259. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35260. + (set (match_operand:SI 5 "register_operand" "")
  35261. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))
  35262. + (set (match_operand:SI 6 "register_operand" "")
  35263. + (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
  35264. + "(XVECLEN (operands[0], 0) == 5)"
  35265. + "lmw.bim\t%3, [%1], %6, 0x0"
  35266. + [(set_attr "type" "load_multiple")
  35267. + (set_attr "combo" "4")
  35268. + (set_attr "length" "4")]
  35269. +)
  35270. +
  35271. +(define_insn "*lmw_bim_si3"
  35272. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35273. + [(set (match_operand:SI 1 "register_operand" "=r")
  35274. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12)))
  35275. + (set (match_operand:SI 3 "register_operand" "")
  35276. + (mem:SI (match_dup 2)))
  35277. + (set (match_operand:SI 4 "register_operand" "")
  35278. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))
  35279. + (set (match_operand:SI 5 "register_operand" "")
  35280. + (mem:SI (plus:SI (match_dup 2) (const_int 8))))])]
  35281. + "(XVECLEN (operands[0], 0) == 4)"
  35282. + "lmw.bim\t%3, [%1], %5, 0x0"
  35283. + [(set_attr "type" "load_multiple")
  35284. + (set_attr "combo" "3")
  35285. + (set_attr "length" "4")]
  35286. +)
  35287. +
  35288. +(define_insn "*lmw_bim_si2"
  35289. + [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
  35290. + [(set (match_operand:SI 1 "register_operand" "=r")
  35291. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8)))
  35292. + (set (match_operand:SI 3 "register_operand" "")
  35293. + (mem:SI (match_dup 2)))
  35294. + (set (match_operand:SI 4 "register_operand" "")
  35295. + (mem:SI (plus:SI (match_dup 2) (const_int 4))))])]
  35296. + "(XVECLEN (operands[0], 0) == 3)"
  35297. + "lmw.bim\t%3, [%1], %4, 0x0"
  35298. + [(set_attr "type" "load_multiple")
  35299. + (set_attr "combo" "2")
  35300. + (set_attr "length" "4")]
  35301. +)
  35302. +
  35303. +(define_expand "unaligned_load_update_base_w"
  35304. + [(parallel [(set (match_operand:SI 0 "register_operand" "")
  35305. + (plus:SI (match_operand:SI 2 "register_operand" "") (const_int 4)))
  35306. + (set (match_operand:SI 1 "register_operand" "")
  35307. + (unspec:SI [(mem:SI (match_dup 2))] UNSPEC_UALOAD_W))])]
  35308. + ""
  35309. +{
  35310. + /* DO NOT emit unaligned_load_w_m immediately since web pass don't
  35311. + recognize post_inc, try it again after GCC 5.0.
  35312. + REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */
  35313. + emit_insn (gen_unaligned_load_w (operands[1], gen_rtx_MEM (SImode, operands[2])));
  35314. + emit_insn (gen_addsi3 (operands[0], operands[2], gen_int_mode (4, Pmode)));
  35315. + DONE;
  35316. +}
  35317. + [(set_attr "type" "load_multiple")
  35318. + (set_attr "combo" "1")
  35319. + (set_attr "length" "4")]
  35320. +)
  35321. +
  35322. +(define_insn "*lmwsi10"
  35323. + [(match_parallel 0 "nds32_load_multiple_operation"
  35324. + [(set (match_operand:SI 2 "register_operand" "")
  35325. + (mem:SI (match_operand:SI 1 "register_operand" "r")))
  35326. + (set (match_operand:SI 3 "register_operand" "")
  35327. + (mem:SI (plus:SI (match_dup 1) (const_int 4))))
  35328. + (set (match_operand:SI 4 "register_operand" "")
  35329. + (mem:SI (plus:SI (match_dup 1) (const_int 8))))
  35330. + (set (match_operand:SI 5 "register_operand" "")
  35331. + (mem:SI (plus:SI (match_dup 1) (const_int 12))))
  35332. + (set (match_operand:SI 6 "register_operand" "")
  35333. + (mem:SI (plus:SI (match_dup 1) (const_int 16))))
  35334. + (set (match_operand:SI 7 "register_operand" "")
  35335. + (mem:SI (plus:SI (match_dup 1) (const_int 20))))
  35336. + (set (match_operand:SI 8 "register_operand" "")
  35337. + (mem:SI (plus:SI (match_dup 1) (const_int 24))))
  35338. + (set (match_operand:SI 9 "register_operand" "")
  35339. + (mem:SI (plus:SI (match_dup 1) (const_int 28))))
  35340. + (set (match_operand:SI 10 "register_operand" "")
  35341. + (mem:SI (plus:SI (match_dup 1) (const_int 32))))
  35342. + (set (match_operand:SI 11 "register_operand" "")
  35343. + (mem:SI (plus:SI (match_dup 1) (const_int 36))))])]
  35344. + "(XVECLEN (operands[0], 0) == 10)"
  35345. + "lmw.bi\t%2, [%1], %11, 0x0"
  35346. + [(set_attr "type" "load_multiple")
  35347. + (set_attr "combo" "10")
  35348. + (set_attr "length" "4")]
  35349. +)
  35350. +
  35351. +(define_insn "*lmwsi9"
  35352. + [(match_parallel 0 "nds32_load_multiple_operation"
  35353. + [(set (match_operand:SI 2 "register_operand" "")
  35354. + (mem:SI (match_operand:SI 1 "register_operand" "r")))
  35355. + (set (match_operand:SI 3 "register_operand" "")
  35356. + (mem:SI (plus:SI (match_dup 1) (const_int 4))))
  35357. + (set (match_operand:SI 4 "register_operand" "")
  35358. + (mem:SI (plus:SI (match_dup 1) (const_int 8))))
  35359. + (set (match_operand:SI 5 "register_operand" "")
  35360. + (mem:SI (plus:SI (match_dup 1) (const_int 12))))
  35361. + (set (match_operand:SI 6 "register_operand" "")
  35362. + (mem:SI (plus:SI (match_dup 1) (const_int 16))))
  35363. + (set (match_operand:SI 7 "register_operand" "")
  35364. + (mem:SI (plus:SI (match_dup 1) (const_int 20))))
  35365. + (set (match_operand:SI 8 "register_operand" "")
  35366. + (mem:SI (plus:SI (match_dup 1) (const_int 24))))
  35367. + (set (match_operand:SI 9 "register_operand" "")
  35368. + (mem:SI (plus:SI (match_dup 1) (const_int 28))))
  35369. + (set (match_operand:SI 10 "register_operand" "")
  35370. + (mem:SI (plus:SI (match_dup 1) (const_int 32))))])]
  35371. + "(XVECLEN (operands[0], 0) == 9)"
  35372. + "lmw.bi\t%2, [%1], %10, 0x0"
  35373. + [(set_attr "type" "load_multiple")
  35374. + (set_attr "combo" "9")
  35375. + (set_attr "length" "4")]
  35376. +)
  35377. +
  35378. (define_insn "*lmwsi8"
  35379. [(match_parallel 0 "nds32_load_multiple_operation"
  35380. [(set (match_operand:SI 2 "register_operand" "")
  35381. @@ -94,8 +379,9 @@
  35382. (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
  35383. "(XVECLEN (operands[0], 0) == 8)"
  35384. "lmw.bi\t%2, [%1], %9, 0x0"
  35385. - [(set_attr "type" "load")
  35386. - (set_attr "length" "4")]
  35387. + [(set_attr "type" "load_multiple")
  35388. + (set_attr "combo" "8")
  35389. + (set_attr "length" "4")]
  35390. )
  35391. (define_insn "*lmwsi7"
  35392. @@ -116,8 +402,9 @@
  35393. (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
  35394. "(XVECLEN (operands[0], 0) == 7)"
  35395. "lmw.bi\t%2, [%1], %8, 0x0"
  35396. - [(set_attr "type" "load")
  35397. - (set_attr "length" "4")]
  35398. + [(set_attr "type" "load_multiple")
  35399. + (set_attr "combo" "7")
  35400. + (set_attr "length" "4")]
  35401. )
  35402. (define_insn "*lmwsi6"
  35403. @@ -136,8 +423,9 @@
  35404. (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
  35405. "(XVECLEN (operands[0], 0) == 6)"
  35406. "lmw.bi\t%2, [%1], %7, 0x0"
  35407. - [(set_attr "type" "load")
  35408. - (set_attr "length" "4")]
  35409. + [(set_attr "type" "load_multiple")
  35410. + (set_attr "combo" "6")
  35411. + (set_attr "length" "4")]
  35412. )
  35413. (define_insn "*lmwsi5"
  35414. @@ -154,8 +442,9 @@
  35415. (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
  35416. "(XVECLEN (operands[0], 0) == 5)"
  35417. "lmw.bi\t%2, [%1], %6, 0x0"
  35418. - [(set_attr "type" "load")
  35419. - (set_attr "length" "4")]
  35420. + [(set_attr "type" "load_multiple")
  35421. + (set_attr "combo" "5")
  35422. + (set_attr "length" "4")]
  35423. )
  35424. (define_insn "*lmwsi4"
  35425. @@ -170,8 +459,9 @@
  35426. (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
  35427. "(XVECLEN (operands[0], 0) == 4)"
  35428. "lmw.bi\t%2, [%1], %5, 0x0"
  35429. - [(set_attr "type" "load")
  35430. - (set_attr "length" "4")]
  35431. + [(set_attr "type" "load_multiple")
  35432. + (set_attr "combo" "4")
  35433. + (set_attr "length" "4")]
  35434. )
  35435. (define_insn "*lmwsi3"
  35436. @@ -184,8 +474,9 @@
  35437. (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
  35438. "(XVECLEN (operands[0], 0) == 3)"
  35439. "lmw.bi\t%2, [%1], %4, 0x0"
  35440. - [(set_attr "type" "load")
  35441. - (set_attr "length" "4")]
  35442. + [(set_attr "type" "load_multiple")
  35443. + (set_attr "combo" "3")
  35444. + (set_attr "length" "4")]
  35445. )
  35446. (define_insn "*lmwsi2"
  35447. @@ -196,15 +487,15 @@
  35448. (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
  35449. "(XVECLEN (operands[0], 0) == 2)"
  35450. "lmw.bi\t%2, [%1], %3, 0x0"
  35451. - [(set_attr "type" "load")
  35452. - (set_attr "length" "4")]
  35453. + [(set_attr "type" "load_multiple")
  35454. + (set_attr "combo" "2")
  35455. + (set_attr "length" "4")]
  35456. )
  35457. -
  35458. ;; Store Multiple Insns.
  35459. ;;
  35460. ;; operands[0] is the first memory location.
  35461. -;; opernads[1] is the first of the consecutive registers.
  35462. +;; operands[1] is the first of the consecutive registers.
  35463. ;; operands[2] is the number of consecutive registers.
  35464. (define_expand "store_multiple"
  35465. @@ -231,17 +522,19 @@
  35466. otherwise we have to FAIL this rtx generation:
  35467. 1. The number of consecutive registers must be integer.
  35468. 2. Maximum 4 or 8 registers for smw.bi instruction
  35469. - (based on this nds32-multiple.md design).
  35470. + (based on this nds32-multiple.md design).
  35471. 3. Minimum 2 registers for smw.bi instruction
  35472. - (based on this nds32-multiple.md design).
  35473. + (based on this nds32-multiple.md design).
  35474. 4. operands[0] must be memory for sure.
  35475. 5. operands[1] must be register for sure.
  35476. - 6. Do not cross $r15 register because it is not allocatable. */
  35477. + 6. operands[0] is not volatile memory access.
  35478. + 7. Do not cross $r15 register because it is not allocatable. */
  35479. if (GET_CODE (operands[2]) != CONST_INT
  35480. || INTVAL (operands[2]) > maximum
  35481. || INTVAL (operands[2]) < 2
  35482. || GET_CODE (operands[0]) != MEM
  35483. || GET_CODE (operands[1]) != REG
  35484. + || MEM_VOLATILE_P (operands[0])
  35485. || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
  35486. FAIL;
  35487. @@ -251,11 +544,295 @@
  35488. INTVAL (operands[2]),
  35489. force_reg (SImode,
  35490. XEXP (operands[0], 0)),
  35491. - operands[0]);
  35492. + operands[0],
  35493. + false, NULL);
  35494. })
  35495. ;; Ordinary Store Multiple.
  35496. +(define_insn "*stm_bim_si10"
  35497. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35498. + [(set (match_operand:SI 1 "register_operand" "=r")
  35499. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40)))
  35500. + (set (mem:SI (match_dup 2))
  35501. + (match_operand:SI 3 "register_operand" ""))
  35502. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35503. + (match_operand:SI 4 "register_operand" ""))
  35504. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35505. + (match_operand:SI 5 "register_operand" ""))
  35506. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35507. + (match_operand:SI 6 "register_operand" ""))
  35508. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35509. + (match_operand:SI 7 "register_operand" ""))
  35510. + (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
  35511. + (match_operand:SI 8 "register_operand" ""))
  35512. + (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
  35513. + (match_operand:SI 9 "register_operand" ""))
  35514. + (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
  35515. + (match_operand:SI 10 "register_operand" ""))
  35516. + (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
  35517. + (match_operand:SI 11 "register_operand" ""))
  35518. + (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
  35519. + (match_operand:SI 12 "register_operand" ""))])]
  35520. + "(XVECLEN (operands[0], 0) == 11)"
  35521. + "smw.bim\t%3, [%1], %12, 0x0"
  35522. + [(set_attr "type" "store_multiple")
  35523. + (set_attr "combo" "10")
  35524. + (set_attr "length" "4")]
  35525. +)
  35526. +
  35527. +(define_insn "*stm_bim_si9"
  35528. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35529. + [(set (match_operand:SI 1 "register_operand" "=r")
  35530. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36)))
  35531. + (set (mem:SI (match_dup 2))
  35532. + (match_operand:SI 3 "register_operand" ""))
  35533. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35534. + (match_operand:SI 4 "register_operand" ""))
  35535. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35536. + (match_operand:SI 5 "register_operand" ""))
  35537. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35538. + (match_operand:SI 6 "register_operand" ""))
  35539. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35540. + (match_operand:SI 7 "register_operand" ""))
  35541. + (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
  35542. + (match_operand:SI 8 "register_operand" ""))
  35543. + (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
  35544. + (match_operand:SI 9 "register_operand" ""))
  35545. + (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
  35546. + (match_operand:SI 10 "register_operand" ""))
  35547. + (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
  35548. + (match_operand:SI 11 "register_operand" ""))])]
  35549. + "(XVECLEN (operands[0], 0) == 10)"
  35550. + "smw.bim\t%3, [%1], %11, 0x0"
  35551. + [(set_attr "type" "store_multiple")
  35552. + (set_attr "combo" "9")
  35553. + (set_attr "length" "4")]
  35554. +)
  35555. +
  35556. +
  35557. +(define_insn "*stm_bim_si8"
  35558. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35559. + [(set (match_operand:SI 1 "register_operand" "=r")
  35560. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32)))
  35561. + (set (mem:SI (match_dup 2))
  35562. + (match_operand:SI 3 "register_operand" ""))
  35563. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35564. + (match_operand:SI 4 "register_operand" ""))
  35565. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35566. + (match_operand:SI 5 "register_operand" ""))
  35567. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35568. + (match_operand:SI 6 "register_operand" ""))
  35569. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35570. + (match_operand:SI 7 "register_operand" ""))
  35571. + (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
  35572. + (match_operand:SI 8 "register_operand" ""))
  35573. + (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
  35574. + (match_operand:SI 9 "register_operand" ""))
  35575. + (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
  35576. + (match_operand:SI 10 "register_operand" ""))])]
  35577. + "(XVECLEN (operands[0], 0) == 9)"
  35578. + "smw.bim\t%3, [%1], %10, 0x0"
  35579. + [(set_attr "type" "store_multiple")
  35580. + (set_attr "combo" "8")
  35581. + (set_attr "length" "4")]
  35582. +)
  35583. +
  35584. +(define_insn "*stm_bim_si7"
  35585. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35586. + [(set (match_operand:SI 1 "register_operand" "=r")
  35587. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28)))
  35588. + (set (mem:SI (match_dup 2))
  35589. + (match_operand:SI 3 "register_operand" ""))
  35590. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35591. + (match_operand:SI 4 "register_operand" ""))
  35592. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35593. + (match_operand:SI 5 "register_operand" ""))
  35594. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35595. + (match_operand:SI 6 "register_operand" ""))
  35596. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35597. + (match_operand:SI 7 "register_operand" ""))
  35598. + (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
  35599. + (match_operand:SI 8 "register_operand" ""))
  35600. + (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
  35601. + (match_operand:SI 9 "register_operand" ""))])]
  35602. + "(XVECLEN (operands[0], 0) == 8)"
  35603. + "smw.bim\t%3, [%1], %9, 0x0"
  35604. + [(set_attr "type" "store_multiple")
  35605. + (set_attr "combo" "7")
  35606. + (set_attr "length" "4")]
  35607. +)
  35608. +
  35609. +(define_insn "*stm_bim_si6"
  35610. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35611. + [(set (match_operand:SI 1 "register_operand" "=r")
  35612. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24)))
  35613. + (set (mem:SI (match_dup 2))
  35614. + (match_operand:SI 3 "register_operand" ""))
  35615. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35616. + (match_operand:SI 4 "register_operand" ""))
  35617. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35618. + (match_operand:SI 5 "register_operand" ""))
  35619. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35620. + (match_operand:SI 6 "register_operand" ""))
  35621. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35622. + (match_operand:SI 7 "register_operand" ""))
  35623. + (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
  35624. + (match_operand:SI 8 "register_operand" ""))])]
  35625. + "(XVECLEN (operands[0], 0) == 7)"
  35626. + "smw.bim\t%3, [%1], %8, 0x0"
  35627. + [(set_attr "type" "store_multiple")
  35628. + (set_attr "combo" "6")
  35629. + (set_attr "length" "4")]
  35630. +)
  35631. +
  35632. +(define_insn "*stm_bim_si5"
  35633. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35634. + [(set (match_operand:SI 1 "register_operand" "=r")
  35635. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20)))
  35636. + (set (mem:SI (match_dup 2))
  35637. + (match_operand:SI 3 "register_operand" ""))
  35638. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35639. + (match_operand:SI 4 "register_operand" ""))
  35640. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35641. + (match_operand:SI 5 "register_operand" ""))
  35642. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35643. + (match_operand:SI 6 "register_operand" ""))
  35644. + (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
  35645. + (match_operand:SI 7 "register_operand" ""))])]
  35646. + "(XVECLEN (operands[0], 0) == 6)"
  35647. + "smw.bim\t%3, [%1], %7, 0x0"
  35648. + [(set_attr "type" "store_multiple")
  35649. + (set_attr "combo" "5")
  35650. + (set_attr "length" "4")]
  35651. +)
  35652. +
  35653. +(define_insn "*stm_bim_si4"
  35654. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35655. + [(set (match_operand:SI 1 "register_operand" "=r")
  35656. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16)))
  35657. + (set (mem:SI (match_dup 2))
  35658. + (match_operand:SI 3 "register_operand" ""))
  35659. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35660. + (match_operand:SI 4 "register_operand" ""))
  35661. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35662. + (match_operand:SI 5 "register_operand" ""))
  35663. + (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
  35664. + (match_operand:SI 6 "register_operand" ""))])]
  35665. + "(XVECLEN (operands[0], 0) == 5)"
  35666. + "smw.bim\t%3, [%1], %6, 0x0"
  35667. + [(set_attr "type" "store_multiple")
  35668. + (set_attr "combo" "4")
  35669. + (set_attr "length" "4")]
  35670. +)
  35671. +
  35672. +(define_insn "*stm_bim_si3"
  35673. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35674. + [(set (match_operand:SI 1 "register_operand" "=r")
  35675. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12)))
  35676. + (set (mem:SI (match_dup 2))
  35677. + (match_operand:SI 3 "register_operand" ""))
  35678. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35679. + (match_operand:SI 4 "register_operand" ""))
  35680. + (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
  35681. + (match_operand:SI 5 "register_operand" ""))])]
  35682. + "(XVECLEN (operands[0], 0) == 4)"
  35683. + "smw.bim\t%3, [%1], %5, 0x0"
  35684. + [(set_attr "type" "store_multiple")
  35685. + (set_attr "combo" "3")
  35686. + (set_attr "length" "4")]
  35687. +)
  35688. +
  35689. +(define_insn "*stm_bim_si2"
  35690. + [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
  35691. + [(set (match_operand:SI 1 "register_operand" "=r")
  35692. + (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8)))
  35693. + (set (mem:SI (match_dup 2))
  35694. + (match_operand:SI 3 "register_operand" ""))
  35695. + (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
  35696. + (match_operand:SI 4 "register_operand" ""))])]
  35697. + "(XVECLEN (operands[0], 0) == 3)"
  35698. + "smw.bim\t%3, [%1], %4, 0x0"
  35699. + [(set_attr "type" "store_multiple")
  35700. + (set_attr "combo" "2")
  35701. + (set_attr "length" "4")]
  35702. +)
  35703. +
  35704. +(define_expand "unaligned_store_update_base_w"
  35705. + [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
  35706. + (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 4)))
  35707. + (set (mem:SI (match_dup 1))
  35708. + (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_UASTORE_W))])]
  35709. + ""
  35710. +{
  35711. + /* DO NOT emit unaligned_store_w_m immediately since web pass don't
  35712. + recognize post_inc, try it again after GCC 5.0.
  35713. + REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */
  35714. + emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[1]), operands[2]));
  35715. + emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (4, Pmode)));
  35716. + DONE;
  35717. +}
  35718. + [(set_attr "type" "store_multiple")
  35719. + (set_attr "combo" "1")
  35720. + (set_attr "length" "4")]
  35721. +)
  35722. +
  35723. +(define_insn "*stmsi10"
  35724. + [(match_parallel 0 "nds32_store_multiple_operation"
  35725. + [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
  35726. + (match_operand:SI 2 "register_operand" ""))
  35727. + (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
  35728. + (match_operand:SI 3 "register_operand" ""))
  35729. + (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
  35730. + (match_operand:SI 4 "register_operand" ""))
  35731. + (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
  35732. + (match_operand:SI 5 "register_operand" ""))
  35733. + (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
  35734. + (match_operand:SI 6 "register_operand" ""))
  35735. + (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
  35736. + (match_operand:SI 7 "register_operand" ""))
  35737. + (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
  35738. + (match_operand:SI 8 "register_operand" ""))
  35739. + (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
  35740. + (match_operand:SI 9 "register_operand" ""))
  35741. + (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
  35742. + (match_operand:SI 10 "register_operand" ""))
  35743. + (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
  35744. + (match_operand:SI 11 "register_operand" ""))])]
  35745. + "(XVECLEN (operands[0], 0) == 10)"
  35746. + "smw.bi\t%2, [%1], %11, 0x0"
  35747. + [(set_attr "type" "store_multiple")
  35748. + (set_attr "combo" "10")
  35749. + (set_attr "length" "4")]
  35750. +)
  35751. +
  35752. +(define_insn "*stmsi9"
  35753. + [(match_parallel 0 "nds32_store_multiple_operation"
  35754. + [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
  35755. + (match_operand:SI 2 "register_operand" ""))
  35756. + (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
  35757. + (match_operand:SI 3 "register_operand" ""))
  35758. + (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
  35759. + (match_operand:SI 4 "register_operand" ""))
  35760. + (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
  35761. + (match_operand:SI 5 "register_operand" ""))
  35762. + (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
  35763. + (match_operand:SI 6 "register_operand" ""))
  35764. + (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
  35765. + (match_operand:SI 7 "register_operand" ""))
  35766. + (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
  35767. + (match_operand:SI 8 "register_operand" ""))
  35768. + (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
  35769. + (match_operand:SI 9 "register_operand" ""))
  35770. + (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
  35771. + (match_operand:SI 10 "register_operand" ""))])]
  35772. + "(XVECLEN (operands[0], 0) == 9)"
  35773. + "smw.bi\t%2, [%1], %10, 0x0"
  35774. + [(set_attr "type" "store_multiple")
  35775. + (set_attr "combo" "9")
  35776. + (set_attr "length" "4")]
  35777. +)
  35778. +
  35779. (define_insn "*stmsi8"
  35780. [(match_parallel 0 "nds32_store_multiple_operation"
  35781. [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
  35782. @@ -276,8 +853,9 @@
  35783. (match_operand:SI 9 "register_operand" ""))])]
  35784. "(XVECLEN (operands[0], 0) == 8)"
  35785. "smw.bi\t%2, [%1], %9, 0x0"
  35786. - [(set_attr "type" "store")
  35787. - (set_attr "length" "4")]
  35788. + [(set_attr "type" "store_multiple")
  35789. + (set_attr "combo" "8")
  35790. + (set_attr "length" "4")]
  35791. )
  35792. (define_insn "*stmsi7"
  35793. @@ -298,8 +876,9 @@
  35794. (match_operand:SI 8 "register_operand" ""))])]
  35795. "(XVECLEN (operands[0], 0) == 7)"
  35796. "smw.bi\t%2, [%1], %8, 0x0"
  35797. - [(set_attr "type" "store")
  35798. - (set_attr "length" "4")]
  35799. + [(set_attr "type" "store_multiple")
  35800. + (set_attr "combo" "7")
  35801. + (set_attr "length" "4")]
  35802. )
  35803. (define_insn "*stmsi6"
  35804. @@ -318,8 +897,9 @@
  35805. (match_operand:SI 7 "register_operand" ""))])]
  35806. "(XVECLEN (operands[0], 0) == 6)"
  35807. "smw.bi\t%2, [%1], %7, 0x0"
  35808. - [(set_attr "type" "store")
  35809. - (set_attr "length" "4")]
  35810. + [(set_attr "type" "store_multiple")
  35811. + (set_attr "combo" "6")
  35812. + (set_attr "length" "4")]
  35813. )
  35814. (define_insn "*stmsi5"
  35815. @@ -336,8 +916,9 @@
  35816. (match_operand:SI 6 "register_operand" ""))])]
  35817. "(XVECLEN (operands[0], 0) == 5)"
  35818. "smw.bi\t%2, [%1], %6, 0x0"
  35819. - [(set_attr "type" "store")
  35820. - (set_attr "length" "4")]
  35821. + [(set_attr "type" "store_multiple")
  35822. + (set_attr "combo" "5")
  35823. + (set_attr "length" "4")]
  35824. )
  35825. (define_insn "*stmsi4"
  35826. @@ -352,8 +933,9 @@
  35827. (match_operand:SI 5 "register_operand" ""))])]
  35828. "(XVECLEN (operands[0], 0) == 4)"
  35829. "smw.bi\t%2, [%1], %5, 0x0"
  35830. - [(set_attr "type" "store")
  35831. - (set_attr "length" "4")]
  35832. + [(set_attr "type" "store_multiple")
  35833. + (set_attr "combo" "4")
  35834. + (set_attr "length" "4")]
  35835. )
  35836. (define_insn "*stmsi3"
  35837. @@ -366,8 +948,9 @@
  35838. (match_operand:SI 4 "register_operand" ""))])]
  35839. "(XVECLEN (operands[0], 0) == 3)"
  35840. "smw.bi\t%2, [%1], %4, 0x0"
  35841. - [(set_attr "type" "store")
  35842. - (set_attr "length" "4")]
  35843. + [(set_attr "type" "store_multiple")
  35844. + (set_attr "combo" "3")
  35845. + (set_attr "length" "4")]
  35846. )
  35847. (define_insn "*stmsi2"
  35848. @@ -378,8 +961,9 @@
  35849. (match_operand:SI 3 "register_operand" ""))])]
  35850. "(XVECLEN (operands[0], 0) == 2)"
  35851. "smw.bi\t%2, [%1], %3, 0x0"
  35852. - [(set_attr "type" "store")
  35853. - (set_attr "length" "4")]
  35854. + [(set_attr "type" "store_multiple")
  35855. + (set_attr "combo" "2")
  35856. + (set_attr "length" "4")]
  35857. )
  35858. ;; Move a block of memory if it is word aligned and MORE than 2 words long.
  35859. @@ -391,14 +975,14 @@
  35860. ;; operands[2] is the number of bytes to move.
  35861. ;; operands[3] is the known shared alignment.
  35862. -(define_expand "movmemqi"
  35863. +(define_expand "movmemsi"
  35864. [(match_operand:BLK 0 "general_operand" "")
  35865. (match_operand:BLK 1 "general_operand" "")
  35866. - (match_operand:SI 2 "const_int_operand" "")
  35867. + (match_operand:SI 2 "nds32_reg_constant_operand" "")
  35868. (match_operand:SI 3 "const_int_operand" "")]
  35869. ""
  35870. {
  35871. - if (nds32_expand_movmemqi (operands[0],
  35872. + if (nds32_expand_movmemsi (operands[0],
  35873. operands[1],
  35874. operands[2],
  35875. operands[3]))
  35876. @@ -408,3 +992,75 @@
  35877. })
  35878. ;; ------------------------------------------------------------------------
  35879. +
  35880. +(define_insn "lmwzb"
  35881. + [(set (match_operand:SI 0 "register_operand" "=r")
  35882. + (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 4)))
  35883. + (set (match_operand:SI 2 "register_operand" "=r")
  35884. + (unspec:SI [(mem:SI (match_dup 1))] UNSPEC_LMWZB))]
  35885. + ""
  35886. + "lmwzb.bm\t%2, [%1], %2, 0x0"
  35887. + [(set_attr "type" "load_multiple")
  35888. + (set_attr "combo" "1")
  35889. + (set_attr "length" "4")]
  35890. +)
  35891. +
  35892. +(define_insn "smwzb"
  35893. + [(set (match_operand:SI 0 "register_operand" "=r")
  35894. + (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 4)))
  35895. + (set (mem:SI (match_dup 1))
  35896. + (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_SMWZB))]
  35897. + ""
  35898. + "smwzb.bm\t%2, [%1], %2, 0x0"
  35899. + [(set_attr "type" "store_multiple")
  35900. + (set_attr "combo" "1")
  35901. + (set_attr "length" "4")]
  35902. +)
  35903. +
  35904. +(define_expand "movstr"
  35905. + [(match_operand:SI 0 "register_operand" "")
  35906. + (match_operand:BLK 1 "memory_operand" "")
  35907. + (match_operand:BLK 2 "memory_operand" "")]
  35908. + "TARGET_EXT_STRING && TARGET_INLINE_STRCPY"
  35909. +{
  35910. + if (nds32_expand_movstr (operands[0],
  35911. + operands[1],
  35912. + operands[2]))
  35913. + DONE;
  35914. +
  35915. + FAIL;
  35916. +})
  35917. +
  35918. +(define_expand "strlensi"
  35919. + [(match_operand:SI 0 "register_operand")
  35920. + (match_operand:BLK 1 "memory_operand")
  35921. + (match_operand:QI 2 "nds32_reg_constant_operand")
  35922. + (match_operand 3 "const_int_operand")]
  35923. + "TARGET_EXT_STRING"
  35924. +{
  35925. + if (nds32_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
  35926. + DONE;
  35927. +
  35928. + FAIL;
  35929. +})
  35930. +
  35931. +(define_expand "setmemsi"
  35932. + [(use (match_operand:BLK 0 "memory_operand"))
  35933. + (use (match_operand:SI 1 "nds32_reg_constant_operand"))
  35934. + (use (match_operand:QI 2 "nonmemory_operand"))
  35935. + (use (match_operand 3 "const_int_operand"))
  35936. + (use (match_operand:SI 4 "const_int_operand"))
  35937. + (use (match_operand:SI 5 "const_int_operand"))]
  35938. + ""
  35939. +{
  35940. + if (nds32_expand_setmem (operands[0], operands[1],
  35941. + operands[2], operands[3],
  35942. + operands[4], operands[5]))
  35943. + DONE;
  35944. +
  35945. + FAIL;
  35946. +})
  35947. +
  35948. +
  35949. +
  35950. +;; ------------------------------------------------------------------------
  35951. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-n13.md gcc-4.9.4/gcc/config/nds32/nds32-n13.md
  35952. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-n13.md 1970-01-01 01:00:00.000000000 +0100
  35953. +++ gcc-4.9.4/gcc/config/nds32/nds32-n13.md 2016-08-08 20:37:45.510270246 +0200
  35954. @@ -0,0 +1,306 @@
  35955. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  35956. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  35957. +;; Contributed by Andes Technology Corporation.
  35958. +;;
  35959. +;; This file is part of GCC.
  35960. +;;
  35961. +;; GCC is free software; you can redistribute it and/or modify it
  35962. +;; under the terms of the GNU General Public License as published
  35963. +;; by the Free Software Foundation; either version 3, or (at your
  35964. +;; option) any later version.
  35965. +;;
  35966. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  35967. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  35968. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  35969. +;; License for more details.
  35970. +;;
  35971. +;; You should have received a copy of the GNU General Public License
  35972. +;; along with GCC; see the file COPYING3. If not see
  35973. +;; <http://www.gnu.org/licenses/>.
  35974. +
  35975. +
  35976. +;; ------------------------------------------------------------------------
  35977. +;; Define N13 pipeline settings.
  35978. +;; ------------------------------------------------------------------------
  35979. +
  35980. +(define_automaton "nds32_n13_machine")
  35981. +
  35982. +(define_cpu_unit "n13_i1" "nds32_n13_machine")
  35983. +(define_cpu_unit "n13_i2" "nds32_n13_machine")
  35984. +(define_cpu_unit "n13_e1" "nds32_n13_machine")
  35985. +(define_cpu_unit "n13_e2" "nds32_n13_machine")
  35986. +(define_cpu_unit "n13_e3" "nds32_n13_machine")
  35987. +(define_cpu_unit "n13_e4" "nds32_n13_machine")
  35988. +
  35989. +(define_insn_reservation "nds_n13_unknown" 1
  35990. + (and (eq_attr "type" "unknown")
  35991. + (eq_attr "pipeline_model" "n13"))
  35992. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  35993. +
  35994. +(define_insn_reservation "nds_n13_misc" 1
  35995. + (and (eq_attr "type" "misc")
  35996. + (eq_attr "pipeline_model" "n13"))
  35997. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  35998. +
  35999. +(define_insn_reservation "nds_n13_mmu" 1
  36000. + (and (eq_attr "type" "mmu")
  36001. + (eq_attr "pipeline_model" "n13"))
  36002. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36003. +
  36004. +(define_insn_reservation "nds_n13_alu" 1
  36005. + (and (eq_attr "type" "alu")
  36006. + (eq_attr "pipeline_model" "n13"))
  36007. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36008. +
  36009. +(define_insn_reservation "nds_n13_alu_shift" 1
  36010. + (and (eq_attr "type" "alu_shift")
  36011. + (eq_attr "pipeline_model" "n13"))
  36012. + "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
  36013. +
  36014. +(define_insn_reservation "nds_n13_pbsad" 1
  36015. + (and (eq_attr "type" "pbsad")
  36016. + (eq_attr "pipeline_model" "n13"))
  36017. + "n13_i1, n13_i2, n13_e1, n13_e2*2, n13_e3, n13_e4")
  36018. +
  36019. +(define_insn_reservation "nds_n13_pbsada" 1
  36020. + (and (eq_attr "type" "pbsada")
  36021. + (eq_attr "pipeline_model" "n13"))
  36022. + "n13_i1, n13_i2, n13_e1, n13_e2*3, n13_e3, n13_e4")
  36023. +
  36024. +(define_insn_reservation "nds_n13_load" 1
  36025. + (and (match_test "nds32_load_single_p (insn)")
  36026. + (eq_attr "pipeline_model" "n13"))
  36027. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36028. +
  36029. +(define_insn_reservation "nds_n13_store" 1
  36030. + (and (match_test "nds32_store_single_p (insn)")
  36031. + (eq_attr "pipeline_model" "n13"))
  36032. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36033. +
  36034. +(define_insn_reservation "nds_n13_load_multiple_1" 1
  36035. + (and (and (eq_attr "type" "load_multiple")
  36036. + (eq_attr "combo" "1"))
  36037. + (eq_attr "pipeline_model" "n13"))
  36038. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36039. +
  36040. +(define_insn_reservation "nds_n13_load_multiple_2" 1
  36041. + (and (ior (and (eq_attr "type" "load_multiple")
  36042. + (eq_attr "combo" "2"))
  36043. + (match_test "nds32_load_double_p (insn)"))
  36044. + (eq_attr "pipeline_model" "n13"))
  36045. + "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
  36046. +
  36047. +(define_insn_reservation "nds_n13_load_multiple_3" 1
  36048. + (and (and (eq_attr "type" "load_multiple")
  36049. + (eq_attr "combo" "3"))
  36050. + (eq_attr "pipeline_model" "n13"))
  36051. + "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36052. +
  36053. +(define_insn_reservation "nds_n13_load_multiple_4" 1
  36054. + (and (and (eq_attr "type" "load_multiple")
  36055. + (eq_attr "combo" "4"))
  36056. + (eq_attr "pipeline_model" "n13"))
  36057. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36058. +
  36059. +(define_insn_reservation "nds_n13_load_multiple_5" 1
  36060. + (and (and (eq_attr "type" "load_multiple")
  36061. + (eq_attr "combo" "5"))
  36062. + (eq_attr "pipeline_model" "n13"))
  36063. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36064. +
  36065. +(define_insn_reservation "nds_n13_load_multiple_6" 1
  36066. + (and (and (eq_attr "type" "load_multiple")
  36067. + (eq_attr "combo" "6"))
  36068. + (eq_attr "pipeline_model" "n13"))
  36069. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36070. +
  36071. +(define_insn_reservation "nds_n13_load_multiple_7" 1
  36072. + (and (and (eq_attr "type" "load_multiple")
  36073. + (eq_attr "combo" "7"))
  36074. + (eq_attr "pipeline_model" "n13"))
  36075. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36076. +
  36077. +(define_insn_reservation "nds_n13_load_multiple_8" 1
  36078. + (and (and (eq_attr "type" "load_multiple")
  36079. + (eq_attr "combo" "8"))
  36080. + (eq_attr "pipeline_model" "n13"))
  36081. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36082. +
  36083. +(define_insn_reservation "nds_n13_load_multiple_12" 1
  36084. + (and (and (eq_attr "type" "load_multiple")
  36085. + (eq_attr "combo" "12"))
  36086. + (eq_attr "pipeline_model" "n13"))
  36087. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36088. +
  36089. +(define_insn_reservation "nds_n13_store_multiple_1" 1
  36090. + (and (and (eq_attr "type" "store_multiple")
  36091. + (eq_attr "combo" "1"))
  36092. + (eq_attr "pipeline_model" "n13"))
  36093. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36094. +
  36095. +(define_insn_reservation "nds_n13_store_multiple_2" 1
  36096. + (and (ior (and (eq_attr "type" "store_multiple")
  36097. + (eq_attr "combo" "2"))
  36098. + (match_test "nds32_store_double_p (insn)"))
  36099. + (eq_attr "pipeline_model" "n13"))
  36100. + "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
  36101. +
  36102. +(define_insn_reservation "nds_n13_store_multiple_3" 1
  36103. + (and (and (eq_attr "type" "store_multiple")
  36104. + (eq_attr "combo" "3"))
  36105. + (eq_attr "pipeline_model" "n13"))
  36106. + "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36107. +
  36108. +(define_insn_reservation "nds_n13_store_multiple_4" 1
  36109. + (and (and (eq_attr "type" "store_multiple")
  36110. + (eq_attr "combo" "4"))
  36111. + (eq_attr "pipeline_model" "n13"))
  36112. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36113. +
  36114. +(define_insn_reservation "nds_n13_store_multiple_5" 1
  36115. + (and (and (eq_attr "type" "store_multiple")
  36116. + (eq_attr "combo" "5"))
  36117. + (eq_attr "pipeline_model" "n13"))
  36118. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36119. +
  36120. +(define_insn_reservation "nds_n13_store_multiple_6" 1
  36121. + (and (and (eq_attr "type" "store_multiple")
  36122. + (eq_attr "combo" "6"))
  36123. + (eq_attr "pipeline_model" "n13"))
  36124. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36125. +
  36126. +(define_insn_reservation "nds_n13_store_multiple_7" 1
  36127. + (and (and (eq_attr "type" "store_multiple")
  36128. + (eq_attr "combo" "7"))
  36129. + (eq_attr "pipeline_model" "n13"))
  36130. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36131. +
  36132. +(define_insn_reservation "nds_n13_store_multiple_8" 1
  36133. + (and (and (eq_attr "type" "store_multiple")
  36134. + (eq_attr "combo" "8"))
  36135. + (eq_attr "pipeline_model" "n13"))
  36136. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36137. +
  36138. +(define_insn_reservation "nds_n13_store_multiple_12" 1
  36139. + (and (and (eq_attr "type" "store_multiple")
  36140. + (eq_attr "combo" "12"))
  36141. + (eq_attr "pipeline_model" "n13"))
  36142. + "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
  36143. +
  36144. +(define_insn_reservation "nds_n13_mul" 1
  36145. + (and (eq_attr "type" "mul")
  36146. + (eq_attr "pipeline_model" "n13"))
  36147. + "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
  36148. +
  36149. +(define_insn_reservation "nds_n13_mac" 1
  36150. + (and (eq_attr "type" "mac")
  36151. + (eq_attr "pipeline_model" "n13"))
  36152. + "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
  36153. +
  36154. +;; The cycles consumed in E2 stage is 32 - CLZ(abs(Ra)) + 2,
  36155. +;; so the worst case is 34.
  36156. +(define_insn_reservation "nds_n13_div" 1
  36157. + (and (eq_attr "type" "div")
  36158. + (eq_attr "pipeline_model" "n13"))
  36159. + "n13_i1, n13_i2, n13_e1, n13_e2*34, n13_e3, n13_e4")
  36160. +
  36161. +(define_insn_reservation "nds_n13_branch" 1
  36162. + (and (eq_attr "type" "branch")
  36163. + (eq_attr "pipeline_model" "n13"))
  36164. + "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
  36165. +
  36166. +;; LD -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
  36167. +(define_bypass 3
  36168. + "nds_n13_load"
  36169. + "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
  36170. + nds_n13_mul, nds_n13_mac, nds_n13_div,\
  36171. + nds_n13_mmu,\
  36172. + nds_n13_load, nds_n13_store,\
  36173. + nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36174. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36175. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
  36176. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36177. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36178. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36179. + "nds32_n13_load_to_e1_p"
  36180. +)
  36181. +
  36182. +;; LD -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
  36183. +(define_bypass 2
  36184. + "nds_n13_load"
  36185. + "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
  36186. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36187. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36188. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36189. + "nds32_n13_load_to_e2_p"
  36190. +)
  36191. +
  36192. +;; LMW(N, N) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
  36193. +(define_bypass 3
  36194. + "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36195. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36196. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
  36197. + "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
  36198. + nds_n13_mul, nds_n13_mac, nds_n13_div,\
  36199. + nds_n13_mmu,\
  36200. + nds_n13_load, nds_n13_store,\
  36201. + nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36202. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36203. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
  36204. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36205. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36206. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36207. + "nds32_n13_last_load_to_e1_p")
  36208. +
  36209. +;; LMW(N, N) -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
  36210. +(define_bypass 2
  36211. + "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36212. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36213. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
  36214. + "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
  36215. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36216. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36217. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36218. + "nds32_n13_last_load_to_e2_p"
  36219. +)
  36220. +
  36221. +;; LMW(N, N - 1) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
  36222. +(define_bypass 2
  36223. + "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36224. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36225. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
  36226. + "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
  36227. + nds_n13_mul, nds_n13_mac, nds_n13_div,\
  36228. + nds_n13_mmu,\
  36229. + nds_n13_load, nds_n13_store,\
  36230. + nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36231. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36232. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
  36233. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36234. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36235. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36236. + "nds32_n13_last_two_load_to_e1_p")
  36237. +
  36238. +;; ALU, ALU_SHIFT, SIMD, BR, MUL, MAC, DIV, ADDR_OUT
  36239. +;; -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
  36240. +(define_bypass 2
  36241. + "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsad, nds_n13_pbsada, nds_n13_branch,\
  36242. + nds_n13_mul, nds_n13_mac, nds_n13_div,\
  36243. + nds_n13_load, nds_n13_store,\
  36244. + nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36245. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36246. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
  36247. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36248. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36249. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36250. + "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
  36251. + nds_n13_mul, nds_n13_mac, nds_n13_div,\
  36252. + nds_n13_mmu,\
  36253. + nds_n13_load, nds_n13_store,\
  36254. + nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
  36255. + nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
  36256. + nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
  36257. + nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
  36258. + nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
  36259. + nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
  36260. + "nds32_n13_e2_to_e1_p")
  36261. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-n7.md gcc-4.9.4/gcc/config/nds32/nds32-n7.md
  36262. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-n7.md 1970-01-01 01:00:00.000000000 +0100
  36263. +++ gcc-4.9.4/gcc/config/nds32/nds32-n7.md 2016-08-08 20:37:45.510270246 +0200
  36264. @@ -0,0 +1,237 @@
  36265. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  36266. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  36267. +;; Contributed by Andes Technology Corporation.
  36268. +;;
  36269. +;; This file is part of GCC.
  36270. +;;
  36271. +;; GCC is free software; you can redistribute it and/or modify it
  36272. +;; under the terms of the GNU General Public License as published
  36273. +;; by the Free Software Foundation; either version 3, or (at your
  36274. +;; option) any later version.
  36275. +;;
  36276. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  36277. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  36278. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  36279. +;; License for more details.
  36280. +;;
  36281. +;; You should have received a copy of the GNU General Public License
  36282. +;; along with GCC; see the file COPYING3. If not see
  36283. +;; <http://www.gnu.org/licenses/>.
  36284. +
  36285. +
  36286. +;; ------------------------------------------------------------------------
  36287. +;; Define N8 pipeline settings.
  36288. +;; ------------------------------------------------------------------------
  36289. +
  36290. +(define_automaton "nds32_n7_machine")
  36291. +
  36292. +(define_cpu_unit "n7_ii" "nds32_n7_machine")
  36293. +
  36294. +(define_insn_reservation "nds_n7_unknown" 1
  36295. + (and (eq_attr "type" "unknown")
  36296. + (eq_attr "pipeline_model" "n7"))
  36297. + "n7_ii")
  36298. +
  36299. +(define_insn_reservation "nds_n7_misc" 1
  36300. + (and (eq_attr "type" "misc")
  36301. + (eq_attr "pipeline_model" "n7"))
  36302. + "n7_ii")
  36303. +
  36304. +(define_insn_reservation "nds_n7_alu" 1
  36305. + (and (eq_attr "type" "alu")
  36306. + (eq_attr "pipeline_model" "n7"))
  36307. + "n7_ii")
  36308. +
  36309. +(define_insn_reservation "nds_n7_load" 1
  36310. + (and (match_test "nds32_load_single_p (insn)")
  36311. + (eq_attr "pipeline_model" "n7"))
  36312. + "n7_ii")
  36313. +
  36314. +(define_insn_reservation "nds_n7_store" 1
  36315. + (and (match_test "nds32_store_single_p (insn)")
  36316. + (eq_attr "pipeline_model" "n7"))
  36317. + "n7_ii")
  36318. +
  36319. +(define_insn_reservation "nds_n7_load_multiple_1" 1
  36320. + (and (and (eq_attr "type" "load_multiple")
  36321. + (eq_attr "combo" "1"))
  36322. + (eq_attr "pipeline_model" "n7"))
  36323. + "n7_ii")
  36324. +
  36325. +(define_insn_reservation "nds_n7_load_multiple_2" 1
  36326. + (and (ior (and (eq_attr "type" "load_multiple")
  36327. + (eq_attr "combo" "2"))
  36328. + (match_test "nds32_load_double_p (insn)"))
  36329. + (eq_attr "pipeline_model" "n7"))
  36330. + "n7_ii*2")
  36331. +
  36332. +(define_insn_reservation "nds_n7_load_multiple_3" 1
  36333. + (and (and (eq_attr "type" "load_multiple")
  36334. + (eq_attr "combo" "3"))
  36335. + (eq_attr "pipeline_model" "n7"))
  36336. + "n7_ii*3")
  36337. +
  36338. +(define_insn_reservation "nds_n7_load_multiple_4" 1
  36339. + (and (and (eq_attr "type" "load_multiple")
  36340. + (eq_attr "combo" "4"))
  36341. + (eq_attr "pipeline_model" "n7"))
  36342. + "n7_ii*4")
  36343. +
  36344. +(define_insn_reservation "nds_n7_load_multiple_5" 1
  36345. + (and (and (eq_attr "type" "load_multiple")
  36346. + (eq_attr "combo" "5"))
  36347. + (eq_attr "pipeline_model" "n7"))
  36348. + "n7_ii*5")
  36349. +
  36350. +(define_insn_reservation "nds_n7_load_multiple_6" 1
  36351. + (and (and (eq_attr "type" "load_multiple")
  36352. + (eq_attr "combo" "6"))
  36353. + (eq_attr "pipeline_model" "n7"))
  36354. + "n7_ii*6")
  36355. +
  36356. +(define_insn_reservation "nds_n7_load_multiple_7" 1
  36357. + (and (and (eq_attr "type" "load_multiple")
  36358. + (eq_attr "combo" "7"))
  36359. + (eq_attr "pipeline_model" "n7"))
  36360. + "n7_ii*7")
  36361. +
  36362. +(define_insn_reservation "nds_n7_load_multiple_8" 1
  36363. + (and (and (eq_attr "type" "load_multiple")
  36364. + (eq_attr "combo" "8"))
  36365. + (eq_attr "pipeline_model" "n7"))
  36366. + "n7_ii*8")
  36367. +
  36368. +(define_insn_reservation "nds_n7_load_multiple_12" 1
  36369. + (and (and (eq_attr "type" "load_multiple")
  36370. + (eq_attr "combo" "12"))
  36371. + (eq_attr "pipeline_model" "n7"))
  36372. + "n7_ii*12")
  36373. +
  36374. +(define_insn_reservation "nds_n7_store_multiple_1" 1
  36375. + (and (and (eq_attr "type" "store_multiple")
  36376. + (eq_attr "combo" "1"))
  36377. + (eq_attr "pipeline_model" "n7"))
  36378. + "n7_ii")
  36379. +
  36380. +(define_insn_reservation "nds_n7_store_multiple_2" 1
  36381. + (and (ior (and (eq_attr "type" "store_multiple")
  36382. + (eq_attr "combo" "2"))
  36383. + (match_test "nds32_store_double_p (insn)"))
  36384. + (eq_attr "pipeline_model" "n7"))
  36385. + "n7_ii*2")
  36386. +
  36387. +(define_insn_reservation "nds_n7_store_multiple_3" 1
  36388. + (and (and (eq_attr "type" "store_multiple")
  36389. + (eq_attr "combo" "3"))
  36390. + (eq_attr "pipeline_model" "n7"))
  36391. + "n7_ii*3")
  36392. +
  36393. +(define_insn_reservation "nds_n7_store_multiple_4" 1
  36394. + (and (and (eq_attr "type" "store_multiple")
  36395. + (eq_attr "combo" "4"))
  36396. + (eq_attr "pipeline_model" "n7"))
  36397. + "n7_ii*4")
  36398. +
  36399. +(define_insn_reservation "nds_n7_store_multiple_5" 1
  36400. + (and (and (eq_attr "type" "store_multiple")
  36401. + (eq_attr "combo" "5"))
  36402. + (eq_attr "pipeline_model" "n7"))
  36403. + "n7_ii*5")
  36404. +
  36405. +(define_insn_reservation "nds_n7_store_multiple_6" 1
  36406. + (and (and (eq_attr "type" "store_multiple")
  36407. + (eq_attr "combo" "6"))
  36408. + (eq_attr "pipeline_model" "n7"))
  36409. + "n7_ii*6")
  36410. +
  36411. +(define_insn_reservation "nds_n7_store_multiple_7" 1
  36412. + (and (and (eq_attr "type" "store_multiple")
  36413. + (eq_attr "combo" "7"))
  36414. + (eq_attr "pipeline_model" "n7"))
  36415. + "n7_ii*7")
  36416. +
  36417. +(define_insn_reservation "nds_n7_store_multiple_8" 1
  36418. + (and (and (eq_attr "type" "store_multiple")
  36419. + (eq_attr "combo" "8"))
  36420. + (eq_attr "pipeline_model" "n7"))
  36421. + "n7_ii*8")
  36422. +
  36423. +(define_insn_reservation "nds_n7_store_multiple_12" 1
  36424. + (and (and (eq_attr "type" "store_multiple")
  36425. + (eq_attr "combo" "12"))
  36426. + (eq_attr "pipeline_model" "n7"))
  36427. + "n7_ii*12")
  36428. +
  36429. +(define_insn_reservation "nds_n7_mul_fast" 1
  36430. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  36431. + (and (eq_attr "type" "mul")
  36432. + (eq_attr "pipeline_model" "n7")))
  36433. + "n7_ii")
  36434. +
  36435. +(define_insn_reservation "nds_n7_mul_slow" 1
  36436. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  36437. + (and (eq_attr "type" "mul")
  36438. + (eq_attr "pipeline_model" "n7")))
  36439. + "n7_ii*17")
  36440. +
  36441. +(define_insn_reservation "nds_n7_mac_fast" 1
  36442. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  36443. + (and (eq_attr "type" "mac")
  36444. + (eq_attr "pipeline_model" "n7")))
  36445. + "n7_ii*2")
  36446. +
  36447. +(define_insn_reservation "nds_n7_mac_slow" 1
  36448. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  36449. + (and (eq_attr "type" "mac")
  36450. + (eq_attr "pipeline_model" "n7")))
  36451. + "n7_ii*18")
  36452. +
  36453. +(define_insn_reservation "nds_n7_div" 1
  36454. + (and (eq_attr "type" "div")
  36455. + (eq_attr "pipeline_model" "n7"))
  36456. + "n7_ii*37")
  36457. +
  36458. +(define_insn_reservation "nds_n7_branch" 1
  36459. + (and (eq_attr "type" "branch")
  36460. + (eq_attr "pipeline_model" "n7"))
  36461. + "n7_ii")
  36462. +
  36463. +;; LD_!bi
  36464. +;; -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR, ADDR_IN_MOP(1), ST_bi, ST_!bi_RI, SMW(N, 1)
  36465. +(define_bypass 2
  36466. + "nds_n7_load"
  36467. + "nds_n7_alu,\
  36468. + nds_n7_mul_fast, nds_n7_mul_slow,\
  36469. + nds_n7_mac_fast, nds_n7_mac_slow,\
  36470. + nds_n7_div,\
  36471. + nds_n7_branch,\
  36472. + nds_n7_load, nds_n7_store,\
  36473. + nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
  36474. + nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
  36475. + nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12,\
  36476. + nds_n7_store_multiple_1,nds_n7_store_multiple_2, nds_n7_store_multiple_3,\
  36477. + nds_n7_store_multiple_4,nds_n7_store_multiple_5, nds_n7_store_multiple_6,\
  36478. + nds_n7_store_multiple_7,nds_n7_store_multiple_8, nds_n7_store_multiple_12"
  36479. + "nds32_n7_load_to_ii_p"
  36480. +)
  36481. +
  36482. +;; LMW(N, N)
  36483. +;; -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR, AADR_IN_MOP(1), ST_bi, ST_!bi_RI, SMW(N, 1)
  36484. +(define_bypass 2
  36485. + "nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
  36486. + nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
  36487. + nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12"
  36488. + "nds_n7_alu,\
  36489. + nds_n7_mul_fast, nds_n7_mul_slow,\
  36490. + nds_n7_mac_fast, nds_n7_mac_slow,\
  36491. + nds_n7_div,\
  36492. + nds_n7_branch,\
  36493. + nds_n7_load, nds_n7_store,\
  36494. + nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
  36495. + nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
  36496. + nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12,\
  36497. + nds_n7_store_multiple_1,nds_n7_store_multiple_2, nds_n7_store_multiple_3,\
  36498. + nds_n7_store_multiple_4,nds_n7_store_multiple_5, nds_n7_store_multiple_6,\
  36499. + nds_n7_store_multiple_7,nds_n7_store_multiple_8, nds_n7_store_multiple_12"
  36500. + "nds32_n7_last_load_to_ii_p"
  36501. +)
  36502. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-n8.md gcc-4.9.4/gcc/config/nds32/nds32-n8.md
  36503. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-n8.md 1970-01-01 01:00:00.000000000 +0100
  36504. +++ gcc-4.9.4/gcc/config/nds32/nds32-n8.md 2016-08-08 20:37:45.510270246 +0200
  36505. @@ -0,0 +1,314 @@
  36506. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  36507. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  36508. +;; Contributed by Andes Technology Corporation.
  36509. +;;
  36510. +;; This file is part of GCC.
  36511. +;;
  36512. +;; GCC is free software; you can redistribute it and/or modify it
  36513. +;; under the terms of the GNU General Public License as published
  36514. +;; by the Free Software Foundation; either version 3, or (at your
  36515. +;; option) any later version.
  36516. +;;
  36517. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  36518. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  36519. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  36520. +;; License for more details.
  36521. +;;
  36522. +;; You should have received a copy of the GNU General Public License
  36523. +;; along with GCC; see the file COPYING3. If not see
  36524. +;; <http://www.gnu.org/licenses/>.
  36525. +
  36526. +
  36527. +;; ------------------------------------------------------------------------
  36528. +;; Define N8 pipeline settings.
  36529. +;; ------------------------------------------------------------------------
  36530. +
  36531. +(define_automaton "nds32_n8_machine")
  36532. +
  36533. +(define_cpu_unit "n8_ii" "nds32_n8_machine")
  36534. +(define_cpu_unit "n8_ex" "nds32_n8_machine")
  36535. +
  36536. +(define_insn_reservation "nds_n8_unknown" 1
  36537. + (and (eq_attr "type" "unknown")
  36538. + (eq_attr "pipeline_model" "n8"))
  36539. + "n8_ii, n8_ex")
  36540. +
  36541. +(define_insn_reservation "nds_n8_misc" 1
  36542. + (and (eq_attr "type" "misc")
  36543. + (eq_attr "pipeline_model" "n8"))
  36544. + "n8_ii, n8_ex")
  36545. +
  36546. +(define_insn_reservation "nds_n8_alu" 1
  36547. + (and (eq_attr "type" "alu")
  36548. + (eq_attr "pipeline_model" "n8"))
  36549. + "n8_ii, n8_ex")
  36550. +
  36551. +(define_insn_reservation "nds_n8_load" 1
  36552. + (and (match_test "nds32_load_single_p (insn)")
  36553. + (eq_attr "pipeline_model" "n8"))
  36554. + "n8_ii, n8_ex")
  36555. +
  36556. +(define_insn_reservation "nds_n8_store" 1
  36557. + (and (match_test "nds32_store_single_p (insn)")
  36558. + (eq_attr "pipeline_model" "n8"))
  36559. + "n8_ii, n8_ex")
  36560. +
  36561. +(define_insn_reservation "nds_n8_load_multiple_1" 1
  36562. + (and (and (eq_attr "type" "load_multiple")
  36563. + (eq_attr "combo" "1"))
  36564. + (eq_attr "pipeline_model" "n8"))
  36565. + "n8_ii, n8_ex")
  36566. +
  36567. +(define_insn_reservation "nds_n8_load_multiple_2" 1
  36568. + (and (ior (and (eq_attr "type" "load_multiple")
  36569. + (eq_attr "combo" "2"))
  36570. + (match_test "nds32_load_double_p (insn)"))
  36571. + (eq_attr "pipeline_model" "n8"))
  36572. + "n8_ii, n8_ii+n8_ex, n8_ex")
  36573. +
  36574. +(define_insn_reservation "nds_n8_load_multiple_3" 1
  36575. + (and (and (eq_attr "type" "load_multiple")
  36576. + (eq_attr "combo" "3"))
  36577. + (eq_attr "pipeline_model" "n8"))
  36578. + "n8_ii, (n8_ii+n8_ex)*2, n8_ex")
  36579. +
  36580. +(define_insn_reservation "nds_n8_load_multiple_4" 1
  36581. + (and (and (eq_attr "type" "load_multiple")
  36582. + (eq_attr "combo" "4"))
  36583. + (eq_attr "pipeline_model" "n8"))
  36584. + "n8_ii, (n8_ii+n8_ex)*3, n8_ex")
  36585. +
  36586. +(define_insn_reservation "nds_n8_load_multiple_5" 1
  36587. + (and (and (eq_attr "type" "load_multiple")
  36588. + (eq_attr "combo" "5"))
  36589. + (eq_attr "pipeline_model" "n8"))
  36590. + "n8_ii, (n8_ii+n8_ex)*4, n8_ex")
  36591. +
  36592. +(define_insn_reservation "nds_n8_load_multiple_6" 1
  36593. + (and (and (eq_attr "type" "load_multiple")
  36594. + (eq_attr "combo" "6"))
  36595. + (eq_attr "pipeline_model" "n8"))
  36596. + "n8_ii, (n8_ii+n8_ex)*5, n8_ex")
  36597. +
  36598. +(define_insn_reservation "nds_n8_load_multiple_7" 1
  36599. + (and (and (eq_attr "type" "load_multiple")
  36600. + (eq_attr "combo" "7"))
  36601. + (eq_attr "pipeline_model" "n8"))
  36602. + "n8_ii, (n8_ii+n8_ex)*6, n8_ex")
  36603. +
  36604. +(define_insn_reservation "nds_n8_load_multiple_8" 1
  36605. + (and (and (eq_attr "type" "load_multiple")
  36606. + (eq_attr "combo" "8"))
  36607. + (eq_attr "pipeline_model" "n8"))
  36608. + "n8_ii, (n8_ii+n8_ex)*7, n8_ex")
  36609. +
  36610. +(define_insn_reservation "nds_n8_load_multiple_12" 1
  36611. + (and (and (eq_attr "type" "load_multiple")
  36612. + (eq_attr "combo" "12"))
  36613. + (eq_attr "pipeline_model" "n8"))
  36614. + "n8_ii, (n8_ii+n8_ex)*11, n8_ex")
  36615. +
  36616. +(define_insn_reservation "nds_n8_store_multiple_1" 1
  36617. + (and (and (eq_attr "type" "store_multiple")
  36618. + (eq_attr "combo" "1"))
  36619. + (eq_attr "pipeline_model" "n8"))
  36620. + "n8_ii, n8_ex")
  36621. +
  36622. +(define_insn_reservation "nds_n8_store_multiple_2" 1
  36623. + (and (ior (and (eq_attr "type" "store_multiple")
  36624. + (eq_attr "combo" "2"))
  36625. + (match_test "nds32_store_double_p (insn)"))
  36626. + (eq_attr "pipeline_model" "n8"))
  36627. + "n8_ii, n8_ii+n8_ex, n8_ex")
  36628. +
  36629. +(define_insn_reservation "nds_n8_store_multiple_3" 1
  36630. + (and (and (eq_attr "type" "store_multiple")
  36631. + (eq_attr "combo" "3"))
  36632. + (eq_attr "pipeline_model" "n8"))
  36633. + "n8_ii, (n8_ii+n8_ex)*2, n8_ex")
  36634. +
  36635. +(define_insn_reservation "nds_n8_store_multiple_4" 1
  36636. + (and (and (eq_attr "type" "store_multiple")
  36637. + (eq_attr "combo" "4"))
  36638. + (eq_attr "pipeline_model" "n8"))
  36639. + "n8_ii, (n8_ii+n8_ex)*3, n8_ex")
  36640. +
  36641. +(define_insn_reservation "nds_n8_store_multiple_5" 1
  36642. + (and (and (eq_attr "type" "store_multiple")
  36643. + (eq_attr "combo" "5"))
  36644. + (eq_attr "pipeline_model" "n8"))
  36645. + "n8_ii, (n8_ii+n8_ex)*4, n8_ex")
  36646. +
  36647. +(define_insn_reservation "nds_n8_store_multiple_6" 1
  36648. + (and (and (eq_attr "type" "store_multiple")
  36649. + (eq_attr "combo" "6"))
  36650. + (eq_attr "pipeline_model" "n8"))
  36651. + "n8_ii, (n8_ii+n8_ex)*5, n8_ex")
  36652. +
  36653. +(define_insn_reservation "nds_n8_store_multiple_7" 1
  36654. + (and (and (eq_attr "type" "store_multiple")
  36655. + (eq_attr "combo" "7"))
  36656. + (eq_attr "pipeline_model" "n8"))
  36657. + "n8_ii, (n8_ii+n8_ex)*6, n8_ex")
  36658. +
  36659. +(define_insn_reservation "nds_n8_store_multiple_8" 1
  36660. + (and (and (eq_attr "type" "store_multiple")
  36661. + (eq_attr "combo" "8"))
  36662. + (eq_attr "pipeline_model" "n8"))
  36663. + "n8_ii, (n8_ii+n8_ex)*7, n8_ex")
  36664. +
  36665. +(define_insn_reservation "nds_n8_store_multiple_12" 1
  36666. + (and (and (eq_attr "type" "store_multiple")
  36667. + (eq_attr "combo" "12"))
  36668. + (eq_attr "pipeline_model" "n8"))
  36669. + "n8_ii, (n8_ii+n8_ex)*11, n8_ex")
  36670. +
  36671. +(define_insn_reservation "nds_n8_mul_fast" 1
  36672. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  36673. + (and (eq_attr "type" "mul")
  36674. + (eq_attr "pipeline_model" "n8")))
  36675. + "n8_ii, n8_ex")
  36676. +
  36677. +(define_insn_reservation "nds_n8_mul_slow" 1
  36678. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  36679. + (and (eq_attr "type" "mul")
  36680. + (eq_attr "pipeline_model" "n8")))
  36681. + "n8_ii, n8_ex*16")
  36682. +
  36683. +(define_insn_reservation "nds_n8_mac_fast" 1
  36684. + (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
  36685. + (and (eq_attr "type" "mac")
  36686. + (eq_attr "pipeline_model" "n8")))
  36687. + "n8_ii, n8_ii+n8_ex, n8_ex")
  36688. +
  36689. +(define_insn_reservation "nds_n8_mac_slow" 1
  36690. + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
  36691. + (and (eq_attr "type" "mac")
  36692. + (eq_attr "pipeline_model" "n8")))
  36693. + "n8_ii, (n8_ii+n8_ex)*16, n8_ex")
  36694. +
  36695. +(define_insn_reservation "nds_n8_div" 1
  36696. + (and (eq_attr "type" "div")
  36697. + (eq_attr "pipeline_model" "n8"))
  36698. + "n8_ii, (n8_ii+n8_ex)*36, n8_ex")
  36699. +
  36700. +(define_insn_reservation "nds_n8_branch" 1
  36701. + (and (eq_attr "type" "branch")
  36702. + (eq_attr "pipeline_model" "n8"))
  36703. + "n8_ii, n8_ex")
  36704. +
  36705. +;; LD_!bi -> ADDR_IN_MOP(1)
  36706. +(define_bypass 3
  36707. + "nds_n8_load"
  36708. + "nds_n8_branch,\
  36709. + nds_n8_load, nds_n8_store,\
  36710. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36711. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36712. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36713. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36714. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36715. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36716. + "nds32_n8_load_to_ii_p"
  36717. +)
  36718. +
  36719. +;; LMW(N, N) -> ADDR_IN_MOP(1)
  36720. +(define_bypass 3
  36721. + "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36722. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36723. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
  36724. + "nds_n8_branch,\
  36725. + nds_n8_load, nds_n8_store,\
  36726. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36727. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36728. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36729. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36730. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36731. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36732. + "nds32_n8_last_load_to_ii_p"
  36733. +)
  36734. +
  36735. +;; LMW(N, N - 1) -> ADDR_IN_MOP(1)
  36736. +(define_bypass 2
  36737. + "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36738. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36739. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
  36740. + "nds_n8_branch,\
  36741. + nds_n8_load, nds_n8_store,\
  36742. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36743. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36744. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36745. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36746. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36747. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36748. + "nds32_n8_last_load_two_to_ii_p"
  36749. +)
  36750. +
  36751. +;; LD_bi -> ADDR_IN_MOP(1)
  36752. +(define_bypass 2
  36753. + "nds_n8_load"
  36754. + "nds_n8_branch,\
  36755. + nds_n8_load, nds_n8_store,\
  36756. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36757. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36758. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36759. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36760. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36761. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36762. + "nds32_n8_load_bi_to_ii_p"
  36763. +)
  36764. +
  36765. +;; LD_!bi -> ALU, MOVD44_E, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
  36766. +(define_bypass 2
  36767. + "nds_n8_load"
  36768. + "nds_n8_alu,
  36769. + nds_n8_mul_fast, nds_n8_mul_slow,\
  36770. + nds_n8_mac_fast, nds_n8_mac_slow,\
  36771. + nds_n8_div,\
  36772. + nds_n8_branch,\
  36773. + nds_n8_store,\
  36774. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36775. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36776. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36777. + "nds32_n8_load_to_ex_p"
  36778. +)
  36779. +
  36780. +;; ALU, MOVD44_O, MUL, MAC, DIV_Rs, LD_bi, ADDR_OUT -> ADDR_IN_MOP(1)
  36781. +(define_bypass 2
  36782. + "nds_n8_alu,
  36783. + nds_n8_mul_fast, nds_n8_mul_slow,\
  36784. + nds_n8_mac_fast, nds_n8_mac_slow,\
  36785. + nds_n8_div,\
  36786. + nds_n8_load, nds_n8_store,\
  36787. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36788. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36789. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36790. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36791. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36792. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36793. + "nds_n8_branch,\
  36794. + nds_n8_load, nds_n8_store,\
  36795. + nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36796. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36797. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
  36798. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36799. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36800. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36801. + "nds32_n8_ex_to_ii_p"
  36802. +)
  36803. +
  36804. +;; LMW(N, N) -> ALU, MOVD44_E, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
  36805. +(define_bypass 2
  36806. + "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
  36807. + nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
  36808. + nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
  36809. + "nds_n8_alu,
  36810. + nds_n8_mul_fast, nds_n8_mul_slow,\
  36811. + nds_n8_mac_fast, nds_n8_mac_slow,\
  36812. + nds_n8_div,\
  36813. + nds_n8_branch,\
  36814. + nds_n8_store,\
  36815. + nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
  36816. + nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
  36817. + nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
  36818. + "nds32_n8_last_load_to_ex_p"
  36819. +)
  36820. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-n9-2r1w.md gcc-4.9.4/gcc/config/nds32/nds32-n9-2r1w.md
  36821. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-n9-2r1w.md 1970-01-01 01:00:00.000000000 +0100
  36822. +++ gcc-4.9.4/gcc/config/nds32/nds32-n9-2r1w.md 2016-08-08 20:37:45.510270246 +0200
  36823. @@ -0,0 +1,295 @@
  36824. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  36825. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  36826. +;; Contributed by Andes Technology Corporation.
  36827. +;;
  36828. +;; This file is part of GCC.
  36829. +;;
  36830. +;; GCC is free software; you can redistribute it and/or modify it
  36831. +;; under the terms of the GNU General Public License as published
  36832. +;; by the Free Software Foundation; either version 3, or (at your
  36833. +;; option) any later version.
  36834. +;;
  36835. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  36836. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  36837. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  36838. +;; License for more details.
  36839. +;;
  36840. +;; You should have received a copy of the GNU General Public License
  36841. +;; along with GCC; see the file COPYING3. If not see
  36842. +;; <http://www.gnu.org/licenses/>.
  36843. +
  36844. +
  36845. +;; ------------------------------------------------------------------------
  36846. +;; Define N9 2R1W pipeline settings.
  36847. +;; ------------------------------------------------------------------------
  36848. +
  36849. +(define_automaton "nds32_n9_2r1w_machine")
  36850. +
  36851. +(define_cpu_unit "n9_2r1w_ii" "nds32_n9_2r1w_machine")
  36852. +(define_cpu_unit "n9_2r1w_ex" "nds32_n9_2r1w_machine")
  36853. +(define_cpu_unit "n9_2r1w_mm" "nds32_n9_2r1w_machine")
  36854. +(define_cpu_unit "n9_2r1w_wb" "nds32_n9_2r1w_machine")
  36855. +
  36856. +(define_insn_reservation "nds_n9_2r1w_unknown" 1
  36857. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36858. + (and (eq_attr "type" "unknown")
  36859. + (eq_attr "pipeline_model" "n9")))
  36860. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36861. +
  36862. +(define_insn_reservation "nds_n9_2r1w_misc" 1
  36863. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36864. + (and (eq_attr "type" "misc")
  36865. + (eq_attr "pipeline_model" "n9")))
  36866. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36867. +
  36868. +(define_insn_reservation "nds_n9_2r1w_mmu" 1
  36869. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36870. + (and (eq_attr "type" "mmu")
  36871. + (eq_attr "pipeline_model" "n9")))
  36872. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36873. +
  36874. +(define_insn_reservation "nds_n9_2r1w_alu" 1
  36875. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36876. + (and (eq_attr "type" "alu")
  36877. + (eq_attr "pipeline_model" "n9")))
  36878. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36879. +
  36880. +(define_insn_reservation "nds_n9_2r1w_alu_shift" 1
  36881. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36882. + (and (eq_attr "type" "alu_shift")
  36883. + (eq_attr "pipeline_model" "n9")))
  36884. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36885. +
  36886. +(define_insn_reservation "nds_n9_2r1w_pbsad" 1
  36887. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36888. + (and (eq_attr "type" "pbsad")
  36889. + (eq_attr "pipeline_model" "n9")))
  36890. + "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb")
  36891. +
  36892. +(define_insn_reservation "nds_n9_2r1w_pbsada" 1
  36893. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36894. + (and (eq_attr "type" "pbsada")
  36895. + (eq_attr "pipeline_model" "n9")))
  36896. + "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb")
  36897. +
  36898. +(define_insn_reservation "nds_n9_2r1w_load" 1
  36899. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36900. + (and (match_test "nds32_load_single_p (insn)")
  36901. + (eq_attr "pipeline_model" "n9")))
  36902. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36903. +
  36904. +(define_insn_reservation "nds_n9_2r1w_store" 1
  36905. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36906. + (and (match_test "nds32_store_single_p (insn)")
  36907. + (eq_attr "pipeline_model" "n9")))
  36908. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36909. +
  36910. +(define_insn_reservation "nds_n9_2r1w_load_multiple_1" 1
  36911. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36912. + (and (eq_attr "pipeline_model" "n9")
  36913. + (and (eq_attr "type" "load_multiple")
  36914. + (eq_attr "combo" "1"))))
  36915. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36916. +
  36917. +(define_insn_reservation "nds_n9_2r1w_load_multiple_2" 1
  36918. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36919. + (and (eq_attr "pipeline_model" "n9")
  36920. + (ior (and (eq_attr "type" "load_multiple")
  36921. + (eq_attr "combo" "2"))
  36922. + (match_test "nds32_load_double_p (insn)"))))
  36923. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36924. +
  36925. +(define_insn_reservation "nds_n9_2r1w_load_multiple_3" 1
  36926. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36927. + (and (eq_attr "pipeline_model" "n9")
  36928. + (and (eq_attr "type" "load_multiple")
  36929. + (eq_attr "combo" "3"))))
  36930. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36931. +
  36932. +(define_insn_reservation "nds_n9_2r1w_load_multiple_4" 1
  36933. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36934. + (and (eq_attr "pipeline_model" "n9")
  36935. + (and (eq_attr "type" "load_multiple")
  36936. + (eq_attr "combo" "4"))))
  36937. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36938. +
  36939. +(define_insn_reservation "nds_n9_2r1w_load_multiple_5" 1
  36940. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36941. + (and (eq_attr "pipeline_model" "n9")
  36942. + (and (eq_attr "type" "load_multiple")
  36943. + (eq_attr "combo" "5"))))
  36944. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36945. +
  36946. +(define_insn_reservation "nds_n9_2r1w_load_multiple_6" 1
  36947. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36948. + (and (eq_attr "pipeline_model" "n9")
  36949. + (and (eq_attr "type" "load_multiple")
  36950. + (eq_attr "combo" "6"))))
  36951. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36952. +
  36953. +(define_insn_reservation "nds_n9_2r1w_load_multiple_7" 1
  36954. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36955. + (and (eq_attr "pipeline_model" "n9")
  36956. + (and (eq_attr "type" "load_multiple")
  36957. + (eq_attr "combo" "7"))))
  36958. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36959. +
  36960. +(define_insn_reservation "nds_n9_2r1w_load_multiple_8" 1
  36961. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36962. + (and (eq_attr "pipeline_model" "n9")
  36963. + (and (eq_attr "type" "load_multiple")
  36964. + (eq_attr "combo" "8"))))
  36965. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36966. +
  36967. +(define_insn_reservation "nds_n9_2r1w_load_multiple_12" 1
  36968. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36969. + (and (eq_attr "pipeline_model" "n9")
  36970. + (and (eq_attr "type" "load_multiple")
  36971. + (eq_attr "combo" "12"))))
  36972. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36973. +
  36974. +(define_insn_reservation "nds_n9_2r1w_store_multiple_1" 1
  36975. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36976. + (and (eq_attr "pipeline_model" "n9")
  36977. + (and (eq_attr "type" "store_multiple")
  36978. + (eq_attr "combo" "1"))))
  36979. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  36980. +
  36981. +(define_insn_reservation "nds_n9_2r1w_store_multiple_2" 1
  36982. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36983. + (and (eq_attr "pipeline_model" "n9")
  36984. + (ior (and (eq_attr "type" "store_multiple")
  36985. + (eq_attr "combo" "2"))
  36986. + (match_test "nds32_store_double_p (insn)"))))
  36987. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36988. +
  36989. +(define_insn_reservation "nds_n9_2r1w_store_multiple_3" 1
  36990. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36991. + (and (eq_attr "pipeline_model" "n9")
  36992. + (and (eq_attr "type" "store_multiple")
  36993. + (eq_attr "combo" "3"))))
  36994. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  36995. +
  36996. +(define_insn_reservation "nds_n9_2r1w_store_multiple_4" 1
  36997. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  36998. + (and (eq_attr "pipeline_model" "n9")
  36999. + (and (eq_attr "type" "store_multiple")
  37000. + (eq_attr "combo" "4"))))
  37001. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37002. +
  37003. +(define_insn_reservation "nds_n9_2r1w_store_multiple_5" 1
  37004. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37005. + (and (eq_attr "pipeline_model" "n9")
  37006. + (and (eq_attr "type" "store_multiple")
  37007. + (eq_attr "combo" "5"))))
  37008. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37009. +
  37010. +(define_insn_reservation "nds_n9_2r1w_store_multiple_6" 1
  37011. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37012. + (and (eq_attr "pipeline_model" "n9")
  37013. + (and (eq_attr "type" "store_multiple")
  37014. + (eq_attr "combo" "6"))))
  37015. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37016. +
  37017. +(define_insn_reservation "nds_n9_2r1w_store_multiple_7" 1
  37018. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37019. + (and (eq_attr "pipeline_model" "n9")
  37020. + (and (eq_attr "type" "store_multiple")
  37021. + (eq_attr "combo" "7"))))
  37022. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37023. +
  37024. +(define_insn_reservation "nds_n9_2r1w_store_multiple_8" 1
  37025. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37026. + (and (eq_attr "pipeline_model" "n9")
  37027. + (and (eq_attr "type" "store_multiple")
  37028. + (eq_attr "combo" "8"))))
  37029. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37030. +
  37031. +(define_insn_reservation "nds_n9_2r1w_store_multiple_12" 1
  37032. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37033. + (and (eq_attr "pipeline_model" "n9")
  37034. + (and (eq_attr "type" "store_multiple")
  37035. + (eq_attr "combo" "12"))))
  37036. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37037. +
  37038. +(define_insn_reservation "nds_n9_2r1w_mul_fast" 1
  37039. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW")
  37040. + (and (eq_attr "type" "mul")
  37041. + (eq_attr "pipeline_model" "n9")))
  37042. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  37043. +
  37044. +(define_insn_reservation "nds_n9_2r1w_mul_slow" 1
  37045. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW")
  37046. + (and (eq_attr "type" "mul")
  37047. + (eq_attr "pipeline_model" "n9")))
  37048. + "n9_2r1w_ii, n9_2r1w_ex*17, n9_2r1w_mm, n9_2r1w_wb")
  37049. +
  37050. +(define_insn_reservation "nds_n9_2r1w_mac_fast" 1
  37051. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW")
  37052. + (and (eq_attr "type" "mac")
  37053. + (eq_attr "pipeline_model" "n9")))
  37054. + "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37055. +
  37056. +(define_insn_reservation "nds_n9_2r1w_mac_slow" 1
  37057. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW")
  37058. + (and (eq_attr "type" "mac")
  37059. + (eq_attr "pipeline_model" "n9")))
  37060. + "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*17, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37061. +
  37062. +(define_insn_reservation "nds_n9_2r1w_div" 1
  37063. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37064. + (and (eq_attr "type" "div")
  37065. + (eq_attr "pipeline_model" "n9")))
  37066. + "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*34, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
  37067. +
  37068. +(define_insn_reservation "nds_n9_2r1w_branch" 1
  37069. + (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
  37070. + (and (eq_attr "type" "branch")
  37071. + (eq_attr "pipeline_model" "n9")))
  37072. + "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
  37073. +
  37074. +;; LD_!bi, MUL, MAC
  37075. +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44_E, MUL, MAC_RaRb, M2R, DIV, ADDR_IN_!bi, ADDR_IN_bi_Ra, ST_bi, ST_!bi_RI, BR, MMU
  37076. +(define_bypass 2
  37077. + "nds_n9_2r1w_load,\
  37078. + nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
  37079. + nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow"
  37080. + "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\
  37081. + nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\
  37082. + nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
  37083. + nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\
  37084. + nds_n9_2r1w_branch,\
  37085. + nds_n9_2r1w_div,\
  37086. + nds_n9_2r1w_load,nds_n9_2r1w_store,\
  37087. + nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
  37088. + nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
  37089. + nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\
  37090. + nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\
  37091. + nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\
  37092. + nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\
  37093. + nds_n9_2r1w_mmu"
  37094. + "nds32_n9_2r1w_mm_to_ex_p"
  37095. +)
  37096. +
  37097. +;; LMW(N, N)
  37098. +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU
  37099. +(define_bypass 2
  37100. + "nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
  37101. + nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
  37102. + nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12"
  37103. + "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\
  37104. + nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\
  37105. + nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
  37106. + nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\
  37107. + nds_n9_2r1w_branch,\
  37108. + nds_n9_2r1w_div,\
  37109. + nds_n9_2r1w_load,nds_n9_2r1w_store,\
  37110. + nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
  37111. + nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
  37112. + nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\
  37113. + nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\
  37114. + nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\
  37115. + nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\
  37116. + nds_n9_2r1w_mmu"
  37117. + "nds32_n9_last_load_to_ex_p"
  37118. +)
  37119. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-n9-3r2w.md gcc-4.9.4/gcc/config/nds32/nds32-n9-3r2w.md
  37120. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-n9-3r2w.md 1970-01-01 01:00:00.000000000 +0100
  37121. +++ gcc-4.9.4/gcc/config/nds32/nds32-n9-3r2w.md 2016-08-08 20:37:45.510270246 +0200
  37122. @@ -0,0 +1,308 @@
  37123. +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  37124. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  37125. +;; Contributed by Andes Technology Corporation.
  37126. +;;
  37127. +;; This file is part of GCC.
  37128. +;;
  37129. +;; GCC is free software; you can redistribute it and/or modify it
  37130. +;; under the terms of the GNU General Public License as published
  37131. +;; by the Free Software Foundation; either version 3, or (at your
  37132. +;; option) any later version.
  37133. +;;
  37134. +;; GCC is distributed in the hope that it will be useful, but WITHOUT
  37135. +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  37136. +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  37137. +;; License for more details.
  37138. +;;
  37139. +;; You should have received a copy of the GNU General Public License
  37140. +;; along with GCC; see the file COPYING3. If not see
  37141. +;; <http://www.gnu.org/licenses/>.
  37142. +
  37143. +
  37144. +;; ------------------------------------------------------------------------
  37145. +;; Define N9 3R2W pipeline settings.
  37146. +;; ------------------------------------------------------------------------
  37147. +
  37148. +(define_automaton "nds32_n9_3r2w_machine")
  37149. +
  37150. +(define_cpu_unit "n9_3r2w_ii" "nds32_n9_3r2w_machine")
  37151. +(define_cpu_unit "n9_3r2w_ex" "nds32_n9_3r2w_machine")
  37152. +(define_cpu_unit "n9_3r2w_mm" "nds32_n9_3r2w_machine")
  37153. +(define_cpu_unit "n9_3r2w_wb" "nds32_n9_3r2w_machine")
  37154. +
  37155. +(define_insn_reservation "nds_n9_3r2w_unknown" 1
  37156. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37157. + (and (eq_attr "type" "unknown")
  37158. + (eq_attr "pipeline_model" "n9")))
  37159. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37160. +
  37161. +(define_insn_reservation "nds_n9_3r2w_misc" 1
  37162. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37163. + (and (eq_attr "type" "misc")
  37164. + (eq_attr "pipeline_model" "n9")))
  37165. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37166. +
  37167. +(define_insn_reservation "nds_n9_3r2w_mmu" 1
  37168. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37169. + (and (eq_attr "type" "mmu")
  37170. + (eq_attr "pipeline_model" "n9")))
  37171. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37172. +
  37173. +(define_insn_reservation "nds_n9_3r2w_alu" 1
  37174. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37175. + (and (eq_attr "type" "alu")
  37176. + (eq_attr "pipeline_model" "n9")))
  37177. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37178. +
  37179. +(define_insn_reservation "nds_n9_3r2w_alu_shift" 1
  37180. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37181. + (and (eq_attr "type" "alu_shift")
  37182. + (eq_attr "pipeline_model" "n9")))
  37183. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37184. +
  37185. +(define_insn_reservation "nds_n9_3r2w_pbsad" 1
  37186. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37187. + (and (eq_attr "type" "pbsad")
  37188. + (eq_attr "pipeline_model" "n9")))
  37189. + "n9_3r2w_ii, n9_3r2w_ex*3, n9_3r2w_mm, n9_3r2w_wb")
  37190. +
  37191. +(define_insn_reservation "nds_n9_3r2w_pbsada" 1
  37192. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37193. + (and (eq_attr "type" "pbsada")
  37194. + (eq_attr "pipeline_model" "n9")))
  37195. + "n9_3r2w_ii, n9_3r2w_ex*3, n9_3r2w_mm, n9_3r2w_wb")
  37196. +
  37197. +(define_insn_reservation "nds_n9_3r2w_load" 1
  37198. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37199. + (and (match_test "nds32_load_single_p (insn)")
  37200. + (eq_attr "pipeline_model" "n9")))
  37201. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37202. +
  37203. +(define_insn_reservation "nds_n9_3r2w_store" 1
  37204. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37205. + (and (match_test "nds32_store_single_p (insn)")
  37206. + (eq_attr "pipeline_model" "n9")))
  37207. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37208. +
  37209. +(define_insn_reservation "nds_n9_3r2w_load_multiple_1" 1
  37210. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37211. + (and (eq_attr "pipeline_model" "n9")
  37212. + (and (eq_attr "type" "load_multiple")
  37213. + (eq_attr "combo" "1"))))
  37214. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37215. +
  37216. +(define_insn_reservation "nds_n9_3r2w_load_multiple_2" 1
  37217. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37218. + (and (eq_attr "pipeline_model" "n9")
  37219. + (ior (and (eq_attr "type" "load_multiple")
  37220. + (eq_attr "combo" "2"))
  37221. + (match_test "nds32_load_double_p (insn)"))))
  37222. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37223. +
  37224. +(define_insn_reservation "nds_n9_3r2w_load_multiple_3" 1
  37225. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37226. + (and (eq_attr "pipeline_model" "n9")
  37227. + (and (eq_attr "type" "load_multiple")
  37228. + (eq_attr "combo" "3"))))
  37229. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37230. +
  37231. +(define_insn_reservation "nds_n9_3r2w_load_multiple_4" 1
  37232. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37233. + (and (eq_attr "pipeline_model" "n9")
  37234. + (and (eq_attr "type" "load_multiple")
  37235. + (eq_attr "combo" "4"))))
  37236. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37237. +
  37238. +(define_insn_reservation "nds_n9_3r2w_load_multiple_5" 1
  37239. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37240. + (and (eq_attr "pipeline_model" "n9")
  37241. + (and (eq_attr "type" "load_multiple")
  37242. + (eq_attr "combo" "5"))))
  37243. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*2, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37244. +
  37245. +(define_insn_reservation "nds_n9_3r2w_load_multiple_6" 1
  37246. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37247. + (and (eq_attr "pipeline_model" "n9")
  37248. + (and (eq_attr "type" "load_multiple")
  37249. + (eq_attr "combo" "6"))))
  37250. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*3, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37251. +
  37252. +(define_insn_reservation "nds_n9_3r2w_load_multiple_7" 1
  37253. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37254. + (and (eq_attr "pipeline_model" "n9")
  37255. + (and (eq_attr "type" "load_multiple")
  37256. + (eq_attr "combo" "7"))))
  37257. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*4, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37258. +
  37259. +(define_insn_reservation "nds_n9_3r2w_load_multiple_8" 1
  37260. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37261. + (and (eq_attr "pipeline_model" "n9")
  37262. + (and (eq_attr "type" "load_multiple")
  37263. + (eq_attr "combo" "8"))))
  37264. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*5, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37265. +
  37266. +(define_insn_reservation "nds_n9_3r2w_load_multiple_12" 1
  37267. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37268. + (and (eq_attr "pipeline_model" "n9")
  37269. + (and (eq_attr "type" "load_multiple")
  37270. + (eq_attr "combo" "12"))))
  37271. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*9, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37272. +
  37273. +(define_insn_reservation "nds_n9_3r2w_store_multiple_1" 1
  37274. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37275. + (and (eq_attr "pipeline_model" "n9")
  37276. + (and (eq_attr "type" "store_multiple")
  37277. + (eq_attr "combo" "1"))))
  37278. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37279. +
  37280. +(define_insn_reservation "nds_n9_3r2w_store_multiple_2" 1
  37281. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37282. + (and (eq_attr "pipeline_model" "n9")
  37283. + (ior (and (eq_attr "type" "store_multiple")
  37284. + (eq_attr "combo" "2"))
  37285. + (match_test "nds32_store_double_p (insn)"))))
  37286. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37287. +
  37288. +(define_insn_reservation "nds_n9_3r2w_store_multiple_3" 1
  37289. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37290. + (and (eq_attr "pipeline_model" "n9")
  37291. + (and (eq_attr "type" "store_multiple")
  37292. + (eq_attr "combo" "3"))))
  37293. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37294. +
  37295. +(define_insn_reservation "nds_n9_3r2w_store_multiple_4" 1
  37296. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37297. + (and (eq_attr "pipeline_model" "n9")
  37298. + (and (eq_attr "type" "store_multiple")
  37299. + (eq_attr "combo" "4"))))
  37300. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37301. +
  37302. +(define_insn_reservation "nds_n9_3r2w_store_multiple_5" 1
  37303. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37304. + (and (eq_attr "pipeline_model" "n9")
  37305. + (and (eq_attr "type" "store_multiple")
  37306. + (eq_attr "combo" "5"))))
  37307. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*2, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37308. +
  37309. +(define_insn_reservation "nds_n9_3r2w_store_multiple_6" 1
  37310. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37311. + (and (eq_attr "pipeline_model" "n9")
  37312. + (and (eq_attr "type" "store_multiple")
  37313. + (eq_attr "combo" "6"))))
  37314. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*3, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37315. +
  37316. +(define_insn_reservation "nds_n9_3r2w_store_multiple_7" 1
  37317. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37318. + (and (eq_attr "pipeline_model" "n9")
  37319. + (and (eq_attr "type" "store_multiple")
  37320. + (eq_attr "combo" "7"))))
  37321. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*4, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37322. +
  37323. +(define_insn_reservation "nds_n9_3r2w_store_multiple_8" 1
  37324. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37325. + (and (eq_attr "pipeline_model" "n9")
  37326. + (and (eq_attr "type" "store_multiple")
  37327. + (eq_attr "combo" "8"))))
  37328. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*5, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37329. +
  37330. +(define_insn_reservation "nds_n9_3r2w_store_multiple_12" 1
  37331. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37332. + (and (eq_attr "pipeline_model" "n9")
  37333. + (and (eq_attr "type" "store_multiple")
  37334. + (eq_attr "combo" "12"))))
  37335. + "n9_3r2w_ii, n9_3r2w_ii+n9_3r2w_ex, n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm, (n9_3r2w_ii+n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb)*9, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_mm+n9_3r2w_wb, n9_3r2w_wb")
  37336. +
  37337. +(define_insn_reservation "nds_n9_3r2w_mul_fast1" 1
  37338. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_1")
  37339. + (and (eq_attr "type" "mul")
  37340. + (eq_attr "pipeline_model" "n9")))
  37341. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37342. +
  37343. +(define_insn_reservation "nds_n9_3r2w_mul_fast2" 1
  37344. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_2")
  37345. + (and (eq_attr "type" "mul")
  37346. + (eq_attr "pipeline_model" "n9")))
  37347. + "n9_3r2w_ii, n9_3r2w_ex*2, n9_3r2w_mm, n9_3r2w_wb")
  37348. +
  37349. +(define_insn_reservation "nds_n9_3r2w_mul_slow" 1
  37350. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_SLOW")
  37351. + (and (eq_attr "type" "mul")
  37352. + (eq_attr "pipeline_model" "n9")))
  37353. + "n9_3r2w_ii, n9_3r2w_ex*17, n9_3r2w_mm, n9_3r2w_wb")
  37354. +
  37355. +(define_insn_reservation "nds_n9_3r2w_mac_fast1" 1
  37356. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_1")
  37357. + (and (eq_attr "type" "mac")
  37358. + (eq_attr "pipeline_model" "n9")))
  37359. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37360. +
  37361. +(define_insn_reservation "nds_n9_3r2w_mac_fast2" 1
  37362. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_FAST_2")
  37363. + (and (eq_attr "type" "mac")
  37364. + (eq_attr "pipeline_model" "n9")))
  37365. + "n9_3r2w_ii, n9_3r2w_ex*2, n9_3r2w_mm, n9_3r2w_wb")
  37366. +
  37367. +(define_insn_reservation "nds_n9_3r2w_mac_slow" 1
  37368. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W && nds32_mul_config == MUL_TYPE_SLOW")
  37369. + (and (eq_attr "type" "mac")
  37370. + (eq_attr "pipeline_model" "n9")))
  37371. + "n9_3r2w_ii, n9_3r2w_ex*17, n9_3r2w_ex+n9_3r2w_mm, n9_3r2w_ex+n9_3r2w_mm+n9_3r2w_wb")
  37372. +
  37373. +(define_insn_reservation "nds_n9_3r2w_div" 1
  37374. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37375. + (and (eq_attr "type" "div")
  37376. + (eq_attr "pipeline_model" "n9")))
  37377. + "n9_3r2w_ii, n9_3r2w_ex*34, n9_3r2w_mm, n9_3r2w_wb")
  37378. +
  37379. +(define_insn_reservation "nds_n9_3r2w_branch" 1
  37380. + (and (match_test "nds32_register_ports_config == REG_PORT_3R2W")
  37381. + (and (eq_attr "type" "branch")
  37382. + (eq_attr "pipeline_model" "n9")))
  37383. + "n9_3r2w_ii, n9_3r2w_ex, n9_3r2w_mm, n9_3r2w_wb")
  37384. +
  37385. +;; LD, MUL, MAC, DIV
  37386. +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU
  37387. +(define_bypass 2
  37388. + "nds_n9_3r2w_load,\
  37389. + nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
  37390. + nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
  37391. + nds_n9_3r2w_div"
  37392. + "nds_n9_3r2w_alu, nds_n9_3r2w_alu_shift,\
  37393. + nds_n9_3r2w_pbsad, nds_n9_3r2w_pbsada,\
  37394. + nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
  37395. + nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
  37396. + nds_n9_3r2w_branch,\
  37397. + nds_n9_3r2w_div,\
  37398. + nds_n9_3r2w_load,nds_n9_3r2w_store,\
  37399. + nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
  37400. + nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
  37401. + nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12,\
  37402. + nds_n9_3r2w_store_multiple_1,nds_n9_3r2w_store_multiple_2, nds_n9_3r2w_store_multiple_3,\
  37403. + nds_n9_3r2w_store_multiple_4,nds_n9_3r2w_store_multiple_5, nds_n9_3r2w_store_multiple_6,\
  37404. + nds_n9_3r2w_store_multiple_7,nds_n9_3r2w_store_multiple_8, nds_n9_3r2w_store_multiple_12,\
  37405. + nds_n9_3r2w_mmu"
  37406. + "nds32_n9_3r2w_mm_to_ex_p"
  37407. +)
  37408. +
  37409. +;; LMW(N, N)
  37410. +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU
  37411. +(define_bypass 2
  37412. + "nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
  37413. + nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
  37414. + nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12"
  37415. + "nds_n9_3r2w_alu, nds_n9_3r2w_alu_shift,\
  37416. + nds_n9_3r2w_pbsad, nds_n9_3r2w_pbsada,\
  37417. + nds_n9_3r2w_mul_fast1, nds_n9_3r2w_mul_fast2, nds_n9_3r2w_mul_slow,\
  37418. + nds_n9_3r2w_mac_fast1, nds_n9_3r2w_mac_fast2, nds_n9_3r2w_mac_slow,\
  37419. + nds_n9_3r2w_branch,\
  37420. + nds_n9_3r2w_div,\
  37421. + nds_n9_3r2w_load,nds_n9_3r2w_store,\
  37422. + nds_n9_3r2w_load_multiple_1,nds_n9_3r2w_load_multiple_2, nds_n9_3r2w_load_multiple_3,\
  37423. + nds_n9_3r2w_load_multiple_4,nds_n9_3r2w_load_multiple_5, nds_n9_3r2w_load_multiple_6,\
  37424. + nds_n9_3r2w_load_multiple_7,nds_n9_3r2w_load_multiple_8, nds_n9_3r2w_load_multiple_12,\
  37425. + nds_n9_3r2w_store_multiple_1,nds_n9_3r2w_store_multiple_2, nds_n9_3r2w_store_multiple_3,\
  37426. + nds_n9_3r2w_store_multiple_4,nds_n9_3r2w_store_multiple_5, nds_n9_3r2w_store_multiple_6,\
  37427. + nds_n9_3r2w_store_multiple_7,nds_n9_3r2w_store_multiple_8, nds_n9_3r2w_store_multiple_12,\
  37428. + nds_n9_3r2w_mmu"
  37429. + "nds32_n9_last_load_to_ex_p"
  37430. +)
  37431. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32.opt gcc-4.9.4/gcc/config/nds32/nds32.opt
  37432. --- gcc-4.9.4.orig/gcc/config/nds32/nds32.opt 2014-01-02 23:23:26.000000000 +0100
  37433. +++ gcc-4.9.4/gcc/config/nds32/nds32.opt 2016-08-08 20:37:45.590273343 +0200
  37434. @@ -1,5 +1,5 @@
  37435. ; Options of Andes NDS32 cpu for GNU compiler
  37436. -; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  37437. +; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  37438. ; Contributed by Andes Technology Corporation.
  37439. ;
  37440. ; This file is part of GCC.
  37441. @@ -21,14 +21,31 @@
  37442. HeaderInclude
  37443. config/nds32/nds32-opts.h
  37444. -mbig-endian
  37445. -Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
  37446. +; ---------------------------------------------------------------
  37447. +; The following options are designed for aliasing and compatibility options.
  37448. +
  37449. +EB
  37450. +Target RejectNegative Alias(mbig-endian)
  37451. Generate code in big-endian mode.
  37452. -mlittle-endian
  37453. -Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
  37454. +EL
  37455. +Target RejectNegative Alias(mlittle-endian)
  37456. Generate code in little-endian mode.
  37457. +mfp-as-gp
  37458. +Target RejectNegative Alias(mforce-fp-as-gp)
  37459. +Force performing fp-as-gp optimization.
  37460. +
  37461. +mno-fp-as-gp
  37462. +Target RejectNegative Alias(mforbid-fp-as-gp)
  37463. +Forbid performing fp-as-gp optimization.
  37464. +
  37465. +m16bit
  37466. +Target Undocumented Alias(m16-bit)
  37467. +Generate 16-bit instructions.
  37468. +
  37469. +; ---------------------------------------------------------------
  37470. +
  37471. mreduced-regs
  37472. Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
  37473. Use reduced-set registers for register allocation.
  37474. @@ -37,14 +54,78 @@
  37475. Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
  37476. Use full-set registers for register allocation.
  37477. +; ---------------------------------------------------------------
  37478. +
  37479. +malways-align
  37480. +Target Mask(ALWAYS_ALIGN)
  37481. +Always align function entry, jump target and return address.
  37482. +
  37483. +malign-functions
  37484. +Target Mask(ALIGN_FUNCTION)
  37485. +Align function entry to 4 byte.
  37486. +
  37487. +mbig-endian
  37488. +Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
  37489. +Generate code in big-endian mode.
  37490. +
  37491. +mlittle-endian
  37492. +Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
  37493. +Generate code in little-endian mode.
  37494. +
  37495. +mforce-fp-as-gp
  37496. +Target Undocumented Mask(FORCE_FP_AS_GP)
  37497. +Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
  37498. +
  37499. +mforbid-fp-as-gp
  37500. +Target Undocumented Mask(FORBID_FP_AS_GP)
  37501. +Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
  37502. +
  37503. +minline-strcpy
  37504. +Target Undocumented Mask(INLINE_STRCPY)
  37505. +Inlining strcpy function.
  37506. +
  37507. +mload-store-opt
  37508. +Target Mask(LOAD_STORE_OPT)
  37509. +Enable load store optimization.
  37510. +
  37511. +mregrename
  37512. +Target Mask(REGRENAME_OPT)
  37513. +Enable target dependent register rename optimization.
  37514. +
  37515. +mgcse
  37516. +Target Mask(GCSE_OPT)
  37517. +Enable target dependent global CSE optimization.
  37518. +
  37519. +msoft-fp-arith-comm
  37520. +Target Mask(SOFT_FP_ARITH_COMM)
  37521. +Enable operand commutative for soft floating point arithmetic optimization.
  37522. +
  37523. +; ---------------------------------------------------------------
  37524. +
  37525. mcmov
  37526. Target Report Mask(CMOV)
  37527. Generate conditional move instructions.
  37528. -mperf-ext
  37529. -Target Report Mask(PERF_EXT)
  37530. +mhw-abs
  37531. +Target Report Mask(HW_ABS)
  37532. +Generate hardware abs instructions.
  37533. +
  37534. +mext-perf
  37535. +Target Report Mask(EXT_PERF)
  37536. Generate performance extension instructions.
  37537. +mext-perf2
  37538. +Target Report Mask(EXT_PERF2)
  37539. +Generate performance extension version 2 instructions.
  37540. +
  37541. +mext-string
  37542. +Target Report Mask(EXT_STRING)
  37543. +Generate string extension instructions.
  37544. +
  37545. +mext-dsp
  37546. +Target Report Mask(EXT_DSP)
  37547. +Generate DSP extension instructions.
  37548. +
  37549. mv3push
  37550. Target Report Mask(V3PUSH)
  37551. Generate v3 push25/pop25 instructions.
  37552. @@ -53,12 +134,16 @@
  37553. Target Report Mask(16_BIT)
  37554. Generate 16-bit instructions.
  37555. -mgp-direct
  37556. -Target Report Mask(GP_DIRECT)
  37557. -Generate GP base instructions directly.
  37558. +mrelax-hint
  37559. +Target Report Mask(RELAX_HINT)
  37560. +Insert relax hint for linker to do relaxation.
  37561. +
  37562. +mvh
  37563. +Target Report Mask(VH) Condition(!TARGET_LINUX_ABI)
  37564. +Enable Virtual Hosting support.
  37565. misr-vector-size=
  37566. -Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
  37567. +Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) Condition(!TARGET_LINUX_ABI)
  37568. Specify the size of each interrupt vector, which must be 4 or 16.
  37569. mcache-block-size=
  37570. @@ -71,32 +156,348 @@
  37571. Enum
  37572. Name(nds32_arch_type) Type(enum nds32_arch_type)
  37573. +Known arch types (for use with the -march= option):
  37574. EnumValue
  37575. Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
  37576. EnumValue
  37577. +Enum(nds32_arch_type) String(v2j) Value(ARCH_V2J)
  37578. +
  37579. +EnumValue
  37580. Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
  37581. EnumValue
  37582. +Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J)
  37583. +
  37584. +EnumValue
  37585. Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
  37586. -mforce-fp-as-gp
  37587. -Target Report Mask(FORCE_FP_AS_GP)
  37588. -Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
  37589. +EnumValue
  37590. +Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)
  37591. -mforbid-fp-as-gp
  37592. -Target Report Mask(FORBID_FP_AS_GP)
  37593. -Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
  37594. +EnumValue
  37595. +Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)
  37596. +
  37597. +mcpu=
  37598. +Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
  37599. +Specify the cpu for pipeline model.
  37600. +
  37601. +Enum
  37602. +Name(nds32_cpu_type) Type(enum nds32_cpu_type)
  37603. +Known cpu types (for use with the -mcpu= option):
  37604. +
  37605. +EnumValue
  37606. +Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
  37607. +
  37608. +EnumValue
  37609. +Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
  37610. +
  37611. +EnumValue
  37612. +Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
  37613. +
  37614. +EnumValue
  37615. +Enum(nds32_cpu_type) String(n801) Value(CPU_N8)
  37616. +
  37617. +EnumValue
  37618. +Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)
  37619. +
  37620. +EnumValue
  37621. +Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)
  37622. +
  37623. +EnumValue
  37624. +Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
  37625. +
  37626. +EnumValue
  37627. +Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
  37628. +
  37629. +EnumValue
  37630. +Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
  37631. +
  37632. +EnumValue
  37633. +Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
  37634. +
  37635. +EnumValue
  37636. +Enum(nds32_cpu_type) String(n9) Value(CPU_N9)
  37637. +
  37638. +EnumValue
  37639. +Enum(nds32_cpu_type) String(n903) Value(CPU_N9)
  37640. +
  37641. +EnumValue
  37642. +Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)
  37643. +
  37644. +EnumValue
  37645. +Enum(nds32_cpu_type) String(n968) Value(CPU_N9)
  37646. +
  37647. +EnumValue
  37648. +Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)
  37649. +
  37650. +EnumValue
  37651. +Enum(nds32_cpu_type) String(n10) Value(CPU_N10)
  37652. +
  37653. +EnumValue
  37654. +Enum(nds32_cpu_type) String(n1033) Value(CPU_N10)
  37655. +
  37656. +EnumValue
  37657. +Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10)
  37658. +
  37659. +EnumValue
  37660. +Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10)
  37661. +
  37662. +EnumValue
  37663. +Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10)
  37664. +
  37665. +EnumValue
  37666. +Enum(nds32_cpu_type) String(n1068) Value(CPU_N10)
  37667. +
  37668. +EnumValue
  37669. +Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10)
  37670. +
  37671. +EnumValue
  37672. +Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10)
  37673. +
  37674. +EnumValue
  37675. +Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10)
  37676. +
  37677. +EnumValue
  37678. +Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10)
  37679. +
  37680. +EnumValue
  37681. +Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10)
  37682. +
  37683. +EnumValue
  37684. +Enum(nds32_cpu_type) String(d10) Value(CPU_N10)
  37685. +
  37686. +EnumValue
  37687. +Enum(nds32_cpu_type) String(d1088) Value(CPU_N10)
  37688. +
  37689. +EnumValue
  37690. +Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10)
  37691. +
  37692. +EnumValue
  37693. +Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10)
  37694. +
  37695. +EnumValue
  37696. +Enum(nds32_cpu_type) String(n12) Value(CPU_N12)
  37697. +
  37698. +EnumValue
  37699. +Enum(nds32_cpu_type) String(n1213) Value(CPU_N12)
  37700. +
  37701. +EnumValue
  37702. +Enum(nds32_cpu_type) String(n1233) Value(CPU_N12)
  37703. +
  37704. +EnumValue
  37705. +Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12)
  37706. +
  37707. +EnumValue
  37708. +Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12)
  37709. +
  37710. +EnumValue
  37711. +Enum(nds32_cpu_type) String(n13) Value(CPU_N13)
  37712. +
  37713. +EnumValue
  37714. +Enum(nds32_cpu_type) String(n1337) Value(CPU_N13)
  37715. +
  37716. +EnumValue
  37717. +Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13)
  37718. +
  37719. +EnumValue
  37720. +Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13)
  37721. +
  37722. +EnumValue
  37723. +Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)
  37724. +
  37725. +mmemory-model=
  37726. +Target RejectNegative Joined Enum(nds32_memory_model_type) Var(nds32_memory_model_option) Init(MEMORY_MODEL_FAST)
  37727. +Specify the memory model, fast or slow memory.
  37728. +
  37729. +Enum
  37730. +Name(nds32_memory_model_type) Type(enum nds32_memory_model_type)
  37731. +
  37732. +EnumValue
  37733. +Enum(nds32_memory_model_type) String(slow) Value(MEMORY_MODEL_SLOW)
  37734. +
  37735. +EnumValue
  37736. +Enum(nds32_memory_model_type) String(fast) Value(MEMORY_MODEL_FAST)
  37737. +
  37738. +mfloat-abi=
  37739. +Target RejectNegative Joined Enum(float_abi_type) Var(nds32_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
  37740. +Specify if floating point hardware should be used. The valid value is : soft, hard.
  37741. +
  37742. +Enum
  37743. +Name(float_abi_type) Type(enum float_abi_type)
  37744. +Known floating-point ABIs (for use with the -mfloat-abi= option):
  37745. +
  37746. +EnumValue
  37747. +Enum(float_abi_type) String(soft) Value(NDS32_FLOAT_ABI_SOFT)
  37748. +
  37749. +EnumValue
  37750. +Enum(float_abi_type) String(hard) Value(NDS32_FLOAT_ABI_HARD)
  37751. +
  37752. +mconfig-fpu=
  37753. +Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
  37754. +Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.
  37755. +
  37756. +Enum
  37757. +Name(float_reg_number) Type(enum float_reg_number)
  37758. +Known floating-point number of registers (for use with the -mconfig-fpu= option):
  37759. +
  37760. +EnumValue
  37761. +Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)
  37762. +
  37763. +EnumValue
  37764. +Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)
  37765. +
  37766. +EnumValue
  37767. +Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)
  37768. +
  37769. +EnumValue
  37770. +Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)
  37771. +
  37772. +EnumValue
  37773. +Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)
  37774. +
  37775. +EnumValue
  37776. +Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)
  37777. +
  37778. +EnumValue
  37779. +Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)
  37780. +
  37781. +EnumValue
  37782. +Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)
  37783. +
  37784. +mconfig-mul=
  37785. +Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
  37786. +Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.
  37787. +
  37788. +Enum
  37789. +Name(nds32_mul_type) Type(enum nds32_mul_type)
  37790. +
  37791. +EnumValue
  37792. +Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)
  37793. +
  37794. +EnumValue
  37795. +Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)
  37796. +
  37797. +EnumValue
  37798. +Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)
  37799. +
  37800. +mconfig-register-ports=
  37801. +Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
  37802. +Specify how many read/write ports for n9/n10 cores. The value should be 3r2w or 2r1w.
  37803. +
  37804. +Enum
  37805. +Name(nds32_register_ports) Type(enum nds32_register_ports)
  37806. +
  37807. +EnumValue
  37808. +Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)
  37809. +
  37810. +EnumValue
  37811. +Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
  37812. +
  37813. +mifc
  37814. +Target Report Mask(IFC)
  37815. +Use special directives to guide linker doing ifc optimization.
  37816. mex9
  37817. Target Report Mask(EX9)
  37818. Use special directives to guide linker doing ex9 optimization.
  37819. +mprint-stall-cycles
  37820. +Target Report Mask(PRINT_STALLS)
  37821. +Print stall cycles due to structural or data dependencies. It should be used with the option '-S'.
  37822. +Note that stall cycles are determined by the compiler's pipeline model and it may not be precise.
  37823. +
  37824. mctor-dtor
  37825. Target Report
  37826. Enable constructor/destructor feature.
  37827. +mcrt-arg
  37828. +Target Report
  37829. +Enable argc/argv passed by simulator.
  37830. +
  37831. mrelax
  37832. Target Report
  37833. Guide linker to relax instructions.
  37834. +
  37835. +minnermost-loop
  37836. +Target Report Mask(INNERMOST_LOOP)
  37837. +Insert the innermost loop directive.
  37838. +
  37839. +mext-fpu-fma
  37840. +Target Report Mask(EXT_FPU_FMA)
  37841. +Generate floating-point multiply-accumulation instructions.
  37842. +
  37843. +mext-fpu-sp
  37844. +Target Report Mask(FPU_SINGLE)
  37845. +Generate single-precision floating-point instructions.
  37846. +
  37847. +mext-fpu-dp
  37848. +Target Report Mask(FPU_DOUBLE)
  37849. +Generate double-precision floating-point instructions.
  37850. +
  37851. +mext-zol
  37852. +Target Report Mask(HWLOOP)
  37853. +Insert the hardware loop directive.
  37854. +
  37855. +mforce-no-ext-zol
  37856. +Target Undocumented Report Mask(FORCE_NO_HWLOOP)
  37857. +Force disable hardware loop, even use -mext-zol.
  37858. +
  37859. +mforce-no-ext-dsp
  37860. +Target Undocumented Report Mask(FORCE_NO_EXT_DSP)
  37861. +Force disable hardware loop, even use -mext-dsp.
  37862. +
  37863. +msched-prolog-epilog
  37864. +Target Var(flag_sched_prolog_epilog) Init(1)
  37865. +Permit scheduling of a function's prologue and epilogue sequence.
  37866. +
  37867. +mret-in-naked-func
  37868. +Target Var(flag_ret_in_naked_func) Init(1)
  37869. +Generate return instruction in naked function.
  37870. +
  37871. +malways-save-lp
  37872. +Target Var(flag_always_save_lp) Init(0)
  37873. +Always save $lp in the stack.
  37874. +
  37875. +; ---------------------------------------------------------------
  37876. +; The following options are designed for compatibility issue.
  37877. +; Hopefully these obsolete options will be removed one day.
  37878. +
  37879. +mg
  37880. +Target Undocumented Warn(%qs is deprecated and has no effect)
  37881. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37882. +
  37883. +mdx-regs
  37884. +Target Undocumented Warn(%qs is deprecated and has no effect)
  37885. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37886. +
  37887. +mexpand-isr
  37888. +Target Undocumented Warn(%qs is deprecated and has no effect)
  37889. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37890. +
  37891. +mcrt-arg=yes
  37892. +Target Undocumented Warn(%qs is deprecated and has no effect, use -mcrt-arg instead)
  37893. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37894. +
  37895. +mcrt-cpp=yes
  37896. +Target Undocumented Warn(%qs is deprecated and has no effect, use -mctor-dtor instead)
  37897. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37898. +
  37899. +mcrt-exit=yes
  37900. +Target Undocumented Warn(%qs is deprecated and has no effect, use -mctor-dtor instead)
  37901. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37902. +
  37903. +Os1
  37904. +Target Undocumented
  37905. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37906. +
  37907. +Os2
  37908. +Target Undocumented
  37909. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37910. +
  37911. +Os3
  37912. +Target Undocumented
  37913. +Obsolete option. Users SHOULD NOT use this option in the command line.
  37914. +
  37915. +; ---------------------------------------------------------------
  37916. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-opts.h gcc-4.9.4/gcc/config/nds32/nds32-opts.h
  37917. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-opts.h 2014-01-02 23:23:26.000000000 +0100
  37918. +++ gcc-4.9.4/gcc/config/nds32/nds32-opts.h 2016-08-08 20:37:45.510270246 +0200
  37919. @@ -1,5 +1,5 @@
  37920. /* Definitions for option handling of Andes NDS32 cpu for GNU compiler
  37921. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  37922. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  37923. Contributed by Andes Technology Corporation.
  37924. This file is part of GCC.
  37925. @@ -22,14 +22,80 @@
  37926. #define NDS32_OPTS_H
  37927. #define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
  37928. -#define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
  37929. +#define NDS32_DEFAULT_ISR_VECTOR_SIZE TARGET_DEFAULT_ISR_VECTOR_SIZE
  37930. /* The various ANDES ISA. */
  37931. enum nds32_arch_type
  37932. {
  37933. ARCH_V2,
  37934. + ARCH_V2J,
  37935. ARCH_V3,
  37936. - ARCH_V3M
  37937. + ARCH_V3J,
  37938. + ARCH_V3M,
  37939. + ARCH_V3F,
  37940. + ARCH_V3S
  37941. };
  37942. +/* The various ANDES CPU. */
  37943. +enum nds32_cpu_type
  37944. +{
  37945. + CPU_N7,
  37946. + CPU_N8,
  37947. + CPU_E8,
  37948. + CPU_N9,
  37949. + CPU_N10,
  37950. + CPU_N12,
  37951. + CPU_N13,
  37952. + CPU_SIMPLE
  37953. +};
  37954. +
  37955. +/* The code model defines the address generation strategy. */
  37956. +enum nds32_memory_model_type
  37957. +{
  37958. + MEMORY_MODEL_SLOW,
  37959. + MEMORY_MODEL_FAST
  37960. +};
  37961. +
  37962. +/* The code model defines the address generation strategy. */
  37963. +enum nds32_cmodel_type
  37964. +{
  37965. + CMODEL_SMALL,
  37966. + CMODEL_MEDIUM,
  37967. + CMODEL_LARGE
  37968. +};
  37969. +
  37970. +/* Multiply instruction configuration. */
  37971. +enum nds32_mul_type
  37972. +{
  37973. + MUL_TYPE_FAST_1,
  37974. + MUL_TYPE_FAST_2,
  37975. + MUL_TYPE_SLOW
  37976. +};
  37977. +
  37978. +/* Register ports configuration. */
  37979. +enum nds32_register_ports
  37980. +{
  37981. + REG_PORT_3R2W,
  37982. + REG_PORT_2R1W
  37983. +};
  37984. +
  37985. +/* Which ABI to use. */
  37986. +enum float_abi_type
  37987. +{
  37988. + NDS32_FLOAT_ABI_SOFT,
  37989. + NDS32_FLOAT_ABI_HARD
  37990. +};
  37991. +
  37992. +/* The various FPU number of registers. */
  37993. +enum float_reg_number
  37994. +{
  37995. + NDS32_CONFIG_FPU_0,
  37996. + NDS32_CONFIG_FPU_1,
  37997. + NDS32_CONFIG_FPU_2,
  37998. + NDS32_CONFIG_FPU_3,
  37999. + NDS32_CONFIG_FPU_4,
  38000. + NDS32_CONFIG_FPU_5,
  38001. + NDS32_CONFIG_FPU_6,
  38002. + NDS32_CONFIG_FPU_7
  38003. +};
  38004. #endif
  38005. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-peephole2.md gcc-4.9.4/gcc/config/nds32/nds32-peephole2.md
  38006. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-peephole2.md 2014-01-02 23:23:26.000000000 +0100
  38007. +++ gcc-4.9.4/gcc/config/nds32/nds32-peephole2.md 2016-08-08 20:37:45.510270246 +0200
  38008. @@ -1,5 +1,5 @@
  38009. ;; define_peephole2 optimization patterns of Andes NDS32 cpu for GNU compiler
  38010. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  38011. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  38012. ;; Contributed by Andes Technology Corporation.
  38013. ;;
  38014. ;; This file is part of GCC.
  38015. @@ -19,7 +19,176 @@
  38016. ;; <http://www.gnu.org/licenses/>.
  38017. -;; Use define_peephole and define_peephole2 to handle possible
  38018. -;; target-specific optimization in this file.
  38019. +;; Use define_split, define_peephole, and define_peephole2 to
  38020. +;; handle possible target-specific optimization in this file.
  38021. ;; ------------------------------------------------------------------------
  38022. +;; Try to utilize 16-bit instruction by swap operand if possible.
  38023. +;; ------------------------------------------------------------------------
  38024. +
  38025. +;; Try to make add as add45.
  38026. +(define_peephole2
  38027. + [(set (match_operand:QIHISI 0 "register_operand" "")
  38028. + (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "")
  38029. + (match_operand:QIHISI 2 "register_operand" "")))]
  38030. + "reload_completed
  38031. + && TARGET_16_BIT
  38032. + && REGNO (operands[0]) == REGNO (operands[2])
  38033. + && REGNO (operands[0]) != REGNO (operands[1])
  38034. + && TEST_HARD_REG_BIT (reg_class_contents[MIDDLE_REGS], REGNO (operands[0]))"
  38035. + [(set (match_dup 0) (plus:QIHISI (match_dup 2) (match_dup 1)))])
  38036. +
  38037. +;; Try to make xor/ior/and/mult as xor33/ior33/and33/mult33.
  38038. +(define_peephole2
  38039. + [(set (match_operand:SI 0 "register_operand" "")
  38040. + (match_operator:SI 1 "nds32_have_33_inst_operator"
  38041. + [(match_operand:SI 2 "register_operand" "")
  38042. + (match_operand:SI 3 "register_operand" "")]))]
  38043. + "reload_completed
  38044. + && TARGET_16_BIT
  38045. + && REGNO (operands[0]) == REGNO (operands[3])
  38046. + && REGNO (operands[0]) != REGNO (operands[2])
  38047. + && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[0]))
  38048. + && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[2]))"
  38049. + [(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (match_dup 2)]))])
  38050. +
  38051. +(define_peephole
  38052. + [(set (match_operand:SI 0 "register_operand" "")
  38053. + (match_operand:SI 1 "register_operand" ""))
  38054. + (set (match_operand:SI 2 "register_operand" "")
  38055. + (match_operand:SI 3 "register_operand" ""))]
  38056. + "TARGET_16_BIT
  38057. + && !TARGET_ISA_V2
  38058. + && NDS32_IS_GPR_REGNUM (REGNO (operands[0]))
  38059. + && NDS32_IS_GPR_REGNUM (REGNO (operands[1]))
  38060. + && ((REGNO (operands[0]) & 0x1) == 0)
  38061. + && ((REGNO (operands[1]) & 0x1) == 0)
  38062. + && (REGNO (operands[0]) + 1) == REGNO (operands[2])
  38063. + && (REGNO (operands[1]) + 1) == REGNO (operands[3])"
  38064. + "movd44\t%0, %1"
  38065. + [(set_attr "type" "alu")
  38066. + (set_attr "length" "2")])
  38067. +
  38068. +;; Merge two fcpyss to fcpysd.
  38069. +(define_peephole2
  38070. + [(set (match_operand:SF 0 "float_even_register_operand" "")
  38071. + (match_operand:SF 1 "float_even_register_operand" ""))
  38072. + (set (match_operand:SF 2 "float_odd_register_operand" "")
  38073. + (match_operand:SF 3 "float_odd_register_operand" ""))]
  38074. + "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  38075. + && REGNO (operands[0]) == REGNO (operands[2]) - 1
  38076. + && REGNO (operands[1]) == REGNO (operands[3]) - 1"
  38077. + [(set (match_dup 4) (match_dup 5))]
  38078. + {
  38079. + operands[4] = gen_rtx_REG (DFmode, REGNO (operands[0]));
  38080. + operands[5] = gen_rtx_REG (DFmode, REGNO (operands[1]));
  38081. + })
  38082. +
  38083. +(define_peephole2
  38084. + [(set (match_operand:SF 0 "float_odd_register_operand" "")
  38085. + (match_operand:SF 1 "float_odd_register_operand" ""))
  38086. + (set (match_operand:SF 2 "float_even_register_operand" "")
  38087. + (match_operand:SF 3 "float_even_register_operand" ""))]
  38088. + "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
  38089. + && REGNO (operands[2]) == REGNO (operands[0]) - 1
  38090. + && REGNO (operands[3]) == REGNO (operands[1]) - 1"
  38091. + [(set (match_dup 4) (match_dup 5))]
  38092. + {
  38093. + operands[4] = gen_rtx_REG (DFmode, REGNO (operands[2]));
  38094. + operands[5] = gen_rtx_REG (DFmode, REGNO (operands[3]));
  38095. + })
  38096. +
  38097. +;; Merge two flsi to fldi.
  38098. +(define_peephole2
  38099. + [(set (match_operand:SF 0 "float_even_register_operand" "")
  38100. + (match_operand:SF 1 "memory_operand" ""))
  38101. + (set (match_operand:SF 2 "float_odd_register_operand" "")
  38102. + (match_operand:SF 3 "memory_operand" ""))]
  38103. + "REGNO (operands[0]) == REGNO (operands[2]) - 1
  38104. + && nds32_memory_merge_peep_p (operands[3], operands[1])"
  38105. + [(set (match_dup 0) (match_dup 1))]
  38106. +{
  38107. + operands[1] = widen_memory_access (operands[3], DFmode, 0);
  38108. + operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));
  38109. +})
  38110. +
  38111. +(define_peephole2
  38112. + [(set (match_operand:SF 0 "float_odd_register_operand" "")
  38113. + (match_operand:SF 1 "memory_operand" ""))
  38114. + (set (match_operand:SF 2 "float_even_register_operand" "")
  38115. + (match_operand:SF 3 "memory_operand" ""))]
  38116. + "REGNO (operands[2]) == REGNO (operands[0]) - 1
  38117. + && nds32_memory_merge_peep_p (operands[1], operands[3])"
  38118. + [(set (match_dup 0) (match_dup 1))]
  38119. +{
  38120. + operands[1] = widen_memory_access (operands[1], DFmode, 0);
  38121. + operands[0] = gen_rtx_REG (DFmode, REGNO (operands[2]));
  38122. +})
  38123. +
  38124. +;; Merge two fssi to fsdi.
  38125. +(define_peephole2
  38126. + [(set (match_operand:SF 0 "memory_operand" "")
  38127. + (match_operand:SF 1 "float_even_register_operand" ""))
  38128. + (set (match_operand:SF 2 "memory_operand" "")
  38129. + (match_operand:SF 3 "float_odd_register_operand" ""))]
  38130. + "REGNO (operands[1]) == REGNO (operands[3]) - 1
  38131. + && nds32_memory_merge_peep_p (operands[2], operands[0])"
  38132. + [(set (match_dup 0) (match_dup 1))]
  38133. +{
  38134. + operands[0] = widen_memory_access (operands[2], DFmode, 0);
  38135. + operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));
  38136. +})
  38137. +
  38138. +(define_peephole2
  38139. + [(set (match_operand:SF 0 "memory_operand" "")
  38140. + (match_operand:SF 1 "float_odd_register_operand" ""))
  38141. + (set (match_operand:SF 2 "memory_operand" "")
  38142. + (match_operand:SF 3 "float_even_register_operand" ""))]
  38143. + "REGNO (operands[3]) == REGNO (operands[1]) - 1
  38144. + && nds32_memory_merge_peep_p (operands[0], operands[2])"
  38145. + [(set (match_dup 0) (match_dup 1))]
  38146. +{
  38147. + operands[0] = widen_memory_access (operands[0], DFmode, 0);
  38148. + operands[1] = gen_rtx_REG (DFmode, REGNO (operands[3]));
  38149. +})
  38150. +
  38151. +;; ------------------------------------------------------------------------
  38152. +;; GCC will prefer [u]divmodsi3 rather than [u]divsi3 even remainder is
  38153. +;; unused, so we use split to drop mod operation for lower register pressure.
  38154. +
  38155. +(define_split
  38156. + [(set (match_operand:SI 0 "register_operand")
  38157. + (div:SI (match_operand:SI 1 "register_operand")
  38158. + (match_operand:SI 2 "register_operand")))
  38159. + (set (match_operand:SI 3 "register_operand")
  38160. + (mod:SI (match_dup 1) (match_dup 2)))]
  38161. + "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL
  38162. + && can_create_pseudo_p ()"
  38163. + [(set (match_dup 0)
  38164. + (div:SI (match_dup 1)
  38165. + (match_dup 2)))])
  38166. +
  38167. +(define_split
  38168. + [(set (match_operand:SI 0 "register_operand")
  38169. + (udiv:SI (match_operand:SI 1 "register_operand")
  38170. + (match_operand:SI 2 "register_operand")))
  38171. + (set (match_operand:SI 3 "register_operand")
  38172. + (umod:SI (match_dup 1) (match_dup 2)))]
  38173. + "find_regno_note (insn, REG_UNUSED, REGNO (operands[3])) != NULL
  38174. + && can_create_pseudo_p ()"
  38175. + [(set (match_dup 0)
  38176. + (udiv:SI (match_dup 1)
  38177. + (match_dup 2)))])
  38178. +
  38179. +(define_peephole2
  38180. + [(set (match_operand:DI 0 "register_operand")
  38181. + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand"))
  38182. + (sign_extend:DI (match_operand:SI 2 "register_operand"))))]
  38183. + "NDS32_EXT_DSP_P ()
  38184. + && peep2_regno_dead_p (1, WORDS_BIG_ENDIAN ? REGNO (operands[0]) + 1 : REGNO (operands[0]))"
  38185. + [(const_int 1)]
  38186. +{
  38187. + rtx highpart = nds32_di_high_part_subreg (operands[0]);
  38188. + emit_insn (gen_smulsi3_highpart (highpart, operands[1], operands[2]));
  38189. + DONE;
  38190. +})
  38191. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c gcc-4.9.4/gcc/config/nds32/nds32-pipelines-auxiliary.c
  38192. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-pipelines-auxiliary.c 1970-01-01 01:00:00.000000000 +0100
  38193. +++ gcc-4.9.4/gcc/config/nds32/nds32-pipelines-auxiliary.c 2016-08-08 20:37:45.582273034 +0200
  38194. @@ -0,0 +1,2341 @@
  38195. +/* Auxiliary functions for pipeline descriptions pattern of Andes
  38196. + NDS32 cpu for GNU compiler
  38197. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  38198. + Contributed by Andes Technology Corporation.
  38199. +
  38200. + This file is part of GCC.
  38201. +
  38202. + GCC is free software; you can redistribute it and/or modify it
  38203. + under the terms of the GNU General Public License as published
  38204. + by the Free Software Foundation; either version 3, or (at your
  38205. + option) any later version.
  38206. +
  38207. + GCC is distributed in the hope that it will be useful, but WITHOUT
  38208. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  38209. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  38210. + License for more details.
  38211. +
  38212. + You should have received a copy of the GNU General Public License
  38213. + along with GCC; see the file COPYING3. If not see
  38214. + <http://www.gnu.org/licenses/>. */
  38215. +
  38216. +/* ------------------------------------------------------------------------ */
  38217. +
  38218. +#include <set>
  38219. +#include "config.h"
  38220. +#include "system.h"
  38221. +#include "coretypes.h"
  38222. +#include "tm.h"
  38223. +#include "tree.h"
  38224. +#include "rtl.h"
  38225. +#include "regs.h"
  38226. +#include "hard-reg-set.h"
  38227. +#include "insn-config.h" /* Required by recog.h. */
  38228. +#include "conditions.h"
  38229. +#include "output.h"
  38230. +#include "insn-attr.h" /* For DFA state_t. */
  38231. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  38232. +#include "reload.h" /* For push_reload(). */
  38233. +#include "flags.h"
  38234. +#include "function.h"
  38235. +#include "expr.h"
  38236. +#include "recog.h"
  38237. +#include "diagnostic-core.h"
  38238. +#include "df.h"
  38239. +#include "tm_p.h"
  38240. +#include "tm-constrs.h"
  38241. +#include "optabs.h" /* For GEN_FCN. */
  38242. +#include "target.h"
  38243. +#include "target-def.h"
  38244. +#include "langhooks.h" /* For add_builtin_function(). */
  38245. +#include "ggc.h"
  38246. +#include "tree-pass.h"
  38247. +
  38248. +/* ------------------------------------------------------------------------ */
  38249. +
  38250. +namespace nds32 {
  38251. +namespace scheduling {
  38252. +
  38253. +/* Classify the memory access direction. It's unknown if the offset register
  38254. + is not a constant value. */
  38255. +enum memory_access_direction
  38256. +{
  38257. + MEM_ACCESS_DIR_POS,
  38258. + MEM_ACCESS_DIR_NEG,
  38259. + MEM_ACCESS_DIR_UNKNOWN
  38260. +};
  38261. +
  38262. +/* This class provides some wrappers of the DFA scheduler. Due to the design
  38263. + drawback of the DFA scheduler, creating two instances at the same time is
  38264. + now allowed. Use the loosest relationship such as 'dependency' instead of
  38265. + 'aggregation' or 'composition' can minimize this issue. */
  38266. +class pipeline_simulator
  38267. +{
  38268. +public:
  38269. + pipeline_simulator ();
  38270. + ~pipeline_simulator ();
  38271. +
  38272. + void advance_cycle (int cycles = 1);
  38273. + int query_latency(rtx producer, rtx consumer) const;
  38274. + int issue_insn (rtx insn);
  38275. + int force_issue_insn (rtx insn);
  38276. +
  38277. +private:
  38278. + static bool gcc_dfa_initialized_;
  38279. + state_t state_;
  38280. +};
  38281. +
  38282. +/* Insert pseudo NOPs so that we can see stall cycles caused by structural or
  38283. + data hazards in the assembly code. The design of this class is similar to
  38284. + the 'template method' pattern, but we don't need to maintain multiple
  38285. + customized algorithms at the same time. Hence this class has no virtual
  38286. + functions providing further customizations. */
  38287. +class stall_inserter
  38288. +{
  38289. +private:
  38290. + enum dep_type { RES_DEP, DATA_DEP };
  38291. +
  38292. +public:
  38293. + void insert_stalls ();
  38294. +
  38295. +private:
  38296. + static void compute_bb_for_insn_safe ();
  38297. + static rtx emit_pseudo_nop_before (rtx insn, int cycles, enum dep_type type);
  38298. +
  38299. + void insert_structural_hazard_stalls ();
  38300. + void insert_data_hazard_stalls ();
  38301. + void emit_pseudo_nops_for_data_hazards (rtx insn,
  38302. + pipeline_simulator &simulator);
  38303. +};
  38304. +
  38305. +static unsigned int nds32_print_stalls (void);
  38306. +
  38307. +const pass_data pass_data_nds32_print_stalls =
  38308. +{
  38309. + RTL_PASS, /* type */
  38310. + "print_stalls", /* name */
  38311. + OPTGROUP_NONE, /* optinfo_flags */
  38312. + false, /* has_gate */
  38313. + true, /* has_execute */
  38314. + TV_MACH_DEP, /* tv_id */
  38315. + 0, /* properties_required */
  38316. + 0, /* properties_provided */
  38317. + 0, /* properties_destroyed */
  38318. + 0, /* todo_flags_start */
  38319. + TODO_verify_rtl_sharing, /* todo_flags_finish */
  38320. +};
  38321. +
  38322. +class pass_nds32_print_stalls : public rtl_opt_pass
  38323. +{
  38324. +public:
  38325. + pass_nds32_print_stalls (gcc::context *ctxt)
  38326. + : rtl_opt_pass (pass_data_nds32_print_stalls, ctxt)
  38327. + {}
  38328. +
  38329. + /* opt_pass methods: */
  38330. + unsigned int execute () { return nds32_print_stalls (); }
  38331. +};
  38332. +
  38333. +rtl_opt_pass *
  38334. +make_pass_nds32_print_stalls (gcc::context *ctxt)
  38335. +{
  38336. + return new pass_nds32_print_stalls (ctxt);
  38337. +}
  38338. +
  38339. +bool pipeline_simulator::gcc_dfa_initialized_ = false;
  38340. +
  38341. +/* A safe wrapper to the function reg_overlap_mentioned_p (). */
  38342. +bool
  38343. +reg_overlap_p (rtx x, rtx in)
  38344. +{
  38345. + if (x == NULL_RTX || in == NULL_RTX)
  38346. + return false;
  38347. +
  38348. + return static_cast <bool> (reg_overlap_mentioned_p (x, in));
  38349. +}
  38350. +
  38351. +/* Get the rtx in the PATTERN field of an insn. If INSN is not an insn,
  38352. + the funciton doesn't change anything and returns it directly. */
  38353. +rtx
  38354. +extract_pattern_from_insn (rtx insn)
  38355. +{
  38356. + if (INSN_P (insn))
  38357. + return PATTERN (insn);
  38358. +
  38359. + return insn;
  38360. +}
  38361. +
  38362. +/* Get the number of elements in a parallel rtx. */
  38363. +size_t
  38364. +parallel_elements (rtx parallel_rtx)
  38365. +{
  38366. + parallel_rtx = extract_pattern_from_insn (parallel_rtx);
  38367. + gcc_assert (GET_CODE (parallel_rtx) == PARALLEL);
  38368. +
  38369. + return XVECLEN (parallel_rtx, 0);
  38370. +}
  38371. +
  38372. +/* Extract an rtx from a parallel rtx with index NTH. If NTH is a negative
  38373. + value, the function returns the last NTH rtx. */
  38374. +rtx
  38375. +parallel_element (rtx parallel_rtx, int nth)
  38376. +{
  38377. + parallel_rtx = extract_pattern_from_insn (parallel_rtx);
  38378. + gcc_assert (GET_CODE (parallel_rtx) == PARALLEL);
  38379. +
  38380. + int len = parallel_elements (parallel_rtx);
  38381. +
  38382. + if (nth >= 0)
  38383. + {
  38384. + if (nth >= len)
  38385. + return NULL_RTX;
  38386. +
  38387. + return XVECEXP (parallel_rtx, 0, nth);
  38388. + }
  38389. + else
  38390. + {
  38391. + if (len + nth < 0)
  38392. + return NULL_RTX;
  38393. +
  38394. + return XVECEXP (parallel_rtx, 0, len + nth);
  38395. + }
  38396. +}
  38397. +
  38398. +/* Return true if an insn is a pseudo NOP that is not a real instruction
  38399. + occupying a real cycle and space of the text section. */
  38400. +bool
  38401. +insn_pseudo_nop_p (rtx insn)
  38402. +{
  38403. + if (INSN_CODE (insn) == CODE_FOR_nop_data_dep
  38404. + || INSN_CODE (insn) == CODE_FOR_nop_res_dep)
  38405. + return true;
  38406. +
  38407. + return false;
  38408. +}
  38409. +
  38410. +/* Indicate whether an insn is a real insn which occupy at least one cycle
  38411. + or not. The determination cannot be target-independent because some targets
  38412. + use UNSPEC or UNSPEC_VOLATILE insns to represent real instructions. */
  38413. +bool
  38414. +insn_executable_p (rtx insn)
  38415. +{
  38416. + if (!INSN_P (insn))
  38417. + return false;
  38418. +
  38419. + if (insn_pseudo_nop_p (insn))
  38420. + return true;
  38421. +
  38422. + if (get_attr_length (insn) == 0)
  38423. + return false;
  38424. +
  38425. + switch (GET_CODE (PATTERN (insn)))
  38426. + {
  38427. + case CONST_INT:
  38428. + case USE:
  38429. + case CLOBBER:
  38430. + case ADDR_VEC:
  38431. + case ADDR_DIFF_VEC:
  38432. + case UNSPEC:
  38433. + case UNSPEC_VOLATILE:
  38434. + return false;
  38435. +
  38436. + default:
  38437. + return true;
  38438. + }
  38439. +
  38440. + return true;
  38441. +}
  38442. +
  38443. +/* Return true if an insn is not marked as deleted. */
  38444. +bool
  38445. +insn_deleted_p (rtx insn)
  38446. +{
  38447. + if (INSN_DELETED_P (insn))
  38448. + return true;
  38449. +
  38450. + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED)
  38451. + return true;
  38452. +
  38453. + return false;
  38454. +}
  38455. +
  38456. +/* Calculate the cycle distance between two insns in pipeline view.
  38457. + Hence each insn can be treated as one cycle.
  38458. + TODO: multi-cycle insns should be handled
  38459. + specially, but we haven't done it here. */
  38460. +int
  38461. +cycle_distance (rtx from, rtx to)
  38462. +{
  38463. + int count = 1;
  38464. +
  38465. + for (from = NEXT_INSN (from); from && from != to; from = NEXT_INSN (from))
  38466. + {
  38467. + if (!insn_executable_p (from))
  38468. + continue;
  38469. +
  38470. + if (insn_pseudo_nop_p (from))
  38471. + count += INTVAL (XVECEXP (PATTERN (from), 0, 0));
  38472. + else
  38473. + ++count;
  38474. + }
  38475. +
  38476. + return count;
  38477. +}
  38478. +
  38479. +/* Extract the MEM rtx from a load/store insn. */
  38480. +rtx
  38481. +extract_mem_rtx (rtx insn)
  38482. +{
  38483. + rtx body = PATTERN (insn);
  38484. +
  38485. + switch (get_attr_type (insn))
  38486. + {
  38487. + case TYPE_LOAD:
  38488. + if (MEM_P (SET_SRC (body)))
  38489. + return SET_SRC (body);
  38490. +
  38491. + /* unaligned address: (unspec [(mem)]) */
  38492. + if (GET_CODE (SET_SRC (body)) == UNSPEC)
  38493. + {
  38494. + gcc_assert (MEM_P (XVECEXP (SET_SRC (body), 0, 0)));
  38495. + return XVECEXP (SET_SRC (body), 0, 0);
  38496. + }
  38497. +
  38498. + /* (sign_extend (mem)) */
  38499. + gcc_assert (MEM_P (XEXP (SET_SRC (body), 0)));
  38500. + return XEXP (SET_SRC (body), 0);
  38501. +
  38502. + case TYPE_STORE:
  38503. + if (MEM_P (SET_DEST (body)))
  38504. + return SET_DEST (body);
  38505. +
  38506. + /* unaligned address: (unspec [(mem)]) */
  38507. + if (GET_CODE (SET_DEST (body)) == UNSPEC)
  38508. + {
  38509. + gcc_assert (MEM_P (XVECEXP (SET_DEST (body), 0, 0)));
  38510. + return XVECEXP (SET_DEST (body), 0, 0);
  38511. + }
  38512. +
  38513. + /* (sign_extend (mem)) */
  38514. + gcc_assert (MEM_P (XEXP (SET_DEST (body), 0)));
  38515. + return XEXP (SET_DEST (body), 0);
  38516. +
  38517. + default:
  38518. + gcc_unreachable ();
  38519. + }
  38520. +}
  38521. +
  38522. +/* Find the post update rtx in INSN. If INSN is a load/store multiple insn,
  38523. + the function returns the vector index of its parallel part. If INSN is a
  38524. + single load/store insn, the function returns 0. If INSN is not a post-
  38525. + update insn, the function returns -1. */
  38526. +int
  38527. +find_post_update_rtx (rtx insn)
  38528. +{
  38529. + rtx mem_rtx;
  38530. + int i, len;
  38531. +
  38532. + switch (get_attr_type (insn))
  38533. + {
  38534. + case TYPE_LOAD_MULTIPLE:
  38535. + case TYPE_STORE_MULTIPLE:
  38536. + /* Find a pattern in a parallel rtx:
  38537. + (set (reg) (plus (reg) (const_int))) */
  38538. + len = parallel_elements (insn);
  38539. + for (i = 0; i < len; ++i)
  38540. + {
  38541. + rtx curr_insn = parallel_element (insn, i);
  38542. +
  38543. + if (GET_CODE (curr_insn) == SET
  38544. + && REG_P (SET_DEST (curr_insn))
  38545. + && GET_CODE (SET_SRC (curr_insn)) == PLUS)
  38546. + return i;
  38547. + }
  38548. + return -1;
  38549. +
  38550. + case TYPE_LOAD:
  38551. + case TYPE_STORE:
  38552. + mem_rtx = extract_mem_rtx (insn);
  38553. + /* (mem (post_inc (reg))) */
  38554. + switch (GET_CODE (XEXP (mem_rtx, 0)))
  38555. + {
  38556. + case POST_INC:
  38557. + case POST_DEC:
  38558. + case POST_MODIFY:
  38559. + return 0;
  38560. +
  38561. + default:
  38562. + return -1;
  38563. + }
  38564. +
  38565. + default:
  38566. + gcc_unreachable ();
  38567. + }
  38568. +}
  38569. +
  38570. +/* Determine if INSN is a post update insn. */
  38571. +bool
  38572. +post_update_insn_p (rtx insn)
  38573. +{
  38574. + if (find_post_update_rtx (insn) == -1)
  38575. + return false;
  38576. + else
  38577. + return true;
  38578. +}
  38579. +
  38580. +/* Extract the base register from load/store insns. The function returns
  38581. + NULL_RTX if the address is not consist of any registers. */
  38582. +rtx
  38583. +extract_base_reg (rtx insn)
  38584. +{
  38585. + int post_update_rtx_index;
  38586. + rtx mem_rtx;
  38587. + rtx plus_rtx;
  38588. +
  38589. + /* Find the MEM rtx. If we can find an insn updating the base register,
  38590. + the base register will be returned directly. */
  38591. + switch (get_attr_type (insn))
  38592. + {
  38593. + case TYPE_LOAD_MULTIPLE:
  38594. + post_update_rtx_index = find_post_update_rtx (insn);
  38595. +
  38596. + if (post_update_rtx_index != -1)
  38597. + return SET_DEST (parallel_element (insn, post_update_rtx_index));
  38598. +
  38599. + mem_rtx = SET_SRC (parallel_element (insn, 0));
  38600. + break;
  38601. +
  38602. + case TYPE_STORE_MULTIPLE:
  38603. + post_update_rtx_index = find_post_update_rtx (insn);
  38604. +
  38605. + if (post_update_rtx_index != -1)
  38606. + return SET_DEST (parallel_element (insn, post_update_rtx_index));
  38607. +
  38608. + mem_rtx = SET_DEST (parallel_element (insn, 0));
  38609. + break;
  38610. +
  38611. + case TYPE_LOAD:
  38612. + case TYPE_STORE:
  38613. + mem_rtx = extract_mem_rtx (insn);
  38614. + break;
  38615. +
  38616. + default:
  38617. + gcc_unreachable ();
  38618. + }
  38619. +
  38620. + gcc_assert (MEM_P (mem_rtx));
  38621. +
  38622. + /* (mem (reg)) */
  38623. + if (REG_P (XEXP (mem_rtx, 0)))
  38624. + return XEXP (mem_rtx, 0);
  38625. +
  38626. + plus_rtx = XEXP (mem_rtx, 0);
  38627. +
  38628. + if (GET_CODE (plus_rtx) == SYMBOL_REF
  38629. + || GET_CODE (plus_rtx) == CONST)
  38630. + return NULL_RTX;
  38631. +
  38632. + gcc_assert (GET_CODE (plus_rtx) == PLUS
  38633. + || GET_CODE (plus_rtx) == POST_INC
  38634. + || GET_CODE (plus_rtx) == POST_DEC
  38635. + || GET_CODE (plus_rtx) == POST_MODIFY);
  38636. + gcc_assert (REG_P (XEXP (plus_rtx, 0)));
  38637. + /* (mem (plus (reg) (const_int))) or
  38638. + (mem (post_inc (reg))) or
  38639. + (mem (post_dec (reg))) or
  38640. + (mem (post_modify (reg) (plus (reg) (reg)))) */
  38641. + return XEXP (plus_rtx, 0);
  38642. +}
  38643. +
  38644. +/* Determine the memory access direction of a load/store insn. */
  38645. +memory_access_direction
  38646. +determine_access_direction (rtx insn)
  38647. +{
  38648. + int post_update_rtx_index;
  38649. + rtx plus_rtx;
  38650. + rtx mem_rtx;
  38651. + rtx offset_rtx;
  38652. +
  38653. + switch (get_attr_type (insn))
  38654. + {
  38655. + case TYPE_LOAD_MULTIPLE:
  38656. + gcc_assert (parallel_elements (insn) >= 2);
  38657. +
  38658. + post_update_rtx_index = find_post_update_rtx (insn);
  38659. + if (post_update_rtx_index != -1)
  38660. + plus_rtx = SET_SRC (parallel_element (insn, post_update_rtx_index));
  38661. + else
  38662. + {
  38663. + /* (parallel
  38664. + [(set (reg) (mem (reg))) : index 0
  38665. + (set (reg) (mem (plus (reg) (...)))) : index 1
  38666. + ...]) */
  38667. + mem_rtx = SET_SRC (parallel_element (insn, 1));
  38668. + if (GET_CODE (mem_rtx) == UNSPEC)
  38669. + mem_rtx = XVECEXP (mem_rtx, 0, 0);
  38670. + gcc_assert (MEM_P (mem_rtx));
  38671. + plus_rtx = XEXP (mem_rtx, 0);
  38672. + }
  38673. + break;
  38674. +
  38675. + case TYPE_STORE_MULTIPLE:
  38676. + gcc_assert (parallel_elements (insn) >= 2);
  38677. +
  38678. + post_update_rtx_index = find_post_update_rtx (insn);
  38679. + if (post_update_rtx_index != -1)
  38680. + plus_rtx = SET_SRC (parallel_element (insn, post_update_rtx_index));
  38681. + else
  38682. + {
  38683. + /* (parallel
  38684. + [(set (mem (reg)) (reg)) : index 0
  38685. + (set (mem (plus (reg) (...))) (reg)) : index 1
  38686. + ...]) */
  38687. + mem_rtx = SET_DEST (parallel_element (insn, 1));
  38688. + if (GET_CODE (mem_rtx) == UNSPEC)
  38689. + mem_rtx = XVECEXP (mem_rtx, 0, 0);
  38690. + gcc_assert (MEM_P (mem_rtx));
  38691. + plus_rtx = XEXP (mem_rtx, 0);
  38692. + }
  38693. + break;
  38694. +
  38695. + case TYPE_LOAD:
  38696. + case TYPE_STORE:
  38697. + mem_rtx = extract_mem_rtx (insn);
  38698. +
  38699. + switch (GET_CODE (XEXP (mem_rtx, 0)))
  38700. + {
  38701. + case POST_INC:
  38702. + /* (mem (post_inc (...))) */
  38703. + return MEM_ACCESS_DIR_POS;
  38704. +
  38705. + case POST_DEC:
  38706. + /* (mem (post_dec (...))) */
  38707. + return MEM_ACCESS_DIR_NEG;
  38708. +
  38709. + case PLUS:
  38710. + /* (mem (plus (reg) (...))) */
  38711. + plus_rtx = XEXP (mem_rtx, 0);
  38712. + break;
  38713. +
  38714. + case POST_MODIFY:
  38715. + /* (mem (post_modify (reg) (plus (reg) (...)))) */
  38716. + plus_rtx = XEXP (XEXP (mem_rtx, 0), 1);
  38717. + break;
  38718. +
  38719. + default:
  38720. + gcc_unreachable ();
  38721. + }
  38722. + break;
  38723. +
  38724. + default:
  38725. + gcc_unreachable ();
  38726. + }
  38727. +
  38728. + gcc_assert (GET_CODE (plus_rtx) == PLUS);
  38729. +
  38730. + offset_rtx = XEXP (plus_rtx, 1);
  38731. + if (GET_CODE (offset_rtx) == CONST_INT)
  38732. + {
  38733. + if (INTVAL (offset_rtx) < 0)
  38734. + return MEM_ACCESS_DIR_NEG;
  38735. + else
  38736. + return MEM_ACCESS_DIR_POS;
  38737. + }
  38738. +
  38739. + return MEM_ACCESS_DIR_UNKNOWN;
  38740. +}
  38741. +
  38742. +/* Return the nth load/store operation in the real micro-operation
  38743. + accessing order. */
  38744. +rtx
  38745. +extract_nth_access_rtx (rtx insn, int n)
  38746. +{
  38747. + int n_elems = parallel_elements (insn);
  38748. + int post_update_rtx_index = find_post_update_rtx (insn);
  38749. + memory_access_direction direction = determine_access_direction (insn);
  38750. +
  38751. + gcc_assert (direction != MEM_ACCESS_DIR_UNKNOWN);
  38752. +
  38753. + /* Reverse the order if the direction negative. */
  38754. + if (direction == MEM_ACCESS_DIR_NEG)
  38755. + n = -1 * n - 1;
  38756. +
  38757. + if (post_update_rtx_index != -1)
  38758. + {
  38759. + if (n >= 0 && post_update_rtx_index <= n)
  38760. + ++n;
  38761. + else if (n < 0 && post_update_rtx_index >= n + n_elems)
  38762. + --n;
  38763. + }
  38764. +
  38765. + return parallel_element (insn, n);
  38766. +}
  38767. +
  38768. +/* Returns the register operated by the nth load/store operation in the real
  38769. + micro-operation accessing order. This function assumes INSN must be a
  38770. + multiple-word load/store insn. */
  38771. +rtx
  38772. +extract_nth_lmsw_access_reg (rtx insn, int n)
  38773. +{
  38774. + rtx nth_rtx = extract_nth_access_rtx (insn, n);
  38775. +
  38776. + if (nth_rtx == NULL_RTX)
  38777. + return NULL_RTX;
  38778. +
  38779. + switch (get_attr_type (insn))
  38780. + {
  38781. + case TYPE_LOAD_MULTIPLE:
  38782. + return SET_DEST (nth_rtx);
  38783. +
  38784. + case TYPE_STORE_MULTIPLE:
  38785. + return SET_SRC (nth_rtx);
  38786. +
  38787. + default:
  38788. + gcc_unreachable ();
  38789. + }
  38790. +}
  38791. +
  38792. +/* Returns the register operated by the nth load/store operation in the real
  38793. + micro-operation accessing order. This function assumes INSN must be a
  38794. + double-word load/store insn. */
  38795. +rtx
  38796. +extract_nth_ls2_access_reg (rtx insn, int n)
  38797. +{
  38798. + rtx reg;
  38799. + enum machine_mode mode;
  38800. +
  38801. + if (post_update_insn_p (insn))
  38802. + {
  38803. + memory_access_direction direction = determine_access_direction (insn);
  38804. + gcc_assert (direction != MEM_ACCESS_DIR_UNKNOWN);
  38805. +
  38806. + /* Reverse the order if the direction negative. */
  38807. + if (direction == MEM_ACCESS_DIR_NEG)
  38808. + n = -1 * n - 1;
  38809. + }
  38810. +
  38811. + /* Handle the out-of-range case. */
  38812. + if (n < -2 || n > 1)
  38813. + return NULL_RTX;
  38814. +
  38815. + /* Convert the index to a positive one. */
  38816. + if (n < 0)
  38817. + n = 2 + n;
  38818. +
  38819. + switch (get_attr_type (insn))
  38820. + {
  38821. + case TYPE_LOAD:
  38822. + reg = SET_DEST (PATTERN (insn));
  38823. + break;
  38824. +
  38825. + case TYPE_STORE:
  38826. + reg = SET_SRC (PATTERN (insn));
  38827. + break;
  38828. +
  38829. + default:
  38830. + gcc_unreachable ();
  38831. + }
  38832. +
  38833. + gcc_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
  38834. +
  38835. + switch (GET_MODE (reg))
  38836. + {
  38837. + case DImode:
  38838. + mode = SImode;
  38839. + break;
  38840. +
  38841. + case DFmode:
  38842. + mode = SFmode;
  38843. + break;
  38844. +
  38845. + default:
  38846. + gcc_unreachable ();
  38847. + }
  38848. +
  38849. + if (n == 0)
  38850. + return gen_lowpart (mode, reg);
  38851. + else
  38852. + return gen_highpart (mode, reg);
  38853. +}
  38854. +
  38855. +/* Returns the register operated by the nth load/store operation in the real
  38856. + micro-operation accessing order. */
  38857. +rtx
  38858. +extract_nth_access_reg (rtx insn, int index)
  38859. +{
  38860. + switch (GET_CODE (PATTERN (insn)))
  38861. + {
  38862. + case PARALLEL:
  38863. + return extract_nth_lmsw_access_reg (insn, index);
  38864. +
  38865. + case SET:
  38866. + return extract_nth_ls2_access_reg (insn, index);
  38867. +
  38868. + default:
  38869. + gcc_unreachable ();
  38870. + }
  38871. +}
  38872. +
  38873. +/* Check if a load/store insn uses a register as a base or offset register. */
  38874. +bool
  38875. +address_use_reg_p (rtx insn, rtx use_reg)
  38876. +{
  38877. + switch (get_attr_type (insn))
  38878. + {
  38879. + case TYPE_LOAD_MULTIPLE:
  38880. + case TYPE_STORE_MULTIPLE:
  38881. + if (rtx_equal_p (use_reg, extract_base_reg (insn)))
  38882. + return true;
  38883. + return false;
  38884. +
  38885. + case TYPE_LOAD:
  38886. + case TYPE_STORE:
  38887. + if (reg_overlap_p (use_reg, extract_mem_rtx (insn)))
  38888. + return true;
  38889. + return false;
  38890. +
  38891. + default:
  38892. + return false;
  38893. + }
  38894. +}
  38895. +
  38896. +/* Extract the register of the shift operand from an ALU_SHIFT rtx. */
  38897. +rtx
  38898. +extract_shift_reg (rtx alu_shift_rtx)
  38899. +{
  38900. + alu_shift_rtx = extract_pattern_from_insn (alu_shift_rtx);
  38901. +
  38902. + rtx alu_rtx = SET_SRC (alu_shift_rtx);
  38903. + rtx shift_rtx;
  38904. +
  38905. + /* Various forms of ALU_SHIFT can be made by the combiner.
  38906. + See the difference between add_slli and sub_slli in nds32.md. */
  38907. + if (REG_P (XEXP (alu_rtx, 0)))
  38908. + shift_rtx = XEXP (alu_rtx, 1);
  38909. + else
  38910. + shift_rtx = XEXP (alu_rtx, 0);
  38911. +
  38912. + return XEXP (shift_rtx, 0);
  38913. +}
  38914. +
  38915. +
  38916. +/* Determine if the latency is occured when the consumer PBSADA_INSN uses the
  38917. + value of DEF_REG in its Ra or Rb fields. */
  38918. +bool
  38919. +pbsada_insn_ra_rb_dep_reg_p (rtx pbsada_insn, rtx def_reg)
  38920. +{
  38921. + rtx unspec_rtx = SET_SRC (PATTERN (pbsada_insn));
  38922. + gcc_assert (GET_CODE (unspec_rtx) == UNSPEC);
  38923. +
  38924. + rtx pbsada_ra = XVECEXP (unspec_rtx, 0, 0);
  38925. + rtx pbsada_rb = XVECEXP (unspec_rtx, 0, 1);
  38926. +
  38927. + if (rtx_equal_p (def_reg, pbsada_ra)
  38928. + || rtx_equal_p (def_reg, pbsada_rb))
  38929. + return true;
  38930. +
  38931. + return false;
  38932. +}
  38933. +
  38934. +/* Determine if the latency is occured when the consumer PBSADA_INSN uses the
  38935. + value of DEF_REG in its Rt field. */
  38936. +bool
  38937. +pbsada_insn_rt_dep_reg_p (rtx pbsada_insn, rtx def_reg)
  38938. +{
  38939. + rtx pbsada_rt = SET_DEST (PATTERN (pbsada_insn));
  38940. +
  38941. + if (rtx_equal_p (def_reg, pbsada_rt))
  38942. + return true;
  38943. +
  38944. + return false;
  38945. +}
  38946. +
  38947. +/* Check if the address of MEM_RTX consists of a base register and an
  38948. + immediate offset. */
  38949. +bool
  38950. +immed_offset_p (rtx mem_rtx)
  38951. +{
  38952. + gcc_assert (MEM_P (mem_rtx));
  38953. +
  38954. + rtx addr_rtx = XEXP (mem_rtx, 0);
  38955. +
  38956. + /* (mem (reg)) is equivalent to (mem (plus (reg) (const_int 0))) */
  38957. + if (REG_P (addr_rtx))
  38958. + return true;
  38959. +
  38960. + /* (mem (plus (reg) (const_int))) */
  38961. + if (GET_CODE (addr_rtx) == PLUS
  38962. + && GET_CODE (XEXP (addr_rtx, 1)) == CONST_INT)
  38963. + return true;
  38964. +
  38965. + return false;
  38966. +}
  38967. +
  38968. +/* Check if INSN is a movd44 insn. */
  38969. +bool
  38970. +movd44_insn_p (rtx insn)
  38971. +{
  38972. + if (get_attr_type (insn) == TYPE_ALU
  38973. + && (INSN_CODE (insn) == CODE_FOR_move_di
  38974. + || INSN_CODE (insn) == CODE_FOR_move_df))
  38975. + {
  38976. + rtx body = PATTERN (insn);
  38977. + gcc_assert (GET_CODE (body) == SET);
  38978. +
  38979. + rtx src = SET_SRC (body);
  38980. + rtx dest = SET_DEST (body);
  38981. +
  38982. + if ((REG_P (src) || GET_CODE (src) == SUBREG)
  38983. + && (REG_P (dest) || GET_CODE (dest) == SUBREG))
  38984. + return true;
  38985. +
  38986. + return false;
  38987. + }
  38988. +
  38989. + return false;
  38990. +}
  38991. +
  38992. +/* Check if INSN is a movd44 insn consuming DEF_REG. */
  38993. +bool
  38994. +movd44_even_dep_p (rtx insn, rtx def_reg)
  38995. +{
  38996. + if (!movd44_insn_p (insn))
  38997. + return false;
  38998. +
  38999. + rtx use_rtx = SET_SRC (PATTERN (insn));
  39000. +
  39001. + if (REG_P (def_reg))
  39002. + {
  39003. + return rtx_equal_p (def_reg, use_rtx);
  39004. + }
  39005. + else if (GET_CODE (def_reg) == SUBREG
  39006. + && GET_MODE (def_reg) == SImode
  39007. + && rtx_equal_p (SUBREG_REG (def_reg), use_rtx))
  39008. + {
  39009. + if (TARGET_BIG_ENDIAN && SUBREG_BYTE (def_reg) == 4)
  39010. + return true;
  39011. +
  39012. + if (!TARGET_BIG_ENDIAN && SUBREG_BYTE (def_reg) == 0)
  39013. + return true;
  39014. +
  39015. + return false;
  39016. + }
  39017. +
  39018. + return false;
  39019. +}
  39020. +
  39021. +/* Extract the first result (even reg) of a movd44 insn. */
  39022. +rtx
  39023. +extract_movd44_even_reg (rtx insn)
  39024. +{
  39025. + gcc_assert (movd44_insn_p (insn));
  39026. +
  39027. + rtx def_reg = SET_DEST (PATTERN (insn));
  39028. + enum machine_mode mode;
  39029. +
  39030. + gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
  39031. + switch (GET_MODE (def_reg))
  39032. + {
  39033. + case DImode:
  39034. + mode = SImode;
  39035. + break;
  39036. +
  39037. + case DFmode:
  39038. + mode = SFmode;
  39039. + break;
  39040. +
  39041. + default:
  39042. + gcc_unreachable ();
  39043. + }
  39044. +
  39045. + return gen_lowpart (mode, def_reg);
  39046. +}
  39047. +
  39048. +/* Extract the second result (odd reg) of a movd44 insn. */
  39049. +rtx
  39050. +extract_movd44_odd_reg (rtx insn)
  39051. +{
  39052. + gcc_assert (movd44_insn_p (insn));
  39053. +
  39054. + rtx def_reg = SET_DEST (PATTERN (insn));
  39055. + enum machine_mode mode;
  39056. +
  39057. + gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
  39058. + switch (GET_MODE (def_reg))
  39059. + {
  39060. + case DImode:
  39061. + mode = SImode;
  39062. + break;
  39063. +
  39064. + case DFmode:
  39065. + mode = SFmode;
  39066. + break;
  39067. +
  39068. + default:
  39069. + gcc_unreachable ();
  39070. + }
  39071. +
  39072. + return gen_highpart (mode, def_reg);
  39073. +}
  39074. +
  39075. +/* Extract the rtx representing the branch target to help recognize
  39076. + data hazards. */
  39077. +rtx
  39078. +extract_branch_target_rtx (rtx insn)
  39079. +{
  39080. + gcc_assert (CALL_P (insn) || JUMP_P (insn));
  39081. +
  39082. + rtx body = PATTERN (insn);
  39083. +
  39084. + if (GET_CODE (body) == SET)
  39085. + {
  39086. + /* RTXs in IF_THEN_ELSE are branch conditions. */
  39087. + if (GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)
  39088. + return NULL_RTX;
  39089. +
  39090. + return SET_SRC (body);
  39091. + }
  39092. +
  39093. + if (GET_CODE (body) == CALL)
  39094. + return XEXP (body, 0);
  39095. +
  39096. + if (GET_CODE (body) == PARALLEL)
  39097. + {
  39098. + rtx first_rtx = parallel_element (body, 0);
  39099. +
  39100. + if (GET_CODE (first_rtx) == SET)
  39101. + return SET_SRC (first_rtx);
  39102. +
  39103. + if (GET_CODE (first_rtx) == CALL)
  39104. + return XEXP (first_rtx, 0);
  39105. + }
  39106. +
  39107. + /* Handle special cases of bltzal, bgezal and jralnez. */
  39108. + if (GET_CODE (body) == COND_EXEC)
  39109. + {
  39110. + rtx addr_rtx = XEXP (body, 1);
  39111. +
  39112. + if (GET_CODE (addr_rtx) == SET)
  39113. + return SET_SRC (addr_rtx);
  39114. +
  39115. + if (GET_CODE (addr_rtx) == PARALLEL)
  39116. + {
  39117. + rtx first_rtx = parallel_element (addr_rtx, 0);
  39118. +
  39119. + if (GET_CODE (first_rtx) == SET)
  39120. + {
  39121. + rtx call_rtx = SET_SRC (first_rtx);
  39122. + gcc_assert (GET_CODE (call_rtx) == CALL);
  39123. +
  39124. + return XEXP (call_rtx, 0);
  39125. + }
  39126. +
  39127. + if (GET_CODE (first_rtx) == CALL)
  39128. + return XEXP (first_rtx, 0);
  39129. + }
  39130. + }
  39131. +
  39132. + gcc_unreachable ();
  39133. +}
  39134. +
  39135. +/* Extract the rtx representing the branch condition to help recognize
  39136. + data hazards. */
  39137. +rtx
  39138. +extract_branch_condition_rtx (rtx insn)
  39139. +{
  39140. + gcc_assert (CALL_P (insn) || JUMP_P (insn));
  39141. +
  39142. + rtx body = PATTERN (insn);
  39143. +
  39144. + if (GET_CODE (body) == SET)
  39145. + {
  39146. + rtx if_then_else_rtx = SET_SRC (body);
  39147. +
  39148. + if (GET_CODE (if_then_else_rtx) == IF_THEN_ELSE)
  39149. + return XEXP (if_then_else_rtx, 0);
  39150. +
  39151. + return NULL_RTX;
  39152. + }
  39153. +
  39154. + if (GET_CODE (body) == COND_EXEC)
  39155. + return XEXP (body, 0);
  39156. +
  39157. + return NULL_RTX;
  39158. +}
  39159. +
  39160. +pipeline_simulator::pipeline_simulator ()
  39161. +{
  39162. + /* The design of dfa_start () operates on static global variables and
  39163. + allocates memory space without checking whether the function is called
  39164. + twice or not. We add some guards in order to protect it from abusing. */
  39165. + gcc_assert(gcc_dfa_initialized_ == false);
  39166. + if(!gcc_dfa_initialized_)
  39167. + {
  39168. + dfa_start ();
  39169. + gcc_dfa_initialized_ = true;
  39170. + }
  39171. +
  39172. + state_ = xmalloc (sizeof (state_size()));
  39173. + state_reset (state_);
  39174. +}
  39175. +
  39176. +pipeline_simulator::~pipeline_simulator ()
  39177. +{
  39178. + /* The design of dfa_finish () operates on a static global variable and
  39179. + deallocates memory space without checking whether the function is called
  39180. + twice or not. We add some guards in order to protect it from abusing. */
  39181. + free (state_);
  39182. +
  39183. + gcc_assert(gcc_dfa_initialized_ == true);
  39184. + if(gcc_dfa_initialized_)
  39185. + {
  39186. + dfa_finish ();
  39187. + gcc_dfa_initialized_ = false;
  39188. + }
  39189. +}
  39190. +
  39191. +void
  39192. +pipeline_simulator::advance_cycle (int cycles)
  39193. +{
  39194. + gcc_assert (cycles > 0);
  39195. +
  39196. + /* The second argument was 'NULL', but we found the expression is directly
  39197. + written in insn-automata.c:
  39198. + if (insn == 0)
  39199. + insn_code = DFA__ADVANCE_CYCLE;
  39200. + Hence we change it to '0' in order to make it consistent. */
  39201. + while (cycles--)
  39202. + state_transition (state_, 0);
  39203. +}
  39204. +
  39205. +/* A wrapper of insn_latency () provided by the insn-attr.h in the object tree.
  39206. + See that file for more information. */
  39207. +int
  39208. +pipeline_simulator::query_latency (rtx producer, rtx consumer) const
  39209. +{
  39210. + return insn_latency (producer, consumer);
  39211. +}
  39212. +
  39213. +/* Return 0 or negative if we can issue INSN at the current cycle. Otherwise,
  39214. + return a postive value indicates how many cycles we have to wait. The
  39215. + interface is consistent with state_transition () provided by insn-attr.h
  39216. + in the object directory. See that file for more information. */
  39217. +int
  39218. +pipeline_simulator::issue_insn (rtx insn)
  39219. +{
  39220. + int stalls;
  39221. +
  39222. + /* Skip cycles specified by pseudo NOPs. */
  39223. + if (insn_pseudo_nop_p (insn))
  39224. + {
  39225. + int nop_stalls = INTVAL (XVECEXP (PATTERN (insn), 0, 0));
  39226. +
  39227. + gcc_assert (nop_stalls > 0);
  39228. + advance_cycle (nop_stalls);
  39229. + stalls = -1;
  39230. + }
  39231. + else
  39232. + {
  39233. + stalls = state_transition (state_, insn);
  39234. +
  39235. + /* All targets are single-issue, so we advance one cycle once after
  39236. + an insn has been issued successfully. */
  39237. + if (stalls <= 0)
  39238. + advance_cycle ();
  39239. + }
  39240. +
  39241. + return stalls;
  39242. +}
  39243. +
  39244. +/* This function is similar to issue_insn (), but it advances cycles until INSN
  39245. + can be issued successfully. If INSN can be issued at the current cycle, the
  39246. + return value will be 0 or negaitive. Otherwise, the function will return
  39247. + the cycles it has been skipped. */
  39248. +int
  39249. +pipeline_simulator::force_issue_insn (rtx insn)
  39250. +{
  39251. + int stalls;
  39252. +
  39253. + stalls = issue_insn (insn);
  39254. +
  39255. + /* Skip cycles until we can issue the insn. */
  39256. + if (stalls > 0)
  39257. + {
  39258. + advance_cycle (stalls);
  39259. + issue_insn (insn);
  39260. + }
  39261. +
  39262. + return stalls;
  39263. +}
  39264. +
  39265. +/* The main flow of the class STALL_INSERTER. We insert NOPs for structural
  39266. + hazards because self-stalled instructions also consume the delay cycles
  39267. + caused by data hazards. */
  39268. +void
  39269. +stall_inserter::insert_stalls ()
  39270. +{
  39271. + compute_bb_for_insn_safe ();
  39272. +
  39273. + insert_structural_hazard_stalls ();
  39274. + insert_data_hazard_stalls ();
  39275. +
  39276. + /* We have to call the following two functions again after we inserting
  39277. + some insns after it has been invoked. Otherwise, an assert expression
  39278. + in final () will be triggered and cause to an internal compiler error. */
  39279. + init_insn_lengths ();
  39280. + shorten_branches (get_insns ());
  39281. +
  39282. + free_bb_for_insn ();
  39283. +}
  39284. +
  39285. +/* Building the CFG in later back end passes cannot call compute_bb_for_insn ()
  39286. + directly because there are deleted and calling to BLOCK_FOR_INSN (insn) will
  39287. + cause the segmentation fault. Use this function to rebuild the CFG can
  39288. + avoid such issues. */
  39289. +void
  39290. +stall_inserter::compute_bb_for_insn_safe ()
  39291. +{
  39292. + basic_block bb;
  39293. +
  39294. + FOR_EACH_BB_FN (bb, cfun)
  39295. + {
  39296. + rtx insn, next_insn, last_insn;
  39297. + bool after_last_insn = false;
  39298. +
  39299. + /* Have last_insn = the last insn which is not deleted. */
  39300. + for (last_insn = BB_END (bb);
  39301. + PREV_INSN (last_insn) && insn_deleted_p (last_insn);
  39302. + last_insn = PREV_INSN (last_insn));
  39303. +
  39304. + /* Bind each insn to its BB and adjust BB_END (bb). */
  39305. + for (insn = BB_HEAD (bb); insn; insn = NEXT_INSN (insn))
  39306. + {
  39307. + BLOCK_FOR_INSN (insn) = bb;
  39308. +
  39309. + if(insn == last_insn) after_last_insn = true;
  39310. + next_insn = NEXT_INSN (insn);
  39311. +
  39312. + if(after_last_insn
  39313. + && (!next_insn
  39314. + || LABEL_P (next_insn)
  39315. + || NOTE_INSN_BASIC_BLOCK_P (next_insn)))
  39316. + {
  39317. + BB_END (bb) = insn;
  39318. + break;
  39319. + }
  39320. + }
  39321. + }
  39322. +}
  39323. +
  39324. +/* A helper function inserting NOPs. CYCLES indicates how many cycles the NOP
  39325. + insn consumes. TYPE indicates what type of the NOP insn we want to insert;
  39326. + now there are two types available: RES_DEP and DATA_DEP. */
  39327. +rtx
  39328. +stall_inserter::emit_pseudo_nop_before (
  39329. + rtx insn, int cycles, enum dep_type type)
  39330. +{
  39331. + rtx nop_insn;
  39332. + int recog;
  39333. +
  39334. + switch (type)
  39335. + {
  39336. + case RES_DEP:
  39337. + nop_insn = gen_nop_res_dep (GEN_INT (cycles));
  39338. + break;
  39339. + case DATA_DEP:
  39340. + nop_insn = gen_nop_data_dep (GEN_INT (cycles));
  39341. + break;
  39342. + default:
  39343. + gcc_unreachable ();
  39344. + }
  39345. +
  39346. + nop_insn = emit_insn_before (nop_insn, insn);
  39347. + recog = recog_memoized (nop_insn);
  39348. + gcc_assert(recog != -1);
  39349. +
  39350. + return nop_insn;
  39351. +}
  39352. +
  39353. +void
  39354. +stall_inserter::insert_structural_hazard_stalls ()
  39355. +{
  39356. + pipeline_simulator simulator;
  39357. + rtx insn;
  39358. +
  39359. + for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
  39360. + {
  39361. + if (!insn_executable_p (insn)) continue;
  39362. +
  39363. + int stalls = simulator.force_issue_insn (insn);
  39364. +
  39365. + if (stalls > 0)
  39366. + emit_pseudo_nop_before (insn, stalls, RES_DEP);
  39367. + }
  39368. +}
  39369. +
  39370. +void
  39371. +stall_inserter::insert_data_hazard_stalls ()
  39372. +{
  39373. + pipeline_simulator simulator;
  39374. + rtx insn;
  39375. +
  39376. + /* Calling to df_insn_rescan_all here is required in order to avoid crash
  39377. + when some special options are specified by users, such as
  39378. + -O0 -fschedule-insns2. */
  39379. + df_chain_add_problem (DF_DU_CHAIN);
  39380. + df_insn_rescan_all ();
  39381. + df_analyze ();
  39382. +
  39383. + for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
  39384. + {
  39385. + if (!insn_executable_p (insn)) continue;
  39386. +
  39387. + simulator.force_issue_insn (insn);
  39388. + emit_pseudo_nops_for_data_hazards (insn, simulator);
  39389. + }
  39390. +
  39391. + /* We must call df_finish_pass manually because it should be invoked before
  39392. + BB information is destroyed. Hence we cannot set the TODO_df_finish flag
  39393. + to the pass manager. */
  39394. + df_insn_rescan_all ();
  39395. + df_finish_pass (false);
  39396. +}
  39397. +
  39398. +/* Traverse all insns using the results produced by INSN and ask SIMULATOR
  39399. + how many delay cycles between them. If there are some delay cycles, insert
  39400. + corresponding NOP insns there. */
  39401. +void
  39402. +stall_inserter::emit_pseudo_nops_for_data_hazards (
  39403. + rtx insn, pipeline_simulator &simulator)
  39404. +{
  39405. + df_ref *def_record;
  39406. + df_link *link;
  39407. + std::set<rtx> processed_insns;
  39408. +
  39409. + for (def_record = DF_INSN_DEFS (insn); *def_record; ++def_record)
  39410. + {
  39411. + for (link = DF_REF_CHAIN (*def_record); link; link = link->next)
  39412. + {
  39413. + if (!DF_REF_INSN_INFO (link->ref))
  39414. + continue;
  39415. +
  39416. + rtx use_insn = DF_REF_INSN (link->ref);
  39417. +
  39418. + if (!insn_executable_p (use_insn)
  39419. + || processed_insns.count (use_insn))
  39420. + continue;
  39421. +
  39422. + int stalls = simulator.query_latency (insn, use_insn);
  39423. + int distance = cycle_distance (insn, use_insn);
  39424. +
  39425. + if (stalls > distance)
  39426. + {
  39427. + stalls -= distance;
  39428. + emit_pseudo_nop_before (use_insn, stalls, DATA_DEP);
  39429. + processed_insns.insert (use_insn);
  39430. + }
  39431. + }
  39432. + }
  39433. +}
  39434. +
  39435. +unsigned int
  39436. +nds32_print_stalls (void)
  39437. +{
  39438. + stall_inserter inserter;
  39439. +
  39440. + inserter.insert_stalls ();
  39441. + return 0;
  39442. +}
  39443. +
  39444. +} // namespace scheduling
  39445. +} // namespace nds32
  39446. +
  39447. +/* ------------------------------------------------------------------------ */
  39448. +
  39449. +using namespace nds32::scheduling;
  39450. +
  39451. +namespace { // anonymous namespace
  39452. +
  39453. +bool
  39454. +n7_consumed_by_ii_dep_p (rtx consumer, rtx def_reg)
  39455. +{
  39456. + rtx use_rtx, acc_rtx;
  39457. +
  39458. + switch (get_attr_type (consumer))
  39459. + {
  39460. + case TYPE_ALU:
  39461. + if (movd44_even_dep_p (consumer, def_reg))
  39462. + return true;
  39463. +
  39464. + use_rtx = SET_SRC (PATTERN (consumer));
  39465. + break;
  39466. +
  39467. + case TYPE_MUL:
  39468. + use_rtx = SET_SRC (PATTERN (consumer));
  39469. + break;
  39470. +
  39471. + case TYPE_MAC:
  39472. + acc_rtx = SET_SRC (PATTERN (consumer));
  39473. +
  39474. + if (REG_P (XEXP (acc_rtx, 0)))
  39475. + use_rtx = XEXP (acc_rtx, 1);
  39476. + else
  39477. + use_rtx = XEXP (acc_rtx, 0);
  39478. + break;
  39479. +
  39480. + case TYPE_DIV:
  39481. + if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
  39482. + || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
  39483. + use_rtx = SET_SRC (parallel_element (consumer, 0));
  39484. + else
  39485. + use_rtx = SET_SRC (PATTERN (consumer));
  39486. + break;
  39487. +
  39488. + case TYPE_LOAD:
  39489. + /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
  39490. + if (post_update_insn_p (consumer))
  39491. + use_rtx = extract_base_reg (consumer);
  39492. + else
  39493. + use_rtx = extract_mem_rtx (consumer);
  39494. + break;
  39495. +
  39496. + case TYPE_STORE:
  39497. + /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
  39498. + if (post_update_insn_p (consumer))
  39499. + use_rtx = extract_base_reg (consumer);
  39500. + else
  39501. + use_rtx = extract_mem_rtx (consumer);
  39502. +
  39503. + if (reg_overlap_p (def_reg, use_rtx))
  39504. + return true;
  39505. +
  39506. + /* ST_bi, ST_!bi_RI */
  39507. + if (!post_update_insn_p (consumer)
  39508. + && !immed_offset_p (extract_mem_rtx (consumer)))
  39509. + return false;
  39510. +
  39511. + use_rtx = SET_SRC (PATTERN (consumer));
  39512. + break;
  39513. +
  39514. + case TYPE_LOAD_MULTIPLE:
  39515. + use_rtx = extract_base_reg (consumer);
  39516. + break;
  39517. +
  39518. + case TYPE_STORE_MULTIPLE:
  39519. + /* ADDR_IN */
  39520. + use_rtx = extract_base_reg (consumer);
  39521. + if (reg_overlap_p (def_reg, use_rtx))
  39522. + return true;
  39523. +
  39524. + /* SMW (N, 1) */
  39525. + use_rtx = extract_nth_access_rtx (consumer, 0);
  39526. + break;
  39527. +
  39528. + case TYPE_BRANCH:
  39529. + use_rtx = PATTERN (consumer);
  39530. + break;
  39531. +
  39532. + default:
  39533. + gcc_unreachable ();
  39534. + }
  39535. +
  39536. + if (reg_overlap_p (def_reg, use_rtx))
  39537. + return true;
  39538. +
  39539. + return false;
  39540. +}
  39541. +
  39542. +bool
  39543. +n8_consumed_by_addr_in_p (rtx consumer, rtx def_reg)
  39544. +{
  39545. + rtx use_rtx;
  39546. +
  39547. + switch (get_attr_type (consumer))
  39548. + {
  39549. + case TYPE_BRANCH:
  39550. + use_rtx = extract_branch_target_rtx (consumer);
  39551. + break;
  39552. +
  39553. + case TYPE_LOAD:
  39554. + if (nds32_load_single_p (consumer))
  39555. + use_rtx = extract_mem_rtx (consumer);
  39556. + else
  39557. + use_rtx = extract_base_reg (consumer);
  39558. + break;
  39559. +
  39560. + case TYPE_STORE:
  39561. + if (nds32_store_single_p (consumer)
  39562. + && (!post_update_insn_p (consumer)
  39563. + || immed_offset_p (extract_mem_rtx (consumer))))
  39564. + use_rtx = extract_mem_rtx (consumer);
  39565. + else
  39566. + use_rtx = extract_base_reg (consumer);
  39567. + break;
  39568. +
  39569. + case TYPE_LOAD_MULTIPLE:
  39570. + case TYPE_STORE_MULTIPLE:
  39571. + use_rtx = extract_base_reg (consumer);
  39572. + break;
  39573. +
  39574. + default:
  39575. + gcc_unreachable ();
  39576. + }
  39577. +
  39578. + return reg_overlap_p (def_reg, use_rtx);
  39579. +}
  39580. +
  39581. +bool
  39582. +n8_consumed_by_ex_p (rtx consumer, rtx def_reg)
  39583. +{
  39584. + rtx use_rtx, acc_rtx;
  39585. +
  39586. + switch (get_attr_type (consumer))
  39587. + {
  39588. + case TYPE_ALU:
  39589. + if (movd44_even_dep_p (consumer, def_reg))
  39590. + return true;
  39591. +
  39592. + use_rtx = SET_SRC (PATTERN (consumer));
  39593. + break;
  39594. +
  39595. + case TYPE_MUL:
  39596. + use_rtx = SET_SRC (PATTERN (consumer));
  39597. + break;
  39598. +
  39599. + case TYPE_MAC:
  39600. + acc_rtx = SET_SRC (PATTERN (consumer));
  39601. +
  39602. + if (REG_P (XEXP (acc_rtx, 0)))
  39603. + use_rtx = XEXP (acc_rtx, 1);
  39604. + else
  39605. + use_rtx = XEXP (acc_rtx, 0);
  39606. + break;
  39607. +
  39608. + case TYPE_DIV:
  39609. + if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
  39610. + || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
  39611. + use_rtx = SET_SRC (parallel_element (consumer, 0));
  39612. + else
  39613. + use_rtx = SET_SRC (PATTERN (consumer));
  39614. + break;
  39615. +
  39616. + case TYPE_BRANCH:
  39617. + use_rtx = extract_branch_condition_rtx (consumer);
  39618. + break;
  39619. +
  39620. + case TYPE_STORE:
  39621. + use_rtx = SET_SRC (PATTERN (consumer));
  39622. + break;
  39623. +
  39624. + case TYPE_STORE_MULTIPLE:
  39625. + use_rtx = extract_nth_access_rtx (consumer, 0);
  39626. + break;
  39627. +
  39628. + default:
  39629. + gcc_unreachable ();
  39630. + }
  39631. +
  39632. + return reg_overlap_p (def_reg, use_rtx);
  39633. +}
  39634. +
  39635. +bool
  39636. +e8_consumed_by_addr_in_p (rtx consumer, rtx def_reg)
  39637. +{
  39638. + return n8_consumed_by_addr_in_p (consumer, def_reg);
  39639. +}
  39640. +
  39641. +bool
  39642. +e8_consumed_by_ex_p (rtx consumer, rtx def_reg)
  39643. +{
  39644. + rtx use_rtx;
  39645. +
  39646. + switch (get_attr_type (consumer))
  39647. + {
  39648. + case TYPE_ALU:
  39649. + use_rtx = SET_SRC (PATTERN (consumer));
  39650. + break;
  39651. +
  39652. + case TYPE_MUL:
  39653. + case TYPE_MAC:
  39654. + case TYPE_DIV:
  39655. + case TYPE_BRANCH:
  39656. + case TYPE_STORE:
  39657. + case TYPE_STORE_MULTIPLE:
  39658. + return n8_consumed_by_ex_p (consumer, def_reg);
  39659. +
  39660. + default:
  39661. + gcc_unreachable ();
  39662. + }
  39663. +
  39664. + return reg_overlap_p (def_reg, use_rtx);
  39665. +}
  39666. +
  39667. +bool
  39668. +n9_2r1w_consumed_by_ex_dep_p (rtx consumer, rtx def_reg)
  39669. +{
  39670. + rtx use_rtx;
  39671. +
  39672. + switch (get_attr_type (consumer))
  39673. + {
  39674. + case TYPE_ALU:
  39675. + if (movd44_even_dep_p (consumer, def_reg))
  39676. + return true;
  39677. +
  39678. + use_rtx = SET_SRC (PATTERN (consumer));
  39679. + break;
  39680. +
  39681. + case TYPE_PBSAD:
  39682. + case TYPE_MUL:
  39683. + use_rtx = SET_SRC (PATTERN (consumer));
  39684. + break;
  39685. +
  39686. + case TYPE_ALU_SHIFT:
  39687. + use_rtx = extract_shift_reg (consumer);
  39688. + break;
  39689. +
  39690. + case TYPE_PBSADA:
  39691. + return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg);
  39692. +
  39693. + case TYPE_MAC:
  39694. + use_rtx = PATTERN (consumer);
  39695. + break;
  39696. +
  39697. + case TYPE_DIV:
  39698. + if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
  39699. + || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
  39700. + use_rtx = SET_SRC (parallel_element (consumer, 0));
  39701. + else
  39702. + use_rtx = SET_SRC (PATTERN (consumer));
  39703. + break;
  39704. +
  39705. + case TYPE_MMU:
  39706. + if (GET_CODE (PATTERN (consumer)) == SET)
  39707. + use_rtx = SET_SRC (PATTERN (consumer));
  39708. + else
  39709. + return true;
  39710. + break;
  39711. +
  39712. + case TYPE_LOAD:
  39713. + /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
  39714. + if (post_update_insn_p (consumer))
  39715. + use_rtx = extract_base_reg (consumer);
  39716. + else
  39717. + use_rtx = extract_mem_rtx (consumer);
  39718. + break;
  39719. +
  39720. + case TYPE_STORE:
  39721. + /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
  39722. + if (post_update_insn_p (consumer))
  39723. + use_rtx = extract_base_reg (consumer);
  39724. + else
  39725. + use_rtx = extract_mem_rtx (consumer);
  39726. +
  39727. + if (reg_overlap_p (def_reg, use_rtx))
  39728. + return true;
  39729. +
  39730. + /* ST_bi, ST_!bi_RI */
  39731. + if (!post_update_insn_p (consumer)
  39732. + && !immed_offset_p (extract_mem_rtx (consumer)))
  39733. + return false;
  39734. +
  39735. + use_rtx = SET_SRC (PATTERN (consumer));
  39736. + break;
  39737. +
  39738. + case TYPE_LOAD_MULTIPLE:
  39739. + use_rtx = extract_base_reg (consumer);
  39740. + break;
  39741. +
  39742. + case TYPE_STORE_MULTIPLE:
  39743. + /* ADDR_IN */
  39744. + use_rtx = extract_base_reg (consumer);
  39745. + if (reg_overlap_p (def_reg, use_rtx))
  39746. + return true;
  39747. +
  39748. + /* SMW (N, 1) */
  39749. + use_rtx = extract_nth_access_rtx (consumer, 0);
  39750. + break;
  39751. +
  39752. + case TYPE_BRANCH:
  39753. + use_rtx = PATTERN (consumer);
  39754. + break;
  39755. +
  39756. + default:
  39757. + gcc_unreachable ();
  39758. + }
  39759. +
  39760. + if (reg_overlap_p (def_reg, use_rtx))
  39761. + return true;
  39762. +
  39763. + return false;
  39764. +}
  39765. +
  39766. +bool
  39767. +n9_3r2w_consumed_by_ex_dep_p (rtx consumer, rtx def_reg)
  39768. +{
  39769. + rtx acc_rtx, use_rtx;
  39770. +
  39771. + switch (get_attr_type (consumer))
  39772. + {
  39773. + case TYPE_ALU:
  39774. + case TYPE_PBSAD:
  39775. + case TYPE_MUL:
  39776. + use_rtx = SET_SRC (PATTERN (consumer));
  39777. + break;
  39778. +
  39779. + case TYPE_ALU_SHIFT:
  39780. + use_rtx = extract_shift_reg (consumer);
  39781. + break;
  39782. +
  39783. + case TYPE_PBSADA:
  39784. + return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg);
  39785. +
  39786. + case TYPE_MAC:
  39787. + acc_rtx = SET_SRC (PATTERN (consumer));
  39788. +
  39789. + if (REG_P (XEXP (acc_rtx, 0)))
  39790. + use_rtx = XEXP (acc_rtx, 1);
  39791. + else
  39792. + use_rtx = XEXP (acc_rtx, 0);
  39793. + break;
  39794. +
  39795. + case TYPE_DIV:
  39796. + if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
  39797. + || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
  39798. + use_rtx = SET_SRC (parallel_element (consumer, 0));
  39799. + else
  39800. + use_rtx = SET_SRC (PATTERN (consumer));
  39801. + break;
  39802. +
  39803. + case TYPE_MMU:
  39804. + if (GET_CODE (PATTERN (consumer)) == SET)
  39805. + use_rtx = SET_SRC (PATTERN (consumer));
  39806. + else
  39807. + return true;
  39808. + break;
  39809. +
  39810. + case TYPE_LOAD:
  39811. + case TYPE_STORE:
  39812. + use_rtx = extract_mem_rtx (consumer);
  39813. + break;
  39814. +
  39815. + case TYPE_LOAD_MULTIPLE:
  39816. + case TYPE_STORE_MULTIPLE:
  39817. + use_rtx = extract_base_reg (consumer);
  39818. + break;
  39819. +
  39820. + case TYPE_BRANCH:
  39821. + use_rtx = PATTERN (consumer);
  39822. + break;
  39823. +
  39824. + default:
  39825. + gcc_unreachable ();
  39826. + }
  39827. +
  39828. + if (reg_overlap_p (def_reg, use_rtx))
  39829. + return true;
  39830. +
  39831. + return false;
  39832. +}
  39833. +
  39834. +bool
  39835. +n13_alu_e1_insn_dep_reg_p (rtx alu_e1_insn, rtx def_reg)
  39836. +{
  39837. + rtx unspec_rtx, operand_ra, operand_rb;
  39838. + rtx src_rtx, dst_rtx;
  39839. +
  39840. + switch (INSN_CODE (alu_e1_insn))
  39841. + {
  39842. + case CODE_FOR_unspec_bsp:
  39843. + case CODE_FOR_unspec_bse:
  39844. + unspec_rtx = SET_SRC (parallel_element (alu_e1_insn, 0));
  39845. + gcc_assert (GET_CODE (unspec_rtx) == UNSPEC);
  39846. +
  39847. + operand_ra = XVECEXP (unspec_rtx, 0, 0);
  39848. + operand_rb = XVECEXP (unspec_rtx, 0, 1);
  39849. +
  39850. + if (rtx_equal_p (def_reg, operand_ra)
  39851. + || rtx_equal_p (def_reg, operand_rb))
  39852. + return true;
  39853. +
  39854. + return false;
  39855. +
  39856. + case CODE_FOR_move_di:
  39857. + case CODE_FOR_move_df:
  39858. + src_rtx = SET_SRC (PATTERN (alu_e1_insn));
  39859. + dst_rtx = SET_DEST (PATTERN (alu_e1_insn));
  39860. +
  39861. + if (REG_P (dst_rtx) && REG_P (src_rtx)
  39862. + && rtx_equal_p (src_rtx, def_reg))
  39863. + return true;
  39864. +
  39865. + return false;
  39866. +
  39867. + default:
  39868. + return false;
  39869. + }
  39870. +}
  39871. +
  39872. +bool
  39873. +n13_consumed_by_e1_dep_p (rtx consumer, rtx def_reg)
  39874. +{
  39875. + rtx use_rtx, acc_rtx;
  39876. +
  39877. + switch (get_attr_type (consumer))
  39878. + {
  39879. + case TYPE_ALU:
  39880. + return n13_alu_e1_insn_dep_reg_p (consumer, def_reg);
  39881. +
  39882. + case TYPE_PBSADA:
  39883. + return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg);
  39884. +
  39885. + case TYPE_PBSAD:
  39886. + case TYPE_MUL:
  39887. + use_rtx = SET_SRC (PATTERN (consumer));
  39888. + break;
  39889. +
  39890. + case TYPE_MAC:
  39891. + acc_rtx = SET_SRC (PATTERN (consumer));
  39892. +
  39893. + if (REG_P (XEXP (acc_rtx, 0)))
  39894. + use_rtx = XEXP (acc_rtx, 1);
  39895. + else
  39896. + use_rtx = XEXP (acc_rtx, 0);
  39897. + break;
  39898. +
  39899. + case TYPE_DIV:
  39900. + if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
  39901. + || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
  39902. + use_rtx = SET_SRC (parallel_element (consumer, 0));
  39903. + else
  39904. + use_rtx = SET_SRC (PATTERN (consumer));
  39905. + break;
  39906. +
  39907. + case TYPE_MMU:
  39908. + if (GET_CODE (PATTERN (consumer)) == SET)
  39909. + use_rtx = SET_SRC (PATTERN (consumer));
  39910. + else
  39911. + return true;
  39912. + break;
  39913. +
  39914. + case TYPE_BRANCH:
  39915. + use_rtx = extract_branch_target_rtx (consumer);
  39916. + break;
  39917. +
  39918. + case TYPE_LOAD:
  39919. + case TYPE_STORE:
  39920. + use_rtx = extract_mem_rtx (consumer);
  39921. + break;
  39922. +
  39923. + case TYPE_LOAD_MULTIPLE:
  39924. + case TYPE_STORE_MULTIPLE:
  39925. + use_rtx = extract_base_reg (consumer);
  39926. + break;
  39927. +
  39928. + default:
  39929. + return false;
  39930. + }
  39931. +
  39932. + if (reg_overlap_p (def_reg, use_rtx))
  39933. + return true;
  39934. +
  39935. + return false;
  39936. +}
  39937. +
  39938. +bool
  39939. +n13_consumed_by_e2_dep_p (rtx consumer, rtx def_reg)
  39940. +{
  39941. + rtx use_rtx;
  39942. +
  39943. + switch (get_attr_type (consumer))
  39944. + {
  39945. + case TYPE_ALU:
  39946. + case TYPE_STORE:
  39947. + use_rtx = SET_SRC (PATTERN (consumer));
  39948. + break;
  39949. +
  39950. + case TYPE_ALU_SHIFT:
  39951. + use_rtx = extract_shift_reg (consumer);
  39952. + break;
  39953. +
  39954. + case TYPE_PBSADA:
  39955. + return pbsada_insn_rt_dep_reg_p (consumer, def_reg);
  39956. +
  39957. + case TYPE_STORE_MULTIPLE:
  39958. + use_rtx = extract_nth_access_rtx (consumer, 0);
  39959. + break;
  39960. +
  39961. + case TYPE_BRANCH:
  39962. + use_rtx = extract_branch_condition_rtx (consumer);
  39963. + break;
  39964. +
  39965. + default:
  39966. + gcc_unreachable();
  39967. + }
  39968. +
  39969. + if (reg_overlap_p (def_reg, use_rtx))
  39970. + return true;
  39971. +
  39972. + return false;
  39973. +}
  39974. +
  39975. +} // anonymous namespace
  39976. +
  39977. +/* ------------------------------------------------------------------------ */
  39978. +
  39979. +/* Functions to determine whether INSN is single-word or double-word
  39980. + load/store insn. */
  39981. +
  39982. +bool
  39983. +nds32_load_single_p (rtx insn)
  39984. +{
  39985. + if (get_attr_type (insn) != TYPE_LOAD)
  39986. + return false;
  39987. +
  39988. + if (INSN_CODE (insn) == CODE_FOR_move_di ||
  39989. + INSN_CODE (insn) == CODE_FOR_move_df)
  39990. + return false;
  39991. +
  39992. + return true;
  39993. +}
  39994. +
  39995. +bool
  39996. +nds32_store_single_p (rtx insn)
  39997. +{
  39998. + if (get_attr_type (insn) != TYPE_STORE)
  39999. + return false;
  40000. +
  40001. + if (INSN_CODE (insn) == CODE_FOR_move_di ||
  40002. + INSN_CODE (insn) == CODE_FOR_move_df)
  40003. + return false;
  40004. +
  40005. + return true;
  40006. +}
  40007. +
  40008. +bool
  40009. +nds32_load_double_p (rtx insn)
  40010. +{
  40011. + if (get_attr_type (insn) != TYPE_LOAD)
  40012. + return false;
  40013. +
  40014. + if (INSN_CODE (insn) != CODE_FOR_move_di &&
  40015. + INSN_CODE (insn) != CODE_FOR_move_df)
  40016. + return false;
  40017. +
  40018. + return true;
  40019. +}
  40020. +
  40021. +bool
  40022. +nds32_store_double_p (rtx insn)
  40023. +{
  40024. + if (get_attr_type (insn) != TYPE_STORE)
  40025. + return false;
  40026. +
  40027. + if (INSN_CODE (insn) != CODE_FOR_move_di &&
  40028. + INSN_CODE (insn) != CODE_FOR_move_df)
  40029. + return false;
  40030. +
  40031. + return true;
  40032. +}
  40033. +
  40034. +/* Guard functions for N7 core. */
  40035. +
  40036. +bool
  40037. +nds32_n7_load_to_ii_p (rtx producer, rtx consumer)
  40038. +{
  40039. + if (post_update_insn_p (producer))
  40040. + return false;
  40041. +
  40042. + rtx def_reg = SET_DEST (PATTERN (producer));
  40043. +
  40044. + return n7_consumed_by_ii_dep_p (consumer, def_reg);
  40045. +}
  40046. +
  40047. +bool
  40048. +nds32_n7_last_load_to_ii_p (rtx producer, rtx consumer)
  40049. +{
  40050. + /* If PRODUCER is a post-update LMW insn, the last micro-operation updates
  40051. + the base register and the result is ready in II stage, so we don't need
  40052. + to handle that case in this guard function and the corresponding bypass
  40053. + rule. */
  40054. + if (post_update_insn_p (producer))
  40055. + return false;
  40056. +
  40057. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40058. +
  40059. + if (last_def_reg == NULL_RTX)
  40060. + return false;
  40061. +
  40062. + gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
  40063. +
  40064. + return n7_consumed_by_ii_dep_p (consumer, last_def_reg);
  40065. +}
  40066. +
  40067. +/* Guard functions for N8 core. */
  40068. +
  40069. +bool
  40070. +nds32_n8_load_to_ii_p (rtx producer, rtx consumer)
  40071. +{
  40072. + if (post_update_insn_p (producer))
  40073. + return false;
  40074. +
  40075. + rtx def_reg = SET_DEST (PATTERN (producer));
  40076. +
  40077. + return n8_consumed_by_addr_in_p (consumer, def_reg);
  40078. +}
  40079. +
  40080. +bool
  40081. +nds32_n8_load_bi_to_ii_p (rtx producer, rtx consumer)
  40082. +{
  40083. + if (!post_update_insn_p (producer))
  40084. + return false;
  40085. +
  40086. + rtx def_reg = SET_DEST (PATTERN (producer));
  40087. +
  40088. + return n8_consumed_by_addr_in_p (consumer, def_reg);
  40089. +}
  40090. +
  40091. +bool
  40092. +nds32_n8_load_to_ex_p (rtx producer, rtx consumer)
  40093. +{
  40094. + if (post_update_insn_p (producer))
  40095. + return false;
  40096. +
  40097. + rtx def_reg = SET_DEST (PATTERN (producer));
  40098. +
  40099. + return n8_consumed_by_ex_p (consumer, def_reg);
  40100. +}
  40101. +
  40102. +bool
  40103. +nds32_n8_ex_to_ii_p (rtx producer, rtx consumer)
  40104. +{
  40105. + rtx def_reg;
  40106. +
  40107. + switch (get_attr_type (producer))
  40108. + {
  40109. + case TYPE_ALU:
  40110. + if (movd44_insn_p (producer))
  40111. + def_reg = extract_movd44_odd_reg (producer);
  40112. + else
  40113. + def_reg = SET_DEST (PATTERN (producer));
  40114. + break;
  40115. +
  40116. + case TYPE_MUL:
  40117. + case TYPE_MAC:
  40118. + def_reg = SET_DEST (PATTERN (producer));
  40119. + break;
  40120. +
  40121. + case TYPE_DIV:
  40122. + if (INSN_CODE (producer) == CODE_FOR_divmodsi4
  40123. + || INSN_CODE (producer) == CODE_FOR_udivmodsi4)
  40124. + def_reg = SET_DEST (parallel_element (producer, 1));
  40125. + else
  40126. + def_reg = SET_DEST (PATTERN (producer));
  40127. + break;
  40128. +
  40129. + case TYPE_LOAD:
  40130. + case TYPE_STORE:
  40131. + case TYPE_LOAD_MULTIPLE:
  40132. + case TYPE_STORE_MULTIPLE:
  40133. + if (!post_update_insn_p (producer))
  40134. + return false;
  40135. +
  40136. + def_reg = extract_base_reg (producer);
  40137. + break;
  40138. +
  40139. + default:
  40140. + gcc_unreachable ();
  40141. + }
  40142. +
  40143. + return n8_consumed_by_addr_in_p (consumer, def_reg);
  40144. +}
  40145. +
  40146. +bool
  40147. +nds32_n8_last_load_to_ii_p (rtx producer, rtx consumer)
  40148. +{
  40149. + /* If PRODUCER is a post-update LMW insn, the last micro-operation updates
  40150. + the base register and the result is ready in EX stage, so we don't need
  40151. + to handle that case in this guard function and the corresponding bypass
  40152. + rule. */
  40153. + if (post_update_insn_p (producer))
  40154. + return false;
  40155. +
  40156. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40157. +
  40158. + if (last_def_reg == NULL_RTX)
  40159. + return false;
  40160. +
  40161. + gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
  40162. +
  40163. + return n8_consumed_by_addr_in_p (consumer, last_def_reg);
  40164. +}
  40165. +
  40166. +bool
  40167. +nds32_n8_last_load_two_to_ii_p (rtx producer, rtx consumer)
  40168. +{
  40169. + int index = -2;
  40170. +
  40171. + /* If PRODUCER is a post-update insn, there is an additional one micro-
  40172. + operation inserted in the end, so the last memory access operation should
  40173. + be handled by this guard function and the corresponding bypass rule. */
  40174. + if (post_update_insn_p (producer))
  40175. + index = -1;
  40176. +
  40177. + rtx last_two_def_reg = extract_nth_access_reg (producer, index);
  40178. +
  40179. + if (last_two_def_reg == NULL_RTX)
  40180. + return false;
  40181. +
  40182. + gcc_assert (REG_P (last_two_def_reg)
  40183. + || GET_CODE (last_two_def_reg) == SUBREG);
  40184. +
  40185. + return n8_consumed_by_addr_in_p (consumer, last_two_def_reg);
  40186. +}
  40187. +
  40188. +bool
  40189. +nds32_n8_last_load_to_ex_p (rtx producer, rtx consumer)
  40190. +{
  40191. + /* If PRODUCER is a post-update LMW insn, the last micro-operation updates
  40192. + the base register and the result is ready in EX stage, so we don't need
  40193. + to handle that case in this guard function and the corresponding bypass
  40194. + rule. */
  40195. + if (post_update_insn_p (producer))
  40196. + return false;
  40197. +
  40198. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40199. +
  40200. + if (last_def_reg == NULL_RTX)
  40201. + return false;
  40202. +
  40203. + gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
  40204. +
  40205. + return n8_consumed_by_ex_p (consumer, last_def_reg);
  40206. +}
  40207. +
  40208. +/* Guard functions for E8 cores. */
  40209. +
  40210. +bool
  40211. +nds32_e8_load_to_ii_p (rtx producer, rtx consumer)
  40212. +{
  40213. + rtx def_reg = SET_DEST (PATTERN (producer));
  40214. +
  40215. + return e8_consumed_by_addr_in_p (consumer, def_reg);
  40216. +}
  40217. +
  40218. +bool
  40219. +nds32_e8_load_to_ex_p (rtx producer, rtx consumer)
  40220. +{
  40221. + rtx def_reg = SET_DEST (PATTERN (producer));
  40222. +
  40223. + return e8_consumed_by_ex_p (consumer, def_reg);
  40224. +}
  40225. +
  40226. +bool
  40227. +nds32_e8_ex_to_ii_p (rtx producer, rtx consumer)
  40228. +{
  40229. + rtx def_reg;
  40230. +
  40231. + switch (get_attr_type (producer))
  40232. + {
  40233. + case TYPE_ALU:
  40234. + /* No data hazards if AGEN's input is produced by MOVI or SETHI. */
  40235. + if (GET_CODE (PATTERN (producer)) == SET)
  40236. + {
  40237. + rtx dest = SET_DEST (PATTERN (producer));
  40238. + rtx src = SET_SRC (PATTERN (producer));
  40239. +
  40240. + if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
  40241. + && (GET_CODE (src) == CONST_INT || GET_CODE (src) == HIGH))
  40242. + return false;
  40243. + }
  40244. +
  40245. + def_reg = SET_DEST (PATTERN (producer));
  40246. + break;
  40247. +
  40248. + case TYPE_MUL:
  40249. + case TYPE_MAC:
  40250. + def_reg = SET_DEST (PATTERN (producer));
  40251. + break;
  40252. +
  40253. + case TYPE_DIV:
  40254. + if (INSN_CODE (producer) == CODE_FOR_divmodsi4
  40255. + || INSN_CODE (producer) == CODE_FOR_udivmodsi4)
  40256. + {
  40257. + rtx def_reg1 = SET_DEST (parallel_element (producer, 0));
  40258. + rtx def_reg2 = SET_DEST (parallel_element (producer, 1));
  40259. +
  40260. + return (e8_consumed_by_addr_in_p (consumer, def_reg1)
  40261. + || e8_consumed_by_addr_in_p (consumer, def_reg2));
  40262. + }
  40263. +
  40264. + def_reg = SET_DEST (PATTERN (producer));
  40265. + break;
  40266. +
  40267. + case TYPE_LOAD:
  40268. + case TYPE_STORE:
  40269. + case TYPE_LOAD_MULTIPLE:
  40270. + case TYPE_STORE_MULTIPLE:
  40271. + if (!post_update_insn_p (producer))
  40272. + return false;
  40273. +
  40274. + def_reg = extract_base_reg (producer);
  40275. + break;
  40276. +
  40277. + default:
  40278. + gcc_unreachable ();
  40279. + }
  40280. +
  40281. + return e8_consumed_by_addr_in_p (consumer, def_reg);
  40282. +}
  40283. +
  40284. +bool
  40285. +nds32_e8_last_load_to_ii_p (rtx producer, rtx consumer)
  40286. +{
  40287. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40288. +
  40289. + if (last_def_reg == NULL_RTX)
  40290. + return false;
  40291. +
  40292. + gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
  40293. +
  40294. + return e8_consumed_by_addr_in_p (consumer, last_def_reg);
  40295. +}
  40296. +
  40297. +bool
  40298. +nds32_e8_last_load_to_ex_p (rtx producer, rtx consumer)
  40299. +{
  40300. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40301. +
  40302. + if (last_def_reg == NULL_RTX)
  40303. + return false;
  40304. +
  40305. + gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
  40306. +
  40307. + return e8_consumed_by_ex_p (consumer, last_def_reg);
  40308. +}
  40309. +
  40310. +/* Guard functions for N9/N10 cores. */
  40311. +
  40312. +bool
  40313. +nds32_n9_2r1w_mm_to_ex_p (rtx producer, rtx consumer)
  40314. +{
  40315. + rtx def_reg;
  40316. +
  40317. + switch (get_attr_type (producer))
  40318. + {
  40319. + case TYPE_LOAD:
  40320. + if (post_update_insn_p (producer))
  40321. + return false;
  40322. +
  40323. + def_reg = SET_DEST (PATTERN (producer));
  40324. + break;
  40325. +
  40326. + case TYPE_MUL:
  40327. + case TYPE_MAC:
  40328. + def_reg = SET_DEST (PATTERN (producer));
  40329. + break;
  40330. +
  40331. + default:
  40332. + gcc_unreachable ();
  40333. + }
  40334. +
  40335. + return n9_2r1w_consumed_by_ex_dep_p (consumer, def_reg);
  40336. +}
  40337. +
  40338. +bool
  40339. +nds32_n9_3r2w_mm_to_ex_p (rtx producer, rtx consumer)
  40340. +{
  40341. + rtx def_reg;
  40342. +
  40343. + switch (get_attr_type (producer))
  40344. + {
  40345. + case TYPE_LOAD:
  40346. + case TYPE_MUL:
  40347. + case TYPE_MAC:
  40348. + def_reg = SET_DEST (PATTERN (producer));
  40349. + break;
  40350. +
  40351. + case TYPE_DIV:
  40352. + if (INSN_CODE (producer) == CODE_FOR_divmodsi4
  40353. + || INSN_CODE (producer) == CODE_FOR_udivmodsi4)
  40354. + {
  40355. + rtx def_reg1 = SET_DEST (parallel_element (producer, 0));
  40356. + rtx def_reg2 = SET_DEST (parallel_element (producer, 1));
  40357. +
  40358. + return (n9_3r2w_consumed_by_ex_dep_p (consumer, def_reg1)
  40359. + || n9_3r2w_consumed_by_ex_dep_p (consumer, def_reg2));
  40360. + }
  40361. +
  40362. + def_reg = SET_DEST (PATTERN (producer));
  40363. + break;
  40364. +
  40365. + default:
  40366. + gcc_unreachable ();
  40367. + }
  40368. +
  40369. + return n9_3r2w_consumed_by_ex_dep_p (consumer, def_reg);
  40370. +}
  40371. +
  40372. +bool
  40373. +nds32_n9_last_load_to_ex_p (rtx producer, rtx consumer)
  40374. +{
  40375. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40376. +
  40377. + if (nds32_register_ports_config == REG_PORT_2R1W)
  40378. + {
  40379. + /* The base-update micro operation occupies the last cycle. */
  40380. + if (post_update_insn_p (producer))
  40381. + return false;
  40382. +
  40383. + /* When the base register is in the list of a load multiple insn and the
  40384. + access order of the base register is not the last one, we need an
  40385. + additional micro operation to commit the load result to the base
  40386. + register -- we can treat the base register as the last defined
  40387. + register. */
  40388. + size_t i;
  40389. + size_t n_elems = parallel_elements (producer);
  40390. + rtx base_reg = extract_base_reg (producer);
  40391. +
  40392. + for (i = 0; i < n_elems; ++i)
  40393. + {
  40394. + rtx load_rtx = extract_nth_access_rtx (producer, i);
  40395. + rtx list_element = SET_DEST (load_rtx);
  40396. +
  40397. + if (rtx_equal_p (base_reg, list_element) && i != n_elems - 1)
  40398. + {
  40399. + last_def_reg = base_reg;
  40400. + break;
  40401. + }
  40402. + }
  40403. +
  40404. + return n9_2r1w_consumed_by_ex_dep_p (consumer, last_def_reg);
  40405. + }
  40406. + else
  40407. + return n9_3r2w_consumed_by_ex_dep_p (consumer, last_def_reg);
  40408. +}
  40409. +
  40410. +/* Guard functions for N12/N13 cores. */
  40411. +
  40412. +bool
  40413. +nds32_n13_addr_in_p (rtx producer, rtx consumer)
  40414. +{
  40415. + rtx reg;
  40416. +
  40417. + switch (get_attr_type (producer))
  40418. + {
  40419. + case TYPE_LOAD:
  40420. + case TYPE_MUL:
  40421. + case TYPE_ALU:
  40422. + case TYPE_ALU_SHIFT:
  40423. + reg = SET_DEST (PATTERN (producer));
  40424. + break;
  40425. +
  40426. + default:
  40427. + return false;
  40428. + }
  40429. +
  40430. + if (address_use_reg_p (consumer, reg))
  40431. + return true;
  40432. +
  40433. + return false;
  40434. +}
  40435. +
  40436. +bool
  40437. +nds32_n13_e2_to_e1_p (rtx producer, rtx consumer)
  40438. +{
  40439. + rtx def_reg;
  40440. +
  40441. + switch (get_attr_type (producer))
  40442. + {
  40443. + case TYPE_LOAD:
  40444. + case TYPE_STORE:
  40445. + case TYPE_LOAD_MULTIPLE:
  40446. + case TYPE_STORE_MULTIPLE:
  40447. + if (!post_update_insn_p (producer))
  40448. + return false;
  40449. +
  40450. + def_reg = extract_base_reg (producer);
  40451. + break;
  40452. +
  40453. + case TYPE_ALU:
  40454. + case TYPE_ALU_SHIFT:
  40455. + case TYPE_PBSAD:
  40456. + case TYPE_PBSADA:
  40457. + case TYPE_MUL:
  40458. + case TYPE_MAC:
  40459. + def_reg = SET_DEST (PATTERN (producer));
  40460. + break;
  40461. +
  40462. + case TYPE_BRANCH:
  40463. + return true;
  40464. +
  40465. + case TYPE_DIV:
  40466. + if (INSN_CODE (producer) == CODE_FOR_divmodsi4
  40467. + || INSN_CODE (producer) == CODE_FOR_udivmodsi4)
  40468. + {
  40469. + rtx def_reg1 = SET_DEST (parallel_element (producer, 0));
  40470. + rtx def_reg2 = SET_DEST (parallel_element (producer, 1));
  40471. +
  40472. + return (n13_consumed_by_e1_dep_p (consumer, def_reg1)
  40473. + || n13_consumed_by_e1_dep_p (consumer, def_reg2));
  40474. + }
  40475. +
  40476. + def_reg = SET_DEST (PATTERN (producer));
  40477. + break;
  40478. +
  40479. + default:
  40480. + gcc_unreachable ();
  40481. + }
  40482. +
  40483. + return n13_consumed_by_e1_dep_p (consumer, def_reg);
  40484. +}
  40485. +
  40486. +bool
  40487. +nds32_n13_load_to_e1_p (rtx producer, rtx consumer)
  40488. +{
  40489. + rtx def_reg = SET_DEST (PATTERN (producer));
  40490. +
  40491. + gcc_assert (get_attr_type (producer) == TYPE_LOAD);
  40492. + gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
  40493. +
  40494. + return n13_consumed_by_e1_dep_p (consumer, def_reg);
  40495. +}
  40496. +
  40497. +bool
  40498. +nds32_n13_load_to_e2_p (rtx producer, rtx consumer)
  40499. +{
  40500. + rtx def_reg = SET_DEST (PATTERN (producer));
  40501. +
  40502. + gcc_assert (get_attr_type (producer) == TYPE_LOAD);
  40503. + gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
  40504. +
  40505. + return n13_consumed_by_e2_dep_p (consumer, def_reg);
  40506. +}
  40507. +
  40508. +bool
  40509. +nds32_n13_last_load_to_e1_p (rtx producer, rtx consumer)
  40510. +{
  40511. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40512. +
  40513. + return n13_consumed_by_e1_dep_p (consumer, last_def_reg);
  40514. +}
  40515. +
  40516. +bool
  40517. +nds32_n13_last_load_to_e2_p (rtx producer, rtx consumer)
  40518. +{
  40519. + rtx last_def_reg = extract_nth_access_reg (producer, -1);
  40520. +
  40521. + return n13_consumed_by_e2_dep_p (consumer, last_def_reg);
  40522. +}
  40523. +
  40524. +bool
  40525. +nds32_n13_last_two_load_to_e1_p (rtx producer, rtx consumer)
  40526. +{
  40527. + rtx last_two_def_reg = extract_nth_access_reg (producer, -2);
  40528. +
  40529. + if (last_two_def_reg == NULL_RTX)
  40530. + return false;
  40531. +
  40532. + return n13_consumed_by_e1_dep_p (consumer, last_two_def_reg);
  40533. +}
  40534. +
  40535. +/* ------------------------------------------------------------------------ */
  40536. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-predicates.c gcc-4.9.4/gcc/config/nds32/nds32-predicates.c
  40537. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-predicates.c 1970-01-01 01:00:00.000000000 +0100
  40538. +++ gcc-4.9.4/gcc/config/nds32/nds32-predicates.c 2016-08-08 20:37:45.582273034 +0200
  40539. @@ -0,0 +1,714 @@
  40540. +/* Predicate functions of Andes NDS32 cpu for GNU compiler
  40541. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  40542. + Contributed by Andes Technology Corporation.
  40543. +
  40544. + This file is part of GCC.
  40545. +
  40546. + GCC is free software; you can redistribute it and/or modify it
  40547. + under the terms of the GNU General Public License as published
  40548. + by the Free Software Foundation; either version 3, or (at your
  40549. + option) any later version.
  40550. +
  40551. + GCC is distributed in the hope that it will be useful, but WITHOUT
  40552. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  40553. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  40554. + License for more details.
  40555. +
  40556. + You should have received a copy of the GNU General Public License
  40557. + along with GCC; see the file COPYING3. If not see
  40558. + <http://www.gnu.org/licenses/>. */
  40559. +
  40560. +/* ------------------------------------------------------------------------ */
  40561. +
  40562. +#include "config.h"
  40563. +#include "system.h"
  40564. +#include "coretypes.h"
  40565. +#include "tm.h"
  40566. +#include "tree.h"
  40567. +#include "rtl.h"
  40568. +#include "regs.h"
  40569. +#include "hard-reg-set.h"
  40570. +#include "insn-config.h" /* Required by recog.h. */
  40571. +#include "conditions.h"
  40572. +#include "output.h"
  40573. +#include "insn-attr.h" /* For DFA state_t. */
  40574. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  40575. +#include "reload.h" /* For push_reload(). */
  40576. +#include "flags.h"
  40577. +#include "function.h"
  40578. +#include "expr.h"
  40579. +#include "recog.h"
  40580. +#include "diagnostic-core.h"
  40581. +#include "df.h"
  40582. +#include "tm_p.h"
  40583. +#include "tm-constrs.h"
  40584. +#include "optabs.h" /* For GEN_FCN. */
  40585. +#include "target.h"
  40586. +#include "target-def.h"
  40587. +#include "langhooks.h" /* For add_builtin_function(). */
  40588. +#include "ggc.h"
  40589. +
  40590. +/* ------------------------------------------------------------------------ */
  40591. +
  40592. +/* A subroutine that checks multiple load and store
  40593. + using consecutive registers.
  40594. + OP is a parallel rtx we would like to check.
  40595. + LOAD_P indicates whether we are checking load operation.
  40596. + PAR_INDEX is starting element of parallel rtx.
  40597. + FIRST_ELT_REGNO is used to tell starting register number.
  40598. + COUNT helps us to check consecutive register numbers. */
  40599. +static bool
  40600. +nds32_consecutive_registers_load_store_p (rtx op,
  40601. + bool load_p,
  40602. + int par_index,
  40603. + int first_elt_regno,
  40604. + int count)
  40605. +{
  40606. + int i;
  40607. + int check_regno;
  40608. + rtx elt;
  40609. + rtx elt_reg;
  40610. + rtx elt_mem;
  40611. +
  40612. + for (i = 0; i < count; i++)
  40613. + {
  40614. + /* Pick up each element from parallel rtx. */
  40615. + elt = XVECEXP (op, 0, i + par_index);
  40616. +
  40617. + /* If this element is not a 'set' rtx, return false immediately. */
  40618. + if (GET_CODE (elt) != SET)
  40619. + return false;
  40620. +
  40621. + /* Pick up reg and mem of this element. */
  40622. + elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
  40623. + elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
  40624. +
  40625. + /* If elt_reg is not a expected reg rtx, return false. */
  40626. + if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
  40627. + return false;
  40628. + /* If elt_mem is not a expected mem rtx, return false. */
  40629. + if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
  40630. + return false;
  40631. +
  40632. + /* The consecutive registers should be in (Rb,Rb+1...Re) order. */
  40633. + check_regno = first_elt_regno + i;
  40634. +
  40635. + /* If the register number is not continuous, return false. */
  40636. + if (REGNO (elt_reg) != (unsigned int) check_regno)
  40637. + return false;
  40638. + }
  40639. +
  40640. + return true;
  40641. +}
  40642. +
  40643. +/* Function to check whether the OP is a valid load/store operation.
  40644. + This is a helper function for the predicates:
  40645. + 'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
  40646. + in predicates.md file.
  40647. +
  40648. + The OP is supposed to be a parallel rtx.
  40649. + For each element within this parallel rtx:
  40650. + (set (reg) (mem addr)) is the form for load operation.
  40651. + (set (mem addr) (reg)) is the form for store operation.
  40652. + We have to extract reg and mem of every element and
  40653. + check if the information is valid for multiple load/store operation. */
  40654. +bool
  40655. +nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
  40656. +{
  40657. + int count;
  40658. + int first_elt_regno;
  40659. + int update_base_elt_idx;
  40660. + int offset;
  40661. + rtx elt;
  40662. + rtx update_base;
  40663. +
  40664. + /* Get the counts of elements in the parallel rtx.
  40665. + Last one is update base register if bim_p.
  40666. + and pick up the first element. */
  40667. + if (bim_p)
  40668. + {
  40669. + count = XVECLEN (op, 0) - 1;
  40670. + elt = XVECEXP (op, 0, 1);
  40671. + }
  40672. + else
  40673. + {
  40674. + count = XVECLEN (op, 0);
  40675. + elt = XVECEXP (op, 0, 0);
  40676. + }
  40677. +
  40678. + /* Perform some quick check for the first element in the parallel rtx. */
  40679. + if (GET_CODE (elt) != SET
  40680. + || count <= 1
  40681. + || count > 10)
  40682. + return false;
  40683. +
  40684. + /* Pick up regno of first element for further detail checking.
  40685. + Note that the form is different between load and store operation. */
  40686. + if (load_p)
  40687. + {
  40688. + if (GET_CODE (SET_DEST (elt)) != REG
  40689. + || GET_CODE (SET_SRC (elt)) != MEM)
  40690. + return false;
  40691. +
  40692. + first_elt_regno = REGNO (SET_DEST (elt));
  40693. + }
  40694. + else
  40695. + {
  40696. + if (GET_CODE (SET_SRC (elt)) != REG
  40697. + || GET_CODE (SET_DEST (elt)) != MEM)
  40698. + return false;
  40699. +
  40700. + first_elt_regno = REGNO (SET_SRC (elt));
  40701. + }
  40702. +
  40703. + /* Perform detail check for each element.
  40704. + Refer to nds32-multiple.md for more information
  40705. + about following checking.
  40706. + The starting element of parallel rtx is index 0. */
  40707. + if (!nds32_consecutive_registers_load_store_p (op, load_p, bim_p ? 1 : 0,
  40708. + first_elt_regno,
  40709. + count))
  40710. + return false;
  40711. +
  40712. + if (bim_p)
  40713. + {
  40714. + update_base_elt_idx = 0;
  40715. + update_base = XVECEXP (op, 0, update_base_elt_idx);
  40716. + if (!REG_P (SET_DEST (update_base)))
  40717. + return false;
  40718. + if (GET_CODE (SET_SRC (update_base)) != PLUS)
  40719. + return false;
  40720. + else
  40721. + {
  40722. + offset = count * UNITS_PER_WORD;
  40723. + elt = XEXP (SET_SRC (update_base), 1);
  40724. + if (GET_CODE (elt) != CONST_INT
  40725. + || (INTVAL (elt) != offset))
  40726. + return false;
  40727. + }
  40728. + }
  40729. +
  40730. + /* Pass all test, this is a valid rtx. */
  40731. + return true;
  40732. +}
  40733. +
  40734. +/* Function to check whether the OP is a valid stack push/pop operation.
  40735. + For a valid stack operation, it must satisfy following conditions:
  40736. + 1. Consecutive registers push/pop operations.
  40737. + 2. Valid $fp/$gp/$lp push/pop operations.
  40738. + 3. The last element must be stack adjustment rtx.
  40739. + See the prologue/epilogue implementation for details. */
  40740. +bool
  40741. +nds32_valid_stack_push_pop_p (rtx op, bool push_p)
  40742. +{
  40743. + int index;
  40744. + int total_count;
  40745. + int rest_count;
  40746. + int first_regno;
  40747. + int save_fp, save_gp, save_lp;
  40748. + rtx elt;
  40749. + rtx elt_reg;
  40750. + rtx elt_mem;
  40751. + rtx elt_plus;
  40752. +
  40753. + /* Get the counts of elements in the parallel rtx. */
  40754. + total_count = XVECLEN (op, 0);
  40755. +
  40756. + /* Perform some quick check for that every element should be 'set'. */
  40757. + for (index = 0; index < total_count; index++)
  40758. + {
  40759. + elt = XVECEXP (op, 0, index);
  40760. + if (GET_CODE (elt) != SET)
  40761. + return false;
  40762. + }
  40763. +
  40764. + /* For push operation, the parallel rtx looks like:
  40765. + (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
  40766. + (reg:SI Rb))
  40767. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
  40768. + (reg:SI Rb+1))
  40769. + ...
  40770. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
  40771. + (reg:SI Re))
  40772. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
  40773. + (reg:SI FP_REGNUM))
  40774. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
  40775. + (reg:SI GP_REGNUM))
  40776. + (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
  40777. + (reg:SI LP_REGNUM))
  40778. + (set (reg:SI SP_REGNUM)
  40779. + (plus (reg:SI SP_REGNUM) (const_int -32)))])
  40780. +
  40781. + For pop operation, the parallel rtx looks like:
  40782. + (parallel [(set (reg:SI Rb)
  40783. + (mem (reg:SI SP_REGNUM)))
  40784. + (set (reg:SI Rb+1)
  40785. + (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
  40786. + ...
  40787. + (set (reg:SI Re)
  40788. + (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
  40789. + (set (reg:SI FP_REGNUM)
  40790. + (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
  40791. + (set (reg:SI GP_REGNUM)
  40792. + (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
  40793. + (set (reg:SI LP_REGNUM)
  40794. + (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
  40795. + (set (reg:SI SP_REGNUM)
  40796. + (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
  40797. +
  40798. + /* 1. Consecutive registers push/pop operations.
  40799. + We need to calculate how many registers should be consecutive.
  40800. + The $sp adjustment rtx, $fp push rtx, $gp push rtx,
  40801. + and $lp push rtx are excluded. */
  40802. +
  40803. + /* Detect whether we have $fp, $gp, or $lp in the parallel rtx. */
  40804. + save_fp = reg_mentioned_p (gen_rtx_REG (SImode, FP_REGNUM), op);
  40805. + save_gp = reg_mentioned_p (gen_rtx_REG (SImode, GP_REGNUM), op);
  40806. + save_lp = reg_mentioned_p (gen_rtx_REG (SImode, LP_REGNUM), op);
  40807. + /* Exclude last $sp adjustment rtx. */
  40808. + rest_count = total_count - 1;
  40809. + /* Exclude $fp, $gp, and $lp if they are in the parallel rtx. */
  40810. + if (save_fp)
  40811. + rest_count--;
  40812. + if (save_gp)
  40813. + rest_count--;
  40814. + if (save_lp)
  40815. + rest_count--;
  40816. +
  40817. + if (rest_count > 0)
  40818. + {
  40819. + elt = XVECEXP (op, 0, 0);
  40820. + /* Pick up register element. */
  40821. + elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  40822. + first_regno = REGNO (elt_reg);
  40823. +
  40824. + /* The 'push' operation is a kind of store operation.
  40825. + The 'pop' operation is a kind of load operation.
  40826. + Pass corresponding false/true as second argument (bool load_p).
  40827. + The par_index is supposed to start with index 0. */
  40828. + if (!nds32_consecutive_registers_load_store_p (op,
  40829. + !push_p ? true : false,
  40830. + 0,
  40831. + first_regno,
  40832. + rest_count))
  40833. + return false;
  40834. + }
  40835. +
  40836. + /* 2. Valid $fp/$gp/$lp push/pop operations.
  40837. + Remember to set start index for checking them. */
  40838. +
  40839. + /* The rest_count is the start index for checking $fp/$gp/$lp. */
  40840. + index = rest_count;
  40841. + /* If index < 0, this parallel rtx is definitely
  40842. + not a valid stack push/pop operation. */
  40843. + if (index < 0)
  40844. + return false;
  40845. +
  40846. + /* Check $fp/$gp/$lp one by one.
  40847. + We use 'push_p' to pick up reg rtx and mem rtx. */
  40848. + if (save_fp)
  40849. + {
  40850. + elt = XVECEXP (op, 0, index);
  40851. + elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  40852. + elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  40853. + index++;
  40854. +
  40855. + if (GET_CODE (elt_mem) != MEM
  40856. + || GET_CODE (elt_reg) != REG
  40857. + || REGNO (elt_reg) != FP_REGNUM)
  40858. + return false;
  40859. + }
  40860. + if (save_gp)
  40861. + {
  40862. + elt = XVECEXP (op, 0, index);
  40863. + elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  40864. + elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  40865. + index++;
  40866. +
  40867. + if (GET_CODE (elt_mem) != MEM
  40868. + || GET_CODE (elt_reg) != REG
  40869. + || REGNO (elt_reg) != GP_REGNUM)
  40870. + return false;
  40871. + }
  40872. + if (save_lp)
  40873. + {
  40874. + elt = XVECEXP (op, 0, index);
  40875. + elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
  40876. + elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
  40877. + index++;
  40878. +
  40879. + if (GET_CODE (elt_mem) != MEM
  40880. + || GET_CODE (elt_reg) != REG
  40881. + || REGNO (elt_reg) != LP_REGNUM)
  40882. + return false;
  40883. + }
  40884. +
  40885. + /* 3. The last element must be stack adjustment rtx.
  40886. + Its form of rtx should be:
  40887. + (set (reg:SI SP_REGNUM)
  40888. + (plus (reg:SI SP_REGNUM) (const_int X)))
  40889. + The X could be positive or negative value. */
  40890. +
  40891. + /* Pick up the last element. */
  40892. + elt = XVECEXP (op, 0, total_count - 1);
  40893. +
  40894. + /* Extract its destination and source rtx. */
  40895. + elt_reg = SET_DEST (elt);
  40896. + elt_plus = SET_SRC (elt);
  40897. +
  40898. + /* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
  40899. + if (GET_CODE (elt_reg) != REG
  40900. + || GET_CODE (elt_plus) != PLUS
  40901. + || REGNO (elt_reg) != SP_REGNUM)
  40902. + return false;
  40903. +
  40904. + /* Pass all test, this is a valid rtx. */
  40905. + return true;
  40906. +}
  40907. +
  40908. +/* Function to check if 'bclr' instruction can be used with IVAL. */
  40909. +bool
  40910. +nds32_can_use_bclr_p (HOST_WIDE_INT ival)
  40911. +{
  40912. + int one_bit_count;
  40913. + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
  40914. +
  40915. + /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
  40916. + it means the original ival has only one 0-bit,
  40917. + So it is ok to perform 'bclr' operation. */
  40918. +
  40919. + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival) & mask);
  40920. +
  40921. + /* 'bclr' is a performance extension instruction. */
  40922. + return (TARGET_EXT_PERF && (one_bit_count == 1));
  40923. +}
  40924. +
  40925. +/* Function to check if 'bset' instruction can be used with IVAL. */
  40926. +bool
  40927. +nds32_can_use_bset_p (HOST_WIDE_INT ival)
  40928. +{
  40929. + int one_bit_count;
  40930. + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
  40931. +
  40932. + /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
  40933. + it is ok to perform 'bset' operation. */
  40934. +
  40935. + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask);
  40936. +
  40937. + /* 'bset' is a performance extension instruction. */
  40938. + return (TARGET_EXT_PERF && (one_bit_count == 1));
  40939. +}
  40940. +
  40941. +/* Function to check if 'btgl' instruction can be used with IVAL. */
  40942. +bool
  40943. +nds32_can_use_btgl_p (HOST_WIDE_INT ival)
  40944. +{
  40945. + int one_bit_count;
  40946. + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode);
  40947. +
  40948. + /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
  40949. + it is ok to perform 'btgl' operation. */
  40950. +
  40951. + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask);
  40952. +
  40953. + /* 'btgl' is a performance extension instruction. */
  40954. + return (TARGET_EXT_PERF && (one_bit_count == 1));
  40955. +}
  40956. +
  40957. +/* Function to check if 'bitci' instruction can be used with IVAL. */
  40958. +bool
  40959. +nds32_can_use_bitci_p (HOST_WIDE_INT ival)
  40960. +{
  40961. + /* If we are using V3 ISA, we have 'bitci' instruction.
  40962. + Try to see if we can present 'andi' semantic with
  40963. + such 'bit-clear-immediate' operation.
  40964. + For example, 'andi $r0,$r0,0xfffffffc' can be
  40965. + presented with 'bitci $r0,$r0,3'. */
  40966. + return (TARGET_ISA_V3
  40967. + && (ival < 0)
  40968. + && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
  40969. +}
  40970. +
  40971. +/* Return true if is load/store with SYMBOL_REF addressing mode
  40972. + and memory mode is SImode. */
  40973. +bool
  40974. +nds32_symbol_load_store_p (rtx insn)
  40975. +{
  40976. + rtx mem_src = NULL_RTX;
  40977. +
  40978. + switch (get_attr_type (insn))
  40979. + {
  40980. + case TYPE_LOAD:
  40981. + mem_src = SET_SRC (PATTERN (insn));
  40982. + break;
  40983. + case TYPE_STORE:
  40984. + mem_src = SET_DEST (PATTERN (insn));
  40985. + break;
  40986. + default:
  40987. + break;
  40988. + }
  40989. +
  40990. + /* Find load/store insn with addressing mode is SYMBOL_REF. */
  40991. + if (mem_src != NULL_RTX)
  40992. + {
  40993. + if ((GET_CODE (mem_src) == ZERO_EXTEND)
  40994. + || (GET_CODE (mem_src) == SIGN_EXTEND))
  40995. + mem_src = XEXP (mem_src, 0);
  40996. +
  40997. + if ((GET_CODE (XEXP (mem_src, 0)) == SYMBOL_REF)
  40998. + || (GET_CODE (XEXP (mem_src, 0)) == LO_SUM))
  40999. + return true;
  41000. + }
  41001. +
  41002. + return false;
  41003. +}
  41004. +
  41005. +/* Vaild memory operand for floating-point loads and stores */
  41006. +bool
  41007. +nds32_float_mem_operand_p (rtx op)
  41008. +{
  41009. + enum machine_mode mode = GET_MODE (op);
  41010. + rtx addr = XEXP (op, 0);
  41011. +
  41012. + /* Not support [symbol] [const] memory */
  41013. + if (GET_CODE (addr) == SYMBOL_REF
  41014. + || GET_CODE (addr) == CONST
  41015. + || GET_CODE (addr) == LO_SUM)
  41016. + return false;
  41017. +
  41018. + if (GET_CODE (addr) == PLUS)
  41019. + {
  41020. + if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF)
  41021. + return false;
  41022. +
  41023. + /* Restrict const range: (imm12s << 2) */
  41024. + if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
  41025. + {
  41026. + if ((mode == SImode || mode == SFmode)
  41027. + && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
  41028. + && !satisfies_constraint_Is14 ( XEXP(addr, 1)))
  41029. + return false;
  41030. +
  41031. + if ((mode == DImode || mode == DFmode)
  41032. + && NDS32_DOUBLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
  41033. + && !satisfies_constraint_Is14 (XEXP (addr, 1)))
  41034. + return false;
  41035. + }
  41036. + }
  41037. +
  41038. + return true;
  41039. +}
  41040. +
  41041. +int
  41042. +nds32_cond_move_p (rtx cmp_rtx)
  41043. +{
  41044. + enum machine_mode cmp0_mode = GET_MODE (XEXP (cmp_rtx, 0));
  41045. + enum machine_mode cmp1_mode = GET_MODE (XEXP (cmp_rtx, 1));
  41046. + enum rtx_code cond = GET_CODE (cmp_rtx);
  41047. +
  41048. + if ((cmp0_mode == DFmode || cmp0_mode == SFmode)
  41049. + && (cmp1_mode == DFmode || cmp1_mode == SFmode)
  41050. + && (cond == ORDERED || cond == UNORDERED))
  41051. + return true;
  41052. + return false;
  41053. +}
  41054. +
  41055. +/* Return true if the addresses in mem1 and mem2 are suitable for use in
  41056. + an fldi or fsdi instruction.
  41057. +
  41058. + This can only happen when addr1 and addr2, the addresses in mem1
  41059. + and mem2, are consecutive memory locations (addr1 + 4 == addr2).
  41060. + addr1 must also be aligned on a 64-bit boundary. */
  41061. +bool
  41062. +nds32_memory_merge_peep_p (rtx mem1, rtx mem2)
  41063. +{
  41064. + rtx addr1, addr2;
  41065. + unsigned int reg1;
  41066. + HOST_WIDE_INT offset1;
  41067. +
  41068. + /* The mems cannot be volatile. */
  41069. + if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
  41070. + return false;
  41071. +
  41072. + /* MEM1 should be aligned on a 64-bit boundary. */
  41073. + if (MEM_ALIGN (mem1) < 64)
  41074. + return false;
  41075. +
  41076. + addr1 = XEXP (mem1, 0);
  41077. + addr2 = XEXP (mem2, 0);
  41078. +
  41079. + /* Extract a register number and offset (if used) from the first addr. */
  41080. + if (GET_CODE (addr1) == PLUS)
  41081. + {
  41082. + if (GET_CODE (XEXP (addr1, 0)) != REG)
  41083. + return false;
  41084. + else
  41085. + {
  41086. + reg1 = REGNO (XEXP (addr1, 0));
  41087. + if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
  41088. + return false;
  41089. +
  41090. + offset1 = INTVAL (XEXP (addr1, 1));
  41091. + }
  41092. + }
  41093. + else if (GET_CODE (addr1) != REG)
  41094. + return false;
  41095. + else
  41096. + {
  41097. + reg1 = REGNO (addr1);
  41098. + /* This was a simple (mem (reg)) expression. Offset is 0. */
  41099. + offset1 = 0;
  41100. + }
  41101. + /* Make sure the second address is a (mem (plus (reg) (const_int). */
  41102. + if (GET_CODE (addr2) != PLUS)
  41103. + return false;
  41104. +
  41105. + if (GET_CODE (XEXP (addr2, 0)) != REG
  41106. + || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
  41107. + return false;
  41108. +
  41109. + if (reg1 != REGNO (XEXP (addr2, 0)))
  41110. + return false;
  41111. +
  41112. + /* The first offset must be evenly divisible by 8 to ensure the
  41113. + address is 64 bit aligned. */
  41114. + if (offset1 % 8 != 0)
  41115. + return false;
  41116. +
  41117. + /* The offset for the second addr must be 4 more than the first addr. */
  41118. + if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
  41119. + return false;
  41120. +
  41121. + return true;
  41122. +}
  41123. +
  41124. +bool
  41125. +nds32_const_double_range_ok_p (rtx op, enum machine_mode mode,
  41126. + HOST_WIDE_INT lower, HOST_WIDE_INT upper)
  41127. +{
  41128. + if (GET_CODE (op) != CONST_DOUBLE
  41129. + || GET_MODE (op) != mode)
  41130. + return false;
  41131. +
  41132. + REAL_VALUE_TYPE rv;
  41133. + long val;
  41134. +
  41135. + REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
  41136. + REAL_VALUE_TO_TARGET_SINGLE (rv, val);
  41137. +
  41138. + return val >= lower && val < upper;
  41139. +}
  41140. +
  41141. +bool
  41142. +nds32_const_unspec_p (rtx x)
  41143. +{
  41144. + if (GET_CODE (x) == CONST)
  41145. + {
  41146. + x = XEXP (x, 0);
  41147. +
  41148. + if (GET_CODE (x) == PLUS)
  41149. + x = XEXP (x, 0);
  41150. +
  41151. + if (GET_CODE (x) == UNSPEC)
  41152. + {
  41153. + switch (XINT (x, 1))
  41154. + {
  41155. + case UNSPEC_GOTINIT:
  41156. + case UNSPEC_GOT:
  41157. + case UNSPEC_GOTOFF:
  41158. + case UNSPEC_PLT:
  41159. + case UNSPEC_TLSGD:
  41160. + case UNSPEC_TLSLD:
  41161. + case UNSPEC_TLSIE:
  41162. + case UNSPEC_TLSLE:
  41163. + return false;
  41164. + default:
  41165. + return true;
  41166. + }
  41167. + }
  41168. + }
  41169. +
  41170. + if (GET_CODE (x) == SYMBOL_REF
  41171. + && SYMBOL_REF_TLS_MODEL (x))
  41172. + return false;
  41173. +
  41174. + return true;
  41175. +}
  41176. +
  41177. +HOST_WIDE_INT
  41178. +const_vector_to_hwint (rtx op)
  41179. +{
  41180. + HOST_WIDE_INT hwint = 0;
  41181. + HOST_WIDE_INT mask;
  41182. + int i;
  41183. + int shift_adv;
  41184. + int shift = 0;
  41185. + int nelem;
  41186. +
  41187. + switch (GET_MODE (op))
  41188. + {
  41189. + case V2HImode:
  41190. + mask = 0xffff;
  41191. + shift_adv = 16;
  41192. + nelem = 2;
  41193. + break;
  41194. + case V4QImode:
  41195. + mask = 0xff;
  41196. + shift_adv = 8;
  41197. + nelem = 4;
  41198. + break;
  41199. + default:
  41200. + gcc_unreachable ();
  41201. + }
  41202. +
  41203. + if (TARGET_BIG_ENDIAN)
  41204. + {
  41205. + for (i = 0; i < nelem; ++i)
  41206. + {
  41207. + HOST_WIDE_INT val = XINT (XVECEXP (op, 0, nelem - i - 1), 0);
  41208. + hwint |= (val & mask) << shift;
  41209. + shift = shift + shift_adv;
  41210. + }
  41211. + }
  41212. + else
  41213. + {
  41214. + for (i = 0; i < nelem; ++i)
  41215. + {
  41216. + HOST_WIDE_INT val = XINT (XVECEXP (op, 0, i), 0);
  41217. + hwint |= (val & mask) << shift;
  41218. + shift = shift + shift_adv;
  41219. + }
  41220. + }
  41221. +
  41222. + return hwint;
  41223. +}
  41224. +
  41225. +bool
  41226. +nds32_valid_CVp5_p (rtx op)
  41227. +{
  41228. + HOST_WIDE_INT ival = const_vector_to_hwint (op);
  41229. + return (ival < ((1 << 5) + 16)) && (ival >= (0 + 16));
  41230. +}
  41231. +
  41232. +bool
  41233. +nds32_valid_CVs5_p (rtx op)
  41234. +{
  41235. + HOST_WIDE_INT ival = const_vector_to_hwint (op);
  41236. + return (ival < (1 << 4)) && (ival >= -(1 << 4));
  41237. +}
  41238. +
  41239. +bool
  41240. +nds32_valid_CVs2_p (rtx op)
  41241. +{
  41242. + HOST_WIDE_INT ival = const_vector_to_hwint (op);
  41243. + return (ival < (1 << 19)) && (ival >= -(1 << 19));
  41244. +}
  41245. +
  41246. +bool
  41247. +nds32_valid_CVhi_p (rtx op)
  41248. +{
  41249. + HOST_WIDE_INT ival = const_vector_to_hwint (op);
  41250. + return (ival != 0) && ((ival & 0xfff) == 0);
  41251. +}
  41252. +
  41253. +/* ------------------------------------------------------------------------ */
  41254. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-protos.h gcc-4.9.4/gcc/config/nds32/nds32-protos.h
  41255. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-protos.h 2014-01-02 23:23:26.000000000 +0100
  41256. +++ gcc-4.9.4/gcc/config/nds32/nds32-protos.h 2016-08-08 20:37:45.582273034 +0200
  41257. @@ -1,5 +1,5 @@
  41258. /* Prototypes for exported functions of Andes NDS32 cpu for GNU compiler
  41259. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  41260. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  41261. Contributed by Andes Technology Corporation.
  41262. This file is part of GCC.
  41263. @@ -28,6 +28,9 @@
  41264. /* Register Usage. */
  41265. +/* -- Order of Allocation of Registers. */
  41266. +extern void nds32_adjust_reg_alloc_order (void);
  41267. +
  41268. /* -- How Values Fit in Registers. */
  41269. extern int nds32_hard_regno_nregs (int, enum machine_mode);
  41270. @@ -43,6 +46,7 @@
  41271. /* -- Basic Stack Layout. */
  41272. +extern rtx nds32_dynamic_chain_address (rtx);
  41273. extern rtx nds32_return_addr_rtx (int, rtx);
  41274. /* -- Eliminating Frame Pointer and Arg Pointer. */
  41275. @@ -58,71 +62,263 @@
  41276. /* -- Function Entry and Exit. */
  41277. extern void nds32_expand_prologue (void);
  41278. -extern void nds32_expand_epilogue (void);
  41279. +extern void nds32_expand_epilogue (bool);
  41280. extern void nds32_expand_prologue_v3push (void);
  41281. -extern void nds32_expand_epilogue_v3pop (void);
  41282. +extern void nds32_expand_epilogue_v3pop (bool);
  41283. +extern void nds32_emit_push_fpr_callee_saved (int);
  41284. +extern void nds32_emit_pop_fpr_callee_saved (int);
  41285. +extern void nds32_emit_v3pop_fpr_callee_saved (int);
  41286. /* ------------------------------------------------------------------------ */
  41287. -/* Auxiliary functions for auxiliary macros in nds32.h. */
  41288. +/* Auxiliary functions for manipulation DI mode. */
  41289. -extern bool nds32_ls_333_p (rtx, rtx, rtx, enum machine_mode);
  41290. +extern rtx nds32_di_high_part_subreg(rtx);
  41291. +extern rtx nds32_di_low_part_subreg(rtx);
  41292. /* Auxiliary functions for expanding rtl used in nds32-multiple.md. */
  41293. -extern rtx nds32_expand_load_multiple (int, int, rtx, rtx);
  41294. -extern rtx nds32_expand_store_multiple (int, int, rtx, rtx);
  41295. -extern int nds32_expand_movmemqi (rtx, rtx, rtx, rtx);
  41296. +extern rtx nds32_expand_load_multiple (int, int, rtx, rtx, bool, rtx *);
  41297. +extern rtx nds32_expand_store_multiple (int, int, rtx, rtx, bool, rtx *);
  41298. +extern bool nds32_expand_movmemsi (rtx, rtx, rtx, rtx);
  41299. +extern bool nds32_expand_setmem (rtx, rtx, rtx, rtx, rtx, rtx);
  41300. +extern bool nds32_expand_movstr (rtx, rtx, rtx);
  41301. +extern bool nds32_expand_strlen (rtx, rtx, rtx, rtx);
  41302. /* Auxiliary functions for multiple load/store predicate checking. */
  41303. -extern bool nds32_valid_multiple_load_store (rtx, bool);
  41304. +extern bool nds32_valid_multiple_load_store_p (rtx, bool, bool);
  41305. +
  41306. +/* Auxiliary functions for guard function checking in pipelines.md. */
  41307. +
  41308. +extern bool nds32_load_single_p (rtx);
  41309. +extern bool nds32_store_single_p (rtx);
  41310. +extern bool nds32_load_double_p (rtx);
  41311. +extern bool nds32_store_double_p (rtx);
  41312. +
  41313. +extern bool nds32_n7_load_to_ii_p (rtx, rtx);
  41314. +extern bool nds32_n7_last_load_to_ii_p (rtx, rtx);
  41315. +
  41316. +extern bool nds32_n8_load_to_ii_p (rtx, rtx);
  41317. +extern bool nds32_n8_load_bi_to_ii_p (rtx, rtx);
  41318. +extern bool nds32_n8_load_to_ex_p (rtx, rtx);
  41319. +extern bool nds32_n8_ex_to_ii_p (rtx, rtx);
  41320. +extern bool nds32_n8_last_load_to_ii_p (rtx, rtx);
  41321. +extern bool nds32_n8_last_load_two_to_ii_p (rtx, rtx);
  41322. +extern bool nds32_n8_last_load_to_ex_p (rtx, rtx);
  41323. +
  41324. +extern bool nds32_e8_load_to_ii_p (rtx, rtx);
  41325. +extern bool nds32_e8_load_to_ex_p (rtx, rtx);
  41326. +extern bool nds32_e8_ex_to_ii_p (rtx, rtx);
  41327. +extern bool nds32_e8_last_load_to_ii_p (rtx, rtx);
  41328. +extern bool nds32_e8_last_load_to_ex_p (rtx, rtx);
  41329. +
  41330. +extern bool nds32_n9_2r1w_mm_to_ex_p (rtx, rtx);
  41331. +extern bool nds32_n9_3r2w_mm_to_ex_p (rtx, rtx);
  41332. +extern bool nds32_n9_last_load_to_ex_p (rtx, rtx);
  41333. +
  41334. +extern bool nds32_n13_addr_in_p (rtx, rtx);
  41335. +extern bool nds32_n13_e2_to_e1_p (rtx, rtx);
  41336. +extern bool nds32_n13_load_to_e1_p (rtx, rtx);
  41337. +extern bool nds32_n13_load_to_e2_p (rtx, rtx);
  41338. +extern bool nds32_n13_last_load_to_e1_p (rtx, rtx);
  41339. +extern bool nds32_n13_last_load_to_e2_p (rtx, rtx);
  41340. +extern bool nds32_n13_last_two_load_to_e1_p (rtx, rtx);
  41341. /* Auxiliary functions for stack operation predicate checking. */
  41342. -extern bool nds32_valid_stack_push_pop (rtx, bool);
  41343. +extern bool nds32_valid_stack_push_pop_p (rtx, bool);
  41344. /* Auxiliary functions for bit operation detection. */
  41345. -extern int nds32_can_use_bclr_p (int);
  41346. -extern int nds32_can_use_bset_p (int);
  41347. -extern int nds32_can_use_btgl_p (int);
  41348. +extern bool nds32_can_use_bclr_p (HOST_WIDE_INT);
  41349. +extern bool nds32_can_use_bset_p (HOST_WIDE_INT);
  41350. +extern bool nds32_can_use_btgl_p (HOST_WIDE_INT);
  41351. -extern int nds32_can_use_bitci_p (int);
  41352. +extern bool nds32_can_use_bitci_p (HOST_WIDE_INT);
  41353. -/* Auxiliary function for 'Computing the Length of an Insn'. */
  41354. +extern bool nds32_const_double_range_ok_p (rtx, enum machine_mode,
  41355. + HOST_WIDE_INT, HOST_WIDE_INT);
  41356. -extern int nds32_adjust_insn_length (rtx, int);
  41357. +extern bool nds32_const_unspec_p (rtx x);
  41358. /* Auxiliary functions for FP_AS_GP detection. */
  41359. extern bool nds32_symbol_load_store_p (rtx);
  41360. -extern int nds32_fp_as_gp_check_available (void);
  41361. +extern bool nds32_naked_function_p (tree);
  41362. /* Auxiliary functions for jump table generation. */
  41363. extern const char *nds32_output_casesi_pc_relative (rtx *);
  41364. extern const char *nds32_output_casesi (rtx *);
  41365. +/* Auxiliary functions for conditional branch generation. */
  41366. +
  41367. +extern enum nds32_expand_result_type nds32_expand_cbranch (rtx *);
  41368. +extern enum nds32_expand_result_type nds32_expand_cstore (rtx *);
  41369. +extern void nds32_expand_float_cbranch (rtx *);
  41370. +extern void nds32_expand_float_cstore (rtx *);
  41371. +
  41372. +/* Auxiliary functions for conditional move generation. */
  41373. +
  41374. +extern enum nds32_expand_result_type nds32_expand_movcc (rtx *);
  41375. +extern void nds32_expand_float_movcc (rtx *);
  41376. +
  41377. +/* Auxiliary functions for expand unalign load instruction. */
  41378. +
  41379. +extern void nds32_expand_unaligned_load (rtx *, enum machine_mode);
  41380. +
  41381. +/* Auxiliary functions for expand unalign store instruction. */
  41382. +
  41383. +extern void nds32_expand_unaligned_store (rtx *, enum machine_mode);
  41384. +
  41385. +/* Auxiliary functions for expand PIC instruction. */
  41386. +
  41387. +extern void nds32_expand_pic_move (rtx *);
  41388. +
  41389. +/* Auxiliary functions for expand call address PIC instruction. */
  41390. +
  41391. +extern void nds32_expand_call_address (rtx *);
  41392. +
  41393. +/* Auxiliary functions for expand TLS instruction. */
  41394. +
  41395. +extern void nds32_expand_tls_move (rtx *);
  41396. +
  41397. +/* Auxiliary functions to legitimize TLS address. */
  41398. +
  41399. +extern rtx nds32_legitimize_tls_address (rtx);
  41400. +
  41401. +/* Auxiliary functions to identify thread-local symbol. */
  41402. +
  41403. +extern bool nds32_tls_referenced_p (rtx);
  41404. +
  41405. +/* Auxiliary functions to identify indirect-call symbol. */
  41406. +
  41407. +extern bool nds32_indirect_call_referenced_p (rtx);
  41408. +
  41409. +/* Auxiliary functions to identify SYMBOL_REF and LABEL_REF pattern. */
  41410. +
  41411. +extern bool symbolic_reference_mentioned_p (rtx);
  41412. +
  41413. +/* Auxiliary functions to identify conditional move comparison operand. */
  41414. +
  41415. +extern int nds32_cond_move_p (rtx);
  41416. +
  41417. +/* Auxiliary functions to identify address for peephole2 merge instruction. */
  41418. +
  41419. +extern bool nds32_memory_merge_peep_p (rtx, rtx);
  41420. +
  41421. /* Auxiliary functions to identify 16 bit addresing mode. */
  41422. extern enum nds32_16bit_address_type nds32_mem_format (rtx);
  41423. +/* Auxiliary functions to identify floating-point addresing mode. */
  41424. +
  41425. +extern bool nds32_float_mem_operand_p (rtx);
  41426. +
  41427. /* Auxiliary functions to output assembly code. */
  41428. extern const char *nds32_output_16bit_store (rtx *, int);
  41429. extern const char *nds32_output_16bit_load (rtx *, int);
  41430. extern const char *nds32_output_32bit_store (rtx *, int);
  41431. extern const char *nds32_output_32bit_load (rtx *, int);
  41432. -extern const char *nds32_output_32bit_load_s (rtx *, int);
  41433. +extern const char *nds32_output_32bit_load_se (rtx *, int);
  41434. +extern const char *nds32_output_float_load(rtx *);
  41435. +extern const char *nds32_output_float_store(rtx *);
  41436. +extern const char *nds32_output_smw_single_word (rtx *);
  41437. +extern const char *nds32_output_lmw_single_word (rtx *);
  41438. +extern const char *nds32_output_double (rtx *, bool);
  41439. +extern const char *nds32_output_cbranchsi4_equality_zero (rtx, rtx *);
  41440. +extern const char *nds32_output_cbranchsi4_equality_reg (rtx, rtx *);
  41441. +extern const char *nds32_output_cbranchsi4_equality_reg_or_const_int (rtx,
  41442. + rtx *);
  41443. +extern const char *nds32_output_cbranchsi4_greater_less_zero (rtx, rtx *);
  41444. +
  41445. +extern const char *nds32_output_unpkd8 (rtx, rtx, rtx, rtx, bool);
  41446. +
  41447. +extern const char *nds32_output_call (rtx, rtx *,
  41448. + const char *, const char *, bool);
  41449. +extern const char *nds32_output_tls_desc (rtx *);
  41450. +extern const char *nds32_output_tls_ie (rtx *);
  41451. /* Auxiliary functions to output stack push/pop instruction. */
  41452. -extern const char *nds32_output_stack_push (void);
  41453. -extern const char *nds32_output_stack_pop (void);
  41454. +extern const char *nds32_output_stack_push (rtx);
  41455. +extern const char *nds32_output_stack_pop (rtx);
  41456. +extern const char *nds32_output_return (void);
  41457. +
  41458. +
  41459. +/* Auxiliary functions to split/output sms pattern. */
  41460. +extern bool nds32_need_split_sms_p (rtx, rtx, rtx, rtx);
  41461. +extern const char *nds32_output_sms (rtx, rtx, rtx, rtx);
  41462. +extern void nds32_split_sms (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
  41463. +
  41464. +/* Auxiliary functions to split double word RTX pattern. */
  41465. +
  41466. +extern void nds32_spilt_doubleword (rtx *, bool);
  41467. +extern void nds32_split_ashiftdi3 (rtx, rtx, rtx);
  41468. +extern void nds32_split_ashiftrtdi3 (rtx, rtx, rtx);
  41469. +extern void nds32_split_lshiftrtdi3 (rtx, rtx, rtx);
  41470. +extern void nds32_split_rotatertdi3 (rtx, rtx, rtx);
  41471. +
  41472. +/* Auxiliary functions to split large constant RTX pattern. */
  41473. +
  41474. +extern void nds32_expand_constant (enum machine_mode,
  41475. + HOST_WIDE_INT, rtx, rtx);
  41476. +
  41477. +/* Auxiliary functions to check using return with null epilogue. */
  41478. +
  41479. +extern int nds32_can_use_return_insn (void);
  41480. +extern enum machine_mode nds32_case_vector_shorten_mode (int, int, rtx);
  41481. /* Auxiliary functions to decide output alignment or not. */
  41482. extern int nds32_target_alignment (rtx);
  41483. +extern unsigned int nds32_data_alignment (tree, unsigned int);
  41484. +extern unsigned int nds32_constant_alignment (tree, unsigned int);
  41485. +extern unsigned int nds32_local_alignment (tree, unsigned int);
  41486. +
  41487. +/* Auxiliary functions to expand builtin functions. */
  41488. +
  41489. +extern void nds32_init_builtins_impl (void);
  41490. +extern rtx nds32_expand_builtin_impl (tree, rtx, rtx,
  41491. + enum machine_mode, int);
  41492. +extern tree nds32_builtin_decl_impl (unsigned, bool);
  41493. +
  41494. +/* Auxiliary functions for ISR implementation. */
  41495. +
  41496. +extern void nds32_check_isr_attrs_conflict (tree, tree);
  41497. +extern void nds32_construct_isr_vectors_information (tree, const char *);
  41498. +extern void nds32_asm_file_start_for_isr (void);
  41499. +extern void nds32_asm_file_end_for_isr (void);
  41500. +extern bool nds32_isr_function_p (tree);
  41501. +extern bool nds32_isr_function_critical_p (tree);
  41502. +
  41503. +/* Auxiliary functions for cost calculation. */
  41504. +
  41505. +extern void nds32_init_rtx_costs (void);
  41506. +extern bool nds32_rtx_costs_impl (rtx, int, int, int, int *, bool);
  41507. +extern int nds32_address_cost_impl (rtx, enum machine_mode, addr_space_t, bool);
  41508. +extern struct register_pass_info insert_pass_fp_as_gp;
  41509. +
  41510. +extern int nds32_adjust_insn_length (rtx, int);
  41511. +
  41512. +/* Auxiliary functions for pre-define marco. */
  41513. +extern void nds32_cpu_cpp_builtins(struct cpp_reader *);
  41514. +
  41515. +/* Auxiliary functions for const_vector's constraints. */
  41516. +
  41517. +extern HOST_WIDE_INT const_vector_to_hwint (rtx);
  41518. +extern bool nds32_valid_CVp5_p (rtx);
  41519. +extern bool nds32_valid_CVs5_p (rtx);
  41520. +extern bool nds32_valid_CVs2_p (rtx);
  41521. +extern bool nds32_valid_CVhi_p (rtx);
  41522. +
  41523. +/* Auxiliary functions for lwm/smw. */
  41524. +
  41525. +extern bool nds32_valid_smw_lwm_base_p (rtx);
  41526. +
  41527. +/* Auxiliary functions for register rename pass. */
  41528. +extern reg_class_t nds32_preferred_rename_class_impl (reg_class_t);
  41529. /* ------------------------------------------------------------------------ */
  41530. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-regrename.c gcc-4.9.4/gcc/config/nds32/nds32-regrename.c
  41531. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-regrename.c 1970-01-01 01:00:00.000000000 +0100
  41532. +++ gcc-4.9.4/gcc/config/nds32/nds32-regrename.c 2016-08-08 20:37:45.582273034 +0200
  41533. @@ -0,0 +1,377 @@
  41534. +/* Register rename pass of Andes NDS32 cpu for GNU compiler
  41535. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  41536. + Contributed by Andes Technology Corporation.
  41537. +
  41538. + This file is part of GCC.
  41539. +
  41540. + GCC is free software; you can redistribute it and/or modify it
  41541. + under the terms of the GNU General Public License as published
  41542. + by the Free Software Foundation; either version 3, or (at your
  41543. + option) any later version.
  41544. +
  41545. + GCC is distributed in the hope that it will be useful, but WITHOUT
  41546. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  41547. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  41548. + License for more details.
  41549. +
  41550. + You should have received a copy of the GNU General Public License
  41551. + along with GCC; see the file COPYING3. If not see
  41552. + <http://www.gnu.org/licenses/>. */
  41553. +
  41554. +
  41555. +#include "config.h"
  41556. +#include "system.h"
  41557. +#include "coretypes.h"
  41558. +#include "tm.h"
  41559. +#include "tree.h"
  41560. +#include "rtl.h"
  41561. +#include "regs.h"
  41562. +#include "hard-reg-set.h"
  41563. +#include "insn-config.h" /* Required by recog.h. */
  41564. +#include "conditions.h"
  41565. +#include "output.h"
  41566. +#include "insn-attr.h" /* For DFA state_t. */
  41567. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  41568. +#include "reload.h" /* For push_reload (). */
  41569. +#include "flags.h"
  41570. +#include "function.h"
  41571. +#include "expr.h"
  41572. +#include "recog.h"
  41573. +#include "diagnostic-core.h"
  41574. +#include "df.h"
  41575. +#include "tm_p.h"
  41576. +#include "tm-constrs.h"
  41577. +#include "target.h"
  41578. +#include "target-def.h"
  41579. +#include "langhooks.h" /* For add_builtin_function (). */
  41580. +#include "ggc.h"
  41581. +#include "tree-pass.h"
  41582. +#include "target-globals.h"
  41583. +#include "regrename.h"
  41584. +
  41585. +static reg_class_t current_preferred_rename_class = NO_REGS;
  41586. +
  41587. +reg_class_t
  41588. +nds32_preferred_rename_class_impl (reg_class_t rclass)
  41589. +{
  41590. + if (rclass == GENERAL_REGS)
  41591. + return current_preferred_rename_class;
  41592. + else
  41593. + return NO_REGS;
  41594. +}
  41595. +
  41596. +static void
  41597. +print_hard_reg_set (FILE *file, HARD_REG_SET set)
  41598. +{
  41599. + int i;
  41600. +
  41601. + fprintf (file, "{ ");
  41602. + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
  41603. + {
  41604. + if (TEST_HARD_REG_BIT (set, i))
  41605. + fprintf (file, "%d ", i);
  41606. + }
  41607. + fprintf (file, "}\n");
  41608. +}
  41609. +
  41610. +void
  41611. +dump_hard_reg_set (FILE *file, HARD_REG_SET set)
  41612. +{
  41613. + print_hard_reg_set (file, set);
  41614. +}
  41615. +
  41616. +static bool
  41617. +in_reg_class_p (unsigned regno, enum reg_class clazz)
  41618. +{
  41619. + return TEST_HARD_REG_BIT (reg_class_contents[clazz], regno);
  41620. +}
  41621. +
  41622. +static unsigned
  41623. +try_find_best_rename_reg (du_head_p op_chain, reg_class_t preferred_class)
  41624. +{
  41625. + HARD_REG_SET unavailable;
  41626. + unsigned new_reg;
  41627. + current_preferred_rename_class = preferred_class;
  41628. +
  41629. + COMPL_HARD_REG_SET (unavailable, reg_class_contents[preferred_class]);
  41630. + CLEAR_HARD_REG_BIT (unavailable, op_chain->regno);
  41631. +
  41632. + new_reg = find_best_rename_reg (op_chain, GENERAL_REGS,
  41633. + &unavailable, op_chain->regno);
  41634. +
  41635. + current_preferred_rename_class = NO_REGS;
  41636. + return new_reg;
  41637. +}
  41638. +
  41639. +static bool
  41640. +try_rename_operand_to (rtx insn, unsigned op_pos,
  41641. + reg_class_t preferred_rename_class)
  41642. +{
  41643. + insn_rr_info *info;
  41644. + du_head_p op_chain;
  41645. + unsigned newreg;
  41646. + unsigned oldreg;
  41647. +
  41648. + info = &insn_rr[INSN_UID (insn)];
  41649. +
  41650. + if (info->op_info == NULL)
  41651. + return false;
  41652. +
  41653. + if (info->op_info[op_pos].n_chains == 0)
  41654. + return false;
  41655. +
  41656. + op_chain = regrename_chain_from_id (info->op_info[op_pos].heads[0]->id);
  41657. +
  41658. + if (op_chain->cannot_rename)
  41659. + return false;
  41660. +
  41661. + /* Already use preferred class, so do nothing. */
  41662. + if (TEST_HARD_REG_BIT (reg_class_contents[preferred_rename_class],
  41663. + op_chain->regno))
  41664. + return false;
  41665. +
  41666. + if (dump_file)
  41667. + {
  41668. + fprintf (dump_file, "Try to rename operand %d to %s:\n",
  41669. + op_pos, reg_class_names[preferred_rename_class]);
  41670. + print_rtl_single (dump_file, insn);
  41671. + }
  41672. +
  41673. + oldreg = op_chain->regno;
  41674. + newreg = try_find_best_rename_reg (op_chain, preferred_rename_class);
  41675. +
  41676. + if (newreg == oldreg)
  41677. + return false;
  41678. +
  41679. + regrename_do_replace (op_chain, newreg);
  41680. +
  41681. + if (dump_file)
  41682. + {
  41683. + fprintf (dump_file, "Rename operand %d to %s is Done:\n",
  41684. + op_pos, reg_class_names[preferred_rename_class]);
  41685. + print_rtl_single (dump_file, insn);
  41686. + }
  41687. + return true;
  41688. +}
  41689. +
  41690. +static bool
  41691. +rename_slt_profitlable (rtx insn)
  41692. +{
  41693. + rtx pattern;
  41694. + pattern = PATTERN (insn);
  41695. + rtx src = SET_SRC (pattern);
  41696. + rtx op0 = XEXP (src, 0);
  41697. + rtx op1 = XEXP (src, 0);
  41698. +
  41699. + insn_rr_info *info;
  41700. + du_head_p op_chain;
  41701. + int op_pos = 0;
  41702. +
  41703. + info = &insn_rr[INSN_UID (insn)];
  41704. +
  41705. + if (info->op_info == NULL)
  41706. + return false;
  41707. +
  41708. + if (info->op_info[op_pos].n_chains == 0)
  41709. + return false;
  41710. +
  41711. + op_chain = regrename_chain_from_id (info->op_info[op_pos].heads[0]->id);
  41712. +
  41713. + if (in_reg_class_p (op_chain->regno, R15_TA_REG))
  41714. + return false;
  41715. +
  41716. + /* slt[s]45 need second operand in MIDDLE_REGS class. */
  41717. + if (!REG_P (op0) || !in_reg_class_p (REGNO (op0), MIDDLE_REGS))
  41718. + return false;
  41719. +
  41720. + /* slt[s]i45 only allow 5 bit unsigned integer. */
  41721. + if (REG_P (op1)
  41722. + || (CONST_INT_P (op1) && satisfies_constraint_Iu05 (op1)))
  41723. + return true;
  41724. +
  41725. + return false;
  41726. +}
  41727. +
  41728. +static bool
  41729. +rename_cbranch_eq0_low_reg_profitlable (rtx insn)
  41730. +{
  41731. + insn_rr_info *info;
  41732. + du_head_p op_chain;
  41733. + int op_pos = 1;
  41734. +
  41735. + info = &insn_rr[INSN_UID (insn)];
  41736. +
  41737. + if (info->op_info == NULL)
  41738. + return false;
  41739. +
  41740. + if (info->op_info[op_pos].n_chains == 0)
  41741. + return false;
  41742. +
  41743. + op_chain = regrename_chain_from_id (info->op_info[op_pos].heads[0]->id);
  41744. +
  41745. + if (in_reg_class_p (op_chain->regno, LOW_REGS))
  41746. + return false;
  41747. +
  41748. + return true;
  41749. +}
  41750. +
  41751. +
  41752. +static bool
  41753. +rename_cbranch_eq0_r15_profitlable (rtx insn)
  41754. +{
  41755. + rtx pattern;
  41756. + pattern = PATTERN (insn);
  41757. + rtx if_then_else = SET_SRC (pattern);
  41758. + rtx cond = XEXP (if_then_else, 0);
  41759. + rtx op0 = XEXP (cond, 0);
  41760. +
  41761. + insn_rr_info *info;
  41762. + du_head_p op_chain;
  41763. + int op_pos = 1;
  41764. +
  41765. + info = &insn_rr[INSN_UID (insn)];
  41766. +
  41767. + if (info->op_info == NULL)
  41768. + return false;
  41769. +
  41770. + if (info->op_info[op_pos].n_chains == 0)
  41771. + return false;
  41772. +
  41773. + op_chain = regrename_chain_from_id (info->op_info[op_pos].heads[0]->id);
  41774. +
  41775. + if (in_reg_class_p (op_chain->regno, R15_TA_REG))
  41776. + return false;
  41777. +
  41778. + /* LOW_REGS or R15_TA_REG both are 2-byte instruction. */
  41779. + if (REG_P (op0) && in_reg_class_p (REGNO (op0), LOW_REGS))
  41780. + return false;
  41781. +
  41782. + return true;
  41783. +}
  41784. +
  41785. +static bool
  41786. +rename_cbranch_eq_reg_profitlable (rtx insn)
  41787. +{
  41788. + rtx pattern;
  41789. + pattern = PATTERN (insn);
  41790. + rtx if_then_else = SET_SRC (pattern);
  41791. + rtx cond = XEXP (if_then_else, 0);
  41792. + rtx op1 = XEXP (cond, 1);
  41793. +
  41794. + insn_rr_info *info;
  41795. + du_head_p op_chain;
  41796. + int op_pos = 1;
  41797. +
  41798. + info = &insn_rr[INSN_UID (insn)];
  41799. +
  41800. + if (info->op_info == NULL)
  41801. + return false;
  41802. +
  41803. + if (info->op_info[op_pos].n_chains == 0)
  41804. + return false;
  41805. +
  41806. + op_chain = regrename_chain_from_id (info->op_info[op_pos].heads[0]->id);
  41807. +
  41808. + if (in_reg_class_p (op_chain->regno, R5_REG))
  41809. + return false;
  41810. +
  41811. + if (REG_P (op1) && in_reg_class_p (REGNO (op1), LOW_REGS))
  41812. + return true;
  41813. + else
  41814. + return false;
  41815. +}
  41816. +
  41817. +static void
  41818. +do_regrename ()
  41819. +{
  41820. + basic_block bb;
  41821. + rtx insn;
  41822. +
  41823. + FOR_EACH_BB_FN (bb, cfun)
  41824. + {
  41825. + FOR_BB_INSNS (bb, insn)
  41826. + {
  41827. + if (!INSN_P (insn))
  41828. + continue;
  41829. +
  41830. + switch (recog_memoized (insn))
  41831. + {
  41832. + case CODE_FOR_slts_compare_impl:
  41833. + case CODE_FOR_slt_compare_impl:
  41834. + /* Try to rename operand 0 to $r15 if profitable. */
  41835. + if (rename_slt_profitlable (insn))
  41836. + try_rename_operand_to (insn, 0, R15_TA_REG);
  41837. + break;
  41838. + case CODE_FOR_slt_eq0:
  41839. + /* Try to rename operand 0 to $r15. */
  41840. + if (rename_slt_profitlable (insn))
  41841. + try_rename_operand_to (insn, 0, R15_TA_REG);
  41842. + break;
  41843. + case CODE_FOR_cbranchsi4_equality_zero:
  41844. + /* Try to rename operand 1 to $r15. */
  41845. + if (rename_cbranch_eq0_r15_profitlable (insn))
  41846. + if (!try_rename_operand_to (insn, 1, R15_TA_REG))
  41847. + if (rename_cbranch_eq0_low_reg_profitlable (insn))
  41848. + try_rename_operand_to (insn, 1, LOW_REGS);
  41849. + break;
  41850. + case CODE_FOR_cbranchsi4_equality_reg:
  41851. + case CODE_FOR_cbranchsi4_equality_reg_or_const_int:
  41852. + /* Try to rename operand 1 to $r5. */
  41853. + if (rename_cbranch_eq_reg_profitlable (insn))
  41854. + try_rename_operand_to (insn, 1, R5_REG);
  41855. + break;
  41856. + }
  41857. + }
  41858. + }
  41859. +}
  41860. +
  41861. +static unsigned int
  41862. +nds32_regrename (void)
  41863. +{
  41864. + df_set_flags (DF_LR_RUN_DCE);
  41865. + df_note_add_problem ();
  41866. + df_analyze ();
  41867. + df_set_flags (DF_DEFER_INSN_RESCAN);
  41868. +
  41869. + regrename_init (true);
  41870. +
  41871. + regrename_analyze (NULL);
  41872. +
  41873. + do_regrename ();
  41874. +
  41875. + regrename_finish ();
  41876. + return 1;
  41877. +}
  41878. +
  41879. +const pass_data pass_data_nds32_regrename =
  41880. +{
  41881. + RTL_PASS, /* type */
  41882. + "nds32-regrename", /* name */
  41883. + OPTGROUP_NONE, /* optinfo_flags */
  41884. + true, /* has_gate */
  41885. + true, /* has_execute */
  41886. + TV_MACH_DEP, /* tv_id */
  41887. + 0, /* properties_required */
  41888. + 0, /* properties_provided */
  41889. + 0, /* properties_destroyed */
  41890. + 0, /* todo_flags_start */
  41891. + ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
  41892. +};
  41893. +
  41894. +class pass_nds32_regrename_opt : public rtl_opt_pass
  41895. +{
  41896. +public:
  41897. + pass_nds32_regrename_opt (gcc::context *ctxt)
  41898. + : rtl_opt_pass (pass_data_nds32_regrename, ctxt)
  41899. + {}
  41900. +
  41901. + /* opt_pass methods: */
  41902. + bool gate () { return TARGET_16_BIT && TARGET_REGRENAME_OPT; }
  41903. + unsigned int execute () { return nds32_regrename (); }
  41904. +};
  41905. +
  41906. +rtl_opt_pass *
  41907. +make_pass_nds32_regrename_opt (gcc::context *ctxt)
  41908. +{
  41909. + return new pass_nds32_regrename_opt (ctxt);
  41910. +}
  41911. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-relax-opt.c gcc-4.9.4/gcc/config/nds32/nds32-relax-opt.c
  41912. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-relax-opt.c 1970-01-01 01:00:00.000000000 +0100
  41913. +++ gcc-4.9.4/gcc/config/nds32/nds32-relax-opt.c 2016-08-08 20:37:45.582273034 +0200
  41914. @@ -0,0 +1,555 @@
  41915. +/* relax-opt pass of Andes NDS32 cpu for GNU compiler
  41916. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  41917. + Contributed by Andes Technology Corporation.
  41918. +
  41919. + This file is part of GCC.
  41920. +
  41921. + GCC is free software; you can redistribute it and/or modify it
  41922. + under the terms of the GNU General Public License as published
  41923. + by the Free Software Foundation; either version 3, or (at your
  41924. + option) any later version.
  41925. +
  41926. + GCC is distributed in the hope that it will be useful, but WITHOUT
  41927. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  41928. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  41929. + License for more details.
  41930. +
  41931. + You should have received a copy of the GNU General Public License
  41932. + along with GCC; see the file COPYING3. If not see
  41933. + <http://www.gnu.org/licenses/>. */
  41934. +
  41935. +#include "config.h"
  41936. +#include "system.h"
  41937. +#include "coretypes.h"
  41938. +#include "tm.h"
  41939. +#include "tree.h"
  41940. +#include "rtl.h"
  41941. +#include "regs.h"
  41942. +#include "hard-reg-set.h"
  41943. +#include "insn-config.h" /* Required by recog.h. */
  41944. +#include "conditions.h"
  41945. +#include "output.h"
  41946. +#include "insn-attr.h" /* For DFA state_t. */
  41947. +#include "insn-codes.h" /* For CODE_FOR_xxx. */
  41948. +#include "reload.h" /* For push_reload (). */
  41949. +#include "flags.h"
  41950. +#include "function.h"
  41951. +#include "expr.h"
  41952. +#include "recog.h"
  41953. +#include "diagnostic-core.h"
  41954. +#include "df.h"
  41955. +#include "tm_p.h"
  41956. +#include "tm-constrs.h"
  41957. +#include "target.h"
  41958. +#include "target-def.h"
  41959. +#include "langhooks.h" /* For add_builtin_function (). */
  41960. +#include "ggc.h"
  41961. +#include "tree-pass.h"
  41962. +#include "target-globals.h"
  41963. +#include "ira-int.h"
  41964. +
  41965. +/* This is used to create unique relax hint id value.
  41966. + The initial value is 0. */
  41967. +static int relax_group_id = 0;
  41968. +
  41969. +/* Group the following pattern as relax candidates:
  41970. +
  41971. + 1. sethi $ra, hi20(sym)
  41972. + ori $ra, $ra, lo12(sym)
  41973. + ==>
  41974. + addi.gp $ra, sym
  41975. +
  41976. + 2. sethi $ra, hi20(sym)
  41977. + lwi $rb, [$ra + lo12(sym)]
  41978. + ==>
  41979. + lwi.gp $rb, [(sym)]
  41980. +
  41981. + 3. sethi $ra, hi20(sym)
  41982. + ori $ra, $ra, lo12(sym)
  41983. + lwi $rb, [$ra]
  41984. + swi $rc, [$ra]
  41985. + ==>
  41986. + lwi37 $rb, [(sym)]
  41987. + swi37 $rc, [(sym)] */
  41988. +
  41989. +/* Return true if is load/store with REG addressing mode
  41990. + and memory mode is SImode. */
  41991. +static bool
  41992. +nds32_reg_base_load_store_p (rtx insn)
  41993. +{
  41994. + rtx mem_src = NULL_RTX;
  41995. +
  41996. + switch (get_attr_type (insn))
  41997. + {
  41998. + case TYPE_LOAD:
  41999. + mem_src = SET_SRC (PATTERN (insn));
  42000. + break;
  42001. + case TYPE_STORE:
  42002. + mem_src = SET_DEST (PATTERN (insn));
  42003. + break;
  42004. + default:
  42005. + break;
  42006. + }
  42007. +
  42008. + /* Find load/store insn with addressing mode is REG. */
  42009. + if (mem_src != NULL_RTX)
  42010. + {
  42011. + if ((GET_CODE (mem_src) == ZERO_EXTEND)
  42012. + || (GET_CODE (mem_src) == SIGN_EXTEND))
  42013. + mem_src = XEXP (mem_src, 0);
  42014. +
  42015. + if (GET_CODE (XEXP (mem_src, 0)) == REG)
  42016. + return true;
  42017. + }
  42018. +
  42019. + return false;
  42020. +}
  42021. +
  42022. +/* Return true if insn is a sp/fp base or sp/fp plus load-store instruction. */
  42023. +
  42024. +static bool
  42025. +nds32_sp_base_or_plus_load_store_p (rtx insn)
  42026. +{
  42027. + rtx mem_src = NULL_RTX;
  42028. +
  42029. + switch (get_attr_type (insn))
  42030. + {
  42031. + case TYPE_LOAD:
  42032. + mem_src = SET_SRC (PATTERN (insn));
  42033. + break;
  42034. + case TYPE_STORE:
  42035. + mem_src = SET_DEST (PATTERN (insn));
  42036. + break;
  42037. + default:
  42038. + break;
  42039. + }
  42040. + /* Find load/store insn with addressing mode is REG. */
  42041. + if (mem_src != NULL_RTX)
  42042. + {
  42043. + if ((GET_CODE (mem_src) == ZERO_EXTEND)
  42044. + || (GET_CODE (mem_src) == SIGN_EXTEND))
  42045. + mem_src = XEXP (mem_src, 0);
  42046. +
  42047. + if ((GET_CODE (XEXP (mem_src, 0)) == PLUS))
  42048. + mem_src = XEXP (mem_src, 0);
  42049. +
  42050. + if (REG_P (XEXP (mem_src, 0))
  42051. + && ((frame_pointer_needed
  42052. + && REGNO (XEXP (mem_src, 0)) == FP_REGNUM)
  42053. + || REGNO (XEXP (mem_src, 0)) == SP_REGNUM))
  42054. + return true;
  42055. + }
  42056. +
  42057. + return false;
  42058. +}
  42059. +
  42060. +/* Return true if is load with REG addressing mode
  42061. + and memory mode is SImode. */
  42062. +static bool
  42063. +nds32_reg_base_load_p (rtx insn)
  42064. +{
  42065. + rtx mem_src = NULL_RTX;
  42066. +
  42067. + if (get_attr_type (insn) == TYPE_LOAD)
  42068. + mem_src = SET_SRC (PATTERN (insn));
  42069. +
  42070. + /* Find load/store insn with addressing mode is REG. */
  42071. + if (mem_src != NULL_RTX)
  42072. + {
  42073. + if (GET_CODE (XEXP (mem_src, 0)) == REG)
  42074. + return true;
  42075. + }
  42076. +
  42077. + return false;
  42078. +}
  42079. +
  42080. +/* Return true if is load with [REG + REG/CONST_INT] addressing mode. */
  42081. +static bool
  42082. +nds32_plus_reg_load_store_p (rtx insn)
  42083. +{
  42084. + rtx mem_src = NULL_RTX;
  42085. +
  42086. + switch (get_attr_type (insn))
  42087. + {
  42088. + case TYPE_LOAD:
  42089. + mem_src = SET_SRC (PATTERN (insn));
  42090. + break;
  42091. + case TYPE_STORE:
  42092. + mem_src = SET_DEST (PATTERN (insn));
  42093. + break;
  42094. + default:
  42095. + break;
  42096. + }
  42097. +
  42098. + /* Find load/store insn with addressing mode is [REG + REG/CONST]. */
  42099. + if (mem_src != NULL_RTX)
  42100. + {
  42101. + if ((GET_CODE (mem_src) == ZERO_EXTEND)
  42102. + || (GET_CODE (mem_src) == SIGN_EXTEND))
  42103. + mem_src = XEXP (mem_src, 0);
  42104. +
  42105. + if ((GET_CODE (XEXP (mem_src, 0)) == PLUS))
  42106. + mem_src = XEXP (mem_src, 0);
  42107. + else
  42108. + return false;
  42109. +
  42110. + if (GET_CODE (XEXP (mem_src, 0)) == REG)
  42111. + return true;
  42112. +
  42113. + }
  42114. +
  42115. + return false;
  42116. +}
  42117. +
  42118. +/* Group the following pattern as relax candidates:
  42119. +
  42120. + GOT:
  42121. + sethi $ra, hi20(sym)
  42122. + ori $ra, $ra, lo12(sym)
  42123. + lw $rb, [$ra + $gp]
  42124. +
  42125. + GOTOFF, TLSLE, TLSIE:
  42126. + sethi $ra, hi20(sym)
  42127. + ori $ra, $ra, lo12(sym)
  42128. + LS $rb, [$ra + $gp]
  42129. +
  42130. + TLSIE (not PIC) !UNSPEC:
  42131. + This is as the same as normal load-store, and it's done as normal pattern.
  42132. + sethi $ra, hi20(sym)
  42133. + lwi $ra, [$ra + lo12(sym)]
  42134. +
  42135. + GOTOFF, TLSLE:
  42136. + sethi $ra, hi20(sym)
  42137. + ori $ra, $ra, lo12(sym)
  42138. + add $rb, $ra, $gp($tp)
  42139. +
  42140. + PLT:
  42141. + sethi $ra, hi20(sym)
  42142. + ori $ra, $ra, lo12(sym)
  42143. + add $ra, $ra, $gp
  42144. + jral $lp, $ra
  42145. +
  42146. + TLSGD and TLSLD !UNSPEC:
  42147. + sethi $ra, hi20(sym)
  42148. + ori $ra, $ra, lo12(sym)
  42149. + add $r0, $ra, $gp
  42150. + lw $rb, [$r0]
  42151. + jral $rb
  42152. + or:
  42153. + sethi $ra, hi20(sym)
  42154. + ori $ra, $ra, lo12(sym)
  42155. + lw $rb, [$ra + $gp]
  42156. + add $r0, $ra, $gp
  42157. + jral $rb
  42158. +
  42159. + Initial GOT table:
  42160. + sethi $gp,hi20(sym)
  42161. + ori $gp, $gp, lo12(sym)
  42162. + add5.pc $gp */
  42163. +
  42164. +static auto_vec<rtx, 32> nds32_group_infos;
  42165. +/* Group the PIC and TLS relax candidate instructions for linker. */
  42166. +static bool
  42167. +nds32_pic_tls_group (rtx def_insn,
  42168. + enum nds32_relax_insn_type relax_type,
  42169. + int sym_type)
  42170. +{
  42171. + df_ref *def_record;
  42172. + df_link *link;
  42173. + rtx use_insn = NULL_RTX;
  42174. + def_record = DF_INSN_DEFS (def_insn);
  42175. + for (link = DF_REF_CHAIN (*def_record); link; link = link->next)
  42176. + {
  42177. + if (!DF_REF_INSN_INFO (link->ref))
  42178. + continue;
  42179. +
  42180. + use_insn = DF_REF_INSN (link->ref);
  42181. +
  42182. + /* Skip if define insn and use insn not in the same basic block. */
  42183. + if (!dominated_by_p (CDI_DOMINATORS,
  42184. + BLOCK_FOR_INSN (use_insn),
  42185. + BLOCK_FOR_INSN (def_insn)))
  42186. + return FALSE;
  42187. +
  42188. + /* Skip if use_insn not active insn. */
  42189. + if (!active_insn_p (use_insn))
  42190. + return FALSE;
  42191. +
  42192. + switch (relax_type)
  42193. + {
  42194. + case RELAX_ORI:
  42195. +
  42196. + /* TLSIE and GOT don't generate ADD instruction,
  42197. + so don't join relax hint above ADD instruction. */
  42198. +
  42199. + /* There are two possible relax patterns of TLSGD (TLSLD),
  42200. + so we have to checkout both possibility.
  42201. + Define: 'ori $ra, $ra, lo12(sym)'
  42202. + Use: 'add $rb, $ra, $gp',
  42203. + or 'lw $rb, [$ra + $gp]'. */
  42204. + if ((sym_type == UNSPEC_TLSGD || sym_type == UNSPEC_TLSLD)
  42205. + && ((recog_memoized (use_insn) == CODE_FOR_addsi3
  42206. + && nds32_pic_tls_group (use_insn, RELAX_TLS_ADD_LW,
  42207. + sym_type))
  42208. + || (nds32_plus_reg_load_store_p (use_insn)
  42209. + && !nds32_sp_base_or_plus_load_store_p (use_insn)
  42210. + && nds32_pic_tls_group (use_insn, RELAX_TLS_LW_JRAL,
  42211. + sym_type))))
  42212. + nds32_group_infos.safe_push (use_insn);
  42213. + /* Define: 'ori $ra, $ra, lo12(sym)'
  42214. + Use: 'add $rb, $ra, $gp'. */
  42215. + else if (recog_memoized (use_insn) == CODE_FOR_addsi3
  42216. + && ((sym_type == UNSPEC_PLT
  42217. + && nds32_pic_tls_group (use_insn,
  42218. + RELAX_PLT_ADD,
  42219. + sym_type))
  42220. + || sym_type == UNSPEC_TLSLE
  42221. + || sym_type == UNSPEC_GOTOFF))
  42222. + nds32_group_infos.safe_push (use_insn);
  42223. + else if (nds32_plus_reg_load_store_p (use_insn)
  42224. + && !nds32_sp_base_or_plus_load_store_p (use_insn))
  42225. + nds32_group_infos.safe_push (use_insn);
  42226. + else
  42227. + return FALSE;
  42228. + break;
  42229. +
  42230. + case RELAX_PLT_ADD:
  42231. + /* Define: 'add $ra, $ra, $gp'
  42232. + Use: 'jral $ra'. */
  42233. + if (get_attr_type (use_insn) == TYPE_BRANCH)
  42234. + nds32_group_infos.safe_push (use_insn);
  42235. + else if (nds32_sp_base_or_plus_load_store_p (use_insn))
  42236. + /* Skip SP base load-store instruction, because it may be a reload
  42237. + instruction. */
  42238. + continue;
  42239. + else
  42240. + return FALSE;
  42241. + break;
  42242. +
  42243. + case RELAX_TLS_ADD_LW:
  42244. + /* This def-use chain's register number is argument, we want
  42245. + to insert relax hint by call register. */
  42246. + if (get_attr_type (use_insn) == TYPE_BRANCH)
  42247. + continue;
  42248. + /* Define: 'add $r0, $ra, $gp'
  42249. + Use: 'lw $rb, [$r0]'. */
  42250. + else if (nds32_reg_base_load_p (use_insn)
  42251. + && nds32_pic_tls_group (use_insn, RELAX_TLS_LW_JRAL,
  42252. + sym_type))
  42253. + nds32_group_infos.safe_push (use_insn);
  42254. + else
  42255. + return FALSE;
  42256. + break;
  42257. +
  42258. + case RELAX_TLS_LW_JRAL:
  42259. + /* Define: 'lw $rb, [$ra + $gp]',
  42260. + or: 'lw $rb, [$r0]'
  42261. + Use: 'jral $rb'. */
  42262. + if (get_attr_type (use_insn) == TYPE_BRANCH)
  42263. + nds32_group_infos.safe_push (use_insn);
  42264. + else
  42265. + return FALSE;
  42266. + break;
  42267. +
  42268. + default:
  42269. + return FALSE;
  42270. + }
  42271. + }
  42272. + return TRUE;
  42273. +}
  42274. +
  42275. +static int
  42276. +nds32_pic_tls_symbol_type (rtx x)
  42277. +{
  42278. + x = XEXP (SET_SRC (PATTERN (x)), 1);
  42279. +
  42280. + if (GET_CODE (x) == CONST)
  42281. + {
  42282. + x = XEXP (x, 0);
  42283. +
  42284. + if (GET_CODE (x) == PLUS)
  42285. + x = XEXP (x, 0);
  42286. +
  42287. + return XINT (x, 1);
  42288. + }
  42289. +
  42290. + return XINT (x, 1);
  42291. +}
  42292. +
  42293. +/* Group the relax candidates with group id. */
  42294. +static void
  42295. +nds32_group_insns (rtx sethi)
  42296. +{
  42297. + df_ref *def_record;
  42298. + df_link *link;
  42299. + rtx use_insn = NULL_RTX, group_id;
  42300. + bool valid;
  42301. +
  42302. + def_record = DF_INSN_DEFS (sethi);
  42303. +
  42304. + for (link = DF_REF_CHAIN (*def_record); link; link = link->next)
  42305. + {
  42306. + if (!DF_REF_INSN_INFO (link->ref))
  42307. + continue;
  42308. +
  42309. + use_insn = DF_REF_INSN (link->ref);
  42310. +
  42311. + /* Skip if define insn and use insn not in the same basic block. */
  42312. + if (!dominated_by_p (CDI_DOMINATORS,
  42313. + BLOCK_FOR_INSN (use_insn),
  42314. + BLOCK_FOR_INSN (sethi)))
  42315. + return;
  42316. +
  42317. + /* Skip if use_insn not active insn. */
  42318. + if (!active_insn_p (use_insn))
  42319. + return;
  42320. +
  42321. + /* Initial use_insn_type. */
  42322. + if (!(recog_memoized (use_insn) == CODE_FOR_lo_sum
  42323. + || nds32_symbol_load_store_p (use_insn)
  42324. + || (nds32_reg_base_load_store_p (use_insn)
  42325. + &&!nds32_sp_base_or_plus_load_store_p (use_insn))))
  42326. + return;
  42327. + }
  42328. +
  42329. + group_id = GEN_INT (relax_group_id);
  42330. + /* Insert .relax_* directive for sethi. */
  42331. + emit_insn_before (gen_relax_group (group_id), sethi);
  42332. +
  42333. + /* Scan the use insns and insert the directive. */
  42334. + for (link = DF_REF_CHAIN (*def_record); link; link = link->next)
  42335. + {
  42336. + if (!DF_REF_INSN_INFO (link->ref))
  42337. + continue;
  42338. +
  42339. + use_insn = DF_REF_INSN (link->ref);
  42340. +
  42341. + /* Insert .relax_* directive. */
  42342. + if (active_insn_p (use_insn))
  42343. + emit_insn_before (gen_relax_group (group_id), use_insn);
  42344. +
  42345. + /* Find ori ra, ra, unspec(symbol) instruction. */
  42346. + if (use_insn != NULL_RTX
  42347. + && recog_memoized (use_insn) == CODE_FOR_lo_sum
  42348. + && !nds32_const_unspec_p (XEXP (SET_SRC (PATTERN (use_insn)), 1)))
  42349. + {
  42350. + int sym_type = nds32_pic_tls_symbol_type (use_insn);
  42351. + valid = nds32_pic_tls_group (use_insn, RELAX_ORI, sym_type);
  42352. +
  42353. + /* Insert .relax_* directive. */
  42354. + while (!nds32_group_infos.is_empty ())
  42355. + {
  42356. + use_insn = nds32_group_infos.pop ();
  42357. + if (valid)
  42358. + emit_insn_before (gen_relax_group (group_id), use_insn);
  42359. + }
  42360. + }
  42361. + }
  42362. +
  42363. + relax_group_id++;
  42364. +}
  42365. +
  42366. +/* Convert relax group id in rtl. */
  42367. +
  42368. +static void
  42369. +nds32_group_tls_insn (rtx insn)
  42370. +{
  42371. + rtx pat = PATTERN (insn);
  42372. + rtx unspec_relax_group = XEXP (XVECEXP (pat, 0, 1), 0);
  42373. +
  42374. + while (GET_CODE (pat) != SET && GET_CODE (pat) == PARALLEL)
  42375. + {
  42376. + pat = XVECEXP (pat, 0, 0);
  42377. + }
  42378. +
  42379. + if (GET_CODE (unspec_relax_group) == UNSPEC
  42380. + && XINT (unspec_relax_group, 1) == UNSPEC_VOLATILE_RELAX_GROUP)
  42381. + {
  42382. + XVECEXP (unspec_relax_group, 0, 0) = GEN_INT (relax_group_id);
  42383. + }
  42384. +
  42385. + relax_group_id++;
  42386. +}
  42387. +
  42388. +/* Group the relax candidate instructions for linker. */
  42389. +static void
  42390. +nds32_relax_group (void)
  42391. +{
  42392. + rtx insn;
  42393. +
  42394. + compute_bb_for_insn ();
  42395. +
  42396. + df_chain_add_problem (DF_DU_CHAIN);
  42397. + df_insn_rescan_all ();
  42398. + df_analyze ();
  42399. + calculate_dominance_info (CDI_DOMINATORS);
  42400. +
  42401. + insn = get_insns ();
  42402. + gcc_assert (NOTE_P (insn));
  42403. +
  42404. + for (insn = next_active_insn (insn); insn; insn = next_active_insn (insn))
  42405. + {
  42406. + if (NONJUMP_INSN_P (insn))
  42407. + {
  42408. + /* Find sethi ra, symbol instruction. */
  42409. + if (recog_memoized (insn) == CODE_FOR_sethi
  42410. + && nds32_symbolic_operand (XEXP (SET_SRC (PATTERN (insn)), 0),
  42411. + SImode))
  42412. + nds32_group_insns (insn);
  42413. + else if (recog_memoized (insn) == CODE_FOR_tls_ie)
  42414. + nds32_group_tls_insn (insn);
  42415. + }
  42416. + else if (CALL_P (insn) && recog_memoized (insn) == CODE_FOR_tls_desc)
  42417. + {
  42418. + nds32_group_tls_insn (insn);
  42419. + }
  42420. + }
  42421. +
  42422. + /* We must call df_finish_pass manually because it should be invoked before
  42423. + BB information is destroyed. Hence we cannot set the TODO_df_finish flag
  42424. + to the pass manager. */
  42425. + df_insn_rescan_all ();
  42426. + df_finish_pass (false);
  42427. + free_dominance_info (CDI_DOMINATORS);
  42428. +}
  42429. +
  42430. +static unsigned int
  42431. +nds32_relax_opt (void)
  42432. +{
  42433. + if (TARGET_RELAX_HINT)
  42434. + nds32_relax_group ();
  42435. + return 1;
  42436. +}
  42437. +
  42438. +const pass_data pass_data_nds32_relax_opt =
  42439. +{
  42440. + RTL_PASS, /* type */
  42441. + "relax_opt", /* name */
  42442. + OPTGROUP_NONE, /* optinfo_flags */
  42443. + true, /* has_gate */
  42444. + true, /* has_execute */
  42445. + TV_MACH_DEP, /* tv_id */
  42446. + 0, /* properties_required */
  42447. + 0, /* properties_provided */
  42448. + 0, /* properties_destroyed */
  42449. + 0, /* todo_flags_start */
  42450. + ( TODO_df_finish | TODO_verify_rtl_sharing), /* todo_flags_finish */
  42451. +};
  42452. +
  42453. +class pass_nds32_relax_opt : public rtl_opt_pass
  42454. +{
  42455. +public:
  42456. + pass_nds32_relax_opt (gcc::context *ctxt)
  42457. + : rtl_opt_pass (pass_data_nds32_relax_opt, ctxt)
  42458. + {}
  42459. +
  42460. + /* opt_pass methods: */
  42461. + bool gate () { return TARGET_RELAX_HINT; }
  42462. + unsigned int execute () { return nds32_relax_opt (); }
  42463. +};
  42464. +
  42465. +rtl_opt_pass *
  42466. +make_pass_nds32_relax_opt (gcc::context *ctxt)
  42467. +{
  42468. + return new pass_nds32_relax_opt (ctxt);
  42469. +}
  42470. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/nds32-soft-fp-comm.c gcc-4.9.4/gcc/config/nds32/nds32-soft-fp-comm.c
  42471. --- gcc-4.9.4.orig/gcc/config/nds32/nds32-soft-fp-comm.c 1970-01-01 01:00:00.000000000 +0100
  42472. +++ gcc-4.9.4/gcc/config/nds32/nds32-soft-fp-comm.c 2016-08-08 20:37:45.582273034 +0200
  42473. @@ -0,0 +1,139 @@
  42474. +/* Operand commutative for soft floating point arithmetic pass
  42475. + of Andes NDS32 cpu for GNU compiler
  42476. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  42477. + Contributed by Andes Technology Corporation.
  42478. +
  42479. + This file is part of GCC.
  42480. +
  42481. + GCC is free software; you can redistribute it and/or modify it
  42482. + under the terms of the GNU General Public License as published
  42483. + by the Free Software Foundation; either version 3, or (at your
  42484. + option) any later version.
  42485. +
  42486. + GCC is distributed in the hope that it will be useful, but WITHOUT
  42487. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  42488. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  42489. + License for more details.
  42490. +
  42491. + You should have received a copy of the GNU General Public License
  42492. + along with GCC; see the file COPYING3. If not see
  42493. + <http://www.gnu.org/licenses/>. */
  42494. +
  42495. +
  42496. +#include "config.h"
  42497. +#include "system.h"
  42498. +#include "coretypes.h"
  42499. +#include "tree.h"
  42500. +#include "function.h"
  42501. +#include "expr.h"
  42502. +#include "df.h"
  42503. +#include "tree-pass.h"
  42504. +
  42505. +#define ARG0_REGNO 0
  42506. +#define ARG1_REGNO 1
  42507. +
  42508. +static int
  42509. +nds32_soft_fp_arith_comm_opt (void)
  42510. +{
  42511. + basic_block bb;
  42512. + rtx insn;
  42513. + FOR_EACH_BB_FN (bb, cfun)
  42514. + {
  42515. + FOR_BB_INSNS (bb, insn)
  42516. + {
  42517. + if (!CALL_P (insn))
  42518. + continue;
  42519. +
  42520. + rtx pat = PATTERN (insn);
  42521. + rtx call_rtx = XVECEXP (pat, 0, 0);
  42522. +
  42523. + if (GET_CODE (call_rtx) == SET)
  42524. + call_rtx = SET_SRC (call_rtx);
  42525. +
  42526. + rtx func_mem = XEXP (call_rtx, 0);
  42527. + rtx symbol = XEXP (func_mem, 0);
  42528. + const char *func_name = XSTR (symbol, 0);
  42529. + if (!((strcmp("__mulsf3", func_name) == 0)
  42530. + || (strcmp("__addsf3", func_name) == 0)))
  42531. + continue;
  42532. +
  42533. + rtx prev_insn = insn;
  42534. + rtx arg0_insn = NULL_RTX;
  42535. + rtx arg1_insn = NULL_RTX;
  42536. + while ((prev_insn = PREV_INSN (prev_insn)) && prev_insn)
  42537. + {
  42538. + if (BLOCK_FOR_INSN (prev_insn) != BLOCK_FOR_INSN (insn))
  42539. + break;
  42540. +
  42541. + rtx set = PATTERN (prev_insn);
  42542. +
  42543. + rtx dst_reg = SET_DEST (set);
  42544. +
  42545. + if (!REG_P (dst_reg))
  42546. + break;
  42547. +
  42548. + unsigned regno = REGNO (dst_reg);
  42549. +
  42550. + if (regno == ARG0_REGNO)
  42551. + {
  42552. + arg0_insn = prev_insn;
  42553. + continue;
  42554. + }
  42555. + else if (regno == ARG1_REGNO)
  42556. + {
  42557. + arg1_insn = prev_insn;
  42558. + continue;
  42559. + }
  42560. + break;
  42561. + }
  42562. + if (arg0_insn == NULL_RTX || arg1_insn == NULL_RTX)
  42563. + continue;
  42564. +
  42565. + rtx arg0_src = SET_SRC (PATTERN (arg0_insn));
  42566. + rtx arg1_src = SET_SRC (PATTERN (arg1_insn));
  42567. +
  42568. + if ((REG_P (arg0_src) && REGNO (arg0_src) == ARG1_REGNO)
  42569. + || (REG_P (arg1_src) && REGNO (arg1_src) == ARG0_REGNO))
  42570. + {
  42571. + /* Swap operand! */
  42572. + rtx tmp = SET_DEST (PATTERN (arg0_insn));
  42573. + SET_DEST (PATTERN (arg0_insn)) = SET_DEST (PATTERN (arg1_insn));
  42574. + SET_DEST (PATTERN (arg1_insn)) = tmp;
  42575. + }
  42576. + }
  42577. + }
  42578. + return 1;
  42579. +}
  42580. +
  42581. +const pass_data pass_data_nds32_soft_fp_arith_comm_opt =
  42582. +{
  42583. + RTL_PASS, /* type */
  42584. + "soft_fp_arith_comm", /* name */
  42585. + OPTGROUP_NONE, /* optinfo_flags */
  42586. + true, /* has_gate */
  42587. + true, /* has_execute */
  42588. + TV_MACH_DEP, /* tv_id */
  42589. + 0, /* properties_required */
  42590. + 0, /* properties_provided */
  42591. + 0, /* properties_destroyed */
  42592. + 0, /* todo_flags_start */
  42593. + TODO_verify_rtl_sharing, /* todo_flags_finish */
  42594. +};
  42595. +
  42596. +class pass_nds32_soft_fp_arith_comm_opt : public rtl_opt_pass
  42597. +{
  42598. +public:
  42599. + pass_nds32_soft_fp_arith_comm_opt (gcc::context *ctxt)
  42600. + : rtl_opt_pass (pass_data_nds32_soft_fp_arith_comm_opt, ctxt)
  42601. + {}
  42602. +
  42603. + /* opt_pass methods: */
  42604. + bool gate () { return TARGET_SOFT_FP_ARITH_COMM && !TARGET_FPU_SINGLE; }
  42605. + unsigned int execute () { return nds32_soft_fp_arith_comm_opt (); }
  42606. +};
  42607. +
  42608. +rtl_opt_pass *
  42609. +make_pass_nds32_soft_fp_arith_comm_opt (gcc::context *ctxt)
  42610. +{
  42611. + return new pass_nds32_soft_fp_arith_comm_opt (ctxt);
  42612. +}
  42613. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/pipelines.md gcc-4.9.4/gcc/config/nds32/pipelines.md
  42614. --- gcc-4.9.4.orig/gcc/config/nds32/pipelines.md 2014-01-02 23:23:26.000000000 +0100
  42615. +++ gcc-4.9.4/gcc/config/nds32/pipelines.md 2016-08-08 20:37:45.594273497 +0200
  42616. @@ -1,5 +1,5 @@
  42617. ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
  42618. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  42619. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  42620. ;; Contributed by Andes Technology Corporation.
  42621. ;;
  42622. ;; This file is part of GCC.
  42623. @@ -18,12 +18,47 @@
  42624. ;; along with GCC; see the file COPYING3. If not see
  42625. ;; <http://www.gnu.org/licenses/>.
  42626. -(define_automaton "nds32_machine")
  42627. +;; ------------------------------------------------------------------------
  42628. +;; Include N7 pipeline settings.
  42629. +;; ------------------------------------------------------------------------
  42630. +(include "nds32-n7.md")
  42631. +
  42632. +
  42633. +;; ------------------------------------------------------------------------
  42634. +;; Include N8 pipeline settings.
  42635. +;; ------------------------------------------------------------------------
  42636. +(include "nds32-n8.md")
  42637. +
  42638. +
  42639. +;; ------------------------------------------------------------------------
  42640. +;; Include E8 pipeline settings.
  42641. +;; ------------------------------------------------------------------------
  42642. +(include "nds32-e8.md")
  42643. +
  42644. +
  42645. +;; ------------------------------------------------------------------------
  42646. +;; Include N9/N10 pipeline settings.
  42647. +;; ------------------------------------------------------------------------
  42648. +(include "nds32-n9-3r2w.md")
  42649. +(include "nds32-n9-2r1w.md")
  42650. +
  42651. +
  42652. +;; ------------------------------------------------------------------------
  42653. +;; Include N12/N13 pipeline settings.
  42654. +;; ------------------------------------------------------------------------
  42655. +(include "nds32-n13.md")
  42656. +
  42657. +
  42658. +;; ------------------------------------------------------------------------
  42659. +;; Define simple pipeline settings.
  42660. +;; ------------------------------------------------------------------------
  42661. +
  42662. +(define_automaton "nds32_simple_machine")
  42663. -(define_cpu_unit "general_unit" "nds32_machine")
  42664. +(define_cpu_unit "simple_unit" "nds32_simple_machine")
  42665. (define_insn_reservation "simple_insn" 1
  42666. - (eq_attr "type" "unknown,load,store,move,alu,compare,branch,call,misc")
  42667. - "general_unit")
  42668. + (eq_attr "pipeline_model" "simple")
  42669. + "simple_unit")
  42670. ;; ------------------------------------------------------------------------
  42671. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/predicates.md gcc-4.9.4/gcc/config/nds32/predicates.md
  42672. --- gcc-4.9.4.orig/gcc/config/nds32/predicates.md 2014-01-02 23:23:26.000000000 +0100
  42673. +++ gcc-4.9.4/gcc/config/nds32/predicates.md 2016-08-08 20:37:45.594273497 +0200
  42674. @@ -1,5 +1,5 @@
  42675. ;; Predicate definitions of Andes NDS32 cpu for GNU compiler
  42676. -;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
  42677. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
  42678. ;; Contributed by Andes Technology Corporation.
  42679. ;;
  42680. ;; This file is part of GCC.
  42681. @@ -24,25 +24,89 @@
  42682. (define_predicate "nds32_greater_less_comparison_operator"
  42683. (match_code "gt,ge,lt,le"))
  42684. +(define_predicate "nds32_float_comparison_operator"
  42685. + (match_code "eq,ne,le,lt,ge,gt,ordered,unordered,ungt,unge,unlt,unle"))
  42686. +
  42687. +(define_predicate "nds32_movecc_comparison_operator"
  42688. + (match_code "eq,ne,le,leu,ge,geu"))
  42689. +
  42690. (define_special_predicate "nds32_logical_binary_operator"
  42691. (match_code "and,ior,xor"))
  42692. +(define_special_predicate "nds32_conditional_call_comparison_operator"
  42693. + (match_code "lt,ge"))
  42694. +
  42695. +(define_special_predicate "nds32_have_33_inst_operator"
  42696. + (match_code "mult,and,ior,xor"))
  42697. +
  42698. (define_predicate "nds32_symbolic_operand"
  42699. (match_code "const,symbol_ref,label_ref"))
  42700. +(define_predicate "nds32_nonunspec_symbolic_operand"
  42701. + (and (match_code "const,symbol_ref,label_ref")
  42702. + (match_test "!flag_pic && nds32_const_unspec_p (op)")))
  42703. +
  42704. +(define_predicate "nds32_label_operand"
  42705. + (match_code "label_ref"))
  42706. +
  42707. (define_predicate "nds32_reg_constant_operand"
  42708. - (ior (match_operand 0 "register_operand")
  42709. - (match_operand 0 "const_int_operand")))
  42710. + (match_code "reg,const_int"))
  42711. (define_predicate "nds32_rimm15s_operand"
  42712. (ior (match_operand 0 "register_operand")
  42713. (and (match_operand 0 "const_int_operand")
  42714. (match_test "satisfies_constraint_Is15 (op)"))))
  42715. +(define_predicate "nds32_rimm11s_operand"
  42716. + (ior (match_operand 0 "register_operand")
  42717. + (and (match_operand 0 "const_int_operand")
  42718. + (match_test "satisfies_constraint_Is11 (op)"))))
  42719. +
  42720. +(define_predicate "nds32_imm_0_1_operand"
  42721. + (and (match_operand 0 "const_int_operand")
  42722. + (ior (match_test "satisfies_constraint_Iv00 (op)")
  42723. + (match_test "satisfies_constraint_Iv01 (op)"))))
  42724. +
  42725. +(define_predicate "nds32_imm_1_2_operand"
  42726. + (and (match_operand 0 "const_int_operand")
  42727. + (ior (match_test "satisfies_constraint_Iv01 (op)")
  42728. + (match_test "satisfies_constraint_Iv02 (op)"))))
  42729. +
  42730. +(define_predicate "nds32_imm_1_2_4_8_operand"
  42731. + (and (match_operand 0 "const_int_operand")
  42732. + (ior (ior (match_test "satisfies_constraint_Iv01 (op)")
  42733. + (match_test "satisfies_constraint_Iv02 (op)"))
  42734. + (ior (match_test "satisfies_constraint_Iv04 (op)")
  42735. + (match_test "satisfies_constraint_Iv08 (op)")))))
  42736. +
  42737. +(define_predicate "nds32_imm2u_operand"
  42738. + (and (match_operand 0 "const_int_operand")
  42739. + (match_test "satisfies_constraint_Iu02 (op)")))
  42740. +
  42741. +(define_predicate "nds32_imm4u_operand"
  42742. + (and (match_operand 0 "const_int_operand")
  42743. + (match_test "satisfies_constraint_Iu04 (op)")))
  42744. +
  42745. (define_predicate "nds32_imm5u_operand"
  42746. (and (match_operand 0 "const_int_operand")
  42747. (match_test "satisfies_constraint_Iu05 (op)")))
  42748. +(define_predicate "nds32_imm6u_operand"
  42749. + (and (match_operand 0 "const_int_operand")
  42750. + (match_test "satisfies_constraint_Iu06 (op)")))
  42751. +
  42752. +(define_predicate "nds32_rimm4u_operand"
  42753. + (ior (match_operand 0 "register_operand")
  42754. + (match_operand 0 "nds32_imm4u_operand")))
  42755. +
  42756. +(define_predicate "nds32_rimm5u_operand"
  42757. + (ior (match_operand 0 "register_operand")
  42758. + (match_operand 0 "nds32_imm5u_operand")))
  42759. +
  42760. +(define_predicate "nds32_rimm6u_operand"
  42761. + (ior (match_operand 0 "register_operand")
  42762. + (match_operand 0 "nds32_imm6u_operand")))
  42763. +
  42764. (define_predicate "nds32_move_operand"
  42765. (and (match_operand 0 "general_operand")
  42766. (not (match_code "high,const,symbol_ref,label_ref")))
  42767. @@ -57,12 +121,103 @@
  42768. return true;
  42769. })
  42770. +(define_predicate "nds32_vmove_operand"
  42771. + (and (match_operand 0 "general_operand")
  42772. + (not (match_code "high,const,symbol_ref,label_ref")))
  42773. +{
  42774. + /* If the constant op does NOT satisfy Is20 nor Ihig,
  42775. + we can not perform move behavior by a single instruction. */
  42776. + if (GET_CODE (op) == CONST_VECTOR
  42777. + && !satisfies_constraint_CVs2 (op)
  42778. + && !satisfies_constraint_CVhi (op))
  42779. + return false;
  42780. +
  42781. + return true;
  42782. +})
  42783. +
  42784. +(define_predicate "nds32_and_operand"
  42785. + (match_code "reg,const_int")
  42786. +{
  42787. + return REG_P (op)
  42788. + || satisfies_constraint_Izeb (op)
  42789. + || satisfies_constraint_Izeh (op)
  42790. + || satisfies_constraint_Ixls (op)
  42791. + || satisfies_constraint_Ix11 (op)
  42792. + || satisfies_constraint_Ibms (op)
  42793. + || satisfies_constraint_Ifex (op)
  42794. + || satisfies_constraint_Iu15 (op)
  42795. + || satisfies_constraint_Ii15 (op)
  42796. + || satisfies_constraint_Ic15 (op);
  42797. +})
  42798. +
  42799. +(define_predicate "nds32_ior_operand"
  42800. + (match_code "reg,const_int")
  42801. +{
  42802. + return REG_P (op)
  42803. + || satisfies_constraint_Iu15 (op)
  42804. + || satisfies_constraint_Ie15 (op);
  42805. +})
  42806. +
  42807. +(define_predicate "nds32_xor_operand"
  42808. + (match_code "reg,const_int")
  42809. +{
  42810. + return REG_P (op)
  42811. + || GET_CODE (op) == SUBREG
  42812. + || satisfies_constraint_Iu15 (op)
  42813. + || satisfies_constraint_It15 (op);
  42814. +})
  42815. +
  42816. +(define_predicate "nds32_general_register_operand"
  42817. + (match_code "reg,subreg")
  42818. +{
  42819. + if (GET_CODE (op) == SUBREG)
  42820. + op = SUBREG_REG (op);
  42821. +
  42822. + return (REG_P (op)
  42823. + && (REGNO (op) >= FIRST_PSEUDO_REGISTER
  42824. + || REGNO (op) <= NDS32_LAST_GPR_REGNUM));
  42825. +})
  42826. +
  42827. +(define_predicate "nds32_insv_operand"
  42828. + (match_code "const_int")
  42829. +{
  42830. + return INTVAL (op) == 0
  42831. + || INTVAL (op) == 8
  42832. + || INTVAL (op) == 16
  42833. + || INTVAL (op) == 24;
  42834. +})
  42835. +
  42836. +(define_predicate "nds32_lmw_smw_base_operand"
  42837. + (and (match_code "mem")
  42838. + (match_test "nds32_valid_smw_lwm_base_p (op)")))
  42839. +
  42840. +(define_predicate "float_even_register_operand"
  42841. + (and (match_code "reg")
  42842. + (and (match_test "REGNO (op) >= NDS32_FIRST_FPR_REGNUM")
  42843. + (match_test "REGNO (op) <= NDS32_LAST_FPR_REGNUM")
  42844. + (match_test "(REGNO (op) & 1) == 0"))))
  42845. +
  42846. +(define_predicate "float_odd_register_operand"
  42847. + (and (match_code "reg")
  42848. + (and (match_test "REGNO (op) >= NDS32_FIRST_FPR_REGNUM")
  42849. + (match_test "REGNO (op) <= NDS32_LAST_FPR_REGNUM")
  42850. + (match_test "(REGNO (op) & 1) != 0"))))
  42851. +
  42852. (define_special_predicate "nds32_load_multiple_operation"
  42853. (match_code "parallel")
  42854. {
  42855. /* To verify 'load' operation, pass 'true' for the second argument.
  42856. See the implementation in nds32.c for details. */
  42857. - return nds32_valid_multiple_load_store (op, true);
  42858. + return nds32_valid_multiple_load_store_p (op, true, false);
  42859. +})
  42860. +
  42861. +(define_special_predicate "nds32_load_multiple_and_update_address_operation"
  42862. + (match_code "parallel")
  42863. +{
  42864. + /* To verify 'load' operation, pass 'true' for the second argument.
  42865. + to verify 'update address' operation, pass 'true' for the third argument
  42866. + See the implementation in nds32.c for details. */
  42867. + return nds32_valid_multiple_load_store_p (op, true, true);
  42868. })
  42869. (define_special_predicate "nds32_store_multiple_operation"
  42870. @@ -70,23 +225,32 @@
  42871. {
  42872. /* To verify 'store' operation, pass 'false' for the second argument.
  42873. See the implementation in nds32.c for details. */
  42874. - return nds32_valid_multiple_load_store (op, false);
  42875. + return nds32_valid_multiple_load_store_p (op, false, false);
  42876. +})
  42877. +
  42878. +(define_special_predicate "nds32_store_multiple_and_update_address_operation"
  42879. + (match_code "parallel")
  42880. +{
  42881. + /* To verify 'store' operation, pass 'false' for the second argument,
  42882. + to verify 'update address' operation, pass 'true' for the third argument
  42883. + See the implementation in nds32.c for details. */
  42884. + return nds32_valid_multiple_load_store_p (op, false, true);
  42885. })
  42886. (define_special_predicate "nds32_stack_push_operation"
  42887. (match_code "parallel")
  42888. {
  42889. /* To verify 'push' operation, pass 'true' for the second argument.
  42890. - See the implementation in nds32.c for details. */
  42891. - return nds32_valid_stack_push_pop (op, true);
  42892. + See the implementation in nds32-predicates.c for details. */
  42893. + return nds32_valid_stack_push_pop_p (op, true);
  42894. })
  42895. (define_special_predicate "nds32_stack_pop_operation"
  42896. (match_code "parallel")
  42897. {
  42898. /* To verify 'pop' operation, pass 'false' for the second argument.
  42899. - See the implementation in nds32.c for details. */
  42900. - return nds32_valid_stack_push_pop (op, false);
  42901. + See the implementation in nds32-predicates.c for details. */
  42902. + return nds32_valid_stack_push_pop_p (op, false);
  42903. })
  42904. ;; ------------------------------------------------------------------------
  42905. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/t-elf gcc-4.9.4/gcc/config/nds32/t-elf
  42906. --- gcc-4.9.4.orig/gcc/config/nds32/t-elf 1970-01-01 01:00:00.000000000 +0100
  42907. +++ gcc-4.9.4/gcc/config/nds32/t-elf 2016-08-08 20:37:45.594273497 +0200
  42908. @@ -0,0 +1,34 @@
  42909. +# The multilib settings of Andes NDS32 cpu for GNU compiler
  42910. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  42911. +# Contributed by Andes Technology Corporation.
  42912. +#
  42913. +# This file is part of GCC.
  42914. +#
  42915. +# GCC is free software; you can redistribute it and/or modify it
  42916. +# under the terms of the GNU General Public License as published
  42917. +# by the Free Software Foundation; either version 3, or (at your
  42918. +# option) any later version.
  42919. +#
  42920. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  42921. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  42922. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  42923. +# License for more details.
  42924. +#
  42925. +# You should have received a copy of the GNU General Public License
  42926. +# along with GCC; see the file COPYING3. If not see
  42927. +# <http://www.gnu.org/licenses/>.
  42928. +
  42929. +# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the
  42930. +# driver program which options are defaults for this target and thus
  42931. +# do not need to be handled specially.
  42932. +MULTILIB_OPTIONS += mcmodel=small/mcmodel=medium/mcmodel=large mvh
  42933. +
  42934. +ifneq ($(filter dsp,$(TM_MULTILIB_CONFIG)),)
  42935. +MULTILIB_OPTIONS += mext-dsp
  42936. +endif
  42937. +
  42938. +ifneq ($(filter zol,$(TM_MULTILIB_CONFIG)),)
  42939. +MULTILIB_OPTIONS += mext-zol
  42940. +endif
  42941. +
  42942. +# ------------------------------------------------------------------------
  42943. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/t-linux gcc-4.9.4/gcc/config/nds32/t-linux
  42944. --- gcc-4.9.4.orig/gcc/config/nds32/t-linux 1970-01-01 01:00:00.000000000 +0100
  42945. +++ gcc-4.9.4/gcc/config/nds32/t-linux 2016-08-08 20:37:45.594273497 +0200
  42946. @@ -0,0 +1,26 @@
  42947. +# The multilib settings of Andes NDS32 cpu for GNU compiler
  42948. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  42949. +# Contributed by Andes Technology Corporation.
  42950. +#
  42951. +# This file is part of GCC.
  42952. +#
  42953. +# GCC is free software; you can redistribute it and/or modify it
  42954. +# under the terms of the GNU General Public License as published
  42955. +# by the Free Software Foundation; either version 3, or (at your
  42956. +# option) any later version.
  42957. +#
  42958. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  42959. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  42960. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  42961. +# License for more details.
  42962. +#
  42963. +# You should have received a copy of the GNU General Public License
  42964. +# along with GCC; see the file COPYING3. If not see
  42965. +# <http://www.gnu.org/licenses/>.
  42966. +
  42967. +# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the
  42968. +# driver program which options are defaults for this target and thus
  42969. +# do not need to be handled specially.
  42970. +MULTILIB_OPTIONS +=
  42971. +
  42972. +# ------------------------------------------------------------------------
  42973. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/t-mlibs gcc-4.9.4/gcc/config/nds32/t-mlibs
  42974. --- gcc-4.9.4.orig/gcc/config/nds32/t-mlibs 2014-02-14 06:01:31.000000000 +0100
  42975. +++ gcc-4.9.4/gcc/config/nds32/t-mlibs 1970-01-01 01:00:00.000000000 +0100
  42976. @@ -1,38 +0,0 @@
  42977. -# The multilib settings of Andes NDS32 cpu for GNU compiler
  42978. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  42979. -# Contributed by Andes Technology Corporation.
  42980. -#
  42981. -# This file is part of GCC.
  42982. -#
  42983. -# GCC is free software; you can redistribute it and/or modify it
  42984. -# under the terms of the GNU General Public License as published
  42985. -# by the Free Software Foundation; either version 3, or (at your
  42986. -# option) any later version.
  42987. -#
  42988. -# GCC is distributed in the hope that it will be useful, but WITHOUT
  42989. -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  42990. -# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  42991. -# License for more details.
  42992. -#
  42993. -# You should have received a copy of the GNU General Public License
  42994. -# along with GCC; see the file COPYING3. If not see
  42995. -# <http://www.gnu.org/licenses/>.
  42996. -
  42997. -# We need to build following multilibs combinations:
  42998. -#
  42999. -# 1. <None multilibs>
  43000. -# 2. -mlittle-endian
  43001. -# 3. -mbig-endian
  43002. -# 4. -mgp-direct
  43003. -# 5. -mno-gp-direct
  43004. -# 6. -mlittle-endian -mgp-direct
  43005. -# 7. -mlittle-endian -mno-gp-direct
  43006. -# 8. -mbig-endian -mgp-direct
  43007. -# 9. -mbig-endian -mno-gp-direct
  43008. -#
  43009. -# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the
  43010. -# driver program which options are defaults for this target and thus
  43011. -# do not need to be handled specially.
  43012. -MULTILIB_OPTIONS = mlittle-endian/mbig-endian mgp-direct/mno-gp-direct
  43013. -
  43014. -# ------------------------------------------------------------------------
  43015. diff -Nur gcc-4.9.4.orig/gcc/config/nds32/t-nds32 gcc-4.9.4/gcc/config/nds32/t-nds32
  43016. --- gcc-4.9.4.orig/gcc/config/nds32/t-nds32 1970-01-01 01:00:00.000000000 +0100
  43017. +++ gcc-4.9.4/gcc/config/nds32/t-nds32 2016-08-08 20:37:45.622274582 +0200
  43018. @@ -0,0 +1,199 @@
  43019. +# Dependency rules rule of Andes NDS32 cpu for GNU compiler
  43020. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  43021. +# Contributed by Andes Technology Corporation.
  43022. +#
  43023. +# This file is part of GCC.
  43024. +#
  43025. +# GCC is free software; you can redistribute it and/or modify it
  43026. +# under the terms of the GNU General Public License as published
  43027. +# by the Free Software Foundation; either version 3, or (at your
  43028. +# option) any later version.
  43029. +#
  43030. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  43031. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  43032. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  43033. +# License for more details.
  43034. +#
  43035. +# You should have received a copy of the GNU General Public License
  43036. +# along with GCC; see the file COPYING3. If not see
  43037. +# <http://www.gnu.org/licenses/>.
  43038. +
  43039. +
  43040. +nds32-md-auxiliary.o: $(srcdir)/config/nds32/nds32-md-auxiliary.c \
  43041. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43042. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43043. + insn-config.h conditions.h output.h dumpfile.h \
  43044. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43045. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43046. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43047. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43048. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43049. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43050. + $(srcdir)/config/nds32/nds32-md-auxiliary.c
  43051. +
  43052. +nds32-memory-manipulation.o: $(srcdir)/config/nds32/nds32-memory-manipulation.c \
  43053. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43054. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43055. + insn-config.h conditions.h output.h dumpfile.h \
  43056. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43057. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43058. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43059. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43060. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43061. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43062. + $(srcdir)/config/nds32/nds32-memory-manipulation.c
  43063. +
  43064. +nds32-predicates.o: $(srcdir)/config/nds32/nds32-predicates.c \
  43065. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43066. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43067. + insn-config.h conditions.h output.h dumpfile.h \
  43068. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43069. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43070. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43071. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43072. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43073. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43074. + $(srcdir)/config/nds32/nds32-predicates.c
  43075. +
  43076. +nds32-intrinsic.o: $(srcdir)/config/nds32/nds32-intrinsic.c \
  43077. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43078. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43079. + insn-config.h conditions.h output.h dumpfile.h \
  43080. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43081. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43082. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43083. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43084. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43085. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43086. + $(srcdir)/config/nds32/nds32-intrinsic.c
  43087. +
  43088. +nds32-pipelines-auxiliary.o: \
  43089. + $(srcdir)/config/nds32/nds32-pipelines-auxiliary.c \
  43090. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43091. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43092. + insn-config.h conditions.h output.h dumpfile.h \
  43093. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43094. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43095. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43096. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43097. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43098. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43099. + $(srcdir)/config/nds32/nds32-pipelines-auxiliary.c
  43100. +
  43101. +nds32-isr.o: \
  43102. + $(srcdir)/config/nds32/nds32-isr.c \
  43103. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43104. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43105. + insn-config.h conditions.h output.h dumpfile.h \
  43106. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43107. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43108. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43109. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43110. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43111. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43112. + $(srcdir)/config/nds32/nds32-isr.c
  43113. +
  43114. +nds32-cost.o: \
  43115. + $(srcdir)/config/nds32/nds32-cost.c \
  43116. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43117. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43118. + insn-config.h conditions.h output.h dumpfile.h \
  43119. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43120. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43121. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43122. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43123. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43124. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43125. + $(srcdir)/config/nds32/nds32-cost.c
  43126. +
  43127. +nds32-fp-as-gp.o: \
  43128. + $(srcdir)/config/nds32/nds32-fp-as-gp.c \
  43129. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43130. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43131. + insn-config.h conditions.h output.h dumpfile.h \
  43132. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43133. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43134. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43135. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43136. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43137. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43138. + $(srcdir)/config/nds32/nds32-fp-as-gp.c
  43139. +
  43140. +nds32-load-store-opt.o: \
  43141. + $(srcdir)/config/nds32/nds32-load-store-opt.c \
  43142. + $(srcdir)/config/nds32/nds32-load-store-opt.h \
  43143. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43144. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43145. + insn-config.h conditions.h output.h dumpfile.h \
  43146. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43147. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43148. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43149. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43150. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43151. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43152. + $(srcdir)/config/nds32/nds32-load-store-opt.c
  43153. +
  43154. +nds32-soft-fp-comm.o: \
  43155. + $(srcdir)/config/nds32/nds32-soft-fp-comm.c \
  43156. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43157. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43158. + insn-config.h conditions.h output.h dumpfile.h \
  43159. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43160. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43161. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43162. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43163. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43164. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43165. + $(srcdir)/config/nds32/nds32-soft-fp-comm.c
  43166. +
  43167. +nds32-regrename.o: \
  43168. + $(srcdir)/config/nds32/nds32-regrename.c \
  43169. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43170. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43171. + insn-config.h conditions.h output.h dumpfile.h \
  43172. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43173. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43174. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43175. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43176. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43177. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43178. + $(srcdir)/config/nds32/nds32-regrename.c
  43179. +
  43180. +nds32-gcse.o: \
  43181. + $(srcdir)/config/nds32/nds32-gcse.c \
  43182. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43183. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43184. + insn-config.h conditions.h output.h dumpfile.h \
  43185. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43186. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43187. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43188. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43189. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43190. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43191. + $(srcdir)/config/nds32/nds32-gcse.c
  43192. +
  43193. +nds32-relax-opt.o: \
  43194. + $(srcdir)/config/nds32/nds32-relax-opt.c \
  43195. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43196. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43197. + insn-config.h conditions.h output.h dumpfile.h \
  43198. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43199. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43200. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43201. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43202. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43203. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43204. + $(srcdir)/config/nds32/nds32-relax-opt.c
  43205. +
  43206. +nds32-hwloop.o: \
  43207. + $(srcdir)/config/nds32/nds32-hwloop.c \
  43208. + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
  43209. + $(RTL_H) $(TREE_H) $(HASH_TABLE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \
  43210. + insn-config.h conditions.h output.h dumpfile.h \
  43211. + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \
  43212. + $(EXPR_H) $(OPTABS_H) $(RECOG_H) $(CGRAPH_H) \
  43213. + $(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
  43214. + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
  43215. + intl.h libfuncs.h $(PARAMS_H) $(OPTS_H)
  43216. + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
  43217. + $(srcdir)/config/nds32/nds32-hwloop.c
  43218. diff -Nur gcc-4.9.4.orig/gcc/config.gcc gcc-4.9.4/gcc/config.gcc
  43219. --- gcc-4.9.4.orig/gcc/config.gcc 2016-03-14 11:03:12.000000000 +0100
  43220. +++ gcc-4.9.4/gcc/config.gcc 2016-08-08 20:37:45.622274582 +0200
  43221. @@ -427,7 +427,25 @@
  43222. ;;
  43223. nds32*)
  43224. cpu_type=nds32
  43225. - extra_headers="nds32_intrinsic.h"
  43226. + need_64bit_hwint=yes
  43227. + extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc"
  43228. + case ${target} in
  43229. + nds32*-*-linux*)
  43230. + extra_options="${extra_options} nds32/nds32-linux.opt"
  43231. + ;;
  43232. + nds32*-*-elf*)
  43233. + extra_options="${extra_options} nds32/nds32-elf.opt"
  43234. + ;;
  43235. + *)
  43236. + ;;
  43237. + esac
  43238. + extra_options="${extra_options} g.opt"
  43239. + extra_objs="nds32-cost.o nds32-intrinsic.o nds32-md-auxiliary.o \
  43240. + nds32-pipelines-auxiliary.o nds32-predicates.o \
  43241. + nds32-memory-manipulation.o nds32-fp-as-gp.o \
  43242. + nds32-load-store-opt.o nds32-soft-fp-comm.o nds32-isr.o \
  43243. + nds32-regrename.o nds32-gcse.o nds32-relax-opt.o \
  43244. + nds32-hwloop.o"
  43245. ;;
  43246. nios2-*-*)
  43247. cpu_type=nios2
  43248. @@ -2135,17 +2153,67 @@
  43249. cxx_target_objs="msp430-c.o"
  43250. tmake_file="${tmake_file} msp430/t-msp430"
  43251. ;;
  43252. -nds32le-*-*)
  43253. +nds32*-*-*)
  43254. target_cpu_default="0"
  43255. tm_defines="${tm_defines}"
  43256. - tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
  43257. - tmake_file="nds32/t-mlibs"
  43258. - ;;
  43259. -nds32be-*-*)
  43260. - target_cpu_default="0|MASK_BIG_ENDIAN"
  43261. - tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
  43262. - tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
  43263. - tmake_file="nds32/t-mlibs"
  43264. + case ${target} in
  43265. + nds32le*-*-*)
  43266. + ;;
  43267. + nds32be-*-*)
  43268. + target_cpu_default="${target_cpu_default}|MASK_BIG_ENDIAN"
  43269. + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
  43270. + ;;
  43271. + esac
  43272. + case ${target} in
  43273. + nds32*-*-elf*)
  43274. + tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file} nds32/elf.h nds32/nds32_intrinsic.h"
  43275. + tmake_file="nds32/t-nds32 nds32/t-elf"
  43276. + ;;
  43277. + nds32*-*-linux*)
  43278. + tm_file="dbxelf.h elfos.h ${tm_file} gnu-user.h linux.h glibc-stdint.h nds32/linux.h nds32/nds32_intrinsic.h"
  43279. + tmake_file="${tmake_file} nds32/t-nds32 nds32/t-linux"
  43280. + ;;
  43281. + esac
  43282. + nds32_multilibs="${with_multilib_list}"
  43283. + if test "$nds32_multilibs" = "default"; then
  43284. + nds32_multilibs=""
  43285. + fi
  43286. + nds32_multilibs=`echo $nds32_multilibs | sed -e 's/,/ /g'`
  43287. + for nds32_multilib in ${nds32_multilibs}; do
  43288. + case ${nds32_multilib} in
  43289. + dsp | zol )
  43290. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG} ${nds32_multilib}"
  43291. + ;;
  43292. + *)
  43293. + echo "--with-multilib-list=${nds32_multilib} not supported."
  43294. + exit 1
  43295. + esac
  43296. + done
  43297. +
  43298. + # Handle --enable-default-relax setting.
  43299. + if test x${enable_default_relax} = xyes; then
  43300. + tm_defines="${tm_defines} TARGET_DEFAULT_RELAX=1"
  43301. + fi
  43302. + # Handle --enable-Os-default-ifc setting.
  43303. + if test x${enable_Os_default_ifc} = xyes; then
  43304. + tm_defines="${tm_defines} TARGET_OS_DEFAULT_IFC=1"
  43305. + fi
  43306. + # Handle --enable-Os-default-ex9 setting.
  43307. + if test x${enable_Os_default_ex9} = xyes; then
  43308. + tm_defines="${tm_defines} TARGET_OS_DEFAULT_EX9=1"
  43309. + fi
  43310. + # Handle --with-ext-dsp
  43311. + if test x${with_ext_dsp} = xyes; then
  43312. + tm_defines="${tm_defines} TARGET_DEFAULT_EXT_DSP=1"
  43313. + fi
  43314. + if test x${with_ext_zol} = xyes; then
  43315. + tm_defines="${tm_defines} TARGET_DEFAULT_HWLOOP=1"
  43316. + fi
  43317. + # Handle --with-16bit-ext, and default is on
  43318. + if test x${with_ext_16bit} != xno; then
  43319. + tm_defines="${tm_defines} TARGET_DEFAULT_16BIT=1"
  43320. + fi
  43321. +
  43322. ;;
  43323. nios2-*-*)
  43324. tm_file="elfos.h ${tm_file}"
  43325. @@ -3867,15 +3935,51 @@
  43326. ;;
  43327. nds32*-*-*)
  43328. - supported_defaults="arch nds32_lib"
  43329. + supported_defaults="arch cpu nds32_lib float fpu_config memory_model"
  43330. # process --with-arch
  43331. case "${with_arch}" in
  43332. - "" | v2 | v3 | v3m)
  43333. + "" | v3 | v3j)
  43334. + # OK
  43335. + tm_defines="${tm_defines} TARGET_ARCH_DEFAULT=0"
  43336. + tm_defines="${tm_defines} TARGET_DEFAULT_ISR_VECTOR_SIZE=4"
  43337. + ;;
  43338. + v2 | v2j | v3m)
  43339. + # OK
  43340. + tm_defines="${tm_defines} TARGET_ARCH_DEFAULT=0"
  43341. + tm_defines="${tm_defines} TARGET_DEFAULT_ISR_VECTOR_SIZE=16"
  43342. + ;;
  43343. + v3f)
  43344. + tm_defines="${tm_defines} TARGET_ARCH_DEFAULT=1"
  43345. + tm_defines="${tm_defines} TARGET_DEFAULT_ISR_VECTOR_SIZE=4"
  43346. + ;;
  43347. + v3s)
  43348. + tm_defines="${tm_defines} TARGET_ARCH_DEFAULT=2"
  43349. + tm_defines="${tm_defines} TARGET_DEFAULT_ISR_VECTOR_SIZE=4"
  43350. + ;;
  43351. + *)
  43352. + echo "Cannot accept --with-arch=$with_arch, available values are: v2 v2j v3 v3j v3m v3f v3s" 1>&2
  43353. + exit 1
  43354. + ;;
  43355. + esac
  43356. +
  43357. + # process --with-memory-model
  43358. + case "${with_memory_model}" in
  43359. + "" | fast | slow)
  43360. + ;;
  43361. + *)
  43362. + echo "Cannot accept --with-memory-model=$with_memory_model, available values are: fast slow" 1>&2
  43363. + exit 1
  43364. + ;;
  43365. + esac
  43366. +
  43367. + # process --with-cpu
  43368. + case "${with_cpu}" in
  43369. + "" | n7 | n8 | e8 | n9 | n10 | n12 | n13)
  43370. # OK
  43371. ;;
  43372. *)
  43373. - echo "Cannot accept --with-arch=$with_arch, available values are: v2 v3 v3m" 1>&2
  43374. + echo "Cannot accept --with-cpu=$with_cpu, available values are: n7 n8 e8 n9 n10 n12 n13" 1>&2
  43375. exit 1
  43376. ;;
  43377. esac
  43378. @@ -3885,18 +3989,50 @@
  43379. "")
  43380. # the default library is newlib
  43381. with_nds32_lib=newlib
  43382. + tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1"
  43383. ;;
  43384. newlib)
  43385. # OK
  43386. + tm_defines="${tm_defines} TARGET_DEFAULT_CTOR_DTOR=1"
  43387. ;;
  43388. mculib)
  43389. # OK
  43390. + # for the arch=v3f or arch=v3s under mculib toolchain,
  43391. + # we would like to set -fno-math-errno as default
  43392. + case "${with_arch}" in
  43393. + v3f | v3s)
  43394. + tm_defines="${tm_defines} TARGET_DEFAULT_NO_MATH_ERRNO=1"
  43395. + ;;
  43396. + esac
  43397. ;;
  43398. *)
  43399. echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
  43400. exit 1
  43401. ;;
  43402. esac
  43403. +
  43404. + # process --with-float
  43405. + case "${with_float}" in
  43406. + "" | soft | hard)
  43407. + # OK
  43408. + ;;
  43409. + *)
  43410. + echo "Cannot accept --with-float=$with_float, available values are: soft hard" 1>&2
  43411. + exit 1
  43412. + ;;
  43413. + esac
  43414. +
  43415. + # process --with-config-fpu
  43416. + case "${with_config_fpu}" in
  43417. + "" | 0 | 1 | 2 | 3)
  43418. + # OK
  43419. + ;;
  43420. + *)
  43421. + echo "Cannot accept --with-config-fpu=$with_config_fpu, available values from 0 to 7" 1>&2
  43422. + exit 1
  43423. + ;;
  43424. + esac
  43425. +
  43426. ;;
  43427. powerpc*-*-* | rs6000-*-*)
  43428. @@ -4201,7 +4337,7 @@
  43429. esac
  43430. t=
  43431. -all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan divide llsc mips-plt synci tls"
  43432. +all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan divide llsc mips-plt synci tls memory_model"
  43433. for option in $all_defaults
  43434. do
  43435. eval "val=\$with_"`echo $option | sed s/-/_/g`
  43436. diff -Nur gcc-4.9.4.orig/gcc/configure gcc-4.9.4/gcc/configure
  43437. --- gcc-4.9.4.orig/gcc/configure 2016-05-22 10:53:32.000000000 +0200
  43438. +++ gcc-4.9.4/gcc/configure 2016-08-08 20:37:45.630274892 +0200
  43439. @@ -26524,7 +26524,7 @@
  43440. # version to the per-target configury.
  43441. case "$cpu_type" in
  43442. aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
  43443. - | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
  43444. + | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
  43445. | xstormy16 | xtensa)
  43446. insn="nop"
  43447. ;;
  43448. diff -Nur gcc-4.9.4.orig/gcc/configure.ac gcc-4.9.4/gcc/configure.ac
  43449. --- gcc-4.9.4.orig/gcc/configure.ac 2016-05-22 10:53:32.000000000 +0200
  43450. +++ gcc-4.9.4/gcc/configure.ac 2016-08-08 20:37:45.630274892 +0200
  43451. @@ -4442,7 +4442,7 @@
  43452. # version to the per-target configury.
  43453. case "$cpu_type" in
  43454. aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
  43455. - | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
  43456. + | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
  43457. | xstormy16 | xtensa)
  43458. insn="nop"
  43459. ;;
  43460. diff -Nur gcc-4.9.4.orig/gcc/cp/g++spec.c gcc-4.9.4/gcc/cp/g++spec.c
  43461. --- gcc-4.9.4.orig/gcc/cp/g++spec.c 2014-01-02 23:23:26.000000000 +0100
  43462. +++ gcc-4.9.4/gcc/cp/g++spec.c 2016-08-08 20:37:45.630274892 +0200
  43463. @@ -401,5 +401,12 @@
  43464. return 0;
  43465. }
  43466. +/* Called before parsing the spec to tell which language driver is used. */
  43467. +int
  43468. +lang_specific_is_c_plus_plus (void)
  43469. +{
  43470. + return 1;
  43471. +}
  43472. +
  43473. /* Number of extra output files that lang_specific_pre_link may generate. */
  43474. int lang_specific_extra_outfiles = 0; /* Not used for C++. */
  43475. diff -Nur gcc-4.9.4.orig/gcc/defaults.h gcc-4.9.4/gcc/defaults.h
  43476. --- gcc-4.9.4.orig/gcc/defaults.h 2014-01-02 23:23:26.000000000 +0100
  43477. +++ gcc-4.9.4/gcc/defaults.h 2016-08-08 20:37:45.646275512 +0200
  43478. @@ -1085,6 +1085,10 @@
  43479. #define LOCAL_REGNO(REGNO) 0
  43480. #endif
  43481. +#ifndef HONOR_REG_ALLOC_ORDER
  43482. +#define HONOR_REG_ALLOC_ORDER 0
  43483. +#endif
  43484. +
  43485. /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
  43486. the stack pointer does not matter. The value is tested only in
  43487. functions that have frame pointers. */
  43488. diff -Nur gcc-4.9.4.orig/gcc/doc/extend.texi gcc-4.9.4/gcc/doc/extend.texi
  43489. --- gcc-4.9.4.orig/gcc/doc/extend.texi 2015-10-15 18:40:14.000000000 +0200
  43490. +++ gcc-4.9.4/gcc/doc/extend.texi 2016-08-08 20:37:47.166334359 +0200
  43491. @@ -12710,38 +12710,33 @@
  43492. These built-in functions are available for the NDS32 target:
  43493. -@deftypefn {Built-in Function} void __builtin_nds32_isync (int *@var{addr})
  43494. +@table @code
  43495. +@item void __builtin_nds32_isync (int *@var{addr})
  43496. Insert an ISYNC instruction into the instruction stream where
  43497. @var{addr} is an instruction address for serialization.
  43498. -@end deftypefn
  43499. -@deftypefn {Built-in Function} void __builtin_nds32_isb (void)
  43500. +@item void __builtin_nds32_isb (void)
  43501. Insert an ISB instruction into the instruction stream.
  43502. -@end deftypefn
  43503. -@deftypefn {Built-in Function} int __builtin_nds32_mfsr (int @var{sr})
  43504. +@item int __builtin_nds32_mfsr (int @var{sr})
  43505. Return the content of a system register which is mapped by @var{sr}.
  43506. -@end deftypefn
  43507. -@deftypefn {Built-in Function} int __builtin_nds32_mfusr (int @var{usr})
  43508. +@item int __builtin_nds32_mfusr (int @var{usr})
  43509. Return the content of a user space register which is mapped by @var{usr}.
  43510. -@end deftypefn
  43511. -@deftypefn {Built-in Function} void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
  43512. +@item void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
  43513. Move the @var{value} to a system register which is mapped by @var{sr}.
  43514. -@end deftypefn
  43515. -@deftypefn {Built-in Function} void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
  43516. +@item void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
  43517. Move the @var{value} to a user space register which is mapped by @var{usr}.
  43518. -@end deftypefn
  43519. -@deftypefn {Built-in Function} void __builtin_nds32_setgie_en (void)
  43520. +@item void __builtin_nds32_setgie_en (void)
  43521. Enable global interrupt.
  43522. -@end deftypefn
  43523. -@deftypefn {Built-in Function} void __builtin_nds32_setgie_dis (void)
  43524. +@item void __builtin_nds32_setgie_dis (void)
  43525. Disable global interrupt.
  43526. -@end deftypefn
  43527. +
  43528. +@end table
  43529. @node picoChip Built-in Functions
  43530. @subsection picoChip Built-in Functions
  43531. diff -Nur gcc-4.9.4.orig/gcc/doc/install.texi gcc-4.9.4/gcc/doc/install.texi
  43532. --- gcc-4.9.4.orig/gcc/doc/install.texi 2015-06-26 19:47:23.000000000 +0200
  43533. +++ gcc-4.9.4/gcc/doc/install.texi 2016-08-08 20:37:50.666469869 +0200
  43534. @@ -1901,7 +1901,7 @@
  43535. @item --with-nds32-lib=@var{library}
  43536. Specifies that @var{library} setting is used for building @file{libgcc.a}.
  43537. -Currently, the valid @var{library} is @samp{newlib} or @samp{mculib}.
  43538. +Currently, the valid @var{library} is 'newlib' or 'mculib'.
  43539. This option is only supported for the NDS32 target.
  43540. @item --with-build-time-tools=@var{dir}
  43541. diff -Nur gcc-4.9.4.orig/gcc/doc/invoke.texi gcc-4.9.4/gcc/doc/invoke.texi
  43542. --- gcc-4.9.4.orig/gcc/doc/invoke.texi 2016-06-07 23:49:58.000000000 +0200
  43543. +++ gcc-4.9.4/gcc/doc/invoke.texi 2016-08-08 20:37:50.670470024 +0200
  43544. @@ -835,12 +835,17 @@
  43545. -mreduced-regs -mfull-regs @gol
  43546. -mcmov -mno-cmov @gol
  43547. -mperf-ext -mno-perf-ext @gol
  43548. +-mperf2-ext -mno-perf2-ext @gol
  43549. +-mstring-ext -mno-string-ext @gol
  43550. -mv3push -mno-v3push @gol
  43551. -m16bit -mno-16bit @gol
  43552. -mgp-direct -mno-gp-direct @gol
  43553. -misr-vector-size=@var{num} @gol
  43554. -mcache-block-size=@var{num} @gol
  43555. -march=@var{arch} @gol
  43556. +-mcpu=@var{cpu} @gol
  43557. +-mmemory-model=@var{cpu} @gol
  43558. +-mconfig-register-ports=@var{ports} @gol
  43559. -mforce-fp-as-gp -mforbid-fp-as-gp @gol
  43560. -mex9 -mctor-dtor -mrelax}
  43561. @@ -18350,6 +18355,22 @@
  43562. @opindex mno-perf-ext
  43563. Do not generate performance extension instructions.
  43564. +@item -mperf2-ext
  43565. +@opindex mperf2-ext
  43566. +Generate performance extension version 2 instructions.
  43567. +
  43568. +@item -mno-perf2-ext
  43569. +@opindex mno-perf2-ext
  43570. +Do not generate performance extension version 2 instructions.
  43571. +
  43572. +@item -mstring-ext
  43573. +@opindex mstring-ext
  43574. +Generate string extension instructions.
  43575. +
  43576. +@item -mno-string-ext
  43577. +@opindex mno-string-ext
  43578. +Do not generate string extension instructions.
  43579. +
  43580. @item -mv3push
  43581. @opindex mv3push
  43582. Generate v3 push25/pop25 instructions.
  43583. @@ -18387,6 +18408,19 @@
  43584. @opindex march
  43585. Specify the name of the target architecture.
  43586. +@item -mcpu=@var{cpu}
  43587. +@opindex mcpu
  43588. +Specify the cpu for pipeline model.
  43589. +
  43590. +@item -mmemory-model=@var{cpu}
  43591. +@opindex mmemory-model
  43592. +Specify fast or slow memory model.
  43593. +
  43594. +@item -mconfig-register-ports=@var{ports}
  43595. +@opindex mconfig-register-ports
  43596. +Specify how many read/write ports for n9/n10 cores.
  43597. +The value should be 3r2w or 2r1w.
  43598. +
  43599. @item -mforce-fp-as-gp
  43600. @opindex mforce-fp-as-gp
  43601. Prevent $fp being allocated during register allocation so that compiler
  43602. diff -Nur gcc-4.9.4.orig/gcc/doc/tm.texi gcc-4.9.4/gcc/doc/tm.texi
  43603. --- gcc-4.9.4.orig/gcc/doc/tm.texi 2014-11-16 16:50:33.000000000 +0100
  43604. +++ gcc-4.9.4/gcc/doc/tm.texi 2016-08-08 20:37:51.174489537 +0200
  43605. @@ -2044,8 +2044,8 @@
  43606. prologue and restoring it in the epilogue. This discourages it from
  43607. using call-saved registers. If a machine wants to ensure that IRA
  43608. allocates registers in the order given by REG_ALLOC_ORDER even if some
  43609. -call-saved registers appear earlier than call-used ones, this macro
  43610. -should be defined.
  43611. +call-saved registers appear earlier than call-used ones, then define this
  43612. + macro as a C expression to nonzero. Default is 0.
  43613. @end defmac
  43614. @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno})
  43615. diff -Nur gcc-4.9.4.orig/gcc/doc/tm.texi.in gcc-4.9.4/gcc/doc/tm.texi.in
  43616. --- gcc-4.9.4.orig/gcc/doc/tm.texi.in 2014-11-16 16:50:33.000000000 +0100
  43617. +++ gcc-4.9.4/gcc/doc/tm.texi.in 2016-08-08 20:37:51.174489537 +0200
  43618. @@ -1849,8 +1849,8 @@
  43619. prologue and restoring it in the epilogue. This discourages it from
  43620. using call-saved registers. If a machine wants to ensure that IRA
  43621. allocates registers in the order given by REG_ALLOC_ORDER even if some
  43622. -call-saved registers appear earlier than call-used ones, this macro
  43623. -should be defined.
  43624. +call-saved registers appear earlier than call-used ones, then define this
  43625. + macro as a C expression to nonzero. Default is 0.
  43626. @end defmac
  43627. @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno})
  43628. diff -Nur gcc-4.9.4.orig/gcc/final.c gcc-4.9.4/gcc/final.c
  43629. --- gcc-4.9.4.orig/gcc/final.c 2014-02-18 22:16:21.000000000 +0100
  43630. +++ gcc-4.9.4/gcc/final.c 2016-08-08 20:37:51.174489537 +0200
  43631. @@ -1004,6 +1004,7 @@
  43632. /* Allocate the rest of the arrays. */
  43633. insn_lengths = XNEWVEC (int, max_uid);
  43634. insn_lengths_max_uid = max_uid;
  43635. + memset (insn_lengths, 0, sizeof (int) * max_uid);
  43636. /* Syntax errors can lead to labels being outside of the main insn stream.
  43637. Initialize insn_addresses, so that we get reproducible results. */
  43638. INSN_ADDRESSES_ALLOC (max_uid);
  43639. diff -Nur gcc-4.9.4.orig/gcc/gcc.c gcc-4.9.4/gcc/gcc.c
  43640. --- gcc-4.9.4.orig/gcc/gcc.c 2015-06-26 19:47:23.000000000 +0200
  43641. +++ gcc-4.9.4/gcc/gcc.c 2016-08-08 20:37:52.410537389 +0200
  43642. @@ -801,6 +801,14 @@
  43643. # define SYSROOT_HEADERS_SUFFIX_SPEC ""
  43644. #endif
  43645. +#ifndef STARTFILE_CXX_SPEC
  43646. +#define STARTFILE_CXX_SPEC STARTFILE_SPEC
  43647. +#endif
  43648. +
  43649. +#ifndef ENDFILE_CXX_SPEC
  43650. +#define ENDFILE_CXX_SPEC ENDFILE_SPEC
  43651. +#endif
  43652. +
  43653. static const char *asm_debug = ASM_DEBUG_SPEC;
  43654. static const char *cpp_spec = CPP_SPEC;
  43655. static const char *cc1_spec = CC1_SPEC;
  43656. @@ -827,6 +835,9 @@
  43657. static const char *sysroot_hdrs_suffix_spec = SYSROOT_HEADERS_SUFFIX_SPEC;
  43658. static const char *self_spec = "";
  43659. +static const char *startfile_cxx_spec = STARTFILE_CXX_SPEC;
  43660. +static const char *endfile_cxx_spec = ENDFILE_CXX_SPEC;
  43661. +
  43662. /* Standard options to cpp, cc1, and as, to reduce duplication in specs.
  43663. There should be no need to override these in target dependent files,
  43664. but we need to copy them to the specs file so that newer versions
  43665. @@ -1326,6 +1337,9 @@
  43666. INIT_STATIC_SPEC ("sysroot_suffix_spec", &sysroot_suffix_spec),
  43667. INIT_STATIC_SPEC ("sysroot_hdrs_suffix_spec", &sysroot_hdrs_suffix_spec),
  43668. INIT_STATIC_SPEC ("self_spec", &self_spec),
  43669. +
  43670. + INIT_STATIC_SPEC ("startfile_cxx", &startfile_cxx_spec),
  43671. + INIT_STATIC_SPEC ("endfile_cxx", &endfile_cxx_spec),
  43672. };
  43673. #ifdef EXTRA_SPECS /* additional specs needed */
  43674. @@ -5256,7 +5270,11 @@
  43675. break;
  43676. case 'E':
  43677. - value = do_spec_1 (endfile_spec, 0, NULL);
  43678. + if (lang_specific_is_c_plus_plus ())
  43679. + value = do_spec_1 (endfile_cxx_spec, 0, NULL);
  43680. + else
  43681. + value = do_spec_1 (endfile_spec, 0, NULL);
  43682. +
  43683. if (value != 0)
  43684. return value;
  43685. break;
  43686. @@ -5301,7 +5319,11 @@
  43687. break;
  43688. case 'S':
  43689. - value = do_spec_1 (startfile_spec, 0, NULL);
  43690. + if (lang_specific_is_c_plus_plus ())
  43691. + value = do_spec_1 (startfile_cxx_spec, 0, NULL);
  43692. + else
  43693. + value = do_spec_1 (startfile_spec, 0, NULL);
  43694. +
  43695. if (value != 0)
  43696. return value;
  43697. break;
  43698. @@ -7496,7 +7518,7 @@
  43699. {
  43700. const char *r;
  43701. - for (q = multilib_options; *q != '\0'; q++)
  43702. + for (q = multilib_options; *q != '\0'; *q && q++)
  43703. {
  43704. while (*q == ' ')
  43705. q++;
  43706. diff -Nur gcc-4.9.4.orig/gcc/gcc.h gcc-4.9.4/gcc/gcc.h
  43707. --- gcc-4.9.4.orig/gcc/gcc.h 2014-01-02 23:23:26.000000000 +0100
  43708. +++ gcc-4.9.4/gcc/gcc.h 2016-08-08 20:37:52.410537389 +0200
  43709. @@ -46,6 +46,9 @@
  43710. /* Called before linking. Returns 0 on success and -1 on failure. */
  43711. extern int lang_specific_pre_link (void);
  43712. +/* Called before parsing the spec to tell which language driver is used. */
  43713. +extern int lang_specific_is_c_plus_plus (void);
  43714. +
  43715. extern int n_infiles;
  43716. /* Number of extra output files that lang_specific_pre_link may generate. */
  43717. diff -Nur gcc-4.9.4.orig/gcc/genoutput.c gcc-4.9.4/gcc/genoutput.c
  43718. --- gcc-4.9.4.orig/gcc/genoutput.c 2014-01-02 23:23:26.000000000 +0100
  43719. +++ gcc-4.9.4/gcc/genoutput.c 2016-08-08 20:37:53.534580908 +0200
  43720. @@ -210,7 +210,7 @@
  43721. /* This is a complete list (unlike the one in genpreds.c) of constraint
  43722. letters and modifiers with machine-independent meaning. The only
  43723. omission is digits, as these are handled specially. */
  43724. -static const char indep_constraints[] = ",=+%*?!#&<>EFVXgimnoprs";
  43725. +static const char indep_constraints[] = ",=+%*$?!#&<>EFVXgimnoprs";
  43726. static struct constraint_data *
  43727. constraints_by_letter_table[1 << CHAR_BIT];
  43728. diff -Nur gcc-4.9.4.orig/gcc/hw-doloop.c gcc-4.9.4/gcc/hw-doloop.c
  43729. --- gcc-4.9.4.orig/gcc/hw-doloop.c 2016-01-22 15:49:22.000000000 +0100
  43730. +++ gcc-4.9.4/gcc/hw-doloop.c 2016-08-08 20:37:53.534580908 +0200
  43731. @@ -57,6 +57,8 @@
  43732. loop->head == NULL ? -1 : loop->head->index,
  43733. loop->depth, REGNO (loop->iter_reg));
  43734. + fprintf (dump_file, " outermost: [%d] ", loop->outermost->loop_no);
  43735. +
  43736. fprintf (dump_file, " blocks: [ ");
  43737. for (ix = 0; loop->blocks.iterate (ix, &b); ix++)
  43738. fprintf (dump_file, "%d ", b->index);
  43739. @@ -84,6 +86,7 @@
  43740. {
  43741. unsigned ix;
  43742. basic_block bb;
  43743. + regset set_this_insn = ALLOC_REG_SET (NULL);
  43744. if (loop->bad)
  43745. return;
  43746. @@ -120,7 +123,6 @@
  43747. insn = NEXT_INSN (insn))
  43748. {
  43749. df_ref *def_rec;
  43750. - HARD_REG_SET set_this_insn;
  43751. if (!NONDEBUG_INSN_P (insn))
  43752. continue;
  43753. @@ -130,23 +132,45 @@
  43754. || asm_noperands (PATTERN (insn)) >= 0))
  43755. loop->has_asm = true;
  43756. - CLEAR_HARD_REG_SET (set_this_insn);
  43757. + CLEAR_REG_SET (set_this_insn);
  43758. for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
  43759. {
  43760. rtx dreg = DF_REF_REG (*def_rec);
  43761. + unsigned int regno, nregs;
  43762. if (!REG_P (dreg))
  43763. continue;
  43764. - add_to_hard_reg_set (&set_this_insn, GET_MODE (dreg),
  43765. - REGNO (dreg));
  43766. + regno = REGNO (dreg);
  43767. + nregs = GET_MODE (dreg) / UNITS_PER_WORD;
  43768. + bitmap_set_range (set_this_insn, regno, nregs);
  43769. }
  43770. if (insn == loop->loop_end)
  43771. - CLEAR_HARD_REG_BIT (set_this_insn, REGNO (loop->iter_reg));
  43772. + CLEAR_REGNO_REG_SET (set_this_insn, REGNO (loop->iter_reg));
  43773. else if (reg_mentioned_p (loop->iter_reg, PATTERN (insn)))
  43774. loop->iter_reg_used = true;
  43775. - IOR_HARD_REG_SET (loop->regs_set_in_loop, set_this_insn);
  43776. + IOR_REG_SET (loop->regs_set_in_loop, set_this_insn);
  43777. + }
  43778. + }
  43779. + FREE_REG_SET (set_this_insn);
  43780. +}
  43781. +
  43782. +/* Get outermost loop for each loop. */
  43783. +static void
  43784. +add_outermost (hwloop_info loop)
  43785. +{
  43786. + int ix;
  43787. + hwloop_info inner;
  43788. +
  43789. + if (!loop->outermost)
  43790. + {
  43791. + loop->outermost = loop;
  43792. +
  43793. + for (ix = 0; loop->loops.iterate (ix, &inner); ix++)
  43794. + {
  43795. + if (loop->loop_no != inner->loop_no)
  43796. + inner->outermost = loop;
  43797. }
  43798. }
  43799. }
  43800. @@ -404,6 +428,7 @@
  43801. loop->loop_no = nloops++;
  43802. loop->blocks.create (20);
  43803. loop->block_bitmap = BITMAP_ALLOC (loop_stack);
  43804. + loop->regs_set_in_loop = ALLOC_REG_SET (NULL);
  43805. if (dump_file)
  43806. {
  43807. @@ -449,6 +474,10 @@
  43808. }
  43809. }
  43810. + /* Get outermost loop for each loop. */
  43811. + for (loop = loops; loop; loop = loop->next)
  43812. + add_outermost (loop);
  43813. +
  43814. if (dump_file)
  43815. dump_hwloops (loops);
  43816. @@ -466,6 +495,7 @@
  43817. loop->loops.release ();
  43818. loop->blocks.release ();
  43819. BITMAP_FREE (loop->block_bitmap);
  43820. + FREE_REG_SET (loop->regs_set_in_loop);
  43821. XDELETE (loop);
  43822. }
  43823. }
  43824. @@ -549,6 +579,32 @@
  43825. df_analyze ();
  43826. }
  43827. +/* Compute real depth for each loop, for example
  43828. + if 3 neseting depth of loop, the depth form
  43829. + outermost to innermost is 1, 2, 3. */
  43830. +static void
  43831. +compute_real_depth (hwloop_info loop)
  43832. +{
  43833. + int ix;
  43834. + hwloop_info inner;
  43835. + int inner_depth = 0;
  43836. +
  43837. + if (loop->computed_depth)
  43838. + return;
  43839. +
  43840. + loop->computed_depth = 1;
  43841. +
  43842. + for (ix = 0; loop->loops.iterate (ix, &inner); ix++)
  43843. + {
  43844. + compute_real_depth (inner);
  43845. +
  43846. + if (inner_depth < inner->real_depth)
  43847. + inner_depth = inner->real_depth;
  43848. + }
  43849. +
  43850. + loop->real_depth = inner_depth + 1;
  43851. +}
  43852. +
  43853. /* Call the OPT function for LOOP and all of its sub-loops. This is
  43854. done in a depth-first search; innermost loops are visited first.
  43855. OPTIMIZE and FAIL are the functions passed to reorg_loops by the
  43856. @@ -585,7 +641,7 @@
  43857. inner_depth = inner->depth;
  43858. /* The set of registers may be changed while optimizing the inner
  43859. loop. */
  43860. - IOR_HARD_REG_SET (loop->regs_set_in_loop, inner->regs_set_in_loop);
  43861. + IOR_REG_SET (loop->regs_set_in_loop, inner->regs_set_in_loop);
  43862. }
  43863. loop->depth = inner_depth + 1;
  43864. @@ -652,6 +708,10 @@
  43865. for (loop = loops; loop; loop = loop->next)
  43866. scan_loop (loop);
  43867. + /* Compute real depth for each loop. */
  43868. + for (loop = loops; loop; loop = loop->next)
  43869. + compute_real_depth (loop);
  43870. +
  43871. /* Now apply the optimizations. */
  43872. for (loop = loops; loop; loop = loop->next)
  43873. optimize_loop (loop, hooks);
  43874. diff -Nur gcc-4.9.4.orig/gcc/hw-doloop.h gcc-4.9.4/gcc/hw-doloop.h
  43875. --- gcc-4.9.4.orig/gcc/hw-doloop.h 2014-01-02 23:23:26.000000000 +0100
  43876. +++ gcc-4.9.4/gcc/hw-doloop.h 2016-08-08 20:37:53.534580908 +0200
  43877. @@ -31,6 +31,9 @@
  43878. /* Next loop in the graph. */
  43879. hwloop_info next;
  43880. + /* Outermost loop in the graph. */
  43881. + hwloop_info outermost;
  43882. +
  43883. /* Vector of blocks only within the loop, including those within
  43884. inner loops. */
  43885. vec<basic_block> blocks;
  43886. @@ -90,12 +93,19 @@
  43887. This value is valid when the target's optimize function is called. */
  43888. int depth;
  43889. + /* The nesting depth of the loop. If 3 neseting depth of loop,
  43890. + the depth form outermost to innermost is 1, 2, 3. */
  43891. + int real_depth;
  43892. +
  43893. /* True if we can't optimize this loop. */
  43894. bool bad;
  43895. /* True if we have visited this loop during the optimization phase. */
  43896. bool visited;
  43897. + /* True if we have computed this loop real depth. */
  43898. + bool computed_depth;
  43899. +
  43900. /* The following values are collected before calling the target's optimize
  43901. function and are not valid earlier. */
  43902. @@ -115,7 +125,7 @@
  43903. /* Hard registers set at any point in the loop, except for the loop counter
  43904. register's set in the doloop_end instruction. */
  43905. - HARD_REG_SET regs_set_in_loop;
  43906. + regset regs_set_in_loop;
  43907. };
  43908. /* A set of hooks to be defined by a target that wants to use the reorg_loops
  43909. diff -Nur gcc-4.9.4.orig/gcc/ira.c gcc-4.9.4/gcc/ira.c
  43910. --- gcc-4.9.4.orig/gcc/ira.c 2016-03-31 15:21:43.000000000 +0200
  43911. +++ gcc-4.9.4/gcc/ira.c 2016-08-08 20:37:53.534580908 +0200
  43912. @@ -5446,14 +5446,16 @@
  43913. #ifdef ENABLE_IRA_CHECKING
  43914. print_redundant_copies ();
  43915. #endif
  43916. -
  43917. - ira_spilled_reg_stack_slots_num = 0;
  43918. - ira_spilled_reg_stack_slots
  43919. - = ((struct ira_spilled_reg_stack_slot *)
  43920. - ira_allocate (max_regno
  43921. - * sizeof (struct ira_spilled_reg_stack_slot)));
  43922. - memset (ira_spilled_reg_stack_slots, 0,
  43923. - max_regno * sizeof (struct ira_spilled_reg_stack_slot));
  43924. + if (! ira_use_lra_p)
  43925. + {
  43926. + ira_spilled_reg_stack_slots_num = 0;
  43927. + ira_spilled_reg_stack_slots
  43928. + = ((struct ira_spilled_reg_stack_slot *)
  43929. + ira_allocate (max_regno
  43930. + * sizeof (struct ira_spilled_reg_stack_slot)));
  43931. + memset (ira_spilled_reg_stack_slots, 0,
  43932. + max_regno * sizeof (struct ira_spilled_reg_stack_slot));
  43933. + }
  43934. }
  43935. allocate_initial_values ();
  43936. @@ -5489,9 +5491,6 @@
  43937. FOR_ALL_BB_FN (bb, cfun)
  43938. bb->loop_father = NULL;
  43939. current_loops = NULL;
  43940. -
  43941. - if (ira_conflicts_p)
  43942. - ira_free (ira_spilled_reg_stack_slots);
  43943. ira_destroy ();
  43944. diff -Nur gcc-4.9.4.orig/gcc/ira-color.c gcc-4.9.4/gcc/ira-color.c
  43945. --- gcc-4.9.4.orig/gcc/ira-color.c 2014-03-26 07:46:27.000000000 +0100
  43946. +++ gcc-4.9.4/gcc/ira-color.c 2016-08-08 20:37:53.534580908 +0200
  43947. @@ -1599,7 +1599,6 @@
  43948. }
  43949. return j == nregs;
  43950. }
  43951. -#ifndef HONOR_REG_ALLOC_ORDER
  43952. /* Return number of registers needed to be saved and restored at
  43953. function prologue/epilogue if we allocate HARD_REGNO to hold value
  43954. @@ -1618,7 +1617,6 @@
  43955. nregs++;
  43956. return nregs;
  43957. }
  43958. -#endif
  43959. /* Choose a hard register for allocno A. If RETRY_P is TRUE, it means
  43960. that the function called from function
  43961. @@ -1653,11 +1651,9 @@
  43962. enum reg_class aclass;
  43963. enum machine_mode mode;
  43964. static int costs[FIRST_PSEUDO_REGISTER], full_costs[FIRST_PSEUDO_REGISTER];
  43965. -#ifndef HONOR_REG_ALLOC_ORDER
  43966. int saved_nregs;
  43967. enum reg_class rclass;
  43968. int add_cost;
  43969. -#endif
  43970. #ifdef STACK_REGS
  43971. bool no_stack_reg_p;
  43972. #endif
  43973. @@ -1823,19 +1819,19 @@
  43974. continue;
  43975. cost = costs[i];
  43976. full_cost = full_costs[i];
  43977. -#ifndef HONOR_REG_ALLOC_ORDER
  43978. - if ((saved_nregs = calculate_saved_nregs (hard_regno, mode)) != 0)
  43979. - /* We need to save/restore the hard register in
  43980. - epilogue/prologue. Therefore we increase the cost. */
  43981. - {
  43982. - rclass = REGNO_REG_CLASS (hard_regno);
  43983. - add_cost = ((ira_memory_move_cost[mode][rclass][0]
  43984. - + ira_memory_move_cost[mode][rclass][1])
  43985. - * saved_nregs / hard_regno_nregs[hard_regno][mode] - 1);
  43986. - cost += add_cost;
  43987. - full_cost += add_cost;
  43988. - }
  43989. -#endif
  43990. + if (!HONOR_REG_ALLOC_ORDER)
  43991. + if ((saved_nregs = calculate_saved_nregs (hard_regno, mode)) != 0)
  43992. + /* We need to save/restore the hard register in
  43993. + epilogue/prologue. Therefore we increase the cost. */
  43994. + {
  43995. + rclass = REGNO_REG_CLASS (hard_regno);
  43996. + add_cost = ((ira_memory_move_cost[mode][rclass][0]
  43997. + + ira_memory_move_cost[mode][rclass][1])
  43998. + * saved_nregs / hard_regno_nregs[hard_regno][mode] - 1);
  43999. + cost += add_cost;
  44000. + full_cost += add_cost;
  44001. + }
  44002. +
  44003. if (min_cost > cost)
  44004. min_cost = cost;
  44005. if (min_full_cost > full_cost)
  44006. @@ -4068,6 +4064,8 @@
  44007. ira_allocno_iterator ai;
  44008. ira_allocno_t *spilled_coalesced_allocnos;
  44009. + ira_assert (! ira_use_lra_p);
  44010. +
  44011. /* Set up allocnos can be coalesced. */
  44012. coloring_allocno_bitmap = ira_allocate_bitmap ();
  44013. for (i = 0; i < n; i++)
  44014. @@ -4417,6 +4415,8 @@
  44015. bitmap_iterator bi;
  44016. struct ira_spilled_reg_stack_slot *slot = NULL;
  44017. + ira_assert (! ira_use_lra_p);
  44018. +
  44019. ira_assert (inherent_size == PSEUDO_REGNO_BYTES (regno)
  44020. && inherent_size <= total_size
  44021. && ALLOCNO_HARD_REGNO (allocno) < 0);
  44022. @@ -4529,6 +4529,8 @@
  44023. int slot_num;
  44024. ira_allocno_t allocno;
  44025. + ira_assert (! ira_use_lra_p);
  44026. +
  44027. ira_assert (PSEUDO_REGNO_BYTES (regno) <= total_size);
  44028. allocno = ira_regno_allocno_map[regno];
  44029. slot_num = -ALLOCNO_HARD_REGNO (allocno) - 2;
  44030. diff -Nur gcc-4.9.4.orig/gcc/ira-costs.c gcc-4.9.4/gcc/ira-costs.c
  44031. --- gcc-4.9.4.orig/gcc/ira-costs.c 2014-05-22 23:10:26.000000000 +0200
  44032. +++ gcc-4.9.4/gcc/ira-costs.c 2016-08-08 20:37:53.534580908 +0200
  44033. @@ -652,6 +652,11 @@
  44034. c = *++p;
  44035. break;
  44036. + case '$':
  44037. + if (optimize_size)
  44038. + alt_cost -= 2;
  44039. + break;
  44040. +
  44041. case '?':
  44042. alt_cost += 2;
  44043. case '!': case '#': case '&':
  44044. diff -Nur gcc-4.9.4.orig/gcc/ira-lives.c gcc-4.9.4/gcc/ira-lives.c
  44045. --- gcc-4.9.4.orig/gcc/ira-lives.c 2014-01-02 23:23:26.000000000 +0100
  44046. +++ gcc-4.9.4/gcc/ira-lives.c 2016-08-08 20:37:53.534580908 +0200
  44047. @@ -770,6 +770,7 @@
  44048. case '%':
  44049. case '!':
  44050. case '?':
  44051. + case '$':
  44052. break;
  44053. case 'i':
  44054. if (CONSTANT_P (op)
  44055. diff -Nur gcc-4.9.4.orig/gcc/lra.c gcc-4.9.4/gcc/lra.c
  44056. --- gcc-4.9.4.orig/gcc/lra.c 2015-04-09 21:42:24.000000000 +0200
  44057. +++ gcc-4.9.4/gcc/lra.c 2016-08-08 20:37:53.538581063 +0200
  44058. @@ -815,7 +815,7 @@
  44059. switch (c)
  44060. {
  44061. - case '=': case '+': case '*':
  44062. + case '=': case '+': case '*': case '$':
  44063. case 'E': case 'F': case 'G': case 'H':
  44064. case 's': case 'i': case 'n':
  44065. case 'I': case 'J': case 'K': case 'L':
  44066. diff -Nur gcc-4.9.4.orig/gcc/lra-constraints.c gcc-4.9.4/gcc/lra-constraints.c
  44067. --- gcc-4.9.4.orig/gcc/lra-constraints.c 2015-11-26 23:13:36.000000000 +0100
  44068. +++ gcc-4.9.4/gcc/lra-constraints.c 2016-08-08 20:37:53.538581063 +0200
  44069. @@ -1698,7 +1698,7 @@
  44070. c = '\0';
  44071. break;
  44072. - case '=': case '+': case '?': case '*': case '!':
  44073. + case '=': case '+': case '?': case '*': case '!': case '$':
  44074. case ' ': case '\t':
  44075. break;
  44076. @@ -4859,9 +4859,8 @@
  44077. reg_renumber[REGNO (new_reg)] = hard_regno;
  44078. }
  44079. save = emit_spill_move (true, new_reg, original_reg);
  44080. - if (NEXT_INSN (save) != NULL_RTX)
  44081. + if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
  44082. {
  44083. - lra_assert (! call_save_p);
  44084. if (lra_dump_file != NULL)
  44085. {
  44086. fprintf
  44087. @@ -4875,9 +4874,8 @@
  44088. return false;
  44089. }
  44090. restore = emit_spill_move (false, new_reg, original_reg);
  44091. - if (NEXT_INSN (restore) != NULL_RTX)
  44092. + if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
  44093. {
  44094. - lra_assert (! call_save_p);
  44095. if (lra_dump_file != NULL)
  44096. {
  44097. fprintf (lra_dump_file,
  44098. diff -Nur gcc-4.9.4.orig/gcc/Makefile.in gcc-4.9.4/gcc/Makefile.in
  44099. --- gcc-4.9.4.orig/gcc/Makefile.in 2014-10-16 15:50:42.000000000 +0200
  44100. +++ gcc-4.9.4/gcc/Makefile.in 2016-08-08 20:37:45.494269627 +0200
  44101. @@ -1402,6 +1402,7 @@
  44102. tree-scalar-evolution.o \
  44103. tree-sra.o \
  44104. tree-switch-conversion.o \
  44105. + tree-switch-shortcut.o \
  44106. tree-ssa-address.o \
  44107. tree-ssa-alias.o \
  44108. tree-ssa-ccp.o \
  44109. diff -Nur gcc-4.9.4.orig/gcc/params.def gcc-4.9.4/gcc/params.def
  44110. --- gcc-4.9.4.orig/gcc/params.def 2014-10-16 15:51:45.000000000 +0200
  44111. +++ gcc-4.9.4/gcc/params.def 2016-08-08 20:37:53.538581063 +0200
  44112. @@ -64,7 +64,7 @@
  44113. DEFPARAM (PARAM_MAX_INLINE_INSNS_SINGLE,
  44114. "max-inline-insns-single",
  44115. "The maximum number of instructions in a single function eligible for inlining",
  44116. - 400, 0, 0)
  44117. + 450, 0, 0)
  44118. /* The single function inlining limit for functions that are
  44119. inlined by virtue of -finline-functions (-O3).
  44120. @@ -76,7 +76,7 @@
  44121. DEFPARAM (PARAM_MAX_INLINE_INSNS_AUTO,
  44122. "max-inline-insns-auto",
  44123. "The maximum number of instructions when automatically inlining",
  44124. - 40, 0, 0)
  44125. + 90, 0, 0)
  44126. DEFPARAM (PARAM_MAX_INLINE_INSNS_RECURSIVE,
  44127. "max-inline-insns-recursive",
  44128. @@ -1054,6 +1054,22 @@
  44129. "strength reduction",
  44130. 50, 1, 999999)
  44131. +/* Maximum number of instructions to duplicate when shortcutting a switch. */
  44132. +DEFPARAM (PARAM_MAX_SWITCH_INSNS,
  44133. + "max-switch-insns",
  44134. + "Maximum number of instructions to duplicate when "
  44135. + "shortcutting a switch statement",
  44136. + 100, 1, 999999)
  44137. +
  44138. +/* Maximum number of paths to duplicate when shortcutting a switch. */
  44139. +DEFPARAM (PARAM_MAX_SWITCH_PATHS,
  44140. + "max-switch-paths",
  44141. + "Maximum number of new paths to create when"
  44142. + " shortcutting a switch statement",
  44143. + 50, 1, 999999)
  44144. +
  44145. +
  44146. +
  44147. DEFPARAM (PARAM_ASAN_STACK,
  44148. "asan-stack",
  44149. "Enable asan stack protection",
  44150. diff -Nur gcc-4.9.4.orig/gcc/passes.def gcc-4.9.4/gcc/passes.def
  44151. --- gcc-4.9.4.orig/gcc/passes.def 2014-01-17 18:50:10.000000000 +0100
  44152. +++ gcc-4.9.4/gcc/passes.def 2016-08-08 20:37:53.538581063 +0200
  44153. @@ -152,6 +152,7 @@
  44154. NEXT_PASS (pass_call_cdce);
  44155. NEXT_PASS (pass_cselim);
  44156. NEXT_PASS (pass_tree_ifcombine);
  44157. + NEXT_PASS (pass_switch_shortcut);
  44158. NEXT_PASS (pass_phiopt);
  44159. NEXT_PASS (pass_tail_recursion);
  44160. NEXT_PASS (pass_ch);
  44161. diff -Nur gcc-4.9.4.orig/gcc/recog.c gcc-4.9.4/gcc/recog.c
  44162. --- gcc-4.9.4.orig/gcc/recog.c 2015-03-24 08:12:03.000000000 +0100
  44163. +++ gcc-4.9.4/gcc/recog.c 2016-08-08 20:37:53.538581063 +0200
  44164. @@ -1690,6 +1690,7 @@
  44165. case '#':
  44166. case '&':
  44167. case '?':
  44168. + case '$':
  44169. break;
  44170. case '0': case '1': case '2': case '3': case '4':
  44171. @@ -2298,6 +2299,7 @@
  44172. switch (c)
  44173. {
  44174. case '=': case '+': case '*': case '%':
  44175. + case '$':
  44176. case 'E': case 'F': case 'G': case 'H':
  44177. case 's': case 'i': case 'n':
  44178. case 'I': case 'J': case 'K': case 'L':
  44179. @@ -2500,7 +2502,7 @@
  44180. c = '\0';
  44181. break;
  44182. - case '?': case '!': case '*': case '%':
  44183. + case '?': case '!': case '*': case '%': case '$':
  44184. case '=': case '+':
  44185. break;
  44186. diff -Nur gcc-4.9.4.orig/gcc/reload1.c gcc-4.9.4/gcc/reload1.c
  44187. --- gcc-4.9.4.orig/gcc/reload1.c 2014-02-26 22:57:40.000000000 +0100
  44188. +++ gcc-4.9.4/gcc/reload1.c 2016-08-08 20:37:53.542581218 +0200
  44189. @@ -1393,6 +1393,7 @@
  44190. case '>': case 'V': case 'o': case '&': case 'E': case 'F':
  44191. case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
  44192. case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
  44193. + case '$':
  44194. case TARGET_MEM_CONSTRAINT:
  44195. break;
  44196. diff -Nur gcc-4.9.4.orig/gcc/reload.c gcc-4.9.4/gcc/reload.c
  44197. --- gcc-4.9.4.orig/gcc/reload.c 2014-12-17 16:07:28.000000000 +0100
  44198. +++ gcc-4.9.4/gcc/reload.c 2016-08-08 20:37:53.542581218 +0200
  44199. @@ -3208,7 +3208,7 @@
  44200. c = '\0';
  44201. break;
  44202. - case '=': case '+': case '*':
  44203. + case '=': case '+': case '*': case '$':
  44204. break;
  44205. case '%':
  44206. diff -Nur gcc-4.9.4.orig/gcc/stmt.c gcc-4.9.4/gcc/stmt.c
  44207. --- gcc-4.9.4.orig/gcc/stmt.c 2014-01-02 23:23:26.000000000 +0100
  44208. +++ gcc-4.9.4/gcc/stmt.c 2016-08-08 20:37:53.542581218 +0200
  44209. @@ -290,6 +290,7 @@
  44210. break;
  44211. case '?': case '!': case '*': case '&': case '#':
  44212. + case '$':
  44213. case 'E': case 'F': case 'G': case 'H':
  44214. case 's': case 'i': case 'n':
  44215. case 'I': case 'J': case 'K': case 'L': case 'M':
  44216. @@ -389,7 +390,7 @@
  44217. break;
  44218. case '<': case '>':
  44219. - case '?': case '!': case '*': case '#':
  44220. + case '?': case '!': case '*': case '#': case '$':
  44221. case 'E': case 'F': case 'G': case 'H':
  44222. case 's': case 'i': case 'n':
  44223. case 'I': case 'J': case 'K': case 'L': case 'M':
  44224. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c gcc-4.9.4/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c
  44225. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c 2009-08-25 23:38:33.000000000 +0200
  44226. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c 2016-08-08 20:37:53.546581373 +0200
  44227. @@ -1,4 +1,5 @@
  44228. /* { dg-skip-if "too complex for avr and picochip" { picochip-*-* avr-*-* } { "*" } { "" } } */
  44229. +/* { dg-skip-if "lto may cause internal compiler error on cygwin with gcc-4.9" { nds32*-*-* } { "*" } { "" } } */
  44230. /* { dg-timeout-factor 4.0 } */
  44231. #define LIM1(x) x##0, x##1, x##2, x##3, x##4, x##5, x##6, x##7, x##8, x##9,
  44232. #define LIM2(x) LIM1(x##0) LIM1(x##1) LIM1(x##2) LIM1(x##3) LIM1(x##4) \
  44233. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.x gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/20010122-1.x
  44234. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/20010122-1.x 2002-07-17 19:54:16.000000000 +0200
  44235. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/20010122-1.x 2016-08-08 20:37:53.546581373 +0200
  44236. @@ -8,4 +8,12 @@
  44237. }
  44238. }
  44239. +# Please see Andes Bugzilla #10942 for the details.
  44240. +if { [istarget "nds32*-*-*"] } {
  44241. + # The __builtin_return_address(1) on nds32 target is able to
  44242. + # return something useful as long as we always save $lp register
  44243. + # in the stack.
  44244. + set additional_flags "-malways-save-lp"
  44245. +}
  44246. +
  44247. return 0
  44248. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/920501-8.x gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/920501-8.x
  44249. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/920501-8.x 1970-01-01 01:00:00.000000000 +0100
  44250. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/920501-8.x 2016-08-08 20:37:53.546581373 +0200
  44251. @@ -0,0 +1,11 @@
  44252. +# Please see Andes Bugzilla #11005 for the details.
  44253. +if { [istarget "nds32*-*-*"] } {
  44254. + # The nds32 mculib toolchains require
  44255. + # "-u_printf_float" and "-u_scanf_float" options
  44256. + # to fully support printf and scanf functionality.
  44257. + # These options are supposed to be harmless to newlib toolchain.
  44258. + set additional_flags "-u_printf_float -u_scanf_float"
  44259. +}
  44260. +
  44261. +return 0
  44262. +
  44263. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/930513-1.x gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/930513-1.x
  44264. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/930513-1.x 1970-01-01 01:00:00.000000000 +0100
  44265. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/930513-1.x 2016-08-08 20:37:53.546581373 +0200
  44266. @@ -0,0 +1,11 @@
  44267. +# Please see Andes Bugzilla #11005 for the details.
  44268. +if { [istarget "nds32*-*-*"] } {
  44269. + # The nds32 mculib toolchains require
  44270. + # "-u_printf_float" and "-u_scanf_float" options
  44271. + # to fully support printf and scanf functionality.
  44272. + # These options are supposed to be harmless to newlib toolchain.
  44273. + set additional_flags "-u_printf_float -u_scanf_float"
  44274. +}
  44275. +
  44276. +return 0
  44277. +
  44278. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp
  44279. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp 2014-01-02 23:23:26.000000000 +0100
  44280. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp 2016-08-08 20:37:53.546581373 +0200
  44281. @@ -30,6 +30,10 @@
  44282. # Disable tests on machines with no hardware support for IEEE arithmetic.
  44283. if { [istarget "vax-*-*"] || [ istarget "powerpc-*-*spe"] || [istarget "pdp11-*-*"] } { return }
  44284. +# Since we cannot use dg-skip-if or dg-require-effective-target for individual
  44285. +# test case under ieee category, we disable all ieee tests on nds32 fpu toolchains.
  44286. +if { [istarget "nds32*-*-*"] && [check_effective_target_nds32_ext_fpu] } { return }
  44287. +
  44288. if $tracelevel then {
  44289. strace $tracelevel
  44290. }
  44291. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/struct-ret-1.x gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/struct-ret-1.x
  44292. --- gcc-4.9.4.orig/gcc/testsuite/gcc.c-torture/execute/struct-ret-1.x 1970-01-01 01:00:00.000000000 +0100
  44293. +++ gcc-4.9.4/gcc/testsuite/gcc.c-torture/execute/struct-ret-1.x 2016-08-08 20:37:53.546581373 +0200
  44294. @@ -0,0 +1,11 @@
  44295. +# Please see Andes Bugzilla #11005 for the details.
  44296. +if { [istarget "nds32*-*-*"] } {
  44297. + # The nds32 mculib toolchains require
  44298. + # "-u_printf_float" and "-u_scanf_float" options
  44299. + # to fully support printf and scanf functionality.
  44300. + # These options are supposed to be harmless to newlib toolchain.
  44301. + set additional_flags "-u_printf_float -u_scanf_float"
  44302. +}
  44303. +
  44304. +return 0
  44305. +
  44306. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/constructor-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/constructor-1.c
  44307. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/constructor-1.c 2011-10-31 15:26:38.000000000 +0100
  44308. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/constructor-1.c 2016-08-08 20:37:53.546581373 +0200
  44309. @@ -1,5 +1,6 @@
  44310. /* { dg-do run } */
  44311. /* { dg-options "-O2" } */
  44312. +/* { dg-options "-O2 -mctor-dtor" { target { nds32*-*-* } } } */
  44313. /* The ipa-split pass pulls the body of the if(!x) block
  44314. into a separate function to make foo a better inlining
  44315. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-0.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-0.c
  44316. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-0.c 2010-04-22 21:50:23.000000000 +0200
  44317. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-0.c 2016-08-08 20:37:53.546581373 +0200
  44318. @@ -1,4 +1,5 @@
  44319. /* { dg-require-effective-target size32plus } */
  44320. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44321. #define DEBUG 0
  44322. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-10.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-10.c
  44323. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-10.c 2010-02-07 20:49:26.000000000 +0100
  44324. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-10.c 2016-08-08 20:37:53.546581373 +0200
  44325. @@ -1,4 +1,6 @@
  44326. /* { dg-require-effective-target size32plus } */
  44327. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44328. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44329. #define DEBUG 0
  44330. #if DEBUG
  44331. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-11.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-11.c
  44332. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-11.c 2011-01-25 07:45:54.000000000 +0100
  44333. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-11.c 2016-08-08 20:37:53.546581373 +0200
  44334. @@ -1,4 +1,6 @@
  44335. /* { dg-require-effective-target size32plus } */
  44336. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44337. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44338. #define DEBUG 0
  44339. #if DEBUG
  44340. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-15.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-15.c
  44341. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-15.c 2015-07-25 22:33:33.000000000 +0200
  44342. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-15.c 2016-08-08 20:37:53.546581373 +0200
  44343. @@ -1,4 +1,6 @@
  44344. /* { dg-require-effective-target size32plus } */
  44345. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44346. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44347. #define DEBUG 0
  44348. #if DEBUG
  44349. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-1.c
  44350. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-1.c 2011-01-25 07:45:54.000000000 +0100
  44351. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-1.c 2016-08-08 20:37:53.546581373 +0200
  44352. @@ -1,4 +1,6 @@
  44353. /* { dg-require-effective-target size32plus } */
  44354. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44355. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44356. /* Formerly known as ltrans-1.c */
  44357. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-2.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-2.c
  44358. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-2.c 2010-02-07 20:49:26.000000000 +0100
  44359. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-2.c 2016-08-08 20:37:53.546581373 +0200
  44360. @@ -1,4 +1,6 @@
  44361. /* { dg-require-effective-target size32plus } */
  44362. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44363. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44364. /* Formerly known as ltrans-2.c */
  44365. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-3.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-3.c
  44366. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-3.c 2011-07-26 20:48:08.000000000 +0200
  44367. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-3.c 2016-08-08 20:37:53.546581373 +0200
  44368. @@ -1,4 +1,6 @@
  44369. /* { dg-require-effective-target size32plus } */
  44370. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44371. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44372. /* Formerly known as ltrans-3.c */
  44373. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-4.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-4.c
  44374. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-4.c 2010-02-07 20:49:26.000000000 +0100
  44375. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-4.c 2016-08-08 20:37:53.546581373 +0200
  44376. @@ -1,4 +1,6 @@
  44377. /* { dg-require-effective-target size32plus } */
  44378. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44379. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44380. /* Formerly known as ltrans-4.c */
  44381. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-5.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-5.c
  44382. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-5.c 2010-02-07 20:49:26.000000000 +0100
  44383. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-5.c 2016-08-08 20:37:53.546581373 +0200
  44384. @@ -1,4 +1,5 @@
  44385. /* { dg-require-effective-target size32plus } */
  44386. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44387. /* Formerly known as ltrans-5.c */
  44388. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-mvt.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-mvt.c
  44389. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/interchange-mvt.c 2015-07-25 22:33:33.000000000 +0200
  44390. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/interchange-mvt.c 2016-08-08 20:37:53.546581373 +0200
  44391. @@ -1,4 +1,6 @@
  44392. /* { dg-require-effective-target size32plus } */
  44393. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44394. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44395. #define DEBUG 0
  44396. #if DEBUG
  44397. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/pr46185.c gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/pr46185.c
  44398. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/graphite/pr46185.c 2010-12-07 02:29:10.000000000 +0100
  44399. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/graphite/pr46185.c 2016-08-08 20:37:53.546581373 +0200
  44400. @@ -1,5 +1,7 @@
  44401. /* { dg-do run } */
  44402. +/* { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } } */
  44403. /* { dg-options "-O2 -floop-interchange -ffast-math -fno-ipa-cp" } */
  44404. +/* { dg-additional-options "-mcmodel=large" { target nds32*-*-elf* } } */
  44405. #define DEBUG 0
  44406. #if DEBUG
  44407. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri1.c gcc-4.9.4/gcc/testsuite/gcc.dg/initpri1.c
  44408. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri1.c 2007-02-25 19:47:05.000000000 +0100
  44409. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/initpri1.c 2016-08-08 20:37:53.546581373 +0200
  44410. @@ -1,4 +1,5 @@
  44411. /* { dg-do run { target init_priority } } */
  44412. +/* { dg-options "-mctor-dtor" { target { nds32*-*-* } } } */
  44413. extern void abort ();
  44414. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri2.c gcc-4.9.4/gcc/testsuite/gcc.dg/initpri2.c
  44415. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri2.c 2007-02-26 16:53:51.000000000 +0100
  44416. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/initpri2.c 2016-08-08 20:37:53.546581373 +0200
  44417. @@ -1,4 +1,5 @@
  44418. /* { dg-do compile { target init_priority } } */
  44419. +/* { dg-options "-mctor-dtor" { target { nds32*-*-* } } } */
  44420. /* Priorities must be in the range [0, 65535]. */
  44421. void c1()
  44422. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri3.c gcc-4.9.4/gcc/testsuite/gcc.dg/initpri3.c
  44423. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/initpri3.c 2011-01-10 22:54:33.000000000 +0100
  44424. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/initpri3.c 2016-08-08 20:37:53.550581527 +0200
  44425. @@ -1,6 +1,7 @@
  44426. /* { dg-do run { target init_priority } } */
  44427. /* { dg-require-effective-target lto } */
  44428. /* { dg-options "-flto -O3" } */
  44429. +/* { dg-options "-flto -O3 -mctor-dtor" { target { nds32*-*-* } } } */
  44430. extern void abort ();
  44431. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
  44432. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c 2010-09-10 01:38:23.000000000 +0200
  44433. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c 2016-08-08 20:37:53.550581527 +0200
  44434. @@ -1,5 +1,6 @@
  44435. /* { dg-do run } */
  44436. /* { dg-options "-O2 -fipa-sra -fdump-tree-eipa_sra-details" } */
  44437. +/* { dg-additional-options "-u_printf_float -u_scanf_float" { target nds32*-*-* } } */
  44438. struct bovid
  44439. {
  44440. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/lower-subreg-1.c
  44441. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/lower-subreg-1.c 2013-08-09 22:48:00.000000000 +0200
  44442. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/lower-subreg-1.c 2016-08-08 20:37:53.550581527 +0200
  44443. @@ -1,4 +1,4 @@
  44444. -/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */
  44445. +/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* nds32*-*-* } } } } } */
  44446. /* { dg-options "-O -fdump-rtl-subreg1" } */
  44447. /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
  44448. /* { dg-require-effective-target ilp32 } */
  44449. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/lto/pr61526_0.c gcc-4.9.4/gcc/testsuite/gcc.dg/lto/pr61526_0.c
  44450. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/lto/pr61526_0.c 2014-06-17 11:08:02.000000000 +0200
  44451. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/lto/pr61526_0.c 2016-08-08 20:37:53.550581527 +0200
  44452. @@ -1,6 +1,7 @@
  44453. /* { dg-lto-do link } */
  44454. /* { dg-lto-options { { -fPIC -flto -flto-partition=1to1 } } } */
  44455. /* { dg-extra-ld-options { -shared } } */
  44456. +/* { dg-require-effective-target fpic } */
  44457. static void *master;
  44458. void *foo () { return master; }
  44459. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/pr28796-2.c gcc-4.9.4/gcc/testsuite/gcc.dg/pr28796-2.c
  44460. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/pr28796-2.c 2012-03-14 18:08:03.000000000 +0100
  44461. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/pr28796-2.c 2016-08-08 20:37:53.550581527 +0200
  44462. @@ -2,6 +2,7 @@
  44463. /* { dg-options "-O2 -funsafe-math-optimizations -fno-finite-math-only -DUNSAFE" } */
  44464. /* { dg-add-options ieee } */
  44465. /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
  44466. +/* { dg-skip-if "No Denormmalized support" { nds32_ext_fpu } } */
  44467. #include "tg-tests.h"
  44468. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/sibcall-3.c gcc-4.9.4/gcc/testsuite/gcc.dg/sibcall-3.c
  44469. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/sibcall-3.c 2013-12-03 11:58:05.000000000 +0100
  44470. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/sibcall-3.c 2016-08-08 20:37:53.550581527 +0200
  44471. @@ -5,7 +5,7 @@
  44472. Copyright (C) 2002 Free Software Foundation Inc.
  44473. Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
  44474. -/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  44475. +/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  44476. /* -mlongcall disables sibcall patterns. */
  44477. /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
  44478. /* { dg-options "-O2 -foptimize-sibling-calls" } */
  44479. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/sibcall-4.c gcc-4.9.4/gcc/testsuite/gcc.dg/sibcall-4.c
  44480. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/sibcall-4.c 2013-12-03 11:58:05.000000000 +0100
  44481. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/sibcall-4.c 2016-08-08 20:37:53.550581527 +0200
  44482. @@ -5,7 +5,7 @@
  44483. Copyright (C) 2002 Free Software Foundation Inc.
  44484. Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
  44485. -/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  44486. +/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  44487. /* -mlongcall disables sibcall patterns. */
  44488. /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
  44489. /* { dg-options "-O2 -foptimize-sibling-calls" } */
  44490. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/stack-usage-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/stack-usage-1.c
  44491. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/stack-usage-1.c 2013-12-31 08:05:35.000000000 +0100
  44492. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/stack-usage-1.c 2016-08-08 20:37:53.550581527 +0200
  44493. @@ -1,5 +1,6 @@
  44494. /* { dg-do compile } */
  44495. /* { dg-options "-fstack-usage" } */
  44496. +/* { dg-options "-fstack-usage -fno-omit-frame-pointer" { target { nds32*-*-* } } } */
  44497. /* This is aimed at testing basic support for -fstack-usage in the back-ends.
  44498. See the SPARC back-end for example (grep flag_stack_usage_info in sparc.c).
  44499. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/torture/type-generic-1.c gcc-4.9.4/gcc/testsuite/gcc.dg/torture/type-generic-1.c
  44500. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/torture/type-generic-1.c 2011-07-16 14:07:17.000000000 +0200
  44501. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/torture/type-generic-1.c 2016-08-08 20:37:53.550581527 +0200
  44502. @@ -3,6 +3,7 @@
  44503. /* { dg-do run } */
  44504. /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
  44505. +/* { dg-skip-if "No Denormmalized support" { nds32_ext_fpu } } */
  44506. /* { dg-options "-DUNSAFE" { target tic6x*-*-* } } */
  44507. /* { dg-add-options ieee } */
  44508. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.dg/tree-ssa/vrp88.c gcc-4.9.4/gcc/testsuite/gcc.dg/tree-ssa/vrp88.c
  44509. --- gcc-4.9.4.orig/gcc/testsuite/gcc.dg/tree-ssa/vrp88.c 2013-04-29 14:52:17.000000000 +0200
  44510. +++ gcc-4.9.4/gcc/testsuite/gcc.dg/tree-ssa/vrp88.c 2016-08-08 20:37:53.550581527 +0200
  44511. @@ -33,7 +33,7 @@
  44512. }
  44513. /* Verify that VRP simplified an "if" statement. */
  44514. -/* { dg-final { scan-tree-dump "Folded into: if.*" "vrp1"} } */
  44515. +/* { dg-final { scan-tree-dump "Folded into: if.*" "vrp1" { xfail *-*-* } } } */
  44516. /* { dg-final { cleanup-tree-dump "vrp1" } } */
  44517. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/basic-main.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/basic-main.c
  44518. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/basic-main.c 2013-12-03 11:58:05.000000000 +0100
  44519. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/basic-main.c 2016-08-08 20:37:53.550581527 +0200
  44520. @@ -1,9 +1,10 @@
  44521. /* This is a basic main function test program. */
  44522. -/* { dg-do run } */
  44523. -/* { dg-options "-O0" } */
  44524. +/* { dg-do run } */
  44525. +/* { dg-options "-O0" } */
  44526. -int main(void)
  44527. +int
  44528. +main (void)
  44529. {
  44530. return 0;
  44531. }
  44532. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-cctl.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-cctl.c
  44533. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-cctl.c 1970-01-01 01:00:00.000000000 +0100
  44534. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-cctl.c 2016-08-08 20:37:53.554581681 +0200
  44535. @@ -0,0 +1,29 @@
  44536. +/* Verify that we generate cache control instruction with builtin function. */
  44537. +
  44538. +/* { dg-do compile } */
  44539. +/* { dg-options "-O0" } */
  44540. +/* { dg-final { scan-assembler "L1D_VA_INVAL" } } */
  44541. +/* { dg-final { scan-assembler "L1D_VA_INVAL" } } */
  44542. +/* { dg-final { scan-assembler "L1D_INVALALL" } } */
  44543. +/* { dg-final { scan-assembler "L1D_IX_WWD" } } */
  44544. +/* { dg-final { scan-assembler "L1D_IX_RWD" } } */
  44545. +/* { dg-final { scan-assembler "PFM_CTL" } } */
  44546. +/* { dg-final { scan-assembler "PFM_CTL" } } */
  44547. +
  44548. +#include <nds32_intrinsic.h>
  44549. +
  44550. +void
  44551. +test (void)
  44552. +{
  44553. + unsigned int va = 0;
  44554. +
  44555. + __nds32__cctlva_lck (NDS32_CCTL_L1D_VA_FILLCK, &va);
  44556. + __nds32__cctlidx_wbinval (NDS32_CCTL_L1D_IX_WBINVAL, va);
  44557. + __nds32__cctlva_wbinval_alvl (NDS32_CCTL_L1D_VA_INVAL, &va);
  44558. + __nds32__cctlva_wbinval_one_lvl (NDS32_CCTL_L1D_VA_INVAL, &va);
  44559. + __nds32__cctl_l1d_invalall ();
  44560. + __nds32__cctlidx_write (NDS32_CCTL_L1D_IX_WWD, va, 1);
  44561. + __nds32__cctlidx_read (NDS32_CCTL_L1D_IX_RWD, 1);
  44562. + __nds32__mtusr (0, NDS32_USR_PFM_CTL);
  44563. + __nds32__mfusr (NDS32_USR_PFM_CTL);
  44564. +}
  44565. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-dpref.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-dpref.c
  44566. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-dpref.c 1970-01-01 01:00:00.000000000 +0100
  44567. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-dpref.c 2016-08-08 20:37:53.554581681 +0200
  44568. @@ -0,0 +1,24 @@
  44569. +/* Verify that we generate data prefetch instruction with builtin function. */
  44570. +
  44571. +/* { dg-do compile } */
  44572. +/* { dg-options "-O0" } */
  44573. +/* { dg-final { scan-assembler "dpref\\tSRD" } } */
  44574. +/* { dg-final { scan-assembler "dpref\\tSRD" } } */
  44575. +/* { dg-final { scan-assembler "dpref\\tSRD" } } */
  44576. +/* { dg-final { scan-assembler "dpref\\tSRD" } } */
  44577. +
  44578. +#include <nds32_intrinsic.h>
  44579. +
  44580. +void
  44581. +test (void)
  44582. +{
  44583. + unsigned char dpref_q = 0;
  44584. + unsigned short dpref_h = 0;
  44585. + unsigned int dpref_w = 0;
  44586. + unsigned long long dpref_dw = 0;
  44587. +
  44588. + __nds32__dpref_qw (&dpref_q, 0, NDS32_DPREF_SRD);
  44589. + __nds32__dpref_hw (&dpref_h, 0, NDS32_DPREF_SRD);
  44590. + __nds32__dpref_w (&dpref_w, 0, NDS32_DPREF_SRD);
  44591. + __nds32__dpref_dw (&dpref_dw, 0, NDS32_DPREF_SRD);
  44592. +}
  44593. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyd.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyd.c
  44594. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyd.c 1970-01-01 01:00:00.000000000 +0100
  44595. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyd.c 2016-08-08 20:37:53.554581681 +0200
  44596. @@ -0,0 +1,21 @@
  44597. +/* This is a test program for fcpysd instruction. */
  44598. +
  44599. +/* { dg-do run } */
  44600. +/* { dg-options "-O1" } */
  44601. +/* { dg-require-effective-target nds32_ext_fpu_dp } */
  44602. +
  44603. +#include <nds32_intrinsic.h>
  44604. +#include <stdlib.h>
  44605. +
  44606. +int
  44607. +main ()
  44608. +{
  44609. + double da = -1.5;
  44610. + double db = 1.3;
  44611. + double dr = __nds32__fcpysd (da, db);
  44612. +
  44613. + if (dr != 1.5)
  44614. + abort ();
  44615. + else
  44616. + exit (0);
  44617. +}
  44618. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpynd.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpynd.c
  44619. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpynd.c 1970-01-01 01:00:00.000000000 +0100
  44620. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpynd.c 2016-08-08 20:37:53.554581681 +0200
  44621. @@ -0,0 +1,21 @@
  44622. +/* This is a test program for fcpynsd instruction. */
  44623. +
  44624. +/* { dg-do run } */
  44625. +/* { dg-options "-O1" } */
  44626. +/* { dg-require-effective-target nds32_ext_fpu_dp } */
  44627. +
  44628. +#include <nds32_intrinsic.h>
  44629. +#include <stdlib.h>
  44630. +
  44631. +int
  44632. +main ()
  44633. +{
  44634. + double da = -1.5;
  44635. + double db = -1.3;
  44636. + double dr = __nds32__fcpynsd (da, db);
  44637. +
  44638. + if (dr != 1.5)
  44639. + abort ();
  44640. + else
  44641. + exit (0);
  44642. +}
  44643. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyns.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyns.c
  44644. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyns.c 1970-01-01 01:00:00.000000000 +0100
  44645. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpyns.c 2016-08-08 20:37:53.554581681 +0200
  44646. @@ -0,0 +1,21 @@
  44647. +/* This is a test program for fcpynss instruction. */
  44648. +
  44649. +/* { dg-do run } */
  44650. +/* { dg-options "-O1" } */
  44651. +/* { dg-require-effective-target nds32_ext_fpu_sp } */
  44652. +
  44653. +#include <nds32_intrinsic.h>
  44654. +#include <stdlib.h>
  44655. +
  44656. +int
  44657. +main ()
  44658. +{
  44659. + float a = -1.5;
  44660. + float b = -1.3;
  44661. + float r = __nds32__fcpynss (a, b);
  44662. +
  44663. + if (r != 1.5)
  44664. + abort ();
  44665. + else
  44666. + exit (0);
  44667. +}
  44668. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpys.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpys.c
  44669. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpys.c 1970-01-01 01:00:00.000000000 +0100
  44670. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fcpys.c 2016-08-08 20:37:53.554581681 +0200
  44671. @@ -0,0 +1,21 @@
  44672. +/* This is a test program for fcpyss instruction. */
  44673. +
  44674. +/* { dg-do run } */
  44675. +/* { dg-options "-O1" } */
  44676. +/* { dg-require-effective-target nds32_ext_fpu_sp } */
  44677. +
  44678. +#include <nds32_intrinsic.h>
  44679. +#include <stdlib.h>
  44680. +
  44681. +int
  44682. +main ()
  44683. +{
  44684. + float a = -1.5;
  44685. + float b = 1.3;
  44686. + float r = __nds32__fcpyss (a, b);
  44687. +
  44688. + if (r != 1.5)
  44689. + abort ();
  44690. + else
  44691. + exit (0);
  44692. +}
  44693. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fmfcfg.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fmfcfg.c
  44694. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fmfcfg.c 1970-01-01 01:00:00.000000000 +0100
  44695. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fmfcfg.c 2016-08-08 20:37:53.554581681 +0200
  44696. @@ -0,0 +1,23 @@
  44697. +/* This is a test program for fmfcfg instruction. */
  44698. +
  44699. +/* { dg-do run } */
  44700. +/* { dg-options "-O1" } */
  44701. +/* { dg-require-effective-target nds32_ext_fpu } */
  44702. +
  44703. +#include <nds32_intrinsic.h>
  44704. +#include <stdlib.h>
  44705. +
  44706. +int
  44707. +main ()
  44708. +{
  44709. + unsigned int intrinsic_fmfcfg = -1;
  44710. + unsigned int inline_assemble_fmfcfg = -2;
  44711. +
  44712. + intrinsic_fmfcfg = __nds32__fmfcfg ();
  44713. + __asm volatile ("fmfcfg %0" : "=r" (inline_assemble_fmfcfg));
  44714. +
  44715. + if (intrinsic_fmfcfg == inline_assemble_fmfcfg)
  44716. + exit (0);
  44717. + else
  44718. + abort ();
  44719. +}
  44720. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fpcsr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fpcsr.c
  44721. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-fpu-fpcsr.c 1970-01-01 01:00:00.000000000 +0100
  44722. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-fpu-fpcsr.c 2016-08-08 20:37:53.554581681 +0200
  44723. @@ -0,0 +1,28 @@
  44724. +/* This is a test program for fmtcsr/fmfcsr instruction. */
  44725. +
  44726. +/* { dg-do run } */
  44727. +/* { dg-options "-O1" } */
  44728. +/* { dg-require-effective-target nds32_ext_fpu } */
  44729. +
  44730. +#include <nds32_intrinsic.h>
  44731. +#include <stdlib.h>
  44732. +
  44733. +int
  44734. +main ()
  44735. +{
  44736. + unsigned int fpcsr;
  44737. +
  44738. + /* write fpcsr */
  44739. + fpcsr = 3;
  44740. + __nds32__fmtcsr (fpcsr);
  44741. +
  44742. + /* read fpcsr */
  44743. + fpcsr = 0;
  44744. + fpcsr = __nds32__fmfcsr ();
  44745. + fpcsr = fpcsr & 0x00001fff;
  44746. +
  44747. + if (fpcsr == 3)
  44748. + exit (0);
  44749. + else
  44750. + abort ();
  44751. +}
  44752. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-get-lp.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-get-lp.c
  44753. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-get-lp.c 1970-01-01 01:00:00.000000000 +0100
  44754. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-get-lp.c 2016-08-08 20:37:53.554581681 +0200
  44755. @@ -0,0 +1,22 @@
  44756. +/* Verify the return address with builtin function. */
  44757. +
  44758. +/* { dg-do run } */
  44759. +/* { dg-options "-O1" } */
  44760. +
  44761. +#include <nds32_intrinsic.h>
  44762. +#include <stdlib.h>
  44763. +
  44764. +int main()
  44765. +{
  44766. + unsigned int intrinsic_lp = -1;
  44767. + unsigned int inline_assemble_lp = -2;
  44768. +
  44769. + intrinsic_lp = __nds32__return_address ();
  44770. +
  44771. + __asm volatile ("mov55 %0, $lp" : "=r" (inline_assemble_lp));
  44772. +
  44773. + if (intrinsic_lp != inline_assemble_lp)
  44774. + abort ();
  44775. + else
  44776. + exit (0);
  44777. +}
  44778. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-isb.c
  44779. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-isb.c 2013-12-03 11:58:05.000000000 +0100
  44780. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-isb.c 2016-08-08 20:37:53.554581681 +0200
  44781. @@ -1,11 +1,13 @@
  44782. /* Verify that we generate isb instruction with builtin function. */
  44783. -/* { dg-do compile } */
  44784. -/* { dg-options "-O0" } */
  44785. -/* { dg-final { scan-assembler "\\tisb" } } */
  44786. +/* { dg-do compile } */
  44787. +/* { dg-options "-O0" } */
  44788. +/* { dg-final { scan-assembler "\\tisb" } } */
  44789. +
  44790. +#include <nds32_intrinsic.h>
  44791. void
  44792. test (void)
  44793. {
  44794. - __builtin_nds32_isb ();
  44795. + __nds32__isb ();
  44796. }
  44797. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-isync.c
  44798. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-isync.c 2013-12-03 11:58:05.000000000 +0100
  44799. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-isync.c 2016-08-08 20:37:53.554581681 +0200
  44800. @@ -1,12 +1,14 @@
  44801. /* Verify that we generate isync instruction with builtin function. */
  44802. -/* { dg-do compile } */
  44803. -/* { dg-options "-O0" } */
  44804. -/* { dg-final { scan-assembler "\\tisync" } } */
  44805. +/* { dg-do compile } */
  44806. +/* { dg-options "-O0" } */
  44807. +/* { dg-final { scan-assembler "\\tisync" } } */
  44808. +
  44809. +#include <nds32_intrinsic.h>
  44810. void
  44811. test (void)
  44812. {
  44813. int *addr = (int *) 0x53000000;
  44814. - __builtin_nds32_isync (addr);
  44815. + __nds32__isync (addr);
  44816. }
  44817. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-load-store.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-load-store.c
  44818. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-load-store.c 1970-01-01 01:00:00.000000000 +0100
  44819. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-load-store.c 2016-08-08 20:37:53.554581681 +0200
  44820. @@ -0,0 +1,25 @@
  44821. +/* Verify that we generate llw/lwup/scw/swup instruction
  44822. + with builtin function. */
  44823. +
  44824. +/* { dg-do compile } */
  44825. +/* { dg-require-effective-target nds32_no_v3m } */
  44826. +/* { dg-options "-O0" } */
  44827. +/* { dg-final { scan-assembler "\\tllw" } } */
  44828. +/* { dg-final { scan-assembler "\\tlwup" } } */
  44829. +/* { dg-final { scan-assembler "\\tscw" } } */
  44830. +/* { dg-final { scan-assembler "\\tswup" } } */
  44831. +
  44832. +#include <nds32_intrinsic.h>
  44833. +
  44834. +void
  44835. +test (void)
  44836. +{
  44837. + int a = 0;
  44838. + int b = 0;
  44839. + unsigned int cc = 0;
  44840. +
  44841. + __nds32__llw (&a);
  44842. + cc = __nds32__lwup (&a);
  44843. + __nds32__scw (&a, b);
  44844. + __nds32__swup (&a, b);
  44845. +}
  44846. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-lto.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-lto.c
  44847. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-lto.c 1970-01-01 01:00:00.000000000 +0100
  44848. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-lto.c 2016-08-08 20:37:53.554581681 +0200
  44849. @@ -0,0 +1,28 @@
  44850. +/* Verify that we use -flto option to generate instructions
  44851. + with builtin function. */
  44852. +
  44853. +/* { dg-do compile } */
  44854. +/* { dg-options "-O0 -flto" } */
  44855. +/* { dg-final { scan-assembler "\\tdsb" } } */
  44856. +/* { dg-final { scan-assembler "\\tisb" } } */
  44857. +/* { dg-final { scan-assembler "\\tmsync\\tall" } } */
  44858. +/* { dg-final { scan-assembler "\\tmsync\\tstore" } } */
  44859. +/* { dg-final { scan-assembler "\\tnop" } } */
  44860. +/* { dg-final { scan-assembler "\\tstandby\\tno_wake_grant" } } */
  44861. +/* { dg-final { scan-assembler "\\tstandby\\twake_grant" } } */
  44862. +/* { dg-final { scan-assembler "\\tstandby\\twait_done" } } */
  44863. +
  44864. +#include <nds32_intrinsic.h>
  44865. +
  44866. +void
  44867. +test (void)
  44868. +{
  44869. + __nds32__dsb ();
  44870. + __nds32__isb ();
  44871. + __nds32__msync_all ();
  44872. + __nds32__msync_store ();
  44873. + __nds32__nop ();
  44874. + __nds32__standby_no_wake_grant ();
  44875. + __nds32__standby_wake_grant ();
  44876. + __nds32__standby_wait_done ();
  44877. +}
  44878. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-machine-sva.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-machine-sva.c
  44879. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-machine-sva.c 1970-01-01 01:00:00.000000000 +0100
  44880. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-machine-sva.c 2016-08-08 20:37:53.554581681 +0200
  44881. @@ -0,0 +1,16 @@
  44882. +/* Verify that we generate sva instruction with builtin function. */
  44883. +
  44884. +/* { dg-do compile } */
  44885. +/* { dg-options "-O0" } */
  44886. +/* { dg-final { scan-assembler "\\tsva" } } */
  44887. +
  44888. +#include <nds32_intrinsic.h>
  44889. +
  44890. +void
  44891. +test (void)
  44892. +{
  44893. + int a, b;
  44894. + char c;
  44895. +
  44896. + c = __nds32__sva (a, b);
  44897. +}
  44898. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-machine-svs.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-machine-svs.c
  44899. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-machine-svs.c 1970-01-01 01:00:00.000000000 +0100
  44900. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-machine-svs.c 2016-08-08 20:37:53.554581681 +0200
  44901. @@ -0,0 +1,16 @@
  44902. +/* Verify that we generate svs instruction with builtin function. */
  44903. +
  44904. +/* { dg-do compile } */
  44905. +/* { dg-options "-O0" } */
  44906. +/* { dg-final { scan-assembler "\\tsvs" } } */
  44907. +
  44908. +#include <nds32_intrinsic.h>
  44909. +
  44910. +void
  44911. +test (void)
  44912. +{
  44913. + int a, b;
  44914. + char c;
  44915. +
  44916. + c = __nds32__svs (a, b);
  44917. +}
  44918. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c
  44919. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 2013-12-03 11:58:05.000000000 +0100
  44920. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c 2016-08-08 20:37:53.554581681 +0200
  44921. @@ -1,9 +1,9 @@
  44922. /* Verify that we generate mfsr/mtsr instruction with builtin function. */
  44923. -/* { dg-do compile } */
  44924. -/* { dg-options "-O0" } */
  44925. -/* { dg-final { scan-assembler "\\tmfsr" } } */
  44926. -/* { dg-final { scan-assembler "\\tmtsr" } } */
  44927. +/* { dg-do compile } */
  44928. +/* { dg-options "-O0" } */
  44929. +/* { dg-final { scan-assembler "\\tmfsr" } } */
  44930. +/* { dg-final { scan-assembler "\\tmtsr" } } */
  44931. #include <nds32_intrinsic.h>
  44932. @@ -12,6 +12,6 @@
  44933. {
  44934. int ipsw_value;
  44935. - ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__);
  44936. - __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__);
  44937. + ipsw_value = __nds32__mfsr (__NDS32_REG_IPSW__);
  44938. + __nds32__mtsr (ipsw_value, __NDS32_REG_IPSW__);
  44939. }
  44940. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c
  44941. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 2013-12-03 11:58:05.000000000 +0100
  44942. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c 2016-08-08 20:37:53.554581681 +0200
  44943. @@ -1,9 +1,9 @@
  44944. /* Verify that we generate mfusr/mtusr instruction with builtin function. */
  44945. -/* { dg-do compile } */
  44946. -/* { dg-options "-O0" } */
  44947. -/* { dg-final { scan-assembler "\\tmfusr" } } */
  44948. -/* { dg-final { scan-assembler "\\tmtusr" } } */
  44949. +/* { dg-do compile } */
  44950. +/* { dg-options "-O0" } */
  44951. +/* { dg-final { scan-assembler "\\tmfusr" } } */
  44952. +/* { dg-final { scan-assembler "\\tmtusr" } } */
  44953. #include <nds32_intrinsic.h>
  44954. @@ -12,6 +12,6 @@
  44955. {
  44956. int itype_value;
  44957. - itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__);
  44958. - __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__);
  44959. + itype_value = __nds32__mfusr (__NDS32_REG_ITYPE__);
  44960. + __nds32__mtusr (itype_value, __NDS32_REG_ITYPE__);
  44961. }
  44962. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-misc.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-misc.c
  44963. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-misc.c 1970-01-01 01:00:00.000000000 +0100
  44964. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-misc.c 2016-08-08 20:37:53.554581681 +0200
  44965. @@ -0,0 +1,39 @@
  44966. +/* Verify that we generate other instructions with builtin function. */
  44967. +
  44968. +/* { dg-do compile } */
  44969. +/* { dg-options "-O0" } */
  44970. +/* { dg-final { scan-assembler "\\tbreak" } } */
  44971. +/* { dg-final { scan-assembler "\\tdsb" } } */
  44972. +/* { dg-final { scan-assembler "\\tisb" } } */
  44973. +/* { dg-final { scan-assembler "\\tisync" } } */
  44974. +/* { dg-final { scan-assembler "\\tmsync\\tall" } } */
  44975. +/* { dg-final { scan-assembler "\\tmsync\\tstore" } } */
  44976. +/* { dg-final { scan-assembler "\\tnop" } } */
  44977. +/* { dg-final { scan-assembler "\\tstandby\\tno_wake_grant" } } */
  44978. +/* { dg-final { scan-assembler "\\tstandby\\twake_grant" } } */
  44979. +/* { dg-final { scan-assembler "\\tstandby\\twait_done" } } */
  44980. +/* { dg-final { scan-assembler "\\tteqz" } } */
  44981. +/* { dg-final { scan-assembler "\\ttnez" } } */
  44982. +/* { dg-final { scan-assembler "\\ttrap" } } */
  44983. +
  44984. +#include <nds32_intrinsic.h>
  44985. +
  44986. +void
  44987. +test (void)
  44988. +{
  44989. + int a = 0;
  44990. +
  44991. + __nds32__break (2);
  44992. + __nds32__dsb ();
  44993. + __nds32__isb ();
  44994. + __nds32__isync (&a);
  44995. + __nds32__msync_all ();
  44996. + __nds32__msync_store ();
  44997. + __nds32__nop ();
  44998. + __nds32__standby_no_wake_grant ();
  44999. + __nds32__standby_wake_grant ();
  45000. + __nds32__standby_wait_done ();
  45001. + __nds32__teqz (a, 2);
  45002. + __nds32__tnez (a, 2);
  45003. + __nds32__trap (2);
  45004. +}
  45005. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mtsr-dsb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mtsr-dsb.c
  45006. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mtsr-dsb.c 1970-01-01 01:00:00.000000000 +0100
  45007. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mtsr-dsb.c 2016-08-08 20:37:53.554581681 +0200
  45008. @@ -0,0 +1,14 @@
  45009. +/* Verify that we generate mtsr and dsb instruction with builtin function. */
  45010. +
  45011. +/* { dg-do compile } */
  45012. +/* { dg-options "-O0" } */
  45013. +/* { dg-final { scan-assembler "\\tmtsr" } } */
  45014. +/* { dg-final { scan-assembler "\\tdsb" } } */
  45015. +
  45016. +#include <nds32_intrinsic.h>
  45017. +
  45018. +void
  45019. +main (void)
  45020. +{
  45021. + __nds32__mtsr_dsb (1, NDS32_SR_ILMB);
  45022. +}
  45023. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mtsr-isb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mtsr-isb.c
  45024. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-mtsr-isb.c 1970-01-01 01:00:00.000000000 +0100
  45025. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-mtsr-isb.c 2016-08-08 20:37:53.554581681 +0200
  45026. @@ -0,0 +1,14 @@
  45027. +/* Verify that we generate mtsr and isb instruction with builtin function. */
  45028. +
  45029. +/* { dg-do compile } */
  45030. +/* { dg-options "-O0" } */
  45031. +/* { dg-final { scan-assembler "\\tmtsr" } } */
  45032. +/* { dg-final { scan-assembler "\\tisb" } } */
  45033. +
  45034. +#include <nds32_intrinsic.h>
  45035. +
  45036. +void
  45037. +main (void)
  45038. +{
  45039. + __nds32__mtsr_isb (1, NDS32_SR_ILMB);
  45040. +}
  45041. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-abs.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-abs.c
  45042. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-abs.c 1970-01-01 01:00:00.000000000 +0100
  45043. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-abs.c 2016-08-08 20:37:53.550581527 +0200
  45044. @@ -0,0 +1,20 @@
  45045. +/* This is a test program for abs instruction. */
  45046. +
  45047. +/* { dg-do run } */
  45048. +/* { dg-options "-O1" } */
  45049. +/* { dg-require-effective-target nds32_ext_perf } */
  45050. +
  45051. +#include <nds32_intrinsic.h>
  45052. +#include <stdlib.h>
  45053. +
  45054. +int
  45055. +main ()
  45056. +{
  45057. + int a = -4;
  45058. + int abs = __nds32__abs (a);
  45059. +
  45060. + if (abs != 4)
  45061. + abort ();
  45062. + else
  45063. + exit (0);
  45064. +}
  45065. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-ave.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-ave.c
  45066. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-ave.c 1970-01-01 01:00:00.000000000 +0100
  45067. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-ave.c 2016-08-08 20:37:53.550581527 +0200
  45068. @@ -0,0 +1,21 @@
  45069. +/* This is a test program for ave instruction. */
  45070. +
  45071. +/* { dg-do run } */
  45072. +/* { dg-options "-O1" } */
  45073. +/* { dg-require-effective-target nds32_ext_perf } */
  45074. +
  45075. +#include <nds32_intrinsic.h>
  45076. +#include <stdlib.h>
  45077. +
  45078. +int
  45079. +main ()
  45080. +{
  45081. + int a = 4;
  45082. + int b = 2;
  45083. + int ave = __nds32__ave (a, b);
  45084. +
  45085. + if (ave != 3)
  45086. + abort ();
  45087. + else
  45088. + exit (0);
  45089. +}
  45090. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-bclr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-bclr.c
  45091. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-bclr.c 1970-01-01 01:00:00.000000000 +0100
  45092. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-bclr.c 2016-08-08 20:37:53.550581527 +0200
  45093. @@ -0,0 +1,20 @@
  45094. +/* This is a test program for bclr instruction. */
  45095. +
  45096. +/* { dg-do run } */
  45097. +/* { dg-options "-O1" } */
  45098. +/* { dg-require-effective-target nds32_ext_perf } */
  45099. +
  45100. +#include <nds32_intrinsic.h>
  45101. +#include <stdlib.h>
  45102. +
  45103. +int
  45104. +main ()
  45105. +{
  45106. + int a = 1;
  45107. + int c = __nds32__bclr (a, 0);
  45108. +
  45109. + if (c != 0)
  45110. + abort ();
  45111. + else
  45112. + exit (0);
  45113. +}
  45114. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-bset.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-bset.c
  45115. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-bset.c 1970-01-01 01:00:00.000000000 +0100
  45116. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-bset.c 2016-08-08 20:37:53.550581527 +0200
  45117. @@ -0,0 +1,20 @@
  45118. +/* This is a test program for bset instruction. */
  45119. +
  45120. +/* { dg-do run } */
  45121. +/* { dg-options "-O1" } */
  45122. +/* { dg-require-effective-target nds32_ext_perf } */
  45123. +
  45124. +#include <nds32_intrinsic.h>
  45125. +#include <stdlib.h>
  45126. +
  45127. +int
  45128. +main ()
  45129. +{
  45130. + int c = 0;
  45131. + c = __nds32__bset (c, 0);
  45132. +
  45133. + if (c != 1)
  45134. + abort ();
  45135. + else
  45136. + exit (0);
  45137. +}
  45138. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-btgl.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-btgl.c
  45139. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-btgl.c 1970-01-01 01:00:00.000000000 +0100
  45140. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-btgl.c 2016-08-08 20:37:53.550581527 +0200
  45141. @@ -0,0 +1,20 @@
  45142. +/* This is a test program for btgl instruction. */
  45143. +
  45144. +/* { dg-do run } */
  45145. +/* { dg-options "-O1" } */
  45146. +/* { dg-require-effective-target nds32_ext_perf } */
  45147. +
  45148. +#include <nds32_intrinsic.h>
  45149. +#include <stdlib.h>
  45150. +
  45151. +int
  45152. +main ()
  45153. +{
  45154. + int a = 1;
  45155. + int c = __nds32__btgl (1, 0);
  45156. +
  45157. + if (c != 0)
  45158. + abort ();
  45159. + else
  45160. + exit (0);
  45161. +}
  45162. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-btst.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-btst.c
  45163. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-btst.c 1970-01-01 01:00:00.000000000 +0100
  45164. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-btst.c 2016-08-08 20:37:53.550581527 +0200
  45165. @@ -0,0 +1,20 @@
  45166. +/* This is a test program for btst instruction. */
  45167. +
  45168. +/* { dg-do run } */
  45169. +/* { dg-options "-O1" } */
  45170. +/* { dg-require-effective-target nds32_ext_perf } */
  45171. +
  45172. +#include <nds32_intrinsic.h>
  45173. +#include <stdlib.h>
  45174. +
  45175. +int
  45176. +main ()
  45177. +{
  45178. + int c = 1;
  45179. + c = __nds32__btst (c, 0);
  45180. +
  45181. + if (c != 1)
  45182. + abort ();
  45183. + else
  45184. + exit (0);
  45185. +}
  45186. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clip.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clip.c
  45187. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clip.c 1970-01-01 01:00:00.000000000 +0100
  45188. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clip.c 2016-08-08 20:37:53.550581527 +0200
  45189. @@ -0,0 +1,20 @@
  45190. +/* This is a test program for clip instruction. */
  45191. +
  45192. +/* { dg-do run } */
  45193. +/* { dg-options "-O1" } */
  45194. +/* { dg-require-effective-target nds32_ext_perf } */
  45195. +
  45196. +#include <nds32_intrinsic.h>
  45197. +#include <stdlib.h>
  45198. +
  45199. +int
  45200. +main ()
  45201. +{
  45202. + int c = 33;
  45203. + c = __nds32__clip (c, 5);
  45204. +
  45205. + if (c != 31)
  45206. + abort ();
  45207. + else
  45208. + exit (0);
  45209. +}
  45210. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clips.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clips.c
  45211. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clips.c 1970-01-01 01:00:00.000000000 +0100
  45212. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clips.c 2016-08-08 20:37:53.550581527 +0200
  45213. @@ -0,0 +1,20 @@
  45214. +/* This is a test program for clips instruction. */
  45215. +
  45216. +/* { dg-do run } */
  45217. +/* { dg-options "-O1" } */
  45218. +/* { dg-require-effective-target nds32_ext_perf } */
  45219. +
  45220. +#include <nds32_intrinsic.h>
  45221. +#include <stdlib.h>
  45222. +
  45223. +int
  45224. +main ()
  45225. +{
  45226. + int a = -33;
  45227. + int c = __nds32__clips (a, 5);
  45228. +
  45229. + if (c != -32)
  45230. + abort ();
  45231. + else
  45232. + exit (0);
  45233. +}
  45234. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clo.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clo.c
  45235. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clo.c 1970-01-01 01:00:00.000000000 +0100
  45236. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clo.c 2016-08-08 20:37:53.550581527 +0200
  45237. @@ -0,0 +1,20 @@
  45238. +/* This is a test program for clo instruction. */
  45239. +
  45240. +/* { dg-do run } */
  45241. +/* { dg-options "-O1" } */
  45242. +/* { dg-require-effective-target nds32_ext_perf } */
  45243. +
  45244. +#include <nds32_intrinsic.h>
  45245. +#include <stdlib.h>
  45246. +
  45247. +int
  45248. +main ()
  45249. +{
  45250. + int c = 0xFFFF0000;
  45251. + c = __nds32__clo (c);
  45252. +
  45253. + if (c != 16)
  45254. + abort ();
  45255. + else
  45256. + exit (0);
  45257. +}
  45258. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clz.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clz.c
  45259. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE1-clz.c 1970-01-01 01:00:00.000000000 +0100
  45260. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE1-clz.c 2016-08-08 20:37:53.550581527 +0200
  45261. @@ -0,0 +1,20 @@
  45262. +/* This is a test program for clz instruction. */
  45263. +
  45264. +/* { dg-do run } */
  45265. +/* { dg-options "-O1" } */
  45266. +/* { dg-require-effective-target nds32_ext_perf } */
  45267. +
  45268. +#include <nds32_intrinsic.h>
  45269. +#include <stdlib.h>
  45270. +
  45271. +int
  45272. +main ()
  45273. +{
  45274. + int c = 0x0000FFFF;
  45275. + c = __nds32__clz (c);
  45276. +
  45277. + if (c != 16)
  45278. + abort ();
  45279. + else
  45280. + exit (0);
  45281. +}
  45282. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-bse.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-bse.c
  45283. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-bse.c 1970-01-01 01:00:00.000000000 +0100
  45284. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-bse.c 2016-08-08 20:37:53.550581527 +0200
  45285. @@ -0,0 +1,28 @@
  45286. +/* This is a test program for bse instruction. */
  45287. +
  45288. +/* { dg-do run } */
  45289. +/* { dg-options "-O1" } */
  45290. +/* { dg-require-effective-target nds32_ext_perf2 } */
  45291. +
  45292. +#include <nds32_intrinsic.h>
  45293. +#include <stdlib.h>
  45294. +
  45295. +int
  45296. +main ()
  45297. +{
  45298. + unsigned int a = 0xF0F0F0F0;
  45299. + unsigned int b = 0x00000300;
  45300. + unsigned int r = 0;
  45301. +
  45302. + unsigned int verify_b = 0x00000300;
  45303. + unsigned int verify_r = 0;
  45304. +
  45305. + __nds32__bse (&r, a, &b);
  45306. + a = 0xF0F0F0F0;
  45307. + asm volatile ("bse %0, %2, %1": "+&r" (verify_r), "+&r" (verify_b) : "r" (a));
  45308. +
  45309. + if ((verify_b == b) && (verify_r == r))
  45310. + exit (0);
  45311. + else
  45312. + abort ();
  45313. +}
  45314. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-bsp.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-bsp.c
  45315. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-bsp.c 1970-01-01 01:00:00.000000000 +0100
  45316. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-bsp.c 2016-08-08 20:37:53.550581527 +0200
  45317. @@ -0,0 +1,26 @@
  45318. +/* This is a test program for bsp instruction. */
  45319. +
  45320. +/* { dg-do run } */
  45321. +/* { dg-options "-O1" } */
  45322. +/* { dg-require-effective-target nds32_ext_perf2 } */
  45323. +
  45324. +#include <nds32_intrinsic.h>
  45325. +#include <stdlib.h>
  45326. +
  45327. +int
  45328. +main ()
  45329. +{
  45330. + unsigned int a = 0x0000000F;
  45331. + unsigned int b = 0x00000300;
  45332. + unsigned int r = 0;
  45333. + unsigned int verify_b = 0x00000300;
  45334. + unsigned int verify_r = 0;
  45335. +
  45336. + __nds32__bsp (&r, a, &b);
  45337. + asm volatile ("bsp %0, %2, %1": "+&r" (verify_r), "+&r" (verify_b) : "r" (a));
  45338. +
  45339. + if ((verify_b == b) && (verify_r == r))
  45340. + exit (0);
  45341. + else
  45342. + abort ();
  45343. +}
  45344. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsada.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsada.c
  45345. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsada.c 1970-01-01 01:00:00.000000000 +0100
  45346. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsada.c 2016-08-08 20:37:53.550581527 +0200
  45347. @@ -0,0 +1,23 @@
  45348. +/* This is a test program for pbsada instruction. */
  45349. +
  45350. +/* { dg-do run } */
  45351. +/* { dg-options "-O1" } */
  45352. +/* { dg-require-effective-target nds32_ext_perf2 } */
  45353. +
  45354. +#include <nds32_intrinsic.h>
  45355. +#include <stdlib.h>
  45356. +
  45357. +int
  45358. +main ()
  45359. +{
  45360. + unsigned int a = 0x09070605;
  45361. + unsigned int b = 0x04020301;
  45362. + unsigned int r = 1;
  45363. +
  45364. + r = __nds32__pbsada(r, a, b);
  45365. +
  45366. + if (r != 18)
  45367. + abort ();
  45368. + else
  45369. + exit (0);
  45370. +}
  45371. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsad.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsad.c
  45372. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsad.c 1970-01-01 01:00:00.000000000 +0100
  45373. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-PE2-pbsad.c 2016-08-08 20:37:53.550581527 +0200
  45374. @@ -0,0 +1,21 @@
  45375. +/* This is a test program for pbsad instruction. */
  45376. +
  45377. +/* { dg-do run } */
  45378. +/* { dg-options "-O1" } */
  45379. +/* { dg-require-effective-target nds32_ext_perf2 } */
  45380. +
  45381. +#include <nds32_intrinsic.h>
  45382. +#include <stdlib.h>
  45383. +
  45384. +int
  45385. +main ()
  45386. +{
  45387. + unsigned int a = 0x09070605;
  45388. + unsigned int b = 0x04020301;
  45389. + unsigned int r = __nds32__pbsad (a, b);
  45390. +
  45391. + if (r != 17)
  45392. + abort ();
  45393. + else
  45394. + exit (0);
  45395. +}
  45396. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-rotr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-rotr.c
  45397. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-rotr.c 1970-01-01 01:00:00.000000000 +0100
  45398. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-rotr.c 2016-08-08 20:37:53.554581681 +0200
  45399. @@ -0,0 +1,19 @@
  45400. +/* This is a test program for rotr instruction. */
  45401. +
  45402. +/* { dg-do run } */
  45403. +/* { dg-options "-O0" } */
  45404. +
  45405. +#include <nds32_intrinsic.h>
  45406. +#include <stdlib.h>
  45407. +
  45408. +int
  45409. +main ()
  45410. +{
  45411. + unsigned int a = 1;
  45412. + a = __nds32__rotr (a, 30);
  45413. +
  45414. + if (a != 4)
  45415. + abort ();
  45416. + else
  45417. + exit (0);
  45418. +}
  45419. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c
  45420. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 2013-12-03 11:58:05.000000000 +0100
  45421. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c 2016-08-08 20:37:53.554581681 +0200
  45422. @@ -1,11 +1,13 @@
  45423. /* Verify that we generate setgie.d instruction with builtin function. */
  45424. -/* { dg-do compile } */
  45425. -/* { dg-options "-O0" } */
  45426. -/* { dg-final { scan-assembler "\\tsetgie.d" } } */
  45427. +/* { dg-do compile } */
  45428. +/* { dg-options "-O0" } */
  45429. +/* { dg-final { scan-assembler "\\tsetgie.d" } } */
  45430. +
  45431. +#include <nds32_intrinsic.h>
  45432. void
  45433. test (void)
  45434. {
  45435. - __builtin_nds32_setgie_dis ();
  45436. + __nds32__setgie_dis ();
  45437. }
  45438. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c
  45439. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 2013-12-03 11:58:05.000000000 +0100
  45440. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c 2016-08-08 20:37:53.554581681 +0200
  45441. @@ -1,11 +1,13 @@
  45442. /* Verify that we generate setgie.e instruction with builtin function. */
  45443. -/* { dg-do compile } */
  45444. -/* { dg-options "-O0" } */
  45445. -/* { dg-final { scan-assembler "\\tsetgie.e" } } */
  45446. +/* { dg-do compile */
  45447. +/* { dg-options "-O0" } */
  45448. +/* { dg-final { scan-assembler "\\tsetgie.e" } } */
  45449. +
  45450. +#include <nds32_intrinsic.h>
  45451. void
  45452. test (void)
  45453. {
  45454. - __builtin_nds32_setgie_en ();
  45455. + __nds32__setgie_en ();
  45456. }
  45457. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c
  45458. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 1970-01-01 01:00:00.000000000 +0100
  45459. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-setgie_mtsr_mfsr.c 2016-08-08 20:37:53.554581681 +0200
  45460. @@ -0,0 +1,36 @@
  45461. +/* This is a test program for checking gie with
  45462. + mtsr/mfsr instruction. */
  45463. +
  45464. +/* { dg-do run } */
  45465. +/* { dg-options "-O0" } */
  45466. +
  45467. +#include <nds32_intrinsic.h>
  45468. +#include <stdlib.h>
  45469. +
  45470. +int
  45471. +main ()
  45472. +{
  45473. + unsigned int psw;
  45474. + unsigned int gie;
  45475. + unsigned int pfm_ctl;
  45476. +
  45477. + __nds32__setgie_en ();
  45478. + __nds32__dsb(); /* This is needed for waiting pipeline. */
  45479. + psw = __nds32__mfsr (NDS32_SR_PSW);
  45480. +
  45481. + gie = psw & 0x00000001;
  45482. +
  45483. + if (gie != 1)
  45484. + abort ();
  45485. +
  45486. + psw = psw & 0xFFFFFFFE;
  45487. + __nds32__mtsr (psw,NDS32_SR_PSW);
  45488. + __nds32__dsb(); /* This is needed for waiting pipeline. */
  45489. + psw = __nds32__mfsr (NDS32_SR_PSW);
  45490. + gie = psw & 0x00000001;
  45491. +
  45492. + if (gie != 0)
  45493. + abort ();
  45494. + else
  45495. + exit (0);
  45496. +}
  45497. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-sp.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-sp.c
  45498. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-sp.c 1970-01-01 01:00:00.000000000 +0100
  45499. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-sp.c 2016-08-08 20:37:53.554581681 +0200
  45500. @@ -0,0 +1,33 @@
  45501. +/* This is a test program for sp intrinsic usage.
  45502. + Because we want to use frame pointer to access local variable,
  45503. + we need to use -fno-omit-frame-pointer to make sure the existence
  45504. + of frame pointer. */
  45505. +
  45506. +/* { dg-do run } */
  45507. +/* { dg-options "-O0 -fno-omit-frame-pointer" } */
  45508. +
  45509. +#include <nds32_intrinsic.h>
  45510. +#include <stdlib.h>
  45511. +
  45512. +int
  45513. +main ()
  45514. +{
  45515. + unsigned int old_sp, new_sp;
  45516. +
  45517. + old_sp = __nds32__get_current_sp ();
  45518. + new_sp = old_sp - 4;
  45519. + __nds32__set_current_sp (new_sp);
  45520. + new_sp = __nds32__get_current_sp ();
  45521. +
  45522. + if (new_sp != (old_sp - 4))
  45523. + abort ();
  45524. +
  45525. + new_sp = new_sp + 4;
  45526. + __nds32__set_current_sp (new_sp);
  45527. + new_sp = __nds32__get_current_sp ();
  45528. +
  45529. + if (new_sp != old_sp)
  45530. + abort ();
  45531. + else
  45532. + exit (0);
  45533. +}
  45534. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-ffb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-ffb.c
  45535. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-ffb.c 1970-01-01 01:00:00.000000000 +0100
  45536. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-ffb.c 2016-08-08 20:37:53.554581681 +0200
  45537. @@ -0,0 +1,28 @@
  45538. +/* This is a test program for ffb instruction. */
  45539. +
  45540. +/* { dg-do run } */
  45541. +/* { dg-options "-O1" } */
  45542. +/* { dg-require-effective-target nds32_ext_string } */
  45543. +
  45544. +#include <nds32_intrinsic.h>
  45545. +#include <stdlib.h>
  45546. +
  45547. +int
  45548. +main ()
  45549. +{
  45550. + unsigned int a = 0x1b2a3d4c;
  45551. + unsigned int b = 0x0000003d;
  45552. + int r;
  45553. +
  45554. + r = __nds32__ffb (a, b);
  45555. +
  45556. +#ifdef __NDS32_EL__
  45557. + if (r != -3)
  45558. + abort ();
  45559. +#else
  45560. + if (r != -2)
  45561. + abort ();
  45562. +#endif
  45563. +
  45564. + exit (0);
  45565. +}
  45566. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-ffmism.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-ffmism.c
  45567. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-ffmism.c 1970-01-01 01:00:00.000000000 +0100
  45568. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-ffmism.c 2016-08-08 20:37:53.554581681 +0200
  45569. @@ -0,0 +1,28 @@
  45570. +/* This is a test program for ffmism instruction. */
  45571. +
  45572. +/* { dg-do run } */
  45573. +/* { dg-options "-O1" } */
  45574. +/* { dg-require-effective-target nds32_ext_string } */
  45575. +
  45576. +#include <nds32_intrinsic.h>
  45577. +#include <stdlib.h>
  45578. +
  45579. +int
  45580. +main ()
  45581. +{
  45582. + unsigned int a = 0x1b2a3d4c;
  45583. + unsigned int b = 0x112a334c;
  45584. + int r;
  45585. +
  45586. + r = __nds32__ffmism (a, b);
  45587. +
  45588. +#ifdef __NDS32_EL__
  45589. + if (r != -3)
  45590. + abort ();
  45591. +#else
  45592. + if (r != -4)
  45593. + abort ();
  45594. +#endif
  45595. +
  45596. + exit (0);
  45597. +}
  45598. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-flmism.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-flmism.c
  45599. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-string-flmism.c 1970-01-01 01:00:00.000000000 +0100
  45600. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-string-flmism.c 2016-08-08 20:37:53.554581681 +0200
  45601. @@ -0,0 +1,28 @@
  45602. +/* This is a test program for flmism instruction. */
  45603. +
  45604. +/* { dg-do run } */
  45605. +/* { dg-options "-O1" } */
  45606. +/* { dg-require-effective-target nds32_ext_string } */
  45607. +
  45608. +#include <nds32_intrinsic.h>
  45609. +#include <stdlib.h>
  45610. +
  45611. +int
  45612. +main ()
  45613. +{
  45614. + unsigned int a = 0x1b2a3d4c;
  45615. + unsigned int b = 0x112a334c;
  45616. + int r;
  45617. +
  45618. + r = __nds32__flmism (a, b);
  45619. +
  45620. +#ifdef __NDS32_EL__
  45621. + if (r != -1)
  45622. + abort ();
  45623. +#else
  45624. + if (r != -2)
  45625. + abort ();
  45626. +#endif
  45627. +
  45628. + exit (0);
  45629. +}
  45630. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add16.c
  45631. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add16.c 1970-01-01 01:00:00.000000000 +0100
  45632. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add16.c 2016-08-08 20:37:53.554581681 +0200
  45633. @@ -0,0 +1,22 @@
  45634. +/* { dg-do compile } */
  45635. +/* { dg-options "-mext-dsp" } */
  45636. +/* { dg-final { scan-assembler "kadd16" } } */
  45637. +/* { dg-final { scan-assembler "kadd16" } } */
  45638. +/* { dg-final { scan-assembler "ukadd16" } } */
  45639. +/* { dg-final { scan-assembler "ukadd16" } } */
  45640. +
  45641. +#include <nds32_intrinsic.h>
  45642. +
  45643. +void
  45644. +test (void)
  45645. +{
  45646. + unsigned int r, a, b;
  45647. + int16x2_t vr, va, vb;
  45648. + uint16x2_t v_ur, v_ua, v_ub;
  45649. +
  45650. + r = __nds32__kadd16 (a, b);
  45651. + vr = __nds32__v_kadd16 (va, vb);
  45652. +
  45653. + r = __nds32__ukadd16 (a, b);
  45654. + v_ur = __nds32__v_ukadd16 (v_ua, v_ub);
  45655. +}
  45656. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add64.c
  45657. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add64.c 1970-01-01 01:00:00.000000000 +0100
  45658. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add64.c 2016-08-08 20:37:53.554581681 +0200
  45659. @@ -0,0 +1,17 @@
  45660. +/* { dg-do compile } */
  45661. +/* { dg-options "-mext-dsp" } */
  45662. +/* { dg-final { scan-assembler "kadd64" } } */
  45663. +/* { dg-final { scan-assembler "ukadd64" } } */
  45664. +
  45665. +#include <nds32_intrinsic.h>
  45666. +
  45667. +void
  45668. +test (void)
  45669. +{
  45670. + long long r, a, b;
  45671. + unsigned long long ur, ua, ub;
  45672. +
  45673. + r = __nds32__kadd64 (a, b);
  45674. + ur = __nds32__ukadd64 (ua, ub);
  45675. +
  45676. +}
  45677. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add8.c
  45678. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-add8.c 1970-01-01 01:00:00.000000000 +0100
  45679. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-add8.c 2016-08-08 20:37:53.558581836 +0200
  45680. @@ -0,0 +1,22 @@
  45681. +/* { dg-do compile } */
  45682. +/* { dg-options "-mext-dsp" } */
  45683. +/* { dg-final { scan-assembler "kadd8" } } */
  45684. +/* { dg-final { scan-assembler "kadd8" } } */
  45685. +/* { dg-final { scan-assembler "ukadd8" } } */
  45686. +/* { dg-final { scan-assembler "ukadd8" } } */
  45687. +
  45688. +#include <nds32_intrinsic.h>
  45689. +
  45690. +void
  45691. +test (void)
  45692. +{
  45693. + unsigned int r, a, b;
  45694. + int8x4_t vr, va, vb;
  45695. + uint8x4_t v_ur, v_ua, v_ub;
  45696. +
  45697. + r = __nds32__kadd8 (a, b);
  45698. + vr = __nds32__v_kadd8 (va, vb);
  45699. +
  45700. + r = __nds32__ukadd8 (a, b);
  45701. + v_ur = __nds32__v_ukadd8 (v_ua, v_ub);
  45702. +}
  45703. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-cras16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-cras16.c
  45704. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-cras16.c 1970-01-01 01:00:00.000000000 +0100
  45705. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-cras16.c 2016-08-08 20:37:53.558581836 +0200
  45706. @@ -0,0 +1,22 @@
  45707. +/* { dg-do compile } */
  45708. +/* { dg-options "-mext-dsp" } */
  45709. +/* { dg-final { scan-assembler "kcras16" } } */
  45710. +/* { dg-final { scan-assembler "kcras16" } } */
  45711. +/* { dg-final { scan-assembler "ukcras16" } } */
  45712. +/* { dg-final { scan-assembler "ukcras16" } } */
  45713. +
  45714. +#include <nds32_intrinsic.h>
  45715. +
  45716. +void
  45717. +test (void)
  45718. +{
  45719. + unsigned int r, a, b;
  45720. + int16x2_t vr, va, vb;
  45721. + uint16x2_t v_ur, v_ua, v_ub;
  45722. +
  45723. + r = __nds32__kcras16 (a, b);
  45724. + vr = __nds32__v_kcras16 (va, vb);
  45725. +
  45726. + r = __nds32__ukcras16 (a, b);
  45727. + v_ur = __nds32__v_ukcras16 (v_ua, v_ub);
  45728. +}
  45729. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-crsa16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-crsa16.c
  45730. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-crsa16.c 1970-01-01 01:00:00.000000000 +0100
  45731. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-crsa16.c 2016-08-08 20:37:53.558581836 +0200
  45732. @@ -0,0 +1,22 @@
  45733. +/* { dg-do compile } */
  45734. +/* { dg-options "-mext-dsp" } */
  45735. +/* { dg-final { scan-assembler "kcrsa16" } } */
  45736. +/* { dg-final { scan-assembler "kcrsa16" } } */
  45737. +/* { dg-final { scan-assembler "ukcrsa16" } } */
  45738. +/* { dg-final { scan-assembler "ukcrsa16" } } */
  45739. +
  45740. +#include <nds32_intrinsic.h>
  45741. +
  45742. +void
  45743. +test (void)
  45744. +{
  45745. + unsigned int r, a, b;
  45746. + int16x2_t vr, va, vb;
  45747. + uint16x2_t v_ur, v_ua, v_ub;
  45748. +
  45749. + r = __nds32__kcrsa16 (a, b);
  45750. + vr = __nds32__v_kcrsa16 (va, vb);
  45751. +
  45752. + r = __nds32__ukcrsa16 (a, b);
  45753. + v_ur = __nds32__v_ukcrsa16 (v_ua, v_ub);
  45754. +}
  45755. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-kabs8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-kabs8.c
  45756. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-kabs8.c 1970-01-01 01:00:00.000000000 +0100
  45757. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-kabs8.c 2016-08-08 20:37:53.558581836 +0200
  45758. @@ -0,0 +1,16 @@
  45759. +/* { dg-do compile } */
  45760. +/* { dg-options "-mext-dsp" } */
  45761. +/* { dg-final { scan-assembler "kabs8" } } */
  45762. +/* { dg-final { scan-assembler "kabs8" } } */
  45763. +
  45764. +#include <nds32_intrinsic.h>
  45765. +
  45766. +void
  45767. +test (void)
  45768. +{
  45769. + unsigned int r, a;
  45770. + int8x4_t vr, va;
  45771. +
  45772. + r = __nds32__kabs8 (a);
  45773. + vr = __nds32__v_kabs8 (va);
  45774. +}
  45775. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll16.c
  45776. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll16.c 1970-01-01 01:00:00.000000000 +0100
  45777. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll16.c 2016-08-08 20:37:53.558581836 +0200
  45778. @@ -0,0 +1,21 @@
  45779. +/* { dg-do compile } */
  45780. +/* { dg-options "-mext-dsp" } */
  45781. +/* { dg-final { scan-assembler "ksll16" } } */
  45782. +/* { dg-final { scan-assembler "ksll16" } } */
  45783. +/* { dg-final { scan-assembler "kslli16" } } */
  45784. +/* { dg-final { scan-assembler "kslli16" } } */
  45785. +
  45786. +#include <nds32_intrinsic.h>
  45787. +
  45788. +void
  45789. +test (void)
  45790. +{
  45791. + unsigned int r, a, b;
  45792. + int16x2_t vr, va;
  45793. +
  45794. + r = __nds32__ksll16 (a, b);
  45795. + vr = __nds32__v_ksll16 (va, b);
  45796. +
  45797. + r = __nds32__ksll16 (a, 0);
  45798. + vr = __nds32__v_ksll16 (va, 0);
  45799. +}
  45800. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll.c
  45801. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll.c 1970-01-01 01:00:00.000000000 +0100
  45802. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-ksll.c 2016-08-08 20:37:53.558581836 +0200
  45803. @@ -0,0 +1,16 @@
  45804. +/* { dg-do compile } */
  45805. +/* { dg-options "-mext-dsp" } */
  45806. +/* { dg-final { scan-assembler "ksll" } } */
  45807. +/* { dg-final { scan-assembler "kslli" } } */
  45808. +
  45809. +#include <nds32_intrinsic.h>
  45810. +
  45811. +void
  45812. +test (void)
  45813. +{
  45814. + int r, a;
  45815. + unsigned int b;
  45816. +
  45817. + r = __nds32__ksll (a, b);
  45818. + r = __nds32__ksll (a, 0);
  45819. +}
  45820. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-kslrawu.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-kslrawu.c
  45821. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-kslrawu.c 1970-01-01 01:00:00.000000000 +0100
  45822. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-kslrawu.c 2016-08-08 20:37:53.558581836 +0200
  45823. @@ -0,0 +1,14 @@
  45824. +/* { dg-do compile } */
  45825. +/* { dg-options "-mext-dsp" } */
  45826. +/* { dg-final { scan-assembler "kslraw.u" } } */
  45827. +
  45828. +#include <nds32_intrinsic.h>
  45829. +
  45830. +void
  45831. +test (void)
  45832. +{
  45833. + int r, a;
  45834. + unsigned int b;
  45835. +
  45836. + r = __nds32__kslraw_u (a, b);
  45837. +}
  45838. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-mar64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-mar64.c
  45839. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-mar64.c 1970-01-01 01:00:00.000000000 +0100
  45840. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-mar64.c 2016-08-08 20:37:53.558581836 +0200
  45841. @@ -0,0 +1,16 @@
  45842. +/* { dg-do compile } */
  45843. +/* { dg-options "-mext-dsp" } */
  45844. +/* { dg-final { scan-assembler "kmar64" } } */
  45845. +/* { dg-final { scan-assembler "ukmar64" } } */
  45846. +
  45847. +#include <nds32_intrinsic.h>
  45848. +
  45849. +void
  45850. +test (void)
  45851. +{
  45852. + long long r, a, b;
  45853. + unsigned long long ur, ua, ub;
  45854. +
  45855. + r = __nds32__kmar64 (r, a, b);
  45856. + ur = __nds32__ukmar64 (ur, ua, ub);
  45857. +}
  45858. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-misc16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-misc16.c
  45859. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-misc16.c 1970-01-01 01:00:00.000000000 +0100
  45860. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-misc16.c 2016-08-08 20:37:53.558581836 +0200
  45861. @@ -0,0 +1,36 @@
  45862. +/* { dg-do compile } */
  45863. +/* { dg-options "-mext-dsp" } */
  45864. +/* { dg-final { scan-assembler "sclip16" } } */
  45865. +/* { dg-final { scan-assembler "sclip16" } } */
  45866. +/* { dg-final { scan-assembler "uclip16" } } */
  45867. +/* { dg-final { scan-assembler "uclip16" } } */
  45868. +/* { dg-final { scan-assembler "khm16" } } */
  45869. +/* { dg-final { scan-assembler "khm16" } } */
  45870. +/* { dg-final { scan-assembler "khmx16" } } */
  45871. +/* { dg-final { scan-assembler "khmx16" } } */
  45872. +/* { dg-final { scan-assembler "kabs16" } } */
  45873. +/* { dg-final { scan-assembler "kabs16" } } */
  45874. +
  45875. +#include <nds32_intrinsic.h>
  45876. +
  45877. +void
  45878. +test (void)
  45879. +{
  45880. + unsigned int r, a, b;
  45881. + int16x2_t vr, va, vb;
  45882. +
  45883. + r = __nds32__sclip16 (a, 0);
  45884. + vr = __nds32__v_sclip16 (va, 0);
  45885. +
  45886. + r = __nds32__uclip16 (a, 0);
  45887. + vr = __nds32__v_uclip16 (va, 0);
  45888. +
  45889. + r = __nds32__khm16 (a, b);
  45890. + vr = __nds32__v_khm16 (va, vb);
  45891. +
  45892. + r = __nds32__khmx16 (a, b);
  45893. + vr = __nds32__v_khmx16 (va, vb);
  45894. +
  45895. + r = __nds32__kabs16 (a);
  45896. + vr = __nds32__v_kabs16 (va);
  45897. +}
  45898. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msr64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msr64.c
  45899. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msr64.c 1970-01-01 01:00:00.000000000 +0100
  45900. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msr64.c 2016-08-08 20:37:53.558581836 +0200
  45901. @@ -0,0 +1,16 @@
  45902. +/* { dg-do compile } */
  45903. +/* { dg-options "-mext-dsp" } */
  45904. +/* { dg-final { scan-assembler "kmsr64" } } */
  45905. +/* { dg-final { scan-assembler "ukmsr64" } } */
  45906. +
  45907. +#include <nds32_intrinsic.h>
  45908. +
  45909. +void
  45910. +test (void)
  45911. +{
  45912. + long long r, a, b;
  45913. + unsigned long long ur, ua, ub;
  45914. +
  45915. + r = __nds32__kmsr64 (r, a, b);
  45916. + ur = __nds32__ukmsr64 (ur, ua, ub);
  45917. +}
  45918. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msw16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msw16.c
  45919. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msw16.c 1970-01-01 01:00:00.000000000 +0100
  45920. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msw16.c 2016-08-08 20:37:53.558581836 +0200
  45921. @@ -0,0 +1,32 @@
  45922. +/* { dg-do compile } */
  45923. +/* { dg-options "-mext-dsp" } */
  45924. +/* { dg-final { scan-assembler "kmmawb" } } */
  45925. +/* { dg-final { scan-assembler "kmmawb" } } */
  45926. +/* { dg-final { scan-assembler "kmmawb.u" } } */
  45927. +/* { dg-final { scan-assembler "kmmawb.u" } } */
  45928. +/* { dg-final { scan-assembler "kmmawt" } } */
  45929. +/* { dg-final { scan-assembler "kmmawt" } } */
  45930. +/* { dg-final { scan-assembler "kmmawt.u" } } */
  45931. +/* { dg-final { scan-assembler "kmmawt.u" } } */
  45932. +
  45933. +#include <nds32_intrinsic.h>
  45934. +
  45935. +void
  45936. +test (void)
  45937. +{
  45938. + int r, a;
  45939. + unsigned int b;
  45940. + int16x2_t vb;
  45941. +
  45942. + r = __nds32__kmmawb (r, a, b);
  45943. + r = __nds32__v_kmmawb (r, a, vb);
  45944. +
  45945. + r = __nds32__kmmawb_u (r, a, b);
  45946. + r = __nds32__v_kmmawb_u (r, a, vb);
  45947. +
  45948. + r = __nds32__kmmawt (r, a, b);
  45949. + r = __nds32__v_kmmawt (r, a, vb);
  45950. +
  45951. + r = __nds32__kmmawt_u (r, a, b);
  45952. + r = __nds32__v_kmmawt_u (r, a, vb);
  45953. +}
  45954. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msw32.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msw32.c
  45955. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-msw32.c 1970-01-01 01:00:00.000000000 +0100
  45956. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-msw32.c 2016-08-08 20:37:53.558581836 +0200
  45957. @@ -0,0 +1,24 @@
  45958. +/* { dg-do compile } */
  45959. +/* { dg-options "-mext-dsp" } */
  45960. +/* { dg-final { scan-assembler "kmmac" } } */
  45961. +/* { dg-final { scan-assembler "kmmac.u" } } */
  45962. +/* { dg-final { scan-assembler "kmmsb" } } */
  45963. +/* { dg-final { scan-assembler "kmmsb.u" } } */
  45964. +/* { dg-final { scan-assembler "kwmmul" } } */
  45965. +/* { dg-final { scan-assembler "kwmmul.u" } } */
  45966. +
  45967. +#include <nds32_intrinsic.h>
  45968. +
  45969. +void
  45970. +test (void)
  45971. +{
  45972. + int r, a, b;
  45973. + r = __nds32__kmmac (r, a, b);
  45974. + r = __nds32__kmmac_u (r, a, b);
  45975. +
  45976. + r = __nds32__kmmsb (r, a, b);
  45977. + r = __nds32__kmmsb_u (r, a, b);
  45978. +
  45979. + r = __nds32__kwmmul (a, b);
  45980. + r = __nds32__kwmmul_u (a, b);
  45981. +}
  45982. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-smul16x32.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-smul16x32.c
  45983. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-smul16x32.c 1970-01-01 01:00:00.000000000 +0100
  45984. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-smul16x32.c 2016-08-08 20:37:53.558581836 +0200
  45985. @@ -0,0 +1,72 @@
  45986. +/* { dg-do compile } */
  45987. +/* { dg-options "-mext-dsp" } */
  45988. +/* { dg-final { scan-assembler "kmda" } } */
  45989. +/* { dg-final { scan-assembler "kmda" } } */
  45990. +/* { dg-final { scan-assembler "kmxda" } } */
  45991. +/* { dg-final { scan-assembler "kmxda" } } */
  45992. +/* { dg-final { scan-assembler "kmabb" } } */
  45993. +/* { dg-final { scan-assembler "kmabb" } } */
  45994. +/* { dg-final { scan-assembler "kmabt" } } */
  45995. +/* { dg-final { scan-assembler "kmabt" } } */
  45996. +/* { dg-final { scan-assembler "kmatt" } } */
  45997. +/* { dg-final { scan-assembler "kmatt" } } */
  45998. +/* { dg-final { scan-assembler "kmada" } } */
  45999. +/* { dg-final { scan-assembler "kmada" } } */
  46000. +/* { dg-final { scan-assembler "kmaxda" } } */
  46001. +/* { dg-final { scan-assembler "kmaxda" } } */
  46002. +/* { dg-final { scan-assembler "kmads" } } */
  46003. +/* { dg-final { scan-assembler "kmads" } } */
  46004. +/* { dg-final { scan-assembler "kmadrs" } } */
  46005. +/* { dg-final { scan-assembler "kmadrs" } } */
  46006. +/* { dg-final { scan-assembler "kmaxds" } } */
  46007. +/* { dg-final { scan-assembler "kmaxds" } } */
  46008. +/* { dg-final { scan-assembler "kmsda" } } */
  46009. +/* { dg-final { scan-assembler "kmsda" } } */
  46010. +/* { dg-final { scan-assembler "kmsxda" } } */
  46011. +/* { dg-final { scan-assembler "kmsxda" } } */
  46012. +
  46013. +#include <nds32_intrinsic.h>
  46014. +
  46015. +void
  46016. +test (void)
  46017. +{
  46018. + int r;
  46019. + unsigned int a, b;
  46020. + int16x2_t va, vb;
  46021. +
  46022. + r = __nds32__kmda (a, b);
  46023. + r = __nds32__v_kmda (va, vb);
  46024. +
  46025. + r = __nds32__kmxda (a, b);
  46026. + r = __nds32__v_kmxda (va, vb);
  46027. +
  46028. + r = __nds32__kmabb (r, a, b);
  46029. + r = __nds32__v_kmabb (r, va, vb);
  46030. +
  46031. + r = __nds32__kmabt (r, a, b);
  46032. + r = __nds32__v_kmabt (r, va, vb);
  46033. +
  46034. + r = __nds32__kmatt (r, a, b);
  46035. + r = __nds32__v_kmatt (r, va, vb);
  46036. +
  46037. + r = __nds32__kmada (r, a, b);
  46038. + r = __nds32__v_kmada (r, va, vb);
  46039. +
  46040. + r = __nds32__kmaxda (r, a, b);
  46041. + r = __nds32__v_kmaxda (r, va, vb);
  46042. +
  46043. + r = __nds32__kmads (r, a, b);
  46044. + r = __nds32__v_kmads (r, va, vb);
  46045. +
  46046. + r = __nds32__kmadrs (r, a, b);
  46047. + r = __nds32__v_kmadrs (r, va, vb);
  46048. +
  46049. + r = __nds32__kmaxds (r, a, b);
  46050. + r = __nds32__v_kmaxds (r, va, vb);
  46051. +
  46052. + r = __nds32__kmsda (r, a, b);
  46053. + r = __nds32__v_kmsda (r, va, vb);
  46054. +
  46055. + r = __nds32__kmsxda (r, a, b);
  46056. + r = __nds32__v_kmsxda (r, va, vb);
  46057. +}
  46058. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub16.c
  46059. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub16.c 1970-01-01 01:00:00.000000000 +0100
  46060. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub16.c 2016-08-08 20:37:53.558581836 +0200
  46061. @@ -0,0 +1,22 @@
  46062. +/* { dg-do compile } */
  46063. +/* { dg-options "-mext-dsp" } */
  46064. +/* { dg-final { scan-assembler "ksub16" } } */
  46065. +/* { dg-final { scan-assembler "ksub16" } } */
  46066. +/* { dg-final { scan-assembler "uksub16" } } */
  46067. +/* { dg-final { scan-assembler "uksub16" } } */
  46068. +
  46069. +#include <nds32_intrinsic.h>
  46070. +
  46071. +void
  46072. +test (void)
  46073. +{
  46074. + unsigned int r, a, b;
  46075. + int16x2_t vr, va, vb;
  46076. + uint16x2_t v_ur, v_ua, v_ub;
  46077. +
  46078. + r = __nds32__ksub16 (a, b);
  46079. + vr = __nds32__v_ksub16 (va, vb);
  46080. +
  46081. + r = __nds32__uksub16 (a, b);
  46082. + v_ur = __nds32__v_uksub16 (v_ua, v_ub);
  46083. +}
  46084. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub64.c
  46085. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub64.c 1970-01-01 01:00:00.000000000 +0100
  46086. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub64.c 2016-08-08 20:37:53.558581836 +0200
  46087. @@ -0,0 +1,17 @@
  46088. +/* { dg-do compile } */
  46089. +/* { dg-options "-mext-dsp" } */
  46090. +/* { dg-final { scan-assembler "ksub64" } } */
  46091. +/* { dg-final { scan-assembler "uksub64" } } */
  46092. +
  46093. +#include <nds32_intrinsic.h>
  46094. +
  46095. +void
  46096. +test (void)
  46097. +{
  46098. + long long r, a, b;
  46099. + unsigned long long ur, ua, ub;
  46100. +
  46101. + r = __nds32__ksub64 (a, b);
  46102. + ur = __nds32__uksub64 (ua, ub);
  46103. +
  46104. +}
  46105. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub8.c
  46106. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-stura-sub8.c 1970-01-01 01:00:00.000000000 +0100
  46107. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-stura-sub8.c 2016-08-08 20:37:53.558581836 +0200
  46108. @@ -0,0 +1,22 @@
  46109. +/* { dg-do compile } */
  46110. +/* { dg-options "-mext-dsp" } */
  46111. +/* { dg-final { scan-assembler "ksub8" } } */
  46112. +/* { dg-final { scan-assembler "ksub8" } } */
  46113. +/* { dg-final { scan-assembler "uksub8" } } */
  46114. +/* { dg-final { scan-assembler "uksub8" } } */
  46115. +
  46116. +#include <nds32_intrinsic.h>
  46117. +
  46118. +void
  46119. +test (void)
  46120. +{
  46121. + unsigned int r, a, b;
  46122. + int8x4_t vr, va, vb;
  46123. + uint8x4_t v_ur, v_ua, v_ub;
  46124. +
  46125. + r = __nds32__ksub8 (a, b);
  46126. + vr = __nds32__v_ksub8 (va, vb);
  46127. +
  46128. + r = __nds32__uksub8 (a, b);
  46129. + v_ur = __nds32__v_uksub8 (v_ua, v_ub);
  46130. +}
  46131. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_dw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_dw.c
  46132. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_dw.c 1970-01-01 01:00:00.000000000 +0100
  46133. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_dw.c 2016-08-08 20:37:53.558581836 +0200
  46134. @@ -0,0 +1,31 @@
  46135. +/* This is a test program for unaligned double word access. */
  46136. +
  46137. +/* { dg-do run } */
  46138. +/* { dg-options "-O0 -std=c99" } */
  46139. +
  46140. +#include <nds32_intrinsic.h>
  46141. +#include <stdlib.h>
  46142. +
  46143. +int
  46144. +main ()
  46145. +{
  46146. + unsigned char data[] = {0x55, 0x66, 0x77, 0x88, 0xAA,
  46147. + 0xBB, 0xCC, 0xDD, 0xEE, 0xFF};
  46148. + unsigned long long* long_long_data = (unsigned long long*) & data[1];
  46149. + unsigned long long test_long_long = 0x1122334455667788LL;
  46150. +
  46151. +#ifdef __NDS32_EL__
  46152. + if (__nds32__get_unaligned_dw (long_long_data) != 0xEEDDCCBBAA887766LL)
  46153. + abort ();
  46154. +#else
  46155. + if (__nds32__get_unaligned_dw (long_long_data) != 0x667788AABBCCDDEELL)
  46156. + abort ();
  46157. +#endif
  46158. +
  46159. + __nds32__put_unaligned_dw (long_long_data, test_long_long);
  46160. +
  46161. + if (__nds32__get_unaligned_dw (long_long_data) != 0x1122334455667788LL)
  46162. + abort ();
  46163. + else
  46164. + exit (0);
  46165. +}
  46166. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_hw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_hw.c
  46167. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_hw.c 1970-01-01 01:00:00.000000000 +0100
  46168. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_hw.c 2016-08-08 20:37:53.558581836 +0200
  46169. @@ -0,0 +1,30 @@
  46170. +/* This is a test program for unaligned half word access. */
  46171. +
  46172. +/* { dg-do run } */
  46173. +/* { dg-options "-O0" } */
  46174. +
  46175. +#include <nds32_intrinsic.h>
  46176. +#include <stdlib.h>
  46177. +
  46178. +int
  46179. +main ()
  46180. +{
  46181. + unsigned char data[] = {0x55,0x66,0x77,0x88};
  46182. + unsigned short* short_data = (unsigned short*)& data[1];
  46183. + unsigned short test_short = 0x5566;
  46184. +
  46185. +#ifdef __NDS32_EL__
  46186. + if (__nds32__get_unaligned_hw (short_data) != 0x7766)
  46187. + abort ();
  46188. +#else
  46189. + if (__nds32__get_unaligned_hw (short_data) != 0x6677)
  46190. + abort ();
  46191. +#endif
  46192. +
  46193. + __nds32__put_unaligned_hw (short_data, test_short);
  46194. +
  46195. + if (__nds32__get_unaligned_hw (short_data) != 0x5566)
  46196. + abort ();
  46197. + else
  46198. + exit (0);
  46199. +}
  46200. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_w.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_w.c
  46201. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-unaligned_w.c 1970-01-01 01:00:00.000000000 +0100
  46202. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-unaligned_w.c 2016-08-08 20:37:53.558581836 +0200
  46203. @@ -0,0 +1,30 @@
  46204. +/* This is a test program for unaligned word access. */
  46205. +
  46206. +/* { dg-do run } */
  46207. +/* { dg-options "-O0 -std=c99" } */
  46208. +
  46209. +#include <nds32_intrinsic.h>
  46210. +#include <stdlib.h>
  46211. +
  46212. +int
  46213. +main ()
  46214. +{
  46215. + unsigned char data[] = {0x55,0x66,0x77,0x88,0xAA,0xBB,0xCC,0xDD};
  46216. + unsigned int* int_data = (unsigned int*)& data[1];
  46217. + unsigned int test_int = 0x55667788;
  46218. +
  46219. +#ifdef __NDS32_EL__
  46220. + if (__nds32__get_unaligned_w (int_data) != 0xAA887766)
  46221. + abort ();
  46222. +#else
  46223. + if (__nds32__get_unaligned_w (int_data) != 0x667788AA)
  46224. + abort ();
  46225. +#endif
  46226. +
  46227. + __nds32__put_unaligned_w (int_data, test_int);
  46228. +
  46229. + if (__nds32__get_unaligned_w (int_data) != 0x55667788)
  46230. + abort ();
  46231. + else
  46232. + exit (0);
  46233. +}
  46234. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-wsbh.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-wsbh.c
  46235. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/builtin-wsbh.c 1970-01-01 01:00:00.000000000 +0100
  46236. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/builtin-wsbh.c 2016-08-08 20:37:53.558581836 +0200
  46237. @@ -0,0 +1,21 @@
  46238. +/* This is a test program for wsbh instruction. */
  46239. +
  46240. +/* { dg-do run } */
  46241. +/* { dg-options "-O0" } */
  46242. +
  46243. +#include <nds32_intrinsic.h>
  46244. +#include <stdlib.h>
  46245. +
  46246. +int
  46247. +main ()
  46248. +{
  46249. + unsigned int a = 0x03020100;
  46250. + unsigned int b;
  46251. +
  46252. + b = __nds32__wsbh (a);
  46253. +
  46254. + if (b != 0x02030001)
  46255. + abort ();
  46256. + else
  46257. + exit (0);
  46258. +}
  46259. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add16.c
  46260. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add16.c 1970-01-01 01:00:00.000000000 +0100
  46261. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add16.c 2016-08-08 20:37:53.558581836 +0200
  46262. @@ -0,0 +1,49 @@
  46263. +/* This is a test program for add16 instruction. */
  46264. +
  46265. +/* { dg-do run } */
  46266. +
  46267. +#include <nds32_intrinsic.h>
  46268. +#include <stdlib.h>
  46269. +
  46270. +#ifdef __NDS32_EXT_DSP__
  46271. +static __attribute__ ((noinline))
  46272. +unsigned int add16 (unsigned int ra, unsigned int rb)
  46273. +{
  46274. + return __nds32__add16 (ra, rb);
  46275. +}
  46276. +
  46277. +static __attribute__ ((noinline))
  46278. +uint16x2_t v_uadd16 (uint16x2_t ra, uint16x2_t rb)
  46279. +{
  46280. + return __nds32__v_uadd16 (ra, rb);
  46281. +}
  46282. +
  46283. +static __attribute__ ((noinline))
  46284. +int16x2_t v_sadd16 (int16x2_t ra, int16x2_t rb)
  46285. +{
  46286. + return __nds32__v_sadd16 (ra, rb);
  46287. +}
  46288. +
  46289. +int
  46290. +main ()
  46291. +{
  46292. + unsigned int a = add16 (0x0001f000, 0x00011000);
  46293. + uint16x2_t v_ua = v_uadd16 ((uint16x2_t) {0xf000, 0xf000},
  46294. + (uint16x2_t) {0x1000, 0x2000});
  46295. + int16x2_t v_sa = v_sadd16 ((int16x2_t) {0xf777, 0xf111},
  46296. + (int16x2_t) {0x1000, 0x2000});
  46297. +
  46298. + if (a != 0x00020000)
  46299. + abort ();
  46300. + else if (v_ua[0] != 0x0000
  46301. + || v_ua[1] != 0x1000)
  46302. + abort ();
  46303. + else if (v_sa[0] != 0x0777
  46304. + || v_sa[1] != 0x1111)
  46305. + abort ();
  46306. + else
  46307. + exit (0);
  46308. +}
  46309. +#else
  46310. +int main(){return 0;}
  46311. +#endif
  46312. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add64.c
  46313. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add64.c 1970-01-01 01:00:00.000000000 +0100
  46314. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add64.c 2016-08-08 20:37:53.558581836 +0200
  46315. @@ -0,0 +1,36 @@
  46316. +/* This is a test program for add64 instruction. */
  46317. +
  46318. +/* { dg-do run } */
  46319. +
  46320. +#include <nds32_intrinsic.h>
  46321. +#include <stdlib.h>
  46322. +
  46323. +#ifdef __NDS32_EXT_DSP__
  46324. +static __attribute__ ((noinline))
  46325. +long long sadd64 (long long ra, long long rb)
  46326. +{
  46327. + return __nds32__sadd64 (ra, rb);
  46328. +}
  46329. +
  46330. +static __attribute__ ((noinline))
  46331. +unsigned long long uadd64 (unsigned long long ra, unsigned long long rb)
  46332. +{
  46333. + return __nds32__uadd64 (ra, rb);
  46334. +}
  46335. +
  46336. +int
  46337. +main ()
  46338. +{
  46339. + long long sa = sadd64 (0x1122334400000000ll, 0x55667788ll);
  46340. + unsigned long long ua = uadd64 (0xffff00000000ull, 0x55667788ull);
  46341. +
  46342. + if (sa != 0x1122334455667788ll)
  46343. + abort ();
  46344. + else if (ua != 0xffff55667788ull)
  46345. + abort ();
  46346. + else
  46347. + exit (0);
  46348. +}
  46349. +#else
  46350. +int main(){return 0;}
  46351. +#endif
  46352. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add8.c
  46353. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add8.c 1970-01-01 01:00:00.000000000 +0100
  46354. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-add8.c 2016-08-08 20:37:53.558581836 +0200
  46355. @@ -0,0 +1,53 @@
  46356. +/* This is a test program for add8 instruction. */
  46357. +
  46358. +/* { dg-do run } */
  46359. +
  46360. +#include <nds32_intrinsic.h>
  46361. +#include <stdlib.h>
  46362. +
  46363. +#ifdef __NDS32_EXT_DSP__
  46364. +static __attribute__ ((noinline))
  46365. +unsigned int add8 (unsigned int ra, unsigned int rb)
  46366. +{
  46367. + return __nds32__add8 (ra, rb);
  46368. +}
  46369. +
  46370. +static __attribute__ ((noinline))
  46371. +uint8x4_t v_uadd8 (uint8x4_t ra, uint8x4_t rb)
  46372. +{
  46373. + return __nds32__v_uadd8 (ra, rb);
  46374. +}
  46375. +
  46376. +static __attribute__ ((noinline))
  46377. +int8x4_t v_sadd8 (int8x4_t ra, int8x4_t rb)
  46378. +{
  46379. + return __nds32__v_sadd8 (ra, rb);
  46380. +}
  46381. +
  46382. +int
  46383. +main ()
  46384. +{
  46385. + unsigned int a = add8 (0x11223344, 0x55667788);
  46386. + uint8x4_t v_ua = v_uadd8 ((uint8x4_t) {0xff, 0xee, 0xdd, 0xcc},
  46387. + (uint8x4_t) {0x1, 0xee, 0xdd, 0xcc});
  46388. + int8x4_t v_sa = v_sadd8 ((int8x4_t) {0x80, 0x7f, 0xbb, 0xaa},
  46389. + (int8x4_t) {0x80, 0x7f, 0xbb, 0xaa});
  46390. +
  46391. + if (a != 0x6688aacc)
  46392. + abort ();
  46393. + else if (v_ua[0] != 0
  46394. + || v_ua[1] != 0xdc
  46395. + || v_ua[2] != 0xba
  46396. + || v_ua[3] != 0x98)
  46397. + abort ();
  46398. + else if (v_sa[0] != 0
  46399. + || v_sa[1] != (char) 0xfe
  46400. + || v_sa[2] != 0x76
  46401. + || v_sa[3] != 0x54)
  46402. + abort ();
  46403. + else
  46404. + exit (0);
  46405. +}
  46406. +#else
  46407. +int main(){return 0;}
  46408. +#endif
  46409. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bitrev.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bitrev.c
  46410. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bitrev.c 1970-01-01 01:00:00.000000000 +0100
  46411. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bitrev.c 2016-08-08 20:37:53.558581836 +0200
  46412. @@ -0,0 +1,27 @@
  46413. +/* This is a test program for bitrev instruction. */
  46414. +
  46415. +/* { dg-do run } */
  46416. +
  46417. +#include <nds32_intrinsic.h>
  46418. +#include <stdlib.h>
  46419. +
  46420. +#ifdef __NDS32_EXT_DSP__
  46421. +static __attribute__ ((noinline))
  46422. +unsigned int bitrev (unsigned int ra, unsigned int rb)
  46423. +{
  46424. + return __nds32__bitrev (ra, rb);
  46425. +}
  46426. +
  46427. +int
  46428. +main ()
  46429. +{
  46430. + unsigned int a = bitrev (0xd, 1);
  46431. +
  46432. + if (a != 0x2)
  46433. + abort ();
  46434. + else
  46435. + exit (0);
  46436. +}
  46437. +#else
  46438. +int main(){return 0;}
  46439. +#endif
  46440. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bpick.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bpick.c
  46441. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bpick.c 1970-01-01 01:00:00.000000000 +0100
  46442. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-bpick.c 2016-08-08 20:37:53.558581836 +0200
  46443. @@ -0,0 +1,27 @@
  46444. +/* This is a test program for bpick instruction. */
  46445. +
  46446. +/* { dg-do run } */
  46447. +
  46448. +#include <nds32_intrinsic.h>
  46449. +#include <stdlib.h>
  46450. +
  46451. +#ifdef __NDS32_EXT_DSP__
  46452. +static __attribute__ ((noinline))
  46453. +unsigned int bpick (unsigned int ra, unsigned int rb, unsigned int rc)
  46454. +{
  46455. + return __nds32__bpick (ra, rb, rc);
  46456. +}
  46457. +
  46458. +int
  46459. +main ()
  46460. +{
  46461. + unsigned int a = bpick (0x11223344, 0x11332244, 0);
  46462. +
  46463. + if (a != 0x11332244)
  46464. + abort ();
  46465. + else
  46466. + exit (0);
  46467. +}
  46468. +#else
  46469. +int main(){return 0;}
  46470. +#endif
  46471. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq16.c
  46472. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq16.c 1970-01-01 01:00:00.000000000 +0100
  46473. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq16.c 2016-08-08 20:37:53.558581836 +0200
  46474. @@ -0,0 +1,49 @@
  46475. +/* This is a test program for cmpeq16 instruction. */
  46476. +
  46477. +/* { dg-do run } */
  46478. +
  46479. +#include <nds32_intrinsic.h>
  46480. +#include <stdlib.h>
  46481. +
  46482. +#ifdef __NDS32_EXT_DSP__
  46483. +static __attribute__ ((noinline))
  46484. +unsigned int cmpeq16 (unsigned int ra, unsigned int rb)
  46485. +{
  46486. + return __nds32__cmpeq16 (ra, rb);
  46487. +}
  46488. +
  46489. +static __attribute__ ((noinline))
  46490. +uint16x2_t v_scmpeq16 (int16x2_t ra, int16x2_t rb)
  46491. +{
  46492. + return __nds32__v_scmpeq16 (ra, rb);
  46493. +}
  46494. +
  46495. +static __attribute__ ((noinline))
  46496. +uint16x2_t v_ucmpeq16 (uint16x2_t ra, uint16x2_t rb)
  46497. +{
  46498. + return __nds32__v_ucmpeq16 (ra, rb);
  46499. +}
  46500. +
  46501. +int
  46502. +main ()
  46503. +{
  46504. + unsigned int a = cmpeq16 (0xffff0000, 0xffff0001);
  46505. + uint16x2_t v_sa = v_scmpeq16 ((int16x2_t) {0x7fff, 0x8000},
  46506. + (int16x2_t) {0x8000, 0x8000});
  46507. + uint16x2_t v_ua = v_ucmpeq16 ((uint16x2_t) {0x7fff, 0x8000},
  46508. + (uint16x2_t) {0x8000, 0x8000});
  46509. +
  46510. + if (a != 0xffff0000)
  46511. + abort ();
  46512. + else if (v_sa[0] != 0
  46513. + || v_sa[1] != 0xffff)
  46514. + abort ();
  46515. + else if (v_ua[0] != 0
  46516. + || v_ua[1] != 0xffff)
  46517. + abort ();
  46518. + else
  46519. + exit (0);
  46520. +}
  46521. +#else
  46522. +int main(){return 0;}
  46523. +#endif
  46524. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq8.c
  46525. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq8.c 1970-01-01 01:00:00.000000000 +0100
  46526. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cmpeq8.c 2016-08-08 20:37:53.558581836 +0200
  46527. @@ -0,0 +1,53 @@
  46528. +/* This is a test program for cmpeq8 instruction. */
  46529. +
  46530. +/* { dg-do run } */
  46531. +
  46532. +#include <nds32_intrinsic.h>
  46533. +#include <stdlib.h>
  46534. +
  46535. +#ifdef __NDS32_EXT_DSP__
  46536. +static __attribute__ ((noinline))
  46537. +unsigned int cmpeq8 (unsigned int ra, unsigned int rb)
  46538. +{
  46539. + return __nds32__cmpeq8 (ra, rb);
  46540. +}
  46541. +
  46542. +static __attribute__ ((noinline))
  46543. +uint8x4_t v_scmpeq8 (int8x4_t ra, int8x4_t rb)
  46544. +{
  46545. + return __nds32__v_scmpeq8 (ra, rb);
  46546. +}
  46547. +
  46548. +static __attribute__ ((noinline))
  46549. +uint8x4_t v_ucmpeq8 (uint8x4_t ra, uint8x4_t rb)
  46550. +{
  46551. + return __nds32__v_ucmpeq8 (ra, rb);
  46552. +}
  46553. +
  46554. +int
  46555. +main ()
  46556. +{
  46557. + unsigned int a = cmpeq8 (0xffff0000, 0xffff0101);
  46558. + uint8x4_t v_sa = v_scmpeq8 ((int8x4_t) { 0x7f, 0x7f, 0x01, 0x01},
  46559. + (int8x4_t) { 0x7f, 0x7f, 0x00, 0x00});
  46560. + uint8x4_t v_ua = v_ucmpeq8 ((uint8x4_t) { 0x7f, 0x7f, 0x01, 0x01},
  46561. + (uint8x4_t) { 0x7f, 0x7f, 0x00, 0x00});
  46562. +
  46563. + if (a != 0xffff0000)
  46564. + abort ();
  46565. + else if (v_sa[0] != 0xff
  46566. + || v_sa[1] != 0xff
  46567. + || v_sa[2] != 0
  46568. + || v_sa[3] != 0)
  46569. + abort ();
  46570. + else if (v_ua[0] != 0xff
  46571. + || v_ua[1] != 0xff
  46572. + || v_ua[2] != 0
  46573. + || v_ua[3] != 0)
  46574. + abort ();
  46575. + else
  46576. + exit (0);
  46577. +}
  46578. +#else
  46579. +int main(){return 0;}
  46580. +#endif
  46581. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cras16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cras16.c
  46582. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cras16.c 1970-01-01 01:00:00.000000000 +0100
  46583. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-cras16.c 2016-08-08 20:37:53.558581836 +0200
  46584. @@ -0,0 +1,58 @@
  46585. +/* This is a test program for cras16 instruction. */
  46586. +
  46587. +/* { dg-do run } */
  46588. +
  46589. +#include <nds32_intrinsic.h>
  46590. +#include <stdlib.h>
  46591. +
  46592. +#ifdef __NDS32_EXT_DSP__
  46593. +static __attribute__ ((noinline))
  46594. +unsigned int cras16 (unsigned int ra, unsigned int rb)
  46595. +{
  46596. + return __nds32__cras16 (ra, rb);
  46597. +}
  46598. +
  46599. +static __attribute__ ((noinline))
  46600. +uint16x2_t v_ucras16 (uint16x2_t ra, uint16x2_t rb)
  46601. +{
  46602. + return __nds32__v_ucras16 (ra, rb);
  46603. +}
  46604. +
  46605. +static __attribute__ ((noinline))
  46606. +int16x2_t v_scras16 (int16x2_t ra, int16x2_t rb)
  46607. +{
  46608. + return __nds32__v_scras16 (ra, rb);
  46609. +}
  46610. +
  46611. +int
  46612. +main ()
  46613. +{
  46614. +
  46615. +#ifdef __NDS32_EL__
  46616. + uint16x2_t v_ua_p = {1, 0};
  46617. + int16x2_t v_sa_p = {0x1000, 0x111};
  46618. +#else
  46619. + uint16x2_t v_ua_p = {0x2469, 0xe000};
  46620. + int16x2_t v_sa_p = {0x3000, 0xe111};
  46621. +#endif
  46622. +
  46623. + unsigned int a = cras16 (0x0001f000, 0x0001f000);
  46624. + uint16x2_t v_ua = v_ucras16 ((uint16x2_t) {0x1235, 0xf000},
  46625. + (uint16x2_t) {0x1000, 0x1234});
  46626. + int16x2_t v_sa = v_scras16 ((int16x2_t) {0x2000, 0xf111},
  46627. + (int16x2_t) {0x1000, 0x1000});
  46628. +
  46629. + if (a != 0xf001efff)
  46630. + abort ();
  46631. + else if (v_ua[0] != v_ua_p[0]
  46632. + || v_ua[1] != v_ua_p[1])
  46633. + abort ();
  46634. + else if (v_sa[0] != v_sa_p[0]
  46635. + || v_sa[1] != v_sa_p[1])
  46636. + abort ();
  46637. + else
  46638. + exit (0);
  46639. +}
  46640. +#else
  46641. +int main(){return 0;}
  46642. +#endif
  46643. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-crsa16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-crsa16.c
  46644. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-crsa16.c 1970-01-01 01:00:00.000000000 +0100
  46645. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-crsa16.c 2016-08-08 20:37:53.558581836 +0200
  46646. @@ -0,0 +1,57 @@
  46647. +/* This is a test program for crsa16 instruction. */
  46648. +
  46649. +/* { dg-do run } */
  46650. +
  46651. +#include <nds32_intrinsic.h>
  46652. +#include <stdlib.h>
  46653. +
  46654. +#ifdef __NDS32_EXT_DSP__
  46655. +static __attribute__ ((noinline))
  46656. +unsigned int crsa16 (unsigned int ra, unsigned int rb)
  46657. +{
  46658. + return __nds32__crsa16 (ra, rb);
  46659. +}
  46660. +
  46661. +static __attribute__ ((noinline))
  46662. +uint16x2_t v_ucrsa16 (uint16x2_t ra, uint16x2_t rb)
  46663. +{
  46664. + return __nds32__v_ucrsa16 (ra, rb);
  46665. +}
  46666. +
  46667. +static __attribute__ ((noinline))
  46668. +int16x2_t v_scrsa16 (int16x2_t ra, int16x2_t rb)
  46669. +{
  46670. + return __nds32__v_scrsa16 (ra, rb);
  46671. +}
  46672. +
  46673. +int
  46674. +main ()
  46675. +{
  46676. +#ifdef __NDS32_EL__
  46677. + uint16x2_t v_ua_p = {0x2469, 0xe000};
  46678. + int16x2_t v_sa_p = {0x3000, 0x110};
  46679. +#else
  46680. + uint16x2_t v_ua_p = {1, 0};
  46681. + int16x2_t v_sa_p = {0x1000, 0x112};
  46682. +#endif
  46683. +
  46684. + unsigned int a = crsa16 (0x0001f000, 0x0001f000);
  46685. + uint16x2_t v_ua = v_ucrsa16 ((uint16x2_t) {0x1235, 0xf000},
  46686. + (uint16x2_t) {0x1000, 0x1234});
  46687. + int16x2_t v_sa = v_scrsa16 ((int16x2_t) {0x2000, 0x0111},
  46688. + (int16x2_t) {0x0001, 0x1000});
  46689. +
  46690. + if (a != 0x1001f001)
  46691. + abort ();
  46692. + else if (v_ua[0] != v_ua_p[0]
  46693. + || v_ua[1] != v_ua_p[1])
  46694. + abort ();
  46695. + else if (v_sa[0] != v_sa_p[0]
  46696. + || v_sa[1] != v_sa_p[1])
  46697. + abort ();
  46698. + else
  46699. + exit (0);
  46700. +}
  46701. +#else
  46702. +int main(){return 0;}
  46703. +#endif
  46704. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-insb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-insb.c
  46705. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-insb.c 1970-01-01 01:00:00.000000000 +0100
  46706. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-insb.c 2016-08-08 20:37:53.558581836 +0200
  46707. @@ -0,0 +1,27 @@
  46708. +/* This is a test program for insb instruction. */
  46709. +
  46710. +/* { dg-do run } */
  46711. +
  46712. +#include <nds32_intrinsic.h>
  46713. +#include <stdlib.h>
  46714. +
  46715. +#ifdef __NDS32_EXT_DSP__
  46716. +static __attribute__ ((noinline))
  46717. +unsigned int insb (unsigned int ra, unsigned int rb)
  46718. +{
  46719. + return __nds32__insb (ra, rb, 1);
  46720. +}
  46721. +
  46722. +int
  46723. +main ()
  46724. +{
  46725. + unsigned int a = insb (0x11220044, 0x33);
  46726. +
  46727. + if (a != 0x11223344)
  46728. + abort ();
  46729. + else
  46730. + exit (0);
  46731. +}
  46732. +#else
  46733. +int main(){return 0;}
  46734. +#endif
  46735. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbb16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbb16.c
  46736. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbb16.c 1970-01-01 01:00:00.000000000 +0100
  46737. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbb16.c 2016-08-08 20:37:53.558581836 +0200
  46738. @@ -0,0 +1,44 @@
  46739. +/* This is a test program for pkbb16 instruction. */
  46740. +
  46741. +/* { dg-do run } */
  46742. +
  46743. +#include <nds32_intrinsic.h>
  46744. +#include <stdlib.h>
  46745. +
  46746. +#ifdef __NDS32_EXT_DSP__
  46747. +static __attribute__ ((noinline))
  46748. +unsigned int pkbb16 (unsigned int ra, unsigned int rb)
  46749. +{
  46750. + return __nds32__pkbb16 (ra, rb);
  46751. +}
  46752. +
  46753. +static __attribute__ ((noinline))
  46754. +uint16x2_t v_pkbb16 (uint16x2_t ra, uint16x2_t rb)
  46755. +{
  46756. + return __nds32__v_pkbb16 (ra, rb);
  46757. +}
  46758. +
  46759. +int
  46760. +main ()
  46761. +{
  46762. +#ifdef __NDS32_EL__
  46763. + uint16x2_t va_p = {0xcccc, 0xaaaa};
  46764. +#else
  46765. + uint16x2_t va_p = {0xbbbb, 0xdddd};
  46766. +#endif
  46767. +
  46768. + unsigned int a = pkbb16 (0x11223344, 0x55667788);
  46769. + uint16x2_t va = v_pkbb16 ((uint16x2_t) {0xaaaa, 0xbbbb},
  46770. + (uint16x2_t) {0xcccc, 0xdddd});
  46771. +
  46772. + if (a != 0x33447788)
  46773. + abort ();
  46774. + else if (va[0] != va_p[0]
  46775. + || va[1] != va_p[1])
  46776. + abort ();
  46777. + else
  46778. + exit (0);
  46779. +}
  46780. +#else
  46781. +int main(){return 0;}
  46782. +#endif
  46783. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbt16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbt16.c
  46784. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbt16.c 1970-01-01 01:00:00.000000000 +0100
  46785. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pkbt16.c 2016-08-08 20:37:53.558581836 +0200
  46786. @@ -0,0 +1,44 @@
  46787. +/* This is a test program for pkbt16 instruction. */
  46788. +
  46789. +/* { dg-do run } */
  46790. +
  46791. +#include <nds32_intrinsic.h>
  46792. +#include <stdlib.h>
  46793. +
  46794. +#ifdef __NDS32_EXT_DSP__
  46795. +static __attribute__ ((noinline))
  46796. +unsigned int pkbt16 (unsigned int ra, unsigned int rb)
  46797. +{
  46798. + return __nds32__pkbt16 (ra, rb);
  46799. +}
  46800. +
  46801. +static __attribute__ ((noinline))
  46802. +uint16x2_t v_pkbt16 (uint16x2_t ra, uint16x2_t rb)
  46803. +{
  46804. + return __nds32__v_pkbt16 (ra, rb);
  46805. +}
  46806. +
  46807. +int
  46808. +main ()
  46809. +{
  46810. +#ifdef __NDS32_EL__
  46811. + uint16x2_t va_p = {0xdddd, 0xaaaa};
  46812. +#else
  46813. + uint16x2_t va_p = {0xbbbb, 0xcccc};
  46814. +#endif
  46815. +
  46816. + unsigned int a = pkbt16 (0x11223344, 0x55667788);
  46817. + uint16x2_t va = v_pkbt16 ((uint16x2_t) {0xaaaa, 0xbbbb},
  46818. + (uint16x2_t) {0xcccc, 0xdddd});
  46819. +
  46820. + if (a != 0x33445566)
  46821. + abort ();
  46822. + else if (va[0] != va_p[0]
  46823. + || va[1] != va_p[1])
  46824. + abort ();
  46825. + else
  46826. + exit (0);
  46827. +}
  46828. +#else
  46829. +int main(){return 0;}
  46830. +#endif
  46831. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktb16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktb16.c
  46832. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktb16.c 1970-01-01 01:00:00.000000000 +0100
  46833. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktb16.c 2016-08-08 20:37:53.562581991 +0200
  46834. @@ -0,0 +1,44 @@
  46835. +/* This is a test program for pktb16 instruction. */
  46836. +
  46837. +/* { dg-do run } */
  46838. +
  46839. +#include <nds32_intrinsic.h>
  46840. +#include <stdlib.h>
  46841. +
  46842. +#ifdef __NDS32_EXT_DSP__
  46843. +static __attribute__ ((noinline))
  46844. +unsigned int pktb16 (unsigned int ra, unsigned int rb)
  46845. +{
  46846. + return __nds32__pktb16 (ra, rb);
  46847. +}
  46848. +
  46849. +static __attribute__ ((noinline))
  46850. +uint16x2_t v_pktb16 (uint16x2_t ra, uint16x2_t rb)
  46851. +{
  46852. + return __nds32__v_pktb16 (ra, rb);
  46853. +}
  46854. +
  46855. +int
  46856. +main ()
  46857. +{
  46858. +#ifdef __NDS32_EL__
  46859. + uint16x2_t va_p = {0xcccc, 0xbbbb};
  46860. +#else
  46861. + uint16x2_t va_p = {0xaaaa, 0xdddd};
  46862. +#endif
  46863. +
  46864. + unsigned int a = pktb16 (0x11223344, 0x55667788);
  46865. + uint16x2_t va = v_pktb16 ((uint16x2_t) {0xaaaa, 0xbbbb},
  46866. + (uint16x2_t) {0xcccc, 0xdddd});
  46867. +
  46868. + if (a != 0x11227788)
  46869. + abort ();
  46870. + else if (va[0] != va_p[0]
  46871. + || va[1] != va_p[1])
  46872. + abort ();
  46873. + else
  46874. + exit (0);
  46875. +}
  46876. +#else
  46877. +int main(){return 0;}
  46878. +#endif
  46879. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktt16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktt16.c
  46880. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktt16.c 1970-01-01 01:00:00.000000000 +0100
  46881. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-pktt16.c 2016-08-08 20:37:53.562581991 +0200
  46882. @@ -0,0 +1,44 @@
  46883. +/* This is a test program for pktt16 instruction. */
  46884. +
  46885. +/* { dg-do run } */
  46886. +
  46887. +#include <nds32_intrinsic.h>
  46888. +#include <stdlib.h>
  46889. +
  46890. +#ifdef __NDS32_EXT_DSP__
  46891. +static __attribute__ ((noinline))
  46892. +unsigned int pktt16 (unsigned int ra, unsigned int rb)
  46893. +{
  46894. + return __nds32__pktt16 (ra, rb);
  46895. +}
  46896. +
  46897. +static __attribute__ ((noinline))
  46898. +uint16x2_t v_pktt16 (uint16x2_t ra, uint16x2_t rb)
  46899. +{
  46900. + return __nds32__v_pktt16 (ra, rb);
  46901. +}
  46902. +
  46903. +int
  46904. +main ()
  46905. +{
  46906. +#ifdef __NDS32_EL__
  46907. + uint16x2_t va_p = {0xdddd, 0xbbbb};
  46908. +#else
  46909. + uint16x2_t va_p = {0xaaaa, 0xcccc};
  46910. +#endif
  46911. +
  46912. + unsigned int a = pktt16 (0x11223344, 0x55667788);
  46913. + uint16x2_t va = v_pktt16 ((uint16x2_t) {0xaaaa, 0xbbbb},
  46914. + (uint16x2_t) {0xcccc, 0xdddd});
  46915. +
  46916. + if (a != 0x11225566)
  46917. + abort ();
  46918. + else if (va[0] != va_p[0]
  46919. + || va[1] != va_p[1])
  46920. + abort ();
  46921. + else
  46922. + exit (0);
  46923. +}
  46924. +#else
  46925. +int main(){return 0;}
  46926. +#endif
  46927. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd16.c
  46928. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd16.c 1970-01-01 01:00:00.000000000 +0100
  46929. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd16.c 2016-08-08 20:37:53.562581991 +0200
  46930. @@ -0,0 +1,38 @@
  46931. +/* This is a test program for radd16 instruction. */
  46932. +
  46933. +/* { dg-do run } */
  46934. +
  46935. +#include <nds32_intrinsic.h>
  46936. +#include <stdlib.h>
  46937. +
  46938. +#ifdef __NDS32_EXT_DSP__
  46939. +static __attribute__ ((noinline))
  46940. +unsigned int radd16 (unsigned int ra, unsigned int rb)
  46941. +{
  46942. + return __nds32__radd16 (ra, rb);
  46943. +}
  46944. +
  46945. +static __attribute__ ((noinline))
  46946. +int16x2_t v_radd16 (int16x2_t ra, int16x2_t rb)
  46947. +{
  46948. + return __nds32__v_radd16 (ra, rb);
  46949. +}
  46950. +
  46951. +int
  46952. +main ()
  46953. +{
  46954. + unsigned int a = radd16 (0x7fff7fff, 0x7fff7fff);
  46955. + int16x2_t va = v_radd16 ((int16x2_t) {0x8000, 0x4000},
  46956. + (int16x2_t) {0x8000, 0x8000});
  46957. +
  46958. + if (a != 0x7fff7fff)
  46959. + abort ();
  46960. + else if (va[0] != (short) 0x8000
  46961. + || va[1] != (short) 0xe000)
  46962. + abort ();
  46963. + else
  46964. + exit (0);
  46965. +}
  46966. +#else
  46967. +int main(){return 0;}
  46968. +#endif
  46969. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd64.c
  46970. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd64.c 1970-01-01 01:00:00.000000000 +0100
  46971. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd64.c 2016-08-08 20:37:53.562581991 +0200
  46972. @@ -0,0 +1,27 @@
  46973. +/* This is a test program for radd64 instruction. */
  46974. +
  46975. +/* { dg-do run } */
  46976. +
  46977. +#include <nds32_intrinsic.h>
  46978. +#include <stdlib.h>
  46979. +
  46980. +#ifdef __NDS32_EXT_DSP__
  46981. +static __attribute__ ((noinline))
  46982. +long long radd64 (long long ra, long long rb)
  46983. +{
  46984. + return __nds32__radd64 (ra, rb);
  46985. +}
  46986. +
  46987. +int
  46988. +main ()
  46989. +{
  46990. + long long a = radd64 (0xf000000000000000ll, 0xf000000000000000ll);
  46991. +
  46992. + if (a != 0xf000000000000000ll)
  46993. + abort ();
  46994. + else
  46995. + exit (0);
  46996. +}
  46997. +#else
  46998. +int main(){return 0;}
  46999. +#endif
  47000. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd8.c
  47001. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd8.c 1970-01-01 01:00:00.000000000 +0100
  47002. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-radd8.c 2016-08-08 20:37:53.562581991 +0200
  47003. @@ -0,0 +1,40 @@
  47004. +/* This is a test program for radd8 instruction. */
  47005. +
  47006. +/* { dg-do run } */
  47007. +
  47008. +#include <nds32_intrinsic.h>
  47009. +#include <stdlib.h>
  47010. +
  47011. +#ifdef __NDS32_EXT_DSP__
  47012. +static __attribute__ ((noinline))
  47013. +unsigned int radd8 (unsigned int ra, unsigned int rb)
  47014. +{
  47015. + return __nds32__radd8 (ra, rb);
  47016. +}
  47017. +
  47018. +static __attribute__ ((noinline))
  47019. +int8x4_t v_radd8 (int8x4_t ra, int8x4_t rb)
  47020. +{
  47021. + return __nds32__v_radd8 (ra, rb);
  47022. +}
  47023. +
  47024. +int
  47025. +main ()
  47026. +{
  47027. + unsigned int a = radd8 (0x11223344, 0x55667788);
  47028. + int8x4_t va = v_radd8 ((int8x4_t) {0x7f, 0x80, 0x80, 0xaa},
  47029. + (int8x4_t) {0x7f, 0x80, 0x40, 0xaa});
  47030. +
  47031. + if (a != 0x334455e6)
  47032. + abort ();
  47033. + else if (va[0] != 0x7f
  47034. + || va[1] != (char) 0x80
  47035. + || va[2] != (char) 0xe0
  47036. + || va[3] != (char) 0xaa)
  47037. + abort ();
  47038. + else
  47039. + exit (0);
  47040. +}
  47041. +#else
  47042. +int main(){return 0;}
  47043. +#endif
  47044. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-raddw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-raddw.c
  47045. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-raddw.c 1970-01-01 01:00:00.000000000 +0100
  47046. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-raddw.c 2016-08-08 20:37:53.562581991 +0200
  47047. @@ -0,0 +1,27 @@
  47048. +/* This is a test program for raddw instruction. */
  47049. +
  47050. +/* { dg-do run } */
  47051. +
  47052. +#include <nds32_intrinsic.h>
  47053. +#include <stdlib.h>
  47054. +
  47055. +#ifdef __NDS32_EXT_DSP__
  47056. +static __attribute__ ((noinline))
  47057. +int raddw (int ra, int rb)
  47058. +{
  47059. + return __nds32__raddw (ra, rb);
  47060. +}
  47061. +
  47062. +int
  47063. +main ()
  47064. +{
  47065. + int a = raddw (0x80000000, 0x80000000);
  47066. +
  47067. + if (a != 0x80000000)
  47068. + abort ();
  47069. + else
  47070. + exit (0);
  47071. +}
  47072. +#else
  47073. +int main(){return 0;}
  47074. +#endif
  47075. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcras16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcras16.c
  47076. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcras16.c 1970-01-01 01:00:00.000000000 +0100
  47077. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcras16.c 2016-08-08 20:37:53.562581991 +0200
  47078. @@ -0,0 +1,44 @@
  47079. +/* This is a test program for rcras16 instruction. */
  47080. +
  47081. +/* { dg-do run } */
  47082. +
  47083. +#include <nds32_intrinsic.h>
  47084. +#include <stdlib.h>
  47085. +
  47086. +#ifdef __NDS32_EXT_DSP__
  47087. +static __attribute__ ((noinline))
  47088. +unsigned int rcras16 (unsigned int ra, unsigned int rb)
  47089. +{
  47090. + return __nds32__rcras16 (ra, rb);
  47091. +}
  47092. +
  47093. +static __attribute__ ((noinline))
  47094. +int16x2_t v_rcras16 (int16x2_t ra, int16x2_t rb)
  47095. +{
  47096. + return __nds32__v_rcras16 (ra, rb);
  47097. +}
  47098. +
  47099. +int
  47100. +main ()
  47101. +{
  47102. +#ifdef __NDS32_EL__
  47103. + int16x2_t va_p = {0x7fff, 0x8000};
  47104. +#else
  47105. + int16x2_t va_p = {0xffff, 0};
  47106. +#endif
  47107. +
  47108. + unsigned int a = rcras16 (0x0fff0000, 0x00000fff);
  47109. + int16x2_t va = v_rcras16 ((int16x2_t) {0x7fff, 0x8000},
  47110. + (int16x2_t) {0x8000, 0x8000});
  47111. +
  47112. + if (a != 0x0fff0000)
  47113. + abort ();
  47114. + else if (va[0] != va_p[0]
  47115. + || va[1] != va_p[1])
  47116. + abort ();
  47117. + else
  47118. + exit (0);
  47119. +}
  47120. +#else
  47121. +int main(){return 0;}
  47122. +#endif
  47123. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcrsa16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcrsa16.c
  47124. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcrsa16.c 1970-01-01 01:00:00.000000000 +0100
  47125. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rcrsa16.c 2016-08-08 20:37:53.562581991 +0200
  47126. @@ -0,0 +1,44 @@
  47127. +/* This is a test program for rcrsa16 instruction. */
  47128. +
  47129. +/* { dg-do run } */
  47130. +
  47131. +#include <nds32_intrinsic.h>
  47132. +#include <stdlib.h>
  47133. +
  47134. +#ifdef __NDS32_EXT_DSP__
  47135. +static __attribute__ ((noinline))
  47136. +unsigned int rcrsa16 (unsigned int ra, unsigned int rb)
  47137. +{
  47138. + return __nds32__rcrsa16 (ra, rb);
  47139. +}
  47140. +
  47141. +static __attribute__ ((noinline))
  47142. +int16x2_t v_rcrsa16 (int16x2_t ra, int16x2_t rb)
  47143. +{
  47144. + return __nds32__v_rcrsa16 (ra, rb);
  47145. +}
  47146. +
  47147. +int
  47148. +main ()
  47149. +{
  47150. +#ifdef __NDS32_EL__
  47151. + int16x2_t va_p = {0x8000, 0x8000};
  47152. +#else
  47153. + int16x2_t va_p = {0, 0xffff};
  47154. +#endif
  47155. +
  47156. + unsigned int a = rcrsa16 (0x7fff7fff, 0x7fff8000);
  47157. + int16x2_t va = v_rcrsa16 ((int16x2_t) {0x8000, 0x8000},
  47158. + (int16x2_t) {0x7fff, 0x8000});
  47159. +
  47160. + if (a != 0x7fff7fff)
  47161. + abort ();
  47162. + else if (va[0] != va_p [0]
  47163. + || va[1] != va_p [1])
  47164. + abort ();
  47165. + else
  47166. + exit (0);
  47167. +}
  47168. +#else
  47169. +int main(){return 0;}
  47170. +#endif
  47171. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub16.c
  47172. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub16.c 1970-01-01 01:00:00.000000000 +0100
  47173. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub16.c 2016-08-08 20:37:53.562581991 +0200
  47174. @@ -0,0 +1,38 @@
  47175. +/* This is a test program for rsub16 instruction. */
  47176. +
  47177. +/* { dg-do run } */
  47178. +
  47179. +#include <nds32_intrinsic.h>
  47180. +#include <stdlib.h>
  47181. +
  47182. +#ifdef __NDS32_EXT_DSP__
  47183. +static __attribute__ ((noinline))
  47184. +unsigned int rsub16 (unsigned int ra, unsigned int rb)
  47185. +{
  47186. + return __nds32__rsub16 (ra, rb);
  47187. +}
  47188. +
  47189. +static __attribute__ ((noinline))
  47190. +int16x2_t v_rsub16 (int16x2_t ra, int16x2_t rb)
  47191. +{
  47192. + return __nds32__v_rsub16 (ra, rb);
  47193. +}
  47194. +
  47195. +int
  47196. +main ()
  47197. +{
  47198. + unsigned int a = rsub16 (0x7fff7fff, 0x80008000);
  47199. + int16x2_t va = v_rsub16 ((int16x2_t) {0x8000, 0x8000},
  47200. + (int16x2_t) {0x7fff, 0x4000});
  47201. +
  47202. + if (a != 0x7fff7fff)
  47203. + abort ();
  47204. + else if (va[0] != (short) 0x8000
  47205. + || va[1] != (short) 0xa000)
  47206. + abort ();
  47207. + else
  47208. + exit (0);
  47209. +}
  47210. +#else
  47211. +int main(){return 0;}
  47212. +#endif
  47213. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub64.c
  47214. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub64.c 1970-01-01 01:00:00.000000000 +0100
  47215. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub64.c 2016-08-08 20:37:53.562581991 +0200
  47216. @@ -0,0 +1,27 @@
  47217. +/* This is a test program for rsub64 instruction. */
  47218. +
  47219. +/* { dg-do run } */
  47220. +
  47221. +#include <nds32_intrinsic.h>
  47222. +#include <stdlib.h>
  47223. +
  47224. +#ifdef __NDS32_EXT_DSP__
  47225. +static __attribute__ ((noinline))
  47226. +long long rsub64 (long long ra, long long rb)
  47227. +{
  47228. + return __nds32__rsub64 (ra, rb);
  47229. +}
  47230. +
  47231. +int
  47232. +main ()
  47233. +{
  47234. + long long a = rsub64 (0xe, 0xf);
  47235. +
  47236. + if (a != 0xffffffffffffffff)
  47237. + abort ();
  47238. + else
  47239. + exit (0);
  47240. +}
  47241. +#else
  47242. +int main(){return 0;}
  47243. +#endif
  47244. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub8.c
  47245. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub8.c 1970-01-01 01:00:00.000000000 +0100
  47246. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsub8.c 2016-08-08 20:37:53.562581991 +0200
  47247. @@ -0,0 +1,40 @@
  47248. +/* This is a test program for rsub8 instruction. */
  47249. +
  47250. +/* { dg-do run } */
  47251. +
  47252. +#include <nds32_intrinsic.h>
  47253. +#include <stdlib.h>
  47254. +
  47255. +#ifdef __NDS32_EXT_DSP__
  47256. +static __attribute__ ((noinline))
  47257. +unsigned int rsub8 (unsigned int ra, unsigned int rb)
  47258. +{
  47259. + return __nds32__rsub8 (ra, rb);
  47260. +}
  47261. +
  47262. +static __attribute__ ((noinline))
  47263. +int8x4_t v_rsub8 (int8x4_t ra, int8x4_t rb)
  47264. +{
  47265. + return __nds32__v_rsub8 (ra, rb);
  47266. +}
  47267. +
  47268. +int
  47269. +main ()
  47270. +{
  47271. + unsigned int a = rsub8 (0x55667788, 0x11223344);
  47272. + int8x4_t va = v_rsub8 ((int8x4_t) {0x7f, 0x80, 0x80, 0xaa},
  47273. + (int8x4_t) {0x80, 0x7f, 0x40, 0xaa});
  47274. +
  47275. + if (a != 0x222222a2)
  47276. + abort ();
  47277. + else if (va[0] != 0x7f
  47278. + || va[1] != (char) 0x80
  47279. + || va[2] != (char) 0xa0
  47280. + || va[3] != 0)
  47281. + abort ();
  47282. + else
  47283. + exit (0);
  47284. +}
  47285. +#else
  47286. +int main(){return 0;}
  47287. +#endif
  47288. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsubw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsubw.c
  47289. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsubw.c 1970-01-01 01:00:00.000000000 +0100
  47290. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-rsubw.c 2016-08-08 20:37:53.562581991 +0200
  47291. @@ -0,0 +1,27 @@
  47292. +/* This is a test program for rsubw instruction. */
  47293. +
  47294. +/* { dg-do run } */
  47295. +
  47296. +#include <nds32_intrinsic.h>
  47297. +#include <stdlib.h>
  47298. +
  47299. +#ifdef __NDS32_EXT_DSP__
  47300. +static __attribute__ ((noinline))
  47301. +int rsubw (int ra, int rb)
  47302. +{
  47303. + return __nds32__rsubw (ra, rb);
  47304. +}
  47305. +
  47306. +int
  47307. +main ()
  47308. +{
  47309. + int a = rsubw (0x80000000, 0x7fffffff);
  47310. +
  47311. + if (a != 0x80000000)
  47312. + abort ();
  47313. + else
  47314. + exit (0);
  47315. +}
  47316. +#else
  47317. +int main(){return 0;}
  47318. +#endif
  47319. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple16.c
  47320. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple16.c 1970-01-01 01:00:00.000000000 +0100
  47321. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple16.c 2016-08-08 20:37:53.562581991 +0200
  47322. @@ -0,0 +1,37 @@
  47323. +/* This is a test program for scmple16 instruction. */
  47324. +
  47325. +/* { dg-do run } */
  47326. +
  47327. +#include <nds32_intrinsic.h>
  47328. +#include <stdlib.h>
  47329. +
  47330. +#ifdef __NDS32_EXT_DSP__
  47331. +static __attribute__ ((noinline))
  47332. +unsigned int scmple16 (unsigned int ra, unsigned int rb)
  47333. +{
  47334. + return __nds32__scmple16 (ra, rb);
  47335. +}
  47336. +
  47337. +static __attribute__ ((noinline))
  47338. +uint16x2_t v_scmple16 (int16x2_t ra, int16x2_t rb)
  47339. +{
  47340. + return __nds32__v_scmple16 (ra, rb);
  47341. +}
  47342. +
  47343. +int
  47344. +main ()
  47345. +{
  47346. + unsigned int a = scmple16 (0xfffe0001, 0xffff0000);
  47347. + uint16x2_t va = v_scmple16 ((int16x2_t) {0x7fff, 0x7ffe},
  47348. + (int16x2_t) {0x7ffe, 0x7fff});
  47349. + if (a != 0xffff0000)
  47350. + abort ();
  47351. + else if (va[0] != 0
  47352. + || va[1] != 0xffff)
  47353. + abort ();
  47354. + else
  47355. + exit (0);
  47356. +}
  47357. +#else
  47358. +int main(){return 0;}
  47359. +#endif
  47360. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple8.c
  47361. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple8.c 1970-01-01 01:00:00.000000000 +0100
  47362. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmple8.c 2016-08-08 20:37:53.562581991 +0200
  47363. @@ -0,0 +1,40 @@
  47364. +/* This is a test program for scmple8 instruction. */
  47365. +
  47366. +/* { dg-do run } */
  47367. +
  47368. +#include <nds32_intrinsic.h>
  47369. +#include <stdlib.h>
  47370. +
  47371. +#ifdef __NDS32_EXT_DSP__
  47372. +static __attribute__ ((noinline))
  47373. +unsigned int scmple8 (unsigned int ra, unsigned int rb)
  47374. +{
  47375. + return __nds32__scmple8 (ra, rb);
  47376. +}
  47377. +
  47378. +static __attribute__ ((noinline))
  47379. +uint8x4_t v_scmple8 (int8x4_t ra, int8x4_t rb)
  47380. +{
  47381. + return __nds32__v_scmple8 (ra, rb);
  47382. +}
  47383. +
  47384. +int
  47385. +main ()
  47386. +{
  47387. + unsigned int a = scmple8 (0xfefe0101, 0xffff0000);
  47388. + uint8x4_t va = v_scmple8 ((int8x4_t) {0x7e, 0x7e, 0x01, 0x01},
  47389. + (int8x4_t) {0x7f, 0x7f, 0x00, 0x00});
  47390. +
  47391. + if (a != 0xffff0000)
  47392. + abort ();
  47393. + else if (va[0] != 0xff
  47394. + || va[1] != 0xff
  47395. + || va[2] != 0
  47396. + || va[3] != 0)
  47397. + abort ();
  47398. + else
  47399. + exit (0);
  47400. +}
  47401. +#else
  47402. +int main(){return 0;}
  47403. +#endif
  47404. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt16.c
  47405. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt16.c 1970-01-01 01:00:00.000000000 +0100
  47406. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt16.c 2016-08-08 20:37:53.562581991 +0200
  47407. @@ -0,0 +1,38 @@
  47408. +/* This is a test program for scmplt16 instruction. */
  47409. +
  47410. +/* { dg-do run } */
  47411. +
  47412. +#include <nds32_intrinsic.h>
  47413. +#include <stdlib.h>
  47414. +
  47415. +#ifdef __NDS32_EXT_DSP__
  47416. +static __attribute__ ((noinline))
  47417. +unsigned int scmplt16 (unsigned int ra, unsigned int rb)
  47418. +{
  47419. + return __nds32__scmplt16 (ra, rb);
  47420. +}
  47421. +
  47422. +static __attribute__ ((noinline))
  47423. +uint16x2_t v_scmplt16 (int16x2_t ra, int16x2_t rb)
  47424. +{
  47425. + return __nds32__v_scmplt16 (ra, rb);
  47426. +}
  47427. +
  47428. +int
  47429. +main ()
  47430. +{
  47431. + unsigned int a = scmplt16 (0xfffe0001, 0xffff0000);
  47432. + uint16x2_t va = v_scmplt16 ((int16x2_t) {0x7fff, 0x7ffe},
  47433. + (int16x2_t) {0x7ffe, 0x7fff});
  47434. +
  47435. + if (a != 0xffff0000)
  47436. + abort ();
  47437. + else if (va[0] != 0
  47438. + || va[1] != 0xffff)
  47439. + abort ();
  47440. + else
  47441. + exit (0);
  47442. +}
  47443. +#else
  47444. +int main(){return 0;}
  47445. +#endif
  47446. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt8.c
  47447. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt8.c 1970-01-01 01:00:00.000000000 +0100
  47448. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-scmplt8.c 2016-08-08 20:37:53.562581991 +0200
  47449. @@ -0,0 +1,40 @@
  47450. +/* This is a test program for scmplt8 instruction. */
  47451. +
  47452. +/* { dg-do run } */
  47453. +
  47454. +#include <nds32_intrinsic.h>
  47455. +#include <stdlib.h>
  47456. +
  47457. +#ifdef __NDS32_EXT_DSP__
  47458. +static __attribute__ ((noinline))
  47459. +unsigned int scmplt8 (unsigned int ra, unsigned int rb)
  47460. +{
  47461. + return __nds32__scmplt8 (ra, rb);
  47462. +}
  47463. +
  47464. +static __attribute__ ((noinline))
  47465. +uint8x4_t v_scmplt8 (int8x4_t ra, int8x4_t rb)
  47466. +{
  47467. + return __nds32__v_scmplt8 (ra, rb);
  47468. +}
  47469. +
  47470. +int
  47471. +main ()
  47472. +{
  47473. + unsigned int a = scmplt8 (0xfefe0101, 0xffff0000);
  47474. + uint8x4_t va = v_scmplt8 ((int8x4_t) {0x7e, 0x7e, 0x01, 0x01},
  47475. + (int8x4_t) {0x7f, 0x7f, 0x00, 0x00});
  47476. +
  47477. + if (a != 0xffff0000)
  47478. + abort ();
  47479. + else if (va[0] != 0xff
  47480. + || va[1] != 0xff
  47481. + || va[2] != 0
  47482. + || va[3] != 0)
  47483. + abort ();
  47484. + else
  47485. + exit (0);
  47486. +}
  47487. +#else
  47488. +int main(){return 0;}
  47489. +#endif
  47490. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sll16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sll16.c
  47491. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sll16.c 1970-01-01 01:00:00.000000000 +0100
  47492. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sll16.c 2016-08-08 20:37:53.562581991 +0200
  47493. @@ -0,0 +1,37 @@
  47494. +/* This is a test program for sll16 instruction. */
  47495. +
  47496. +/* { dg-do run } */
  47497. +
  47498. +#include <nds32_intrinsic.h>
  47499. +#include <stdlib.h>
  47500. +
  47501. +#ifdef __NDS32_EXT_DSP__
  47502. +static __attribute__ ((noinline))
  47503. +unsigned int sll16 (unsigned int ra, unsigned int rb)
  47504. +{
  47505. + return __nds32__sll16 (ra, rb);
  47506. +}
  47507. +
  47508. +static __attribute__ ((noinline))
  47509. +uint16x2_t v_sll16 (uint16x2_t ra, unsigned int rb)
  47510. +{
  47511. + return __nds32__v_sll16 (ra, rb);
  47512. +}
  47513. +
  47514. +int
  47515. +main ()
  47516. +{
  47517. + unsigned int a = sll16 (0x0f00f000, 4);
  47518. + uint16x2_t va = v_sll16 ((uint16x2_t) {0x7fff, 0x8000}, 4);
  47519. +
  47520. + if (a != 0xf0000000)
  47521. + abort ();
  47522. + else if (va[0] != 0xfff0
  47523. + || va[1] != 0)
  47524. + abort ();
  47525. + else
  47526. + exit (0);
  47527. +}
  47528. +#else
  47529. +int main(){return 0;}
  47530. +#endif
  47531. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbb.c
  47532. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbb.c 1970-01-01 01:00:00.000000000 +0100
  47533. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbb.c 2016-08-08 20:37:53.562581991 +0200
  47534. @@ -0,0 +1,45 @@
  47535. +/* This is a test program for smalbb instruction. */
  47536. +
  47537. +/* { dg-do run } */
  47538. +
  47539. +#include <nds32_intrinsic.h>
  47540. +#include <stdlib.h>
  47541. +
  47542. +#ifdef __NDS32_EXT_DSP__
  47543. +static __attribute__ ((noinline))
  47544. +long long smalbb (long long t, unsigned int a, unsigned int b)
  47545. +{
  47546. + return __nds32__smalbb (t, a, b);
  47547. +}
  47548. +
  47549. +static __attribute__ ((noinline))
  47550. +long long v_smalbb (long long t, int16x2_t a, int16x2_t b)
  47551. +{
  47552. + return __nds32__v_smalbb (t, a, b);
  47553. +}
  47554. +
  47555. +
  47556. +int
  47557. +main ()
  47558. +{
  47559. +#ifdef __NDS32_EL__
  47560. + long long a_p = 0x12345679075ca9d3ll;
  47561. + long long va_p = 0x12345679075ca9d3ll;
  47562. +#else
  47563. + long long a_p = 0x12345679075ca9d3ll;
  47564. + long long va_p = 0x12345678ffffffffll;
  47565. +#endif
  47566. +
  47567. + long long a = smalbb (0x12345678ffffffffll,0x00006789, 0x00001234);
  47568. + long long va = v_smalbb (0x12345678ffffffffll, (int16x2_t) {0x6789, 0},
  47569. + (int16x2_t) {0x1234, 0});
  47570. + if (a != a_p)
  47571. + abort ();
  47572. + else if (va != va_p)
  47573. + abort ();
  47574. + else
  47575. + exit (0);
  47576. +}
  47577. +#else
  47578. +int main(){return 0;}
  47579. +#endif
  47580. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbt.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbt.c
  47581. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbt.c 1970-01-01 01:00:00.000000000 +0100
  47582. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalbt.c 2016-08-08 20:37:53.562581991 +0200
  47583. @@ -0,0 +1,45 @@
  47584. +/* This is a test program for smalbt instruction. */
  47585. +
  47586. +/* { dg-do run } */
  47587. +
  47588. +#include <nds32_intrinsic.h>
  47589. +#include <stdlib.h>
  47590. +
  47591. +#ifdef __NDS32_EXT_DSP__
  47592. +static __attribute__ ((noinline))
  47593. +long long smalbt (long long t, unsigned int a, unsigned int b)
  47594. +{
  47595. + return __nds32__smalbt (t, a, b);
  47596. +}
  47597. +
  47598. +static __attribute__ ((noinline))
  47599. +long long v_smalbt (long long t, int16x2_t a, int16x2_t b)
  47600. +{
  47601. + return __nds32__v_smalbt (t, a, b);
  47602. +}
  47603. +
  47604. +
  47605. +int
  47606. +main ()
  47607. +{
  47608. +#ifdef __NDS32_EL__
  47609. + long long a_p = 0x12345679075ca9d3ll;
  47610. + long long va_p = 0x12345679075ca9d3ll;
  47611. +#else
  47612. + long long a_p = 0x12345679075ca9d3ll;
  47613. + long long va_p = 0x12345678ffffffffll;
  47614. +#endif
  47615. +
  47616. + long long a = smalbt (0x12345678ffffffffll, 0x00006789, 0x12340000);
  47617. + long long va = v_smalbt (0x12345678ffffffffll, (int16x2_t) {0x6789, 0},
  47618. + (int16x2_t) {0, 0x1234});
  47619. + if (a != a_p)
  47620. + abort ();
  47621. + else if (va != va_p)
  47622. + abort ();
  47623. + else
  47624. + exit (0);
  47625. +}
  47626. +#else
  47627. +int main(){return 0;}
  47628. +#endif
  47629. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smal.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smal.c
  47630. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smal.c 1970-01-01 01:00:00.000000000 +0100
  47631. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smal.c 2016-08-08 20:37:53.562581991 +0200
  47632. @@ -0,0 +1,36 @@
  47633. +/* This is a test program for smal instruction. */
  47634. +
  47635. +/* { dg-do run } */
  47636. +
  47637. +#include <nds32_intrinsic.h>
  47638. +#include <stdlib.h>
  47639. +
  47640. +#ifdef __NDS32_EXT_DSP__
  47641. +static __attribute__ ((noinline))
  47642. +long long smal (long long ra, unsigned int rb)
  47643. +{
  47644. + return __nds32__smal (ra, rb);
  47645. +}
  47646. +
  47647. +static __attribute__ ((noinline))
  47648. +long long v_smal (long long ra, int16x2_t rb)
  47649. +{
  47650. + return __nds32__v_smal (ra, rb);
  47651. +}
  47652. +
  47653. +int
  47654. +main ()
  47655. +{
  47656. + long long a = smal (0xfffff0000ll, 0x0001ffff);
  47657. + long long va = v_smal (0xffffff0000ll,
  47658. + (int16x2_t) {0x0002, 0xffff});
  47659. + if (a != 0xffffeffffll)
  47660. + abort ();
  47661. + else if (va != 0xfffffefffell)
  47662. + abort ();
  47663. + else
  47664. + exit (0);
  47665. +}
  47666. +#else
  47667. +int main(){return 0;}
  47668. +#endif
  47669. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalda.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalda.c
  47670. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalda.c 1970-01-01 01:00:00.000000000 +0100
  47671. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalda.c 2016-08-08 20:37:53.562581991 +0200
  47672. @@ -0,0 +1,38 @@
  47673. +/* This is a test program for smalda instruction. */
  47674. +
  47675. +/* { dg-do run } */
  47676. +
  47677. +#include <nds32_intrinsic.h>
  47678. +#include <stdlib.h>
  47679. +
  47680. +#ifdef __NDS32_EXT_DSP__
  47681. +static __attribute__ ((noinline))
  47682. +long long smalda (long long t, unsigned int a, unsigned int b)
  47683. +{
  47684. + return __nds32__smalda (t, a, b);
  47685. +}
  47686. +
  47687. +static __attribute__ ((noinline))
  47688. +long long v_smalda (long long t, int16x2_t a, int16x2_t b)
  47689. +{
  47690. + return __nds32__v_smalda (t, a, b);
  47691. +}
  47692. +
  47693. +
  47694. +int
  47695. +main ()
  47696. +{
  47697. + long long a = smalda (0x12345678ffffffffll, 0x67890000, 0x12340000);
  47698. + long long va = v_smalda (0x12345678ffffffffll, (int16x2_t) {0, 0x6789},
  47699. + (int16x2_t) {0, 0x1234});
  47700. +
  47701. + if (a != 0x12345679075CA9D3ll)
  47702. + abort ();
  47703. + else if (va != 0x12345679075CA9D3ll)
  47704. + abort ();
  47705. + else
  47706. + exit (0);
  47707. +}
  47708. +#else
  47709. +int main(){return 0;}
  47710. +#endif
  47711. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaldrs.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaldrs.c
  47712. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaldrs.c 1970-01-01 01:00:00.000000000 +0100
  47713. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaldrs.c 2016-08-08 20:37:53.562581991 +0200
  47714. @@ -0,0 +1,46 @@
  47715. +/* This is a test program for smaldrs instruction. */
  47716. +
  47717. +/* { dg-do run } */
  47718. +
  47719. +#include <nds32_intrinsic.h>
  47720. +#include <stdlib.h>
  47721. +
  47722. +#ifdef __NDS32_EXT_DSP__
  47723. +static __attribute__ ((noinline))
  47724. +long long smaldrs (long long t, unsigned int a, unsigned int b)
  47725. +{
  47726. + return __nds32__smaldrs (t, a, b);
  47727. +}
  47728. +
  47729. +static __attribute__ ((noinline))
  47730. +long long v_smaldrs (long long t, int16x2_t a, int16x2_t b)
  47731. +{
  47732. + return __nds32__v_smaldrs (t, a, b);
  47733. +}
  47734. +
  47735. +
  47736. +int
  47737. +main ()
  47738. +{
  47739. +#ifdef __NDS32_EL__
  47740. + long long a_p = 0x12345678ffffaaaall;
  47741. + long long va_p = 0x12345678ffffaaaall;
  47742. +#else
  47743. + long long a_p = 0x12345678ffffaaaall;
  47744. + long long va_p = 0x1234567900005554ll;
  47745. +#endif
  47746. +
  47747. + long long a = smaldrs (0x12345678ffffffffll, 0x67890001, 0x00011234);
  47748. + long long va = v_smaldrs (0x12345678ffffffffll, (int16x2_t) {0x0001, 0x6789},
  47749. + (int16x2_t) {0x1234, 0x0001});
  47750. +
  47751. + if (a != a_p)
  47752. + abort ();
  47753. + else if (va != va_p)
  47754. + abort ();
  47755. + else
  47756. + exit (0);
  47757. +}
  47758. +#else
  47759. +int main(){return 0;}
  47760. +#endif
  47761. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalds.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalds.c
  47762. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalds.c 1970-01-01 01:00:00.000000000 +0100
  47763. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalds.c 2016-08-08 20:37:53.562581991 +0200
  47764. @@ -0,0 +1,46 @@
  47765. +/* This is a test program for smalds instruction. */
  47766. +
  47767. +/* { dg-do run } */
  47768. +
  47769. +#include <nds32_intrinsic.h>
  47770. +#include <stdlib.h>
  47771. +
  47772. +#ifdef __NDS32_EXT_DSP__
  47773. +static __attribute__ ((noinline))
  47774. +long long smalds (long long t, unsigned int a, unsigned int b)
  47775. +{
  47776. + return __nds32__smalds (t, a, b);
  47777. +}
  47778. +
  47779. +static __attribute__ ((noinline))
  47780. +long long v_smalds (long long t, int16x2_t a, int16x2_t b)
  47781. +{
  47782. + return __nds32__v_smalds (t, a, b);
  47783. +}
  47784. +
  47785. +
  47786. +int
  47787. +main ()
  47788. +{
  47789. +#ifdef __NDS32_EL__
  47790. + long long a_p = 0x12345678ffffaaaall;
  47791. + long long va_p = 0x12345678ffffaaaall;
  47792. +#else
  47793. + long long a_p = 0x12345678ffffaaaall;
  47794. + long long va_p = 0x1234567900005554ll;
  47795. +#endif
  47796. +
  47797. + long long a = smalds (0x12345678ffffffffll, 0x12340001, 0x00016789);
  47798. + long long va = v_smalds (0x12345678ffffffffll, (int16x2_t) {0x0001, 0x1234},
  47799. + (int16x2_t) {0x6789, 0x0001});
  47800. +
  47801. + if (a != a_p)
  47802. + abort ();
  47803. + else if (va != va_p)
  47804. + abort ();
  47805. + else
  47806. + exit (0);
  47807. +}
  47808. +#else
  47809. +int main(){return 0;}
  47810. +#endif
  47811. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaltt.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaltt.c
  47812. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaltt.c 1970-01-01 01:00:00.000000000 +0100
  47813. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smaltt.c 2016-08-08 20:37:53.562581991 +0200
  47814. @@ -0,0 +1,46 @@
  47815. +/* This is a test program for smaltt instruction. */
  47816. +
  47817. +/* { dg-do run } */
  47818. +
  47819. +#include <nds32_intrinsic.h>
  47820. +#include <stdlib.h>
  47821. +
  47822. +#ifdef __NDS32_EXT_DSP__
  47823. +static __attribute__ ((noinline))
  47824. +long long smaltt (long long t, unsigned int a, unsigned int b)
  47825. +{
  47826. + return __nds32__smaltt (t, a, b);
  47827. +}
  47828. +
  47829. +static __attribute__ ((noinline))
  47830. +long long v_smaltt (long long t, int16x2_t a, int16x2_t b)
  47831. +{
  47832. + return __nds32__v_smaltt (t, a, b);
  47833. +}
  47834. +
  47835. +
  47836. +int
  47837. +main ()
  47838. +{
  47839. +#ifdef __NDS32_EL__
  47840. + long long a_p = 0x12345679075ca9d3ll;
  47841. + long long va_p = 0x12345679075ca9d3ll;
  47842. +#else
  47843. + long long a_p = 0x12345679075ca9d3ll;
  47844. + long long va_p = 0x12345678ffffffffll;
  47845. +#endif
  47846. +
  47847. + long long a = smaltt (0x12345678ffffffffll, 0x67890000, 0x12340000);
  47848. + long long va = v_smaltt (0x12345678ffffffffll, (int16x2_t) {0, 0x6789},
  47849. + (int16x2_t) {0, 0x1234});
  47850. +
  47851. + if (a != a_p)
  47852. + abort ();
  47853. + else if (va != va_p)
  47854. + abort ();
  47855. + else
  47856. + exit (0);
  47857. +}
  47858. +#else
  47859. +int main(){return 0;}
  47860. +#endif
  47861. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxda.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxda.c
  47862. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxda.c 1970-01-01 01:00:00.000000000 +0100
  47863. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxda.c 2016-08-08 20:37:53.562581991 +0200
  47864. @@ -0,0 +1,38 @@
  47865. +/* This is a test program for smalxda instruction. */
  47866. +
  47867. +/* { dg-do run } */
  47868. +
  47869. +#include <nds32_intrinsic.h>
  47870. +#include <stdlib.h>
  47871. +
  47872. +#ifdef __NDS32_EXT_DSP__
  47873. +static __attribute__ ((noinline))
  47874. +long long smalxda (long long t, unsigned int a, unsigned int b)
  47875. +{
  47876. + return __nds32__smalxda (t, a, b);
  47877. +}
  47878. +
  47879. +static __attribute__ ((noinline))
  47880. +long long v_smalxda (long long t, int16x2_t a, int16x2_t b)
  47881. +{
  47882. + return __nds32__v_smalxda (t, a, b);
  47883. +}
  47884. +
  47885. +
  47886. +int
  47887. +main ()
  47888. +{
  47889. + long long a = smalxda (0x12345678ffffffffll, 0x67890000, 0x00001234);
  47890. + long long va = v_smalxda (0x12345678ffffffffll, (int16x2_t) {0, 0x6789},
  47891. + (int16x2_t) {0x1234, 0});
  47892. +
  47893. + if (a != 0x12345679075CA9D3)
  47894. + abort ();
  47895. + else if (va != 0x12345679075CA9D3)
  47896. + abort ();
  47897. + else
  47898. + exit (0);
  47899. +}
  47900. +#else
  47901. +int main(){return 0;}
  47902. +#endif
  47903. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxds.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxds.c
  47904. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxds.c 1970-01-01 01:00:00.000000000 +0100
  47905. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smalxds.c 2016-08-08 20:37:53.562581991 +0200
  47906. @@ -0,0 +1,46 @@
  47907. +/* This is a test program for smalxds instruction. */
  47908. +
  47909. +/* { dg-do run } */
  47910. +
  47911. +#include <nds32_intrinsic.h>
  47912. +#include <stdlib.h>
  47913. +
  47914. +#ifdef __NDS32_EXT_DSP__
  47915. +static __attribute__ ((noinline))
  47916. +long long smalxds (long long t, unsigned int a, unsigned int b)
  47917. +{
  47918. + return __nds32__smalxds (t, a, b);
  47919. +}
  47920. +
  47921. +static __attribute__ ((noinline))
  47922. +long long v_smalxds (long long t, int16x2_t a, int16x2_t b)
  47923. +{
  47924. + return __nds32__v_smalxds (t, a, b);
  47925. +}
  47926. +
  47927. +
  47928. +int
  47929. +main ()
  47930. +{
  47931. +#ifdef __NDS32_EL__
  47932. + long long a_p = 0x12345678ffffaaaall;
  47933. + long long va_p = 0x12345678ffffaaaall;
  47934. +#else
  47935. + long long a_p = 0x12345678ffffaaaall;
  47936. + long long va_p = 0x1234567900005554ll;
  47937. +#endif
  47938. +
  47939. + long long a = smalxds (0x12345678ffffffffll, 0x12340001, 0x67890001);
  47940. + long long va = v_smalxds (0x12345678ffffffffll, (int16x2_t) {0x0001, 0x1234},
  47941. + (int16x2_t) {0x0001, 0x6789});
  47942. +
  47943. + if (a != a_p)
  47944. + abort ();
  47945. + else if (va != va_p)
  47946. + abort ();
  47947. + else
  47948. + exit (0);
  47949. +}
  47950. +#else
  47951. +int main(){return 0;}
  47952. +#endif
  47953. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smar64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smar64.c
  47954. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smar64.c 1970-01-01 01:00:00.000000000 +0100
  47955. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smar64.c 2016-08-08 20:37:53.562581991 +0200
  47956. @@ -0,0 +1,27 @@
  47957. +/* This is a test program for smar64 instruction. */
  47958. +
  47959. +/* { dg-do run } */
  47960. +
  47961. +#include <nds32_intrinsic.h>
  47962. +#include <stdlib.h>
  47963. +
  47964. +#ifdef __NDS32_EXT_DSP__
  47965. +static __attribute__ ((noinline))
  47966. +long long smar64 (long long t, int a, int b)
  47967. +{
  47968. + return __nds32__smar64 (t, a, b);
  47969. +}
  47970. +
  47971. +int
  47972. +main ()
  47973. +{
  47974. + long long a = smar64 (0xf000000000000000ll, 0x12345678, 0x23);
  47975. +
  47976. + if (a != 0xf00000027d27d268ll)
  47977. + abort ();
  47978. + else
  47979. + exit (0);
  47980. +}
  47981. +#else
  47982. +int main(){return 0;}
  47983. +#endif
  47984. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax16.c
  47985. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax16.c 1970-01-01 01:00:00.000000000 +0100
  47986. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax16.c 2016-08-08 20:37:53.562581991 +0200
  47987. @@ -0,0 +1,37 @@
  47988. +/* This is a test program for smax16 instruction. */
  47989. +
  47990. +/* { dg-do run } */
  47991. +
  47992. +#include <nds32_intrinsic.h>
  47993. +#include <stdlib.h>
  47994. +
  47995. +#ifdef __NDS32_EXT_DSP__
  47996. +static __attribute__ ((noinline))
  47997. +unsigned int smax16 (unsigned int ra, unsigned int rb)
  47998. +{
  47999. + return __nds32__smax16 (ra, rb);
  48000. +}
  48001. +
  48002. +static __attribute__ ((noinline))
  48003. +int16x2_t v_smax16 (int16x2_t ra, int16x2_t rb)
  48004. +{
  48005. + return __nds32__v_smax16 (ra, rb);
  48006. +}
  48007. +
  48008. +int
  48009. +main ()
  48010. +{
  48011. + unsigned int a = smax16 (0xfffe0001, 0xffff0000);
  48012. + int16x2_t va = v_smax16 ((int16x2_t) {0x7fff, 0},
  48013. + (int16x2_t) {0x7ffe, 1});
  48014. + if (a != 0xffff0001)
  48015. + abort ();
  48016. + else if (va[0] != 0x7fff
  48017. + || va[1] != 1)
  48018. + abort ();
  48019. + else
  48020. + exit (0);
  48021. +}
  48022. +#else
  48023. +int main(){return 0;}
  48024. +#endif
  48025. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax8.c
  48026. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax8.c 1970-01-01 01:00:00.000000000 +0100
  48027. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smax8.c 2016-08-08 20:37:53.562581991 +0200
  48028. @@ -0,0 +1,41 @@
  48029. +/* This is a test program for smax8 instruction. */
  48030. +
  48031. +/* { dg-do run } */
  48032. +
  48033. +#include <nds32_intrinsic.h>
  48034. +#include <stdlib.h>
  48035. +
  48036. +#ifdef __NDS32_EXT_DSP__
  48037. +static __attribute__ ((noinline))
  48038. +unsigned int smax8 (unsigned int ra, unsigned int rb)
  48039. +{
  48040. + return __nds32__smax8 (ra, rb);
  48041. +}
  48042. +
  48043. +static __attribute__ ((noinline))
  48044. +int8x4_t v_smax8 (int8x4_t ra, int8x4_t rb)
  48045. +{
  48046. + return __nds32__v_smax8 (ra, rb);
  48047. +}
  48048. +
  48049. +
  48050. +int
  48051. +main ()
  48052. +{
  48053. + unsigned int a = smax8 (0xffff0000, 0xfefe0001);
  48054. + int8x4_t va = v_smax8 ((int8x4_t) {0x7f, 0x7f, 0x01, 0x01},
  48055. + (int8x4_t) {0x7e, 0x7e, 0x00, 0x00});
  48056. +
  48057. + if (a != 0xffff0001)
  48058. + abort ();
  48059. + else if (va[0] != 0x7f
  48060. + || va[1] != 0x7f
  48061. + || va[2] != 1
  48062. + || va[3] != 1)
  48063. + abort ();
  48064. + else
  48065. + exit (0);
  48066. +}
  48067. +#else
  48068. +int main(){return 0;}
  48069. +#endif
  48070. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbb.c
  48071. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbb.c 1970-01-01 01:00:00.000000000 +0100
  48072. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbb.c 2016-08-08 20:37:53.562581991 +0200
  48073. @@ -0,0 +1,44 @@
  48074. +/* This is a test program for smbb instruction. */
  48075. +
  48076. +/* { dg-do run } */
  48077. +
  48078. +#include <nds32_intrinsic.h>
  48079. +#include <stdlib.h>
  48080. +
  48081. +#ifdef __NDS32_EXT_DSP__
  48082. +static __attribute__ ((noinline))
  48083. +int smbb (unsigned int ra, unsigned int rb)
  48084. +{
  48085. + return __nds32__smbb (ra, rb);
  48086. +}
  48087. +
  48088. +static __attribute__ ((noinline))
  48089. +int v_smbb (int16x2_t ra, int16x2_t rb)
  48090. +{
  48091. + return __nds32__v_smbb (ra, rb);
  48092. +}
  48093. +
  48094. +int
  48095. +main ()
  48096. +{
  48097. +#ifdef __NDS32_EL__
  48098. + int va_p = 1;
  48099. +#else
  48100. + int va_p = 2;
  48101. +#endif
  48102. +
  48103. + int a = smbb (0x80000002, 0x80000001);
  48104. +
  48105. + int va = v_smbb ((int16x2_t) {0xffff, 0x0002},
  48106. + (int16x2_t) {0xffff, 0x0001});
  48107. +
  48108. + if (a != 2)
  48109. + abort ();
  48110. + else if (va != va_p)
  48111. + abort ();
  48112. + else
  48113. + exit (0);
  48114. +}
  48115. +#else
  48116. +int main(){return 0;}
  48117. +#endif
  48118. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbt.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbt.c
  48119. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbt.c 1970-01-01 01:00:00.000000000 +0100
  48120. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smbt.c 2016-08-08 20:37:53.562581991 +0200
  48121. @@ -0,0 +1,44 @@
  48122. +/* This is a test program for smbt instruction. */
  48123. +
  48124. +/* { dg-do run } */
  48125. +
  48126. +#include <nds32_intrinsic.h>
  48127. +#include <stdlib.h>
  48128. +
  48129. +#ifdef __NDS32_EXT_DSP__
  48130. +static __attribute__ ((noinline))
  48131. +int smbt (unsigned int ra, unsigned int rb)
  48132. +{
  48133. + return __nds32__smbt (ra, rb);
  48134. +}
  48135. +
  48136. +static __attribute__ ((noinline))
  48137. +int v_smbt (int16x2_t ra, int16x2_t rb)
  48138. +{
  48139. + return __nds32__v_smbt (ra, rb);
  48140. +}
  48141. +
  48142. +int
  48143. +main ()
  48144. +{
  48145. +#ifdef __NDS32_EL__
  48146. + int va_p = 0xffffffff;
  48147. +#else
  48148. + int va_p = 0xfffffffe;
  48149. +#endif
  48150. +
  48151. + int a = smbt (0x80000002, 0x80000001);
  48152. +
  48153. + int va = v_smbt ((int16x2_t) {0xffff, 0x0002},
  48154. + (int16x2_t) {0xffff, 0x0001});
  48155. +
  48156. + if (a != 0xffff0000)
  48157. + abort ();
  48158. + else if (va != va_p)
  48159. + abort ();
  48160. + else
  48161. + exit (0);
  48162. +}
  48163. +#else
  48164. +int main(){return 0;}
  48165. +#endif
  48166. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smdrs.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smdrs.c
  48167. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smdrs.c 1970-01-01 01:00:00.000000000 +0100
  48168. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smdrs.c 2016-08-08 20:37:53.562581991 +0200
  48169. @@ -0,0 +1,43 @@
  48170. +/* This is a test program for smdrs instruction. */
  48171. +
  48172. +/* { dg-do run } */
  48173. +
  48174. +#include <nds32_intrinsic.h>
  48175. +#include <stdlib.h>
  48176. +
  48177. +#ifdef __NDS32_EXT_DSP__
  48178. +static __attribute__ ((noinline))
  48179. +int smdrs (unsigned int ra, unsigned int rb)
  48180. +{
  48181. + return __nds32__smdrs (ra, rb);
  48182. +}
  48183. +
  48184. +static __attribute__ ((noinline))
  48185. +int v_smdrs (int16x2_t ra, int16x2_t rb)
  48186. +{
  48187. + return __nds32__v_smdrs (ra, rb);
  48188. +}
  48189. +
  48190. +int
  48191. +main ()
  48192. +{
  48193. +#ifdef __NDS32_EL__
  48194. + int va_p = 0xffffffff;
  48195. +#else
  48196. + int va_p = 1;
  48197. +#endif
  48198. +
  48199. + int a = smdrs (0x80000002, 0x80000001);
  48200. + int va = v_smdrs ((int16x2_t) {0xffff, 0x0002},
  48201. + (int16x2_t) {0xffff, 0x0001});
  48202. +
  48203. + if (a != 0xc0000002)
  48204. + abort ();
  48205. + else if (va != va_p)
  48206. + abort ();
  48207. + else
  48208. + exit (0);
  48209. +}
  48210. +#else
  48211. +int main(){return 0;}
  48212. +#endif
  48213. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smds.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smds.c
  48214. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smds.c 1970-01-01 01:00:00.000000000 +0100
  48215. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smds.c 2016-08-08 20:37:53.566582146 +0200
  48216. @@ -0,0 +1,43 @@
  48217. +/* This is a test program for smds instruction. */
  48218. +
  48219. +/* { dg-do run } */
  48220. +
  48221. +#include <nds32_intrinsic.h>
  48222. +#include <stdlib.h>
  48223. +
  48224. +#ifdef __NDS32_EXT_DSP__
  48225. +static __attribute__ ((noinline))
  48226. +int smds (unsigned int ra, unsigned int rb)
  48227. +{
  48228. + return __nds32__smds (ra, rb);
  48229. +}
  48230. +
  48231. +static __attribute__ ((noinline))
  48232. +int v_smds (int16x2_t ra, int16x2_t rb)
  48233. +{
  48234. + return __nds32__v_smds (ra, rb);
  48235. +}
  48236. +
  48237. +int
  48238. +main ()
  48239. +{
  48240. +#ifdef __NDS32_EL__
  48241. + int va_p = 1;
  48242. +#else
  48243. + int va_p = 0xffffffff;
  48244. +#endif
  48245. +
  48246. + int a = smds (0x80000002, 0x80000001);
  48247. + int va = v_smds ((int16x2_t) {0xffff, 0x0002},
  48248. + (int16x2_t) {0xffff, 0x0001});
  48249. +
  48250. + if (a != 0x3ffffffe)
  48251. + abort ();
  48252. + else if (va != va_p)
  48253. + abort ();
  48254. + else
  48255. + exit (0);
  48256. +}
  48257. +#else
  48258. +int main(){return 0;}
  48259. +#endif
  48260. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smin16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smin16.c
  48261. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smin16.c 1970-01-01 01:00:00.000000000 +0100
  48262. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smin16.c 2016-08-08 20:37:53.566582146 +0200
  48263. @@ -0,0 +1,37 @@
  48264. +/* This is a test program for smin16 instruction. */
  48265. +
  48266. +/* { dg-do run } */
  48267. +
  48268. +#include <nds32_intrinsic.h>
  48269. +#include <stdlib.h>
  48270. +
  48271. +#ifdef __NDS32_EXT_DSP__
  48272. +static __attribute__ ((noinline))
  48273. +unsigned int smin16 (unsigned int ra, unsigned int rb)
  48274. +{
  48275. + return __nds32__smin16 (ra, rb);
  48276. +}
  48277. +
  48278. +static __attribute__ ((noinline))
  48279. +int16x2_t v_smin16 (int16x2_t ra, int16x2_t rb)
  48280. +{
  48281. + return __nds32__v_smin16 (ra, rb);
  48282. +}
  48283. +
  48284. +int
  48285. +main ()
  48286. +{
  48287. + unsigned int a = smin16 (0xfffe0001, 0xffff0000);
  48288. + int16x2_t v_sa = v_smin16 ((int16x2_t) {0x7fff, 0},
  48289. + (int16x2_t) {0x7ffe, 1});
  48290. + if (a != 0xfffe0000)
  48291. + abort ();
  48292. + else if (v_sa[0] != 0x7ffe
  48293. + || v_sa[1] != 0)
  48294. + abort ();
  48295. + else
  48296. + exit (0);
  48297. +}
  48298. +#else
  48299. +int main(){return 0;}
  48300. +#endif
  48301. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmul.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmul.c
  48302. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmul.c 1970-01-01 01:00:00.000000000 +0100
  48303. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmul.c 2016-08-08 20:37:53.566582146 +0200
  48304. @@ -0,0 +1,27 @@
  48305. +/* This is a test program for smmul instruction. */
  48306. +
  48307. +/* { dg-do run } */
  48308. +
  48309. +#include <nds32_intrinsic.h>
  48310. +#include <stdlib.h>
  48311. +
  48312. +#ifdef __NDS32_EXT_DSP__
  48313. +static __attribute__ ((noinline))
  48314. +int smmul (int ra, int rb)
  48315. +{
  48316. + return __nds32__smmul (ra, rb);
  48317. +}
  48318. +
  48319. +int
  48320. +main ()
  48321. +{
  48322. + int a = smmul (0x80000000, 0x80000000);
  48323. +
  48324. + if (a != 0x40000000)
  48325. + abort ();
  48326. + else
  48327. + exit (0);
  48328. +}
  48329. +#else
  48330. +int main(){return 0;}
  48331. +#endif
  48332. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmulu.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmulu.c
  48333. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmulu.c 1970-01-01 01:00:00.000000000 +0100
  48334. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmulu.c 2016-08-08 20:37:53.566582146 +0200
  48335. @@ -0,0 +1,27 @@
  48336. +/* This is a test program for smmul.u instruction. */
  48337. +
  48338. +/* { dg-do run } */
  48339. +
  48340. +#include <nds32_intrinsic.h>
  48341. +#include <stdlib.h>
  48342. +
  48343. +#ifdef __NDS32_EXT_DSP__
  48344. +static __attribute__ ((noinline))
  48345. +int smmul_u (int ra, int rb)
  48346. +{
  48347. + return __nds32__smmul_u (ra, rb);
  48348. +}
  48349. +
  48350. +int
  48351. +main ()
  48352. +{
  48353. + int a = smmul_u (0x80000002, 0x80000001);
  48354. +
  48355. + if (a != 0x3fffffff)
  48356. + abort ();
  48357. + else
  48358. + exit (0);
  48359. +}
  48360. +#else
  48361. +int main(){return 0;}
  48362. +#endif
  48363. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwb.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwb.c
  48364. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwb.c 1970-01-01 01:00:00.000000000 +0100
  48365. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwb.c 2016-08-08 20:37:53.566582146 +0200
  48366. @@ -0,0 +1,43 @@
  48367. +/* This is a test program for smmwb instruction. */
  48368. +
  48369. +/* { dg-do run } */
  48370. +
  48371. +#include <nds32_intrinsic.h>
  48372. +#include <stdlib.h>
  48373. +
  48374. +#ifdef __NDS32_EXT_DSP__
  48375. +static __attribute__ ((noinline))
  48376. +int smmwb (int ra, unsigned int rb)
  48377. +{
  48378. + return __nds32__smmwb (ra, rb);
  48379. +}
  48380. +
  48381. +static __attribute__ ((noinline))
  48382. +int v_smmwb (int ra, int16x2_t rb)
  48383. +{
  48384. + return __nds32__v_smmwb (ra, rb);
  48385. +}
  48386. +
  48387. +int
  48388. +main ()
  48389. +{
  48390. +#ifdef __NDS32_EL__
  48391. + int va_p = 0;
  48392. +#else
  48393. + int va_p = 0xffffffff;
  48394. +#endif
  48395. +
  48396. + int a = smmwb (0x80000002, 0x80000001);
  48397. +
  48398. + int va = v_smmwb (0xffff0002, (int16x2_t) {0xffff, 0x0001});
  48399. +
  48400. + if (a != 0xffff8000)
  48401. + abort ();
  48402. + else if (va != va_p)
  48403. + abort ();
  48404. + else
  48405. + exit (0);
  48406. +}
  48407. +#else
  48408. +int main(){return 0;}
  48409. +#endif
  48410. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwbu.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwbu.c
  48411. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwbu.c 1970-01-01 01:00:00.000000000 +0100
  48412. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwbu.c 2016-08-08 20:37:53.566582146 +0200
  48413. @@ -0,0 +1,43 @@
  48414. +/* This is a test program for smmwb.u instruction. */
  48415. +
  48416. +/* { dg-do run } */
  48417. +
  48418. +#include <nds32_intrinsic.h>
  48419. +#include <stdlib.h>
  48420. +
  48421. +#ifdef __NDS32_EXT_DSP__
  48422. +static __attribute__ ((noinline))
  48423. +int smmwb_u (int ra, unsigned int rb)
  48424. +{
  48425. + return __nds32__smmwb_u (ra, rb);
  48426. +}
  48427. +
  48428. +static __attribute__ ((noinline))
  48429. +int v_smmwb_u (int ra, int16x2_t rb)
  48430. +{
  48431. + return __nds32__v_smmwb_u (ra, rb);
  48432. +}
  48433. +
  48434. +int
  48435. +main ()
  48436. +{
  48437. +#ifdef __NDS32_EL__
  48438. + int va_p = 1;
  48439. +#else
  48440. + int va_p = 0xffffffff;
  48441. +#endif
  48442. +
  48443. + int a = smmwb_u (0x80000002, 0x80000001);
  48444. +
  48445. + int va = v_smmwb_u (0xffff0002, (int16x2_t) {0xffff, 0x0001});
  48446. +
  48447. + if (a != 0xffff8000)
  48448. + abort ();
  48449. + else if (va != va_p)
  48450. + abort ();
  48451. + else
  48452. + exit (0);
  48453. +}
  48454. +#else
  48455. +int main(){return 0;}
  48456. +#endif
  48457. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwt.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwt.c
  48458. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwt.c 1970-01-01 01:00:00.000000000 +0100
  48459. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwt.c 2016-08-08 20:37:53.566582146 +0200
  48460. @@ -0,0 +1,43 @@
  48461. +/* This is a test program for smmwt instruction. */
  48462. +
  48463. +/* { dg-do run } */
  48464. +
  48465. +#include <nds32_intrinsic.h>
  48466. +#include <stdlib.h>
  48467. +
  48468. +#ifdef __NDS32_EXT_DSP__
  48469. +static __attribute__ ((noinline))
  48470. +int smmwt (int ra, unsigned int rb)
  48471. +{
  48472. + return __nds32__smmwt (ra, rb);
  48473. +}
  48474. +
  48475. +static __attribute__ ((noinline))
  48476. +int v_smmwt (int ra, int16x2_t rb)
  48477. +{
  48478. + return __nds32__v_smmwt (ra, rb);
  48479. +}
  48480. +
  48481. +int
  48482. +main ()
  48483. +{
  48484. +#ifdef __NDS32_EL__
  48485. + int va_p = 0xffffffff;
  48486. +#else
  48487. + int va_p = 0;
  48488. +#endif
  48489. +
  48490. + int a = smmwt (0x80000002, 0x80000001);
  48491. +
  48492. + int va = v_smmwt (0xffff0002, (int16x2_t) {0xffff, 0x0001});
  48493. +
  48494. + if (a != 0x3fffffff)
  48495. + abort ();
  48496. + else if (va != va_p)
  48497. + abort ();
  48498. + else
  48499. + exit (0);
  48500. +}
  48501. +#else
  48502. +int main(){return 0;}
  48503. +#endif
  48504. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwtu.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwtu.c
  48505. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwtu.c 1970-01-01 01:00:00.000000000 +0100
  48506. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smmwtu.c 2016-08-08 20:37:53.566582146 +0200
  48507. @@ -0,0 +1,43 @@
  48508. +/* This is a test program for smmwt.u instruction. */
  48509. +
  48510. +/* { dg-do run } */
  48511. +
  48512. +#include <nds32_intrinsic.h>
  48513. +#include <stdlib.h>
  48514. +
  48515. +#ifdef __NDS32_EXT_DSP__
  48516. +static __attribute__ ((noinline))
  48517. +int smmwt_u (int ra, unsigned int rb)
  48518. +{
  48519. + return __nds32__smmwt_u (ra, rb);
  48520. +}
  48521. +
  48522. +static __attribute__ ((noinline))
  48523. +int v_smmwt_u (int ra, int16x2_t rb)
  48524. +{
  48525. + return __nds32__v_smmwt_u (ra, rb);
  48526. +}
  48527. +
  48528. +int
  48529. +main ()
  48530. +{
  48531. +#ifdef __NDS32_EL__
  48532. + int va_p = 0xffffffff;
  48533. +#else
  48534. + int va_p = 1;
  48535. +#endif
  48536. +
  48537. + int a = smmwt_u (0x80000002, 0x80000001);
  48538. +
  48539. + int va = v_smmwt_u (0xffff0002, (int16x2_t) {0xffff, 0x0001});
  48540. +
  48541. + if (a != 0x3fffffff)
  48542. + abort ();
  48543. + else if (va != va_p)
  48544. + abort ();
  48545. + else
  48546. + exit (0);
  48547. +}
  48548. +#else
  48549. +int main(){return 0;}
  48550. +#endif
  48551. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslda.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslda.c
  48552. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslda.c 1970-01-01 01:00:00.000000000 +0100
  48553. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslda.c 2016-08-08 20:37:53.566582146 +0200
  48554. @@ -0,0 +1,37 @@
  48555. +/* This is a test program for smslda instruction. */
  48556. +
  48557. +/* { dg-do run } */
  48558. +
  48559. +#include <nds32_intrinsic.h>
  48560. +#include <stdlib.h>
  48561. +
  48562. +#ifdef __NDS32_EXT_DSP__
  48563. +static __attribute__ ((noinline))
  48564. +long long smslda (long long rt, unsigned int ra, unsigned int rb)
  48565. +{
  48566. + return __nds32__smslda (rt, ra, rb);
  48567. +}
  48568. +
  48569. +static __attribute__ ((noinline))
  48570. +long long v_smslda (long long rt, int16x2_t ra, int16x2_t rb)
  48571. +{
  48572. + return __nds32__v_smslda (rt, ra, rb);
  48573. +}
  48574. +
  48575. +int
  48576. +main ()
  48577. +{
  48578. + long long a = smslda (0xff0000000000ll, 0xffffffff, 0x2);
  48579. + long long va = v_smslda (0x100000000ll,
  48580. + (int16x2_t) {0xf000, 0}, (int16x2_t) {0, 3});
  48581. +
  48582. + if (a != 0xff0000000002ll)
  48583. + abort ();
  48584. + else if (va != 0x100000000ll)
  48585. + abort ();
  48586. + else
  48587. + exit (0);
  48588. +}
  48589. +#else
  48590. +int main(){return 0;}
  48591. +#endif
  48592. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslxda.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslxda.c
  48593. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslxda.c 1970-01-01 01:00:00.000000000 +0100
  48594. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smslxda.c 2016-08-08 20:37:53.566582146 +0200
  48595. @@ -0,0 +1,37 @@
  48596. +/* This is a test program for smslxda instruction. */
  48597. +
  48598. +/* { dg-do run } */
  48599. +
  48600. +#include <nds32_intrinsic.h>
  48601. +#include <stdlib.h>
  48602. +
  48603. +#ifdef __NDS32_EXT_DSP__
  48604. +static __attribute__ ((noinline))
  48605. +long long smslxda (long long rt, unsigned int ra, unsigned int rb)
  48606. +{
  48607. + return __nds32__smslxda (rt, ra, rb);
  48608. +}
  48609. +
  48610. +static __attribute__ ((noinline))
  48611. +long long v_smslxda (long long rt, int16x2_t ra, int16x2_t rb)
  48612. +{
  48613. + return __nds32__v_smslxda (rt, ra, rb);
  48614. +}
  48615. +
  48616. +int
  48617. +main ()
  48618. +{
  48619. + long long a = smslxda (0xff0000000000ll, 0xffffffff, 0x2);
  48620. + long long va = v_smslxda (0x100000000ll,
  48621. + (int16x2_t) {0xf000, 0}, (int16x2_t) {0, 3});
  48622. +
  48623. + if (a != 0xff0000000002ll)
  48624. + abort ();
  48625. + else if (va != 0x100003000ll)
  48626. + abort ();
  48627. + else
  48628. + exit (0);
  48629. +}
  48630. +#else
  48631. +int main(){return 0;}
  48632. +#endif
  48633. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smsr64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smsr64.c
  48634. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smsr64.c 1970-01-01 01:00:00.000000000 +0100
  48635. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smsr64.c 2016-08-08 20:37:53.566582146 +0200
  48636. @@ -0,0 +1,27 @@
  48637. +/* This is a test program for smsr64 instruction. */
  48638. +
  48639. +/* { dg-do run } */
  48640. +
  48641. +#include <nds32_intrinsic.h>
  48642. +#include <stdlib.h>
  48643. +
  48644. +#ifdef __NDS32_EXT_DSP__
  48645. +static __attribute__ ((noinline))
  48646. +long long smsr64 (long long t, int a, int b)
  48647. +{
  48648. + return __nds32__smsr64 (t, a, b);
  48649. +}
  48650. +
  48651. +int
  48652. +main ()
  48653. +{
  48654. + long long a = smsr64 (0x5000000300000000ll, 0x12345678, 0x23);
  48655. +
  48656. + if (a != 0x5000000082D82D98ll)
  48657. + abort ();
  48658. + else
  48659. + exit (0);
  48660. +}
  48661. +#else
  48662. +int main(){return 0;}
  48663. +#endif
  48664. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smtt.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smtt.c
  48665. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smtt.c 1970-01-01 01:00:00.000000000 +0100
  48666. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smtt.c 2016-08-08 20:37:53.566582146 +0200
  48667. @@ -0,0 +1,44 @@
  48668. +/* This is a test program for smtt instruction. */
  48669. +
  48670. +/* { dg-do run } */
  48671. +
  48672. +#include <nds32_intrinsic.h>
  48673. +#include <stdlib.h>
  48674. +
  48675. +#ifdef __NDS32_EXT_DSP__
  48676. +static __attribute__ ((noinline))
  48677. +int smtt (unsigned int ra, unsigned int rb)
  48678. +{
  48679. + return __nds32__smtt (ra, rb);
  48680. +}
  48681. +
  48682. +static __attribute__ ((noinline))
  48683. +int v_smtt (int16x2_t ra, int16x2_t rb)
  48684. +{
  48685. + return __nds32__v_smtt (ra, rb);
  48686. +}
  48687. +
  48688. +int
  48689. +main ()
  48690. +{
  48691. +#ifdef __NDS32_EL__
  48692. + int va_p = 2;
  48693. +#else
  48694. + int va_p = 1;
  48695. +#endif
  48696. +
  48697. + int a = smtt (0x80000002, 0x80000001);
  48698. +
  48699. + int va = v_smtt ((int16x2_t) {0xffff, 0x0002},
  48700. + (int16x2_t) {0xffff, 0x0001});
  48701. +
  48702. + if (a != 0x40000000)
  48703. + abort ();
  48704. + else if (va != va_p)
  48705. + abort ();
  48706. + else
  48707. + exit (0);
  48708. +}
  48709. +#else
  48710. +int main(){return 0;}
  48711. +#endif
  48712. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smul16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smul16.c
  48713. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smul16.c 1970-01-01 01:00:00.000000000 +0100
  48714. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smul16.c 2016-08-08 20:37:53.566582146 +0200
  48715. @@ -0,0 +1,38 @@
  48716. +/* This is a test program for smul16 instruction. */
  48717. +
  48718. +/* { dg-do run } */
  48719. +
  48720. +#include <nds32_intrinsic.h>
  48721. +#include <stdlib.h>
  48722. +
  48723. +#ifdef __NDS32_EXT_DSP__
  48724. +static __attribute__ ((noinline))
  48725. +unsigned long long smul16 (unsigned int ra, unsigned int rb)
  48726. +{
  48727. + return __nds32__smul16 (ra, rb);
  48728. +}
  48729. +
  48730. +static __attribute__ ((noinline))
  48731. +int32x2_t v_smul16 (int16x2_t ra, int16x2_t rb)
  48732. +{
  48733. + return __nds32__v_smul16 (ra, rb);
  48734. +}
  48735. +
  48736. +int
  48737. +main ()
  48738. +{
  48739. + unsigned long long a = smul16 (0xffff0000, 0x0001ffff);
  48740. + int32x2_t va = v_smul16 ((int16x2_t) {0xffff, 0},
  48741. + (int16x2_t) {0x0001, 0xffff});
  48742. +
  48743. + if (a != 0xffffffff00000000)
  48744. + abort ();
  48745. + else if (va[0] != 0xffffffff
  48746. + || va[1] != 0)
  48747. + abort ();
  48748. + else
  48749. + exit (0);
  48750. +}
  48751. +#else
  48752. +int main(){return 0;}
  48753. +#endif
  48754. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smulx16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smulx16.c
  48755. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smulx16.c 1970-01-01 01:00:00.000000000 +0100
  48756. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smulx16.c 2016-08-08 20:37:53.566582146 +0200
  48757. @@ -0,0 +1,37 @@
  48758. +/* This is a test program for smulx16 instruction. */
  48759. +
  48760. +/* { dg-do run } */
  48761. +
  48762. +#include <nds32_intrinsic.h>
  48763. +#include <stdlib.h>
  48764. +
  48765. +#ifdef __NDS32_EXT_DSP__
  48766. +static __attribute__ ((noinline))
  48767. +unsigned long long smulx16 (unsigned int ra, unsigned int rb)
  48768. +{
  48769. + return __nds32__smulx16 (ra, rb);
  48770. +}
  48771. +
  48772. +static __attribute__ ((noinline))
  48773. +int32x2_t v_smulx16 (int16x2_t ra, int16x2_t rb)
  48774. +{
  48775. + return __nds32__v_smulx16 (ra, rb);
  48776. +}
  48777. +
  48778. +int
  48779. +main ()
  48780. +{
  48781. + unsigned long long a = smulx16 (0xffff0000, 0xffff0001);
  48782. + int32x2_t va = v_smulx16 ((int16x2_t) {0xffff, 0xffff},
  48783. + (int16x2_t) {1, 0});
  48784. + if (a != 0xffffffff00000000)
  48785. + abort ();
  48786. + else if (va[0] != 0
  48787. + || va[1] != 0xffffffff)
  48788. + abort ();
  48789. + else
  48790. + exit (0);
  48791. +}
  48792. +#else
  48793. +int main(){return 0;}
  48794. +#endif
  48795. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smxds.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smxds.c
  48796. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smxds.c 1970-01-01 01:00:00.000000000 +0100
  48797. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-smxds.c 2016-08-08 20:37:53.566582146 +0200
  48798. @@ -0,0 +1,45 @@
  48799. +/* This is a test program for smxds instruction. */
  48800. +
  48801. +/* { dg-do run } */
  48802. +
  48803. +#include <nds32_intrinsic.h>
  48804. +#include <stdlib.h>
  48805. +
  48806. +#ifdef __NDS32_EXT_DSP__
  48807. +static __attribute__ ((noinline))
  48808. +int smxds (unsigned int ra, unsigned int rb)
  48809. +{
  48810. + return __nds32__smxds (ra, rb);
  48811. +}
  48812. +
  48813. +static __attribute__ ((noinline))
  48814. +int v_smxds (int16x2_t ra, int16x2_t rb)
  48815. +{
  48816. + return __nds32__v_smxds (ra, rb);
  48817. +}
  48818. +
  48819. +int
  48820. +main ()
  48821. +{
  48822. +#ifdef __NDS32_EL__
  48823. + int a_p = 0x8000;
  48824. + int va_p = 0xffffffff;
  48825. +#else
  48826. + int a_p = 0x8000;
  48827. + int va_p = 1;
  48828. +#endif
  48829. +
  48830. + int a = smxds (0x80000002, 0x80000001);
  48831. + int va = v_smxds ((int16x2_t) {0xffff, 0x0002},
  48832. + (int16x2_t) {0xffff, 0x0001});
  48833. +
  48834. + if (a != a_p)
  48835. + abort ();
  48836. + else if (va != va_p)
  48837. + abort ();
  48838. + else
  48839. + exit (0);
  48840. +}
  48841. +#else
  48842. +int main(){return 0;}
  48843. +#endif
  48844. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16.c
  48845. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16.c 1970-01-01 01:00:00.000000000 +0100
  48846. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16.c 2016-08-08 20:37:53.566582146 +0200
  48847. @@ -0,0 +1,37 @@
  48848. +/* This is a test program for sra16 instruction. */
  48849. +
  48850. +/* { dg-do run } */
  48851. +
  48852. +#include <nds32_intrinsic.h>
  48853. +#include <stdlib.h>
  48854. +
  48855. +#ifdef __NDS32_EXT_DSP__
  48856. +static __attribute__ ((noinline))
  48857. +unsigned int sra16 (unsigned int ra, unsigned int rb)
  48858. +{
  48859. + return __nds32__sra16 (ra, rb);
  48860. +}
  48861. +
  48862. +static __attribute__ ((noinline))
  48863. +int16x2_t v_sra16 (int16x2_t ra, unsigned int rb)
  48864. +{
  48865. + return __nds32__v_sra16 (ra, rb);
  48866. +}
  48867. +
  48868. +int
  48869. +main ()
  48870. +{
  48871. + unsigned int a = sra16 (0x0ffff000, 4);
  48872. + int16x2_t va = v_sra16 ((int16x2_t) {0x7fff, 0x8000}, 4);
  48873. +
  48874. + if (a != 0x00ffff00)
  48875. + abort ();
  48876. + else if (va[0] != 0x7ff
  48877. + || va[1] != (short) 0xf800)
  48878. + abort ();
  48879. + else
  48880. + exit (0);
  48881. +}
  48882. +#else
  48883. +int main(){return 0;}
  48884. +#endif
  48885. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16u.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16u.c
  48886. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16u.c 1970-01-01 01:00:00.000000000 +0100
  48887. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sra16u.c 2016-08-08 20:37:53.566582146 +0200
  48888. @@ -0,0 +1,37 @@
  48889. +/* This is a test program for sra16.u instruction. */
  48890. +
  48891. +/* { dg-do run } */
  48892. +
  48893. +#include <nds32_intrinsic.h>
  48894. +#include <stdlib.h>
  48895. +
  48896. +#ifdef __NDS32_EXT_DSP__
  48897. +static __attribute__ ((noinline))
  48898. +unsigned int sra16u (unsigned int ra, unsigned int rb)
  48899. +{
  48900. + return __nds32__sra16_u (ra, rb);
  48901. +}
  48902. +
  48903. +static __attribute__ ((noinline))
  48904. +int16x2_t v_sra16u (int16x2_t ra, unsigned int rb)
  48905. +{
  48906. + return __nds32__v_sra16_u (ra, rb);
  48907. +}
  48908. +
  48909. +int
  48910. +main ()
  48911. +{
  48912. + unsigned int a = sra16u (0x0ffff000, 4);
  48913. + int16x2_t va = v_sra16u ((int16x2_t) {0x7fff, 0x8000}, 4);
  48914. +
  48915. + if (a != 0x100ff00)
  48916. + abort ();
  48917. + else if (va[0] != 0x800
  48918. + || va[1] != (short) 0xf800)
  48919. + abort ();
  48920. + else
  48921. + exit (0);
  48922. +}
  48923. +#else
  48924. +int main(){return 0;}
  48925. +#endif
  48926. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16.c
  48927. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16.c 1970-01-01 01:00:00.000000000 +0100
  48928. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16.c 2016-08-08 20:37:53.566582146 +0200
  48929. @@ -0,0 +1,39 @@
  48930. +/* This is a test program for srai16 instruction. */
  48931. +
  48932. +/* { dg-do run } */
  48933. +
  48934. +#include <nds32_intrinsic.h>
  48935. +#include <stdlib.h>
  48936. +
  48937. +#ifdef __NDS32_EXT_DSP__
  48938. +static __attribute__ ((noinline))
  48939. +unsigned int srai16 (unsigned int ra)
  48940. +{
  48941. + return __nds32__sra16 (ra, 4);
  48942. +}
  48943. +
  48944. +static __attribute__ ((noinline))
  48945. +int16x2_t v_srai16 (int16x2_t ra)
  48946. +{
  48947. + return __nds32__v_sra16 (ra, 4);
  48948. +}
  48949. +
  48950. +int
  48951. +main ()
  48952. +{
  48953. + unsigned int a = srai16 (0x0ffff000);
  48954. +
  48955. + int16x2_t aa;
  48956. + int16x2_t va = v_srai16 ((int16x2_t) {0x7fff, 0x8000});
  48957. +
  48958. + if (a != 0x00ffff00)
  48959. + abort ();
  48960. + else if (va[0] != 0x7ff
  48961. + || va[1] != (short) 0xf800)
  48962. + abort ();
  48963. + else
  48964. + exit (0);
  48965. +}
  48966. +#else
  48967. +int main(){return 0;}
  48968. +#endif
  48969. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16u.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16u.c
  48970. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16u.c 1970-01-01 01:00:00.000000000 +0100
  48971. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srai16u.c 2016-08-08 20:37:53.566582146 +0200
  48972. @@ -0,0 +1,37 @@
  48973. +/* This is a test program for srai16.u instruction. */
  48974. +
  48975. +/* { dg-do run } */
  48976. +
  48977. +#include <nds32_intrinsic.h>
  48978. +#include <stdlib.h>
  48979. +
  48980. +#ifdef __NDS32_EXT_DSP__
  48981. +static __attribute__ ((noinline))
  48982. +unsigned int srai16u (unsigned int ra)
  48983. +{
  48984. + return __nds32__sra16_u (ra, 4);
  48985. +}
  48986. +
  48987. +static __attribute__ ((noinline))
  48988. +int16x2_t v_srai16u (int16x2_t ra)
  48989. +{
  48990. + return __nds32__v_sra16_u (ra, 4);
  48991. +}
  48992. +
  48993. +int
  48994. +main ()
  48995. +{
  48996. + unsigned int a = srai16u (0x0ffff000);
  48997. + int16x2_t va = v_srai16u ((int16x2_t) {0x7fff, 0x8000});
  48998. +
  48999. + if (a != 0x100ff00)
  49000. + abort ();
  49001. + else if (va[0] != 0x800
  49002. + || va[1] != (short) 0xf800)
  49003. + abort ();
  49004. + else
  49005. + exit (0);
  49006. +}
  49007. +#else
  49008. +int main(){return 0;}
  49009. +#endif
  49010. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sraiu.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sraiu.c
  49011. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sraiu.c 1970-01-01 01:00:00.000000000 +0100
  49012. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sraiu.c 2016-08-08 20:37:53.566582146 +0200
  49013. @@ -0,0 +1,27 @@
  49014. +/* This is a test program for srai.u instruction. */
  49015. +
  49016. +/* { dg-do run } */
  49017. +
  49018. +#include <nds32_intrinsic.h>
  49019. +#include <stdlib.h>
  49020. +
  49021. +#ifdef __NDS32_EXT_DSP__
  49022. +static __attribute__ ((noinline))
  49023. +int sraiu (int ra)
  49024. +{
  49025. + return __nds32__sra_u (ra, 8);
  49026. +}
  49027. +
  49028. +int
  49029. +main ()
  49030. +{
  49031. + int a = sraiu (0xf00ff);
  49032. +
  49033. + if (a != 0xf01)
  49034. + abort ();
  49035. + else
  49036. + exit (0);
  49037. +}
  49038. +#else
  49039. +int main(){return 0;}
  49040. +#endif
  49041. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srau.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srau.c
  49042. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srau.c 1970-01-01 01:00:00.000000000 +0100
  49043. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srau.c 2016-08-08 20:37:53.566582146 +0200
  49044. @@ -0,0 +1,27 @@
  49045. +/* This is a test program for sra.u instruction. */
  49046. +
  49047. +/* { dg-do run } */
  49048. +
  49049. +#include <nds32_intrinsic.h>
  49050. +#include <stdlib.h>
  49051. +
  49052. +#ifdef __NDS32_EXT_DSP__
  49053. +static __attribute__ ((noinline))
  49054. +int srau (int ra, unsigned int rb)
  49055. +{
  49056. + return __nds32__sra_u (ra, rb);
  49057. +}
  49058. +
  49059. +int
  49060. +main ()
  49061. +{
  49062. + int a = srau (0xf00ff, 8);
  49063. +
  49064. + if (a != 0xf01)
  49065. + abort ();
  49066. + else
  49067. + exit (0);
  49068. +}
  49069. +#else
  49070. +int main(){return 0;}
  49071. +#endif
  49072. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16.c
  49073. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16.c 1970-01-01 01:00:00.000000000 +0100
  49074. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16.c 2016-08-08 20:37:53.566582146 +0200
  49075. @@ -0,0 +1,37 @@
  49076. +/* This is a test program for srl16 instruction. */
  49077. +
  49078. +/* { dg-do run } */
  49079. +
  49080. +#include <nds32_intrinsic.h>
  49081. +#include <stdlib.h>
  49082. +
  49083. +#ifdef __NDS32_EXT_DSP__
  49084. +static __attribute__ ((noinline))
  49085. +unsigned int srl16 (unsigned int ra, unsigned int rb)
  49086. +{
  49087. + return __nds32__srl16 (ra, rb);
  49088. +}
  49089. +
  49090. +static __attribute__ ((noinline))
  49091. +uint16x2_t v_srl16 (uint16x2_t ra, unsigned int rb)
  49092. +{
  49093. + return __nds32__v_srl16 (ra, rb);
  49094. +}
  49095. +
  49096. +int
  49097. +main ()
  49098. +{
  49099. + unsigned int a = srl16 (0x0f00f000, 4);
  49100. + uint16x2_t va = v_srl16 ((uint16x2_t) {0x7fff, 0x8000}, 4);
  49101. +
  49102. + if (a != 0xf00f00)
  49103. + abort ();
  49104. + else if (va[0] != 0x7ff
  49105. + || va[1] != 0x0800)
  49106. + abort ();
  49107. + else
  49108. + exit (0);
  49109. +}
  49110. +#else
  49111. +int main(){return 0;}
  49112. +#endif
  49113. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16u.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16u.c
  49114. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16u.c 1970-01-01 01:00:00.000000000 +0100
  49115. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srl16u.c 2016-08-08 20:37:53.566582146 +0200
  49116. @@ -0,0 +1,37 @@
  49117. +/* This is a test program for srl16.u instruction. */
  49118. +
  49119. +/* { dg-do run } */
  49120. +
  49121. +#include <nds32_intrinsic.h>
  49122. +#include <stdlib.h>
  49123. +
  49124. +#ifdef __NDS32_EXT_DSP__
  49125. +static __attribute__ ((noinline))
  49126. +unsigned int srl16_u (unsigned int ra, unsigned int rb)
  49127. +{
  49128. + return __nds32__srl16_u (ra, rb);
  49129. +}
  49130. +
  49131. +static __attribute__ ((noinline))
  49132. +uint16x2_t v_srl16_u (uint16x2_t ra, unsigned int rb)
  49133. +{
  49134. + return __nds32__v_srl16_u (ra, rb);
  49135. +}
  49136. +
  49137. +int
  49138. +main ()
  49139. +{
  49140. + unsigned int a = srl16_u (0x0f00f000, 4);
  49141. + uint16x2_t va = v_srl16_u ((uint16x2_t) {0x7fff, 0x8000}, 4);
  49142. +
  49143. + if (a != 0xf00f00)
  49144. + abort ();
  49145. + else if (va[0] != 0x800
  49146. + || va[1] != 0x800)
  49147. + abort ();
  49148. + else
  49149. + exit (0);
  49150. +}
  49151. +#else
  49152. +int main(){return 0;}
  49153. +#endif
  49154. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16.c
  49155. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16.c 1970-01-01 01:00:00.000000000 +0100
  49156. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16.c 2016-08-08 20:37:53.566582146 +0200
  49157. @@ -0,0 +1,37 @@
  49158. +/* This is a test program for srli16 instruction. */
  49159. +
  49160. +/* { dg-do run } */
  49161. +
  49162. +#include <nds32_intrinsic.h>
  49163. +#include <stdlib.h>
  49164. +
  49165. +#ifdef __NDS32_EXT_DSP__
  49166. +static __attribute__ ((noinline))
  49167. +unsigned int srli16 (unsigned int ra)
  49168. +{
  49169. + return __nds32__srl16 (ra, 4);
  49170. +}
  49171. +
  49172. +static __attribute__ ((noinline))
  49173. +uint16x2_t v_srli16 (uint16x2_t ra)
  49174. +{
  49175. + return __nds32__v_srl16 (ra, 4);
  49176. +}
  49177. +
  49178. +int
  49179. +main ()
  49180. +{
  49181. + unsigned int a = srli16 (0x0f00f000);
  49182. + uint16x2_t va = v_srli16 ((uint16x2_t) {0x7fff, 0x8000});
  49183. +
  49184. + if (a != 0xf00f00)
  49185. + abort ();
  49186. + else if (va[0] != 0x7ff
  49187. + || va[1] != 0x0800)
  49188. + abort ();
  49189. + else
  49190. + exit (0);
  49191. +}
  49192. +#else
  49193. +int main(){return 0;}
  49194. +#endif
  49195. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16u.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16u.c
  49196. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16u.c 1970-01-01 01:00:00.000000000 +0100
  49197. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-srli16u.c 2016-08-08 20:37:53.566582146 +0200
  49198. @@ -0,0 +1,37 @@
  49199. +/* This is a test program for sril16.u instruction. */
  49200. +
  49201. +/* { dg-do run } */
  49202. +
  49203. +#include <nds32_intrinsic.h>
  49204. +#include <stdlib.h>
  49205. +
  49206. +#ifdef __NDS32_EXT_DSP__
  49207. +static __attribute__ ((noinline))
  49208. +unsigned int srli16_u (unsigned int ra)
  49209. +{
  49210. + return __nds32__srl16_u (ra, 4);
  49211. +}
  49212. +
  49213. +static __attribute__ ((noinline))
  49214. +uint16x2_t v_srli16_u (uint16x2_t ra)
  49215. +{
  49216. + return __nds32__v_srl16_u (ra, 4);
  49217. +}
  49218. +
  49219. +int
  49220. +main ()
  49221. +{
  49222. + unsigned int a = srli16_u (0x0f00f000);
  49223. + uint16x2_t va = v_srli16_u ((uint16x2_t) {0x7fff, 0x8000});
  49224. +
  49225. + if (a != 0xf00f00)
  49226. + abort ();
  49227. + else if (va[0] != 0x800
  49228. + || va[1] != 0x800)
  49229. + abort ();
  49230. + else
  49231. + exit (0);
  49232. +}
  49233. +#else
  49234. +int main(){return 0;}
  49235. +#endif
  49236. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub16.c
  49237. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub16.c 1970-01-01 01:00:00.000000000 +0100
  49238. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub16.c 2016-08-08 20:37:53.566582146 +0200
  49239. @@ -0,0 +1,49 @@
  49240. +/* This is a test program for sub16 instruction. */
  49241. +
  49242. +/* { dg-do run } */
  49243. +
  49244. +#include <nds32_intrinsic.h>
  49245. +#include <stdlib.h>
  49246. +
  49247. +#ifdef __NDS32_EXT_DSP__
  49248. +static __attribute__ ((noinline))
  49249. +unsigned int sub16 (unsigned int ra, unsigned int rb)
  49250. +{
  49251. + return __nds32__sub16 (ra, rb);
  49252. +}
  49253. +
  49254. +static __attribute__ ((noinline))
  49255. +uint16x2_t v_usub16 (uint16x2_t ra, uint16x2_t rb)
  49256. +{
  49257. + return __nds32__v_usub16 (ra, rb);
  49258. +}
  49259. +
  49260. +static __attribute__ ((noinline))
  49261. +int16x2_t v_ssub16 (int16x2_t ra, int16x2_t rb)
  49262. +{
  49263. + return __nds32__v_ssub16 (ra, rb);
  49264. +}
  49265. +
  49266. +int
  49267. +main ()
  49268. +{
  49269. + unsigned int a = sub16 (0x00010000, 0x00010001);
  49270. + uint16x2_t v_ua = v_usub16 ((uint16x2_t) {0x1000, 0x0001},
  49271. + (uint16x2_t) {0xf000, 0x0000});
  49272. + int16x2_t v_sa = v_ssub16 ((int16x2_t) {0x7777, 0x2111},
  49273. + (int16x2_t) {0x1000, 0x2000});
  49274. +
  49275. + if (a != 0x0000ffff)
  49276. + abort ();
  49277. + else if (v_ua[0] != 0x2000
  49278. + || v_ua[1] != 0x0001)
  49279. + abort ();
  49280. + else if (v_sa[0] != 0x6777
  49281. + || v_sa[1] != 0x0111)
  49282. + abort ();
  49283. + else
  49284. + exit (0);
  49285. +}
  49286. +#else
  49287. +int main(){return 0;}
  49288. +#endif
  49289. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub64.c
  49290. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub64.c 1970-01-01 01:00:00.000000000 +0100
  49291. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub64.c 2016-08-08 20:37:53.566582146 +0200
  49292. @@ -0,0 +1,36 @@
  49293. +/* This is a test program for sub64 instruction. */
  49294. +
  49295. +/* { dg-do run } */
  49296. +
  49297. +#include <nds32_intrinsic.h>
  49298. +#include <stdlib.h>
  49299. +
  49300. +#ifdef __NDS32_EXT_DSP__
  49301. +static __attribute__ ((noinline))
  49302. +long long ssub64 (long long ra, long long rb)
  49303. +{
  49304. + return __nds32__ssub64 (ra, rb);
  49305. +}
  49306. +
  49307. +static __attribute__ ((noinline))
  49308. +unsigned long long usub64 (unsigned long long ra, unsigned long long rb)
  49309. +{
  49310. + return __nds32__usub64 (ra, rb);
  49311. +}
  49312. +
  49313. +int
  49314. +main ()
  49315. +{
  49316. + long long sa = ssub64 (0x100000000ll, 0xffffffffll);
  49317. + unsigned long long ua = usub64 (0xf00000000ull, 0x1111ull);
  49318. +
  49319. + if (sa != 1ll)
  49320. + abort ();
  49321. + else if (ua != 0xeffffeeefull)
  49322. + abort ();
  49323. + else
  49324. + exit (0);
  49325. +}
  49326. +#else
  49327. +int main(){return 0;}
  49328. +#endif
  49329. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub8.c
  49330. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub8.c 1970-01-01 01:00:00.000000000 +0100
  49331. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sub8.c 2016-08-08 20:37:53.566582146 +0200
  49332. @@ -0,0 +1,53 @@
  49333. +/* This is a test program for sub8 instruction. */
  49334. +
  49335. +/* { dg-do run } */
  49336. +
  49337. +#include <nds32_intrinsic.h>
  49338. +#include <stdlib.h>
  49339. +
  49340. +#ifdef __NDS32_EXT_DSP__
  49341. +static __attribute__ ((noinline))
  49342. +unsigned int sub8 (unsigned int ra, unsigned int rb)
  49343. +{
  49344. + return __nds32__sub8 (ra, rb);
  49345. +}
  49346. +
  49347. +static __attribute__ ((noinline))
  49348. +uint8x4_t v_usub8 (uint8x4_t ra, uint8x4_t rb)
  49349. +{
  49350. + return __nds32__v_usub8 (ra, rb);
  49351. +}
  49352. +
  49353. +static __attribute__ ((noinline))
  49354. +int8x4_t v_ssub8 (int8x4_t ra, int8x4_t rb)
  49355. +{
  49356. + return __nds32__v_ssub8 (ra, rb);
  49357. +}
  49358. +
  49359. +int
  49360. +main ()
  49361. +{
  49362. + unsigned int a = sub8 (0x55667788, 0x11223344);
  49363. + uint8x4_t v_ua = v_usub8 ((uint8x4_t) {0xff, 0xee, 0xee, 0xcc},
  49364. + (uint8x4_t) {0x1, 0xee, 0xdd, 0xdd});
  49365. + int8x4_t v_sa = v_ssub8 ((int8x4_t) {0x81, 0x0, 0xdd, 0xaa},
  49366. + (int8x4_t) {0x80, 0x1, 0xcc, 0xaa});
  49367. +
  49368. + if (a != 0x44444444)
  49369. + abort ();
  49370. + else if (v_ua[0] != 0xfe
  49371. + || v_ua[1] != 0
  49372. + || v_ua[2] != 0x11
  49373. + || v_ua[3] != 0xef)
  49374. + abort ();
  49375. + else if (v_sa[0] != 1
  49376. + || v_sa[1] != (char) 0xff
  49377. + || v_sa[2] != 0x11
  49378. + || v_sa[3] != 0)
  49379. + abort ();
  49380. + else
  49381. + exit (0);
  49382. +}
  49383. +#else
  49384. +int main(){return 0;}
  49385. +#endif
  49386. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd810.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd810.c
  49387. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd810.c 1970-01-01 01:00:00.000000000 +0100
  49388. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd810.c 2016-08-08 20:37:53.566582146 +0200
  49389. @@ -0,0 +1,43 @@
  49390. +/* This is a test program for sunpkd810 instruction. */
  49391. +
  49392. +/* { dg-do run } */
  49393. +
  49394. +#include <nds32_intrinsic.h>
  49395. +#include <stdlib.h>
  49396. +
  49397. +#ifdef __NDS32_EXT_DSP__
  49398. +static __attribute__ ((noinline))
  49399. +unsigned int sunpkd810 (unsigned int a)
  49400. +{
  49401. + return __nds32__sunpkd810 (a);
  49402. +}
  49403. +
  49404. +static __attribute__ ((noinline))
  49405. +int16x2_t v_sunpkd810 (int8x4_t a)
  49406. +{
  49407. + return __nds32__v_sunpkd810 (a);
  49408. +}
  49409. +
  49410. +int
  49411. +main ()
  49412. +{
  49413. +#ifdef __NDS32_EL__
  49414. + int16x2_t va_p = {0xfff8, 0x56};
  49415. +#else
  49416. + int16x2_t va_p = {0, 0};
  49417. +#endif
  49418. +
  49419. + unsigned int a = sunpkd810 (0x000056f8);
  49420. + int16x2_t va = v_sunpkd810 ((int8x4_t) {0xf8, 0x56, 0, 0});
  49421. +
  49422. + if (a != 0x0056fff8)
  49423. + abort ();
  49424. + else if (va[0] != va_p[0]
  49425. + || va[1] != va_p[1])
  49426. + abort ();
  49427. + else
  49428. + exit (0);
  49429. +}
  49430. +#else
  49431. +int main(){return 0;}
  49432. +#endif
  49433. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd820.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd820.c
  49434. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd820.c 1970-01-01 01:00:00.000000000 +0100
  49435. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd820.c 2016-08-08 20:37:53.566582146 +0200
  49436. @@ -0,0 +1,43 @@
  49437. +/* This is a test program for sunpkd820 instruction. */
  49438. +
  49439. +/* { dg-do run } */
  49440. +
  49441. +#include <nds32_intrinsic.h>
  49442. +#include <stdlib.h>
  49443. +
  49444. +#ifdef __NDS32_EXT_DSP__
  49445. +static __attribute__ ((noinline))
  49446. +unsigned int sunpkd820 (unsigned int a)
  49447. +{
  49448. + return __nds32__sunpkd820 (a);
  49449. +}
  49450. +
  49451. +static __attribute__ ((noinline))
  49452. +int16x2_t v_sunpkd820 (int8x4_t a)
  49453. +{
  49454. + return __nds32__v_sunpkd820 (a);
  49455. +}
  49456. +
  49457. +int
  49458. +main ()
  49459. +{
  49460. +#ifdef __NDS32_EL__
  49461. + int16x2_t va_p = {0xfff8, 0x34};
  49462. +#else
  49463. + int16x2_t va_p = {0, 0};
  49464. +#endif
  49465. +
  49466. + unsigned int a = sunpkd820 (0x003400f8);
  49467. + int16x2_t va = v_sunpkd820 ((int8x4_t) {0xf8, 0, 0x34, 0});
  49468. +
  49469. + if (a != 0x0034fff8)
  49470. + abort ();
  49471. + else if (va[0] != va_p[0]
  49472. + || va[1] != va_p[1])
  49473. + abort ();
  49474. + else
  49475. + exit (0);
  49476. +}
  49477. +#else
  49478. +int main(){return 0;}
  49479. +#endif
  49480. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd830.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd830.c
  49481. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd830.c 1970-01-01 01:00:00.000000000 +0100
  49482. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd830.c 2016-08-08 20:37:53.566582146 +0200
  49483. @@ -0,0 +1,37 @@
  49484. +/* This is a test program for sunpkd830 instruction. */
  49485. +
  49486. +/* { dg-do run } */
  49487. +
  49488. +#include <nds32_intrinsic.h>
  49489. +#include <stdlib.h>
  49490. +
  49491. +#ifdef __NDS32_EXT_DSP__
  49492. +static __attribute__ ((noinline))
  49493. +unsigned int sunpkd830 (unsigned int a)
  49494. +{
  49495. + return __nds32__sunpkd830 (a);
  49496. +}
  49497. +
  49498. +static __attribute__ ((noinline))
  49499. +int16x2_t v_sunpkd830 (int8x4_t a)
  49500. +{
  49501. + return __nds32__v_sunpkd830 (a);
  49502. +}
  49503. +
  49504. +int
  49505. +main ()
  49506. +{
  49507. + unsigned int a = sunpkd830 (0x120000f8);
  49508. + int16x2_t va = v_sunpkd830 ((int8x4_t) {0xf8, 0x00, 0, 0x12});
  49509. +
  49510. + if (a != 0x0012fff8)
  49511. + abort ();
  49512. + else if (va[0] != (short) 0xfff8
  49513. + || va[1] != 0x0012)
  49514. + abort ();
  49515. + else
  49516. + exit (0);
  49517. +}
  49518. +#else
  49519. +int main(){return 0;}
  49520. +#endif
  49521. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd831.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd831.c
  49522. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd831.c 1970-01-01 01:00:00.000000000 +0100
  49523. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-sunpkd831.c 2016-08-08 20:37:53.566582146 +0200
  49524. @@ -0,0 +1,43 @@
  49525. +/* This is a test program for sunpkd831 instruction. */
  49526. +
  49527. +/* { dg-do run } */
  49528. +
  49529. +#include <nds32_intrinsic.h>
  49530. +#include <stdlib.h>
  49531. +
  49532. +#ifdef __NDS32_EXT_DSP__
  49533. +static __attribute__ ((noinline))
  49534. +unsigned int sunpkd831 (unsigned int a)
  49535. +{
  49536. + return __nds32__sunpkd831 (a);
  49537. +}
  49538. +
  49539. +static __attribute__ ((noinline))
  49540. +int16x2_t v_sunpkd831 (int8x4_t a)
  49541. +{
  49542. + return __nds32__v_sunpkd831 (a);
  49543. +}
  49544. +
  49545. +int
  49546. +main ()
  49547. +{
  49548. +#ifdef __NDS32_EL__
  49549. + int16x2_t va_p = {0xfff8, 0x12};
  49550. +#else
  49551. + int16x2_t va_p = {0, 0};
  49552. +#endif
  49553. +
  49554. + unsigned int a = sunpkd831 (0x1200f800);
  49555. + int16x2_t va = v_sunpkd831 ((int8x4_t) {0, 0xf8, 0, 0x12});
  49556. +
  49557. + if (a != 0x0012fff8)
  49558. + abort ();
  49559. + else if (va[0] != va_p[0]
  49560. + || va[1] != va_p[1])
  49561. + abort ();
  49562. + else
  49563. + exit (0);
  49564. +}
  49565. +#else
  49566. +int main(){return 0;}
  49567. +#endif
  49568. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple16.c
  49569. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple16.c 1970-01-01 01:00:00.000000000 +0100
  49570. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple16.c 2016-08-08 20:37:53.570582300 +0200
  49571. @@ -0,0 +1,37 @@
  49572. +/* This is a test program for ucmple16 instruction. */
  49573. +
  49574. +/* { dg-do run } */
  49575. +
  49576. +#include <nds32_intrinsic.h>
  49577. +#include <stdlib.h>
  49578. +
  49579. +#ifdef __NDS32_EXT_DSP__
  49580. +static __attribute__ ((noinline))
  49581. +unsigned int ucmple16 (unsigned int ra, unsigned int rb)
  49582. +{
  49583. + return __nds32__ucmple16 (ra, rb);
  49584. +}
  49585. +
  49586. +static __attribute__ ((noinline))
  49587. +uint16x2_t v_ucmple16 (uint16x2_t ra, uint16x2_t rb)
  49588. +{
  49589. + return __nds32__v_ucmple16 (ra, rb);
  49590. +}
  49591. +
  49592. +int
  49593. +main ()
  49594. +{
  49595. + unsigned int a = ucmple16 (0xfffe0001, 0xffff0000);
  49596. + uint16x2_t va = v_ucmple16 ((uint16x2_t) {0x7fff, 0x7ffe},
  49597. + (uint16x2_t) {0x7ffe, 0x7fff});
  49598. + if (a != 0xffff0000)
  49599. + abort ();
  49600. + else if (va[0] != 0
  49601. + || va[1] != 0xffff)
  49602. + abort ();
  49603. + else
  49604. + exit (0);
  49605. +}
  49606. +#else
  49607. +int main(){return 0;}
  49608. +#endif
  49609. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple8.c
  49610. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple8.c 1970-01-01 01:00:00.000000000 +0100
  49611. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmple8.c 2016-08-08 20:37:53.570582300 +0200
  49612. @@ -0,0 +1,40 @@
  49613. +/* This is a test program for ucmple8 instruction. */
  49614. +
  49615. +/* { dg-do run } */
  49616. +
  49617. +#include <nds32_intrinsic.h>
  49618. +#include <stdlib.h>
  49619. +
  49620. +#ifdef __NDS32_EXT_DSP__
  49621. +static __attribute__ ((noinline))
  49622. +unsigned int ucmple8 (unsigned int ra, unsigned int rb)
  49623. +{
  49624. + return __nds32__ucmple8 (ra, rb);
  49625. +}
  49626. +
  49627. +static __attribute__ ((noinline))
  49628. +uint8x4_t v_ucmple8 (uint8x4_t ra, uint8x4_t rb)
  49629. +{
  49630. + return __nds32__v_ucmple8 (ra, rb);
  49631. +}
  49632. +
  49633. +int
  49634. +main ()
  49635. +{
  49636. + unsigned int a = ucmple8 (0xfefe0101, 0xffff0000);
  49637. + uint8x4_t va = v_ucmple8 ((uint8x4_t) {0x7e, 0x7e, 0x01, 0x01},
  49638. + (uint8x4_t) {0x7f, 0x7f, 0x00, 0x00});
  49639. +
  49640. + if (a != 0xffff0000)
  49641. + abort ();
  49642. + else if (va[0] != 0xff
  49643. + || va[1] != 0xff
  49644. + || va[2] != 0
  49645. + || va[3] != 0)
  49646. + abort ();
  49647. + else
  49648. + exit (0);
  49649. +}
  49650. +#else
  49651. +int main(){return 0;}
  49652. +#endif
  49653. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt16.c
  49654. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt16.c 1970-01-01 01:00:00.000000000 +0100
  49655. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt16.c 2016-08-08 20:37:53.570582300 +0200
  49656. @@ -0,0 +1,37 @@
  49657. +/* This is a test program for ucmplt16 instruction. */
  49658. +
  49659. +/* { dg-do run } */
  49660. +
  49661. +#include <nds32_intrinsic.h>
  49662. +#include <stdlib.h>
  49663. +
  49664. +#ifdef __NDS32_EXT_DSP__
  49665. +static __attribute__ ((noinline))
  49666. +unsigned int ucmplt16 (unsigned int ra, unsigned int rb)
  49667. +{
  49668. + return __nds32__ucmplt16 (ra, rb);
  49669. +}
  49670. +
  49671. +static __attribute__ ((noinline))
  49672. +uint16x2_t v_ucmplt16 (uint16x2_t ra, uint16x2_t rb)
  49673. +{
  49674. + return __nds32__v_ucmplt16 (ra, rb);
  49675. +}
  49676. +
  49677. +int
  49678. +main ()
  49679. +{
  49680. + unsigned int a = ucmplt16 (0xfffe0001, 0xffff0000);
  49681. + uint16x2_t va = v_ucmplt16 ((uint16x2_t) {0x7fff, 0x7ffe},
  49682. + (uint16x2_t) {0x7ffe, 0x7fff});
  49683. + if (a != 0xffff0000)
  49684. + abort ();
  49685. + else if (va[0] != 0
  49686. + || va[1] != 0xffff)
  49687. + abort ();
  49688. + else
  49689. + exit (0);
  49690. +}
  49691. +#else
  49692. +int main(){return 0;}
  49693. +#endif
  49694. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt8.c
  49695. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt8.c 1970-01-01 01:00:00.000000000 +0100
  49696. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ucmplt8.c 2016-08-08 20:37:53.570582300 +0200
  49697. @@ -0,0 +1,40 @@
  49698. +/* This is a test program for ucmplt8 instruction. */
  49699. +
  49700. +/* { dg-do run } */
  49701. +
  49702. +#include <nds32_intrinsic.h>
  49703. +#include <stdlib.h>
  49704. +
  49705. +#ifdef __NDS32_EXT_DSP__
  49706. +static __attribute__ ((noinline))
  49707. +unsigned int ucmplt8 (unsigned int ra, unsigned int rb)
  49708. +{
  49709. + return __nds32__ucmplt8 (ra, rb);
  49710. +}
  49711. +
  49712. +static __attribute__ ((noinline))
  49713. +uint8x4_t v_ucmplt8 (uint8x4_t ra, uint8x4_t rb)
  49714. +{
  49715. + return __nds32__v_ucmplt8 (ra, rb);
  49716. +}
  49717. +
  49718. +int
  49719. +main ()
  49720. +{
  49721. + unsigned int a = ucmplt8 (0xfefe0101, 0xffff0000);
  49722. + uint8x4_t va = v_ucmplt8 ((uint8x4_t) {0x7e, 0x7e, 0x01, 0x01},
  49723. + (uint8x4_t) {0x7f, 0x7f, 0x00, 0x00});
  49724. +
  49725. + if (a != 0xffff0000)
  49726. + abort ();
  49727. + else if (va[0] != 0xff
  49728. + || va[1] != 0xff
  49729. + || va[2] != 0
  49730. + || va[3] != 0)
  49731. + abort ();
  49732. + else
  49733. + exit (0);
  49734. +}
  49735. +#else
  49736. +int main(){return 0;}
  49737. +#endif
  49738. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umar64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umar64.c
  49739. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umar64.c 1970-01-01 01:00:00.000000000 +0100
  49740. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umar64.c 2016-08-08 20:37:53.570582300 +0200
  49741. @@ -0,0 +1,27 @@
  49742. +/* This is a test program for umar64 instruction. */
  49743. +
  49744. +/* { dg-do run } */
  49745. +
  49746. +#include <nds32_intrinsic.h>
  49747. +#include <stdlib.h>
  49748. +
  49749. +#ifdef __NDS32_EXT_DSP__
  49750. +static __attribute__ ((noinline))
  49751. +unsigned long long umar64 (unsigned long long t,unsigned int a,unsigned int b)
  49752. +{
  49753. + return __nds32__umar64 (t, a, b);
  49754. +}
  49755. +
  49756. +int
  49757. +main ()
  49758. +{
  49759. + unsigned long long a = umar64 (0xf000000000000000ull, 0x12345678, 0x23);
  49760. +
  49761. + if (a != 0xf00000027d27d268ull)
  49762. + abort ();
  49763. + else
  49764. + exit (0);
  49765. +}
  49766. +#else
  49767. +int main(){return 0;}
  49768. +#endif
  49769. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax16.c
  49770. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax16.c 1970-01-01 01:00:00.000000000 +0100
  49771. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax16.c 2016-08-08 20:37:53.570582300 +0200
  49772. @@ -0,0 +1,37 @@
  49773. +/* This is a test program for umax16 instruction. */
  49774. +
  49775. +/* { dg-do run } */
  49776. +
  49777. +#include <nds32_intrinsic.h>
  49778. +#include <stdlib.h>
  49779. +
  49780. +#ifdef __NDS32_EXT_DSP__
  49781. +static __attribute__ ((noinline))
  49782. +unsigned int umax16 (unsigned int ra, unsigned int rb)
  49783. +{
  49784. + return __nds32__umax16 (ra, rb);
  49785. +}
  49786. +
  49787. +static __attribute__ ((noinline))
  49788. +uint16x2_t v_umax16 (uint16x2_t ra, uint16x2_t rb)
  49789. +{
  49790. + return __nds32__v_umax16 (ra, rb);
  49791. +}
  49792. +
  49793. +int
  49794. +main ()
  49795. +{
  49796. + unsigned int a = umax16 (0xfffe0001, 0xffff0000);
  49797. + uint16x2_t va = v_umax16 ((uint16x2_t) {0xffff, 0},
  49798. + (uint16x2_t) {0xfffe, 1});
  49799. + if (a != 0xffff0001)
  49800. + abort ();
  49801. + else if (va[0] != 0xffff
  49802. + || va[1] != 1)
  49803. + abort ();
  49804. + else
  49805. + exit (0);
  49806. +}
  49807. +#else
  49808. +int main(){return 0;}
  49809. +#endif
  49810. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax8.c
  49811. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax8.c 1970-01-01 01:00:00.000000000 +0100
  49812. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umax8.c 2016-08-08 20:37:53.570582300 +0200
  49813. @@ -0,0 +1,41 @@
  49814. +/* This is a test program for umax8 instruction. */
  49815. +
  49816. +/* { dg-do run } */
  49817. +
  49818. +#include <nds32_intrinsic.h>
  49819. +#include <stdlib.h>
  49820. +
  49821. +#ifdef __NDS32_EXT_DSP__
  49822. +static __attribute__ ((noinline))
  49823. +unsigned int umax8 (unsigned int ra, unsigned int rb)
  49824. +{
  49825. + return __nds32__umax8 (ra, rb);
  49826. +}
  49827. +
  49828. +static __attribute__ ((noinline))
  49829. +uint8x4_t v_umax8 (uint8x4_t ra, uint8x4_t rb)
  49830. +{
  49831. + return __nds32__v_umax8 (ra, rb);
  49832. +}
  49833. +
  49834. +
  49835. +int
  49836. +main ()
  49837. +{
  49838. + unsigned int a = umax8 (0xffff0000, 0xfffe0001);
  49839. + uint8x4_t va = v_umax8 ((uint8x4_t) {0xff, 0xff, 0x01, 0x01},
  49840. + (uint8x4_t) {0xfe, 0xfe, 0x00, 0x00});
  49841. +
  49842. + if (a != 0xffff0001)
  49843. + abort ();
  49844. + else if (va[0] != 0xff
  49845. + || va[1] != 0xff
  49846. + || va[2] != 1
  49847. + || va[3] != 1)
  49848. + abort ();
  49849. + else
  49850. + exit (0);
  49851. +}
  49852. +#else
  49853. +int main(){return 0;}
  49854. +#endif
  49855. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umin16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umin16.c
  49856. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umin16.c 1970-01-01 01:00:00.000000000 +0100
  49857. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umin16.c 2016-08-08 20:37:53.570582300 +0200
  49858. @@ -0,0 +1,37 @@
  49859. +/* This is a test program for umin16 instruction. */
  49860. +
  49861. +/* { dg-do run } */
  49862. +
  49863. +#include <nds32_intrinsic.h>
  49864. +#include <stdlib.h>
  49865. +
  49866. +#ifdef __NDS32_EXT_DSP__
  49867. +static __attribute__ ((noinline))
  49868. +unsigned int umin16 (unsigned int ra, unsigned int rb)
  49869. +{
  49870. + return __nds32__umin16 (ra, rb);
  49871. +}
  49872. +
  49873. +static __attribute__ ((noinline))
  49874. +uint16x2_t v_umin16 (uint16x2_t ra, uint16x2_t rb)
  49875. +{
  49876. + return __nds32__v_umin16 (ra, rb);
  49877. +}
  49878. +
  49879. +int
  49880. +main ()
  49881. +{
  49882. + unsigned int a = umin16 (0xfffe0001, 0xffff0000);
  49883. + uint16x2_t va = v_umin16 ((uint16x2_t) {0x7fff, 0},
  49884. + (uint16x2_t) {0x7ffe, 1});
  49885. + if (a != 0xfffe0000)
  49886. + abort ();
  49887. + else if (va[0] != 0x7ffe
  49888. + || va[1] != 0)
  49889. + abort ();
  49890. + else
  49891. + exit (0);
  49892. +}
  49893. +#else
  49894. +int main(){return 0;}
  49895. +#endif
  49896. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umsr64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umsr64.c
  49897. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umsr64.c 1970-01-01 01:00:00.000000000 +0100
  49898. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umsr64.c 2016-08-08 20:37:53.570582300 +0200
  49899. @@ -0,0 +1,27 @@
  49900. +/* This is a test program for umsr64 instruction. */
  49901. +
  49902. +/* { dg-do run } */
  49903. +
  49904. +#include <nds32_intrinsic.h>
  49905. +#include <stdlib.h>
  49906. +
  49907. +#ifdef __NDS32_EXT_DSP__
  49908. +static __attribute__ ((noinline))
  49909. +unsigned long long umsr64 (unsigned long long t, unsigned int a, unsigned int b)
  49910. +{
  49911. + return __nds32__umsr64 (t, a, b);
  49912. +}
  49913. +
  49914. +int
  49915. +main ()
  49916. +{
  49917. + unsigned long long a = umsr64 (0x5000000300000000ull, 0x12345678, 0x23);
  49918. +
  49919. + if (a != 0x5000000082D82D98ull)
  49920. + abort ();
  49921. + else
  49922. + exit (0);
  49923. +}
  49924. +#else
  49925. +int main(){return 0;}
  49926. +#endif
  49927. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umul16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umul16.c
  49928. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umul16.c 1970-01-01 01:00:00.000000000 +0100
  49929. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umul16.c 2016-08-08 20:37:53.570582300 +0200
  49930. @@ -0,0 +1,37 @@
  49931. +/* This is a test program for umul16 instruction. */
  49932. +
  49933. +/* { dg-do run } */
  49934. +
  49935. +#include <nds32_intrinsic.h>
  49936. +#include <stdlib.h>
  49937. +
  49938. +#ifdef __NDS32_EXT_DSP__
  49939. +static __attribute__ ((noinline))
  49940. +unsigned long long umul16 (unsigned int ra, unsigned int rb)
  49941. +{
  49942. + return __nds32__umul16 (ra, rb);
  49943. +}
  49944. +
  49945. +static __attribute__ ((noinline))
  49946. +uint32x2_t v_umul16 (uint16x2_t ra, uint16x2_t rb)
  49947. +{
  49948. + return __nds32__v_umul16 (ra, rb);
  49949. +}
  49950. +
  49951. +int
  49952. +main ()
  49953. +{
  49954. + unsigned long long a = umul16 (0xffff0000, 0x0001ffff);
  49955. + uint32x2_t va = v_umul16 ((uint16x2_t) {0xffff, 0},
  49956. + (uint16x2_t) {0x0001, 0xffff});
  49957. + if (a != 0xffff00000000)
  49958. + abort ();
  49959. + else if (va[0] != 0xffff
  49960. + || va[1] != 0)
  49961. + abort ();
  49962. + else
  49963. + exit (0);
  49964. +}
  49965. +#else
  49966. +int main(){return 0;}
  49967. +#endif
  49968. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umulx16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umulx16.c
  49969. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umulx16.c 1970-01-01 01:00:00.000000000 +0100
  49970. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-umulx16.c 2016-08-08 20:37:53.570582300 +0200
  49971. @@ -0,0 +1,37 @@
  49972. +/* This is a test program for umulx16 instruction. */
  49973. +
  49974. +/* { dg-do run } */
  49975. +
  49976. +#include <nds32_intrinsic.h>
  49977. +#include <stdlib.h>
  49978. +
  49979. +#ifdef __NDS32_EXT_DSP__
  49980. +static __attribute__ ((noinline))
  49981. +unsigned long long umulx16 (unsigned int ra, unsigned int rb)
  49982. +{
  49983. + return __nds32__umulx16 (ra, rb);
  49984. +}
  49985. +
  49986. +static __attribute__ ((noinline))
  49987. +uint32x2_t v_umulx16 (uint16x2_t ra, uint16x2_t rb)
  49988. +{
  49989. + return __nds32__v_umulx16 (ra, rb);
  49990. +}
  49991. +
  49992. +int
  49993. +main ()
  49994. +{
  49995. + unsigned long long a = umulx16 (0xffff0000, 0xffff0001);
  49996. + uint32x2_t va = v_umulx16 ((uint16x2_t) {0xffff, 0xffff},
  49997. + (uint16x2_t) {1, 0});
  49998. + if (a != 0xffff00000000)
  49999. + abort ();
  50000. + else if (va[0] != 0
  50001. + || va[1] != 0xffff)
  50002. + abort ();
  50003. + else
  50004. + exit (0);
  50005. +}
  50006. +#else
  50007. +int main(){return 0;}
  50008. +#endif
  50009. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd16.c
  50010. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd16.c 1970-01-01 01:00:00.000000000 +0100
  50011. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd16.c 2016-08-08 20:37:53.570582300 +0200
  50012. @@ -0,0 +1,38 @@
  50013. +/* This is a test program for uradd16 instruction. */
  50014. +
  50015. +/* { dg-do run } */
  50016. +
  50017. +#include <nds32_intrinsic.h>
  50018. +#include <stdlib.h>
  50019. +
  50020. +#ifdef __NDS32_EXT_DSP__
  50021. +static __attribute__ ((noinline))
  50022. +unsigned int uradd16 (unsigned int ra, unsigned int rb)
  50023. +{
  50024. + return __nds32__uradd16 (ra, rb);
  50025. +}
  50026. +
  50027. +static __attribute__ ((noinline))
  50028. +uint16x2_t v_uradd16 (uint16x2_t ra, uint16x2_t rb)
  50029. +{
  50030. + return __nds32__v_uradd16 (ra, rb);
  50031. +}
  50032. +
  50033. +int
  50034. +main ()
  50035. +{
  50036. + unsigned int a = uradd16 (0x7fff7fff, 0x7fff7fff);
  50037. + uint16x2_t va = v_uradd16 ((uint16x2_t) {0x8000, 0x4000},
  50038. + (uint16x2_t) {0x8000, 0x8000});
  50039. +
  50040. + if (a != 0x7fff7fff)
  50041. + abort ();
  50042. + else if (va[0] != 0x8000
  50043. + || va[1] != 0x6000)
  50044. + abort ();
  50045. + else
  50046. + exit (0);
  50047. +}
  50048. +#else
  50049. +int main(){return 0;}
  50050. +#endif
  50051. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd64.c
  50052. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd64.c 1970-01-01 01:00:00.000000000 +0100
  50053. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd64.c 2016-08-08 20:37:53.570582300 +0200
  50054. @@ -0,0 +1,27 @@
  50055. +/* This is a test program for uradd64 instruction. */
  50056. +
  50057. +/* { dg-do run } */
  50058. +
  50059. +#include <nds32_intrinsic.h>
  50060. +#include <stdlib.h>
  50061. +
  50062. +#ifdef __NDS32_EXT_DSP__
  50063. +static __attribute__ ((noinline))
  50064. +unsigned long long uradd64 (unsigned long long ra, unsigned long long rb)
  50065. +{
  50066. + return __nds32__uradd64 (ra, rb);
  50067. +}
  50068. +
  50069. +int
  50070. +main ()
  50071. +{
  50072. + unsigned long long a = uradd64 (0xf000000000000000ull, 0xf000000000000000ull);
  50073. +
  50074. + if (a != 0xf000000000000000ull)
  50075. + abort ();
  50076. + else
  50077. + exit (0);
  50078. +}
  50079. +#else
  50080. +int main(){return 0;}
  50081. +#endif
  50082. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd8.c
  50083. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd8.c 1970-01-01 01:00:00.000000000 +0100
  50084. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uradd8.c 2016-08-08 20:37:53.570582300 +0200
  50085. @@ -0,0 +1,40 @@
  50086. +/* This is a test program for uradd8 instruction. */
  50087. +
  50088. +/* { dg-do run } */
  50089. +
  50090. +#include <nds32_intrinsic.h>
  50091. +#include <stdlib.h>
  50092. +
  50093. +#ifdef __NDS32_EXT_DSP__
  50094. +static __attribute__ ((noinline))
  50095. +unsigned int uradd8 (unsigned int ra, unsigned int rb)
  50096. +{
  50097. + return __nds32__uradd8 (ra, rb);
  50098. +}
  50099. +
  50100. +static __attribute__ ((noinline))
  50101. +uint8x4_t v_uradd8 (uint8x4_t ra, uint8x4_t rb)
  50102. +{
  50103. + return __nds32__v_uradd8 (ra, rb);
  50104. +}
  50105. +
  50106. +int
  50107. +main ()
  50108. +{
  50109. + unsigned int a = uradd8 (0x11223344, 0x55667788);
  50110. + uint8x4_t va = v_uradd8 ((uint8x4_t) {0x7f, 0x80, 0x40, 0xaa},
  50111. + (uint8x4_t) {0x7f, 0x80, 0x80, 0xaa});
  50112. +
  50113. + if (a != 0x33445566)
  50114. + abort ();
  50115. + else if (va[0] != 0x7f
  50116. + || va[1] != 0x80
  50117. + || va[2] != 0x60
  50118. + || va[3] != 0xaa)
  50119. + abort ();
  50120. + else
  50121. + exit (0);
  50122. +}
  50123. +#else
  50124. +int main(){return 0;}
  50125. +#endif
  50126. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uraddw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uraddw.c
  50127. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uraddw.c 1970-01-01 01:00:00.000000000 +0100
  50128. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-uraddw.c 2016-08-08 20:37:53.570582300 +0200
  50129. @@ -0,0 +1,27 @@
  50130. +/* This is a test program for uraddw instruction. */
  50131. +
  50132. +/* { dg-do run } */
  50133. +
  50134. +#include <nds32_intrinsic.h>
  50135. +#include <stdlib.h>
  50136. +
  50137. +#ifdef __NDS32_EXT_DSP__
  50138. +static __attribute__ ((noinline))
  50139. +unsigned int uraddw (unsigned int ra, unsigned int rb)
  50140. +{
  50141. + return __nds32__uraddw (ra, rb);
  50142. +}
  50143. +
  50144. +unsigned int
  50145. +main ()
  50146. +{
  50147. + unsigned int a = uraddw (0x80000000, 0x80000000);
  50148. +
  50149. + if (a != 0x80000000)
  50150. + abort ();
  50151. + else
  50152. + exit (0);
  50153. +}
  50154. +#else
  50155. +int main(){return 0;}
  50156. +#endif
  50157. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcras16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcras16.c
  50158. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcras16.c 1970-01-01 01:00:00.000000000 +0100
  50159. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcras16.c 2016-08-08 20:37:53.570582300 +0200
  50160. @@ -0,0 +1,44 @@
  50161. +/* This is a test program for urcras16 instruction. */
  50162. +
  50163. +/* { dg-do run } */
  50164. +
  50165. +#include <nds32_intrinsic.h>
  50166. +#include <stdlib.h>
  50167. +
  50168. +#ifdef __NDS32_EXT_DSP__
  50169. +static __attribute__ ((noinline))
  50170. +unsigned int urcras16 (unsigned int ra, unsigned int rb)
  50171. +{
  50172. + return __nds32__urcras16 (ra, rb);
  50173. +}
  50174. +
  50175. +static __attribute__ ((noinline))
  50176. +uint16x2_t v_urcras16 (uint16x2_t ra, uint16x2_t rb)
  50177. +{
  50178. + return __nds32__v_urcras16 (ra, rb);
  50179. +}
  50180. +
  50181. +int
  50182. +main ()
  50183. +{
  50184. +#ifdef __NDS32_EL__
  50185. + uint16x2_t va_p = {0xffff, 0x8000};
  50186. +#else
  50187. + uint16x2_t va_p = {0x7fff, 0};
  50188. +#endif
  50189. +
  50190. + unsigned int a = urcras16 (0x7fff7fff, 0x80007fff);
  50191. + uint16x2_t va = v_urcras16 ((uint16x2_t) {0x7fff, 0x8000},
  50192. + (uint16x2_t) {0x8000, 0x8000});
  50193. +
  50194. + if (a != 0x7fffffff)
  50195. + abort ();
  50196. + else if (va[0] != va_p[0]
  50197. + || va[1] != va_p[1])
  50198. + abort ();
  50199. + else
  50200. + exit (0);
  50201. +}
  50202. +#else
  50203. +int main(){return 0;}
  50204. +#endif
  50205. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcrsa16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcrsa16.c
  50206. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcrsa16.c 1970-01-01 01:00:00.000000000 +0100
  50207. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-urcrsa16.c 2016-08-08 20:37:53.570582300 +0200
  50208. @@ -0,0 +1,44 @@
  50209. +/* This is a test program for urcrsa16 instruction. */
  50210. +
  50211. +/* { dg-do run } */
  50212. +
  50213. +#include <nds32_intrinsic.h>
  50214. +#include <stdlib.h>
  50215. +
  50216. +#ifdef __NDS32_EXT_DSP__
  50217. +static __attribute__ ((noinline))
  50218. +unsigned int urcrsa16 (unsigned int ra, unsigned int rb)
  50219. +{
  50220. + return __nds32__urcrsa16 (ra, rb);
  50221. +}
  50222. +
  50223. +static __attribute__ ((noinline))
  50224. +uint16x2_t v_urcrsa16 (uint16x2_t ra, uint16x2_t rb)
  50225. +{
  50226. + return __nds32__v_urcrsa16 (ra, rb);
  50227. +}
  50228. +
  50229. +int
  50230. +main ()
  50231. +{
  50232. +#ifdef __NDS32_EL__
  50233. + uint16x2_t va_p = {0x8000, 0xffff};
  50234. +#else
  50235. + uint16x2_t va_p = {0, 0x7fff};
  50236. +#endif
  50237. +
  50238. + unsigned int a = urcrsa16 (0x7fff7fff, 0x7fff8000);
  50239. + uint16x2_t va = v_urcrsa16 ((uint16x2_t) {0x8000, 0x7fff},
  50240. + (uint16x2_t) {0x8000, 0x8000});
  50241. +
  50242. + if (a != 0xffff7fff)
  50243. + abort ();
  50244. + else if (va[0] != va_p[0]
  50245. + || va[1] != va_p[1])
  50246. + abort ();
  50247. + else
  50248. + exit (0);
  50249. +}
  50250. +#else
  50251. +int main(){return 0;}
  50252. +#endif
  50253. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub16.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub16.c
  50254. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub16.c 1970-01-01 01:00:00.000000000 +0100
  50255. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub16.c 2016-08-08 20:37:53.570582300 +0200
  50256. @@ -0,0 +1,38 @@
  50257. +/* This is a test program for ursub16 instruction. */
  50258. +
  50259. +/* { dg-do run } */
  50260. +
  50261. +#include <nds32_intrinsic.h>
  50262. +#include <stdlib.h>
  50263. +
  50264. +#ifdef __NDS32_EXT_DSP__
  50265. +static __attribute__ ((noinline))
  50266. +unsigned int ursub16 (unsigned int ra, unsigned int rb)
  50267. +{
  50268. + return __nds32__ursub16 (ra, rb);
  50269. +}
  50270. +
  50271. +static __attribute__ ((noinline))
  50272. +uint16x2_t v_ursub16 (uint16x2_t ra, uint16x2_t rb)
  50273. +{
  50274. + return __nds32__v_ursub16 (ra, rb);
  50275. +}
  50276. +
  50277. +int
  50278. +main ()
  50279. +{
  50280. + unsigned int a = ursub16 (0x7fff7fff, 0x80008000);
  50281. + uint16x2_t va = v_ursub16 ((uint16x2_t) {0x8000, 0x8000},
  50282. + (uint16x2_t) {0x7fff, 0x4000});
  50283. +
  50284. + if (a != 0xffffffff)
  50285. + abort ();
  50286. + else if (va[0] != 0
  50287. + || va[1] != 0x2000)
  50288. + abort ();
  50289. + else
  50290. + exit (0);
  50291. +}
  50292. +#else
  50293. +int main(){return 0;}
  50294. +#endif
  50295. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub64.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub64.c
  50296. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub64.c 1970-01-01 01:00:00.000000000 +0100
  50297. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub64.c 2016-08-08 20:37:53.570582300 +0200
  50298. @@ -0,0 +1,27 @@
  50299. +/* This is a test program for ursub64 instruction. */
  50300. +
  50301. +/* { dg-do run } */
  50302. +
  50303. +#include <nds32_intrinsic.h>
  50304. +#include <stdlib.h>
  50305. +
  50306. +#ifdef __NDS32_EXT_DSP__
  50307. +static __attribute__ ((noinline))
  50308. +unsigned long long ursub64 (unsigned long long ra, unsigned long long rb)
  50309. +{
  50310. + return __nds32__ursub64 (ra, rb);
  50311. +}
  50312. +
  50313. +int
  50314. +main ()
  50315. +{
  50316. + unsigned long long a = ursub64 (0xeull, 0xfull);
  50317. +
  50318. + if (a != 0xffffffffffffffffull)
  50319. + abort ();
  50320. + else
  50321. + exit (0);
  50322. +}
  50323. +#else
  50324. +int main(){return 0;}
  50325. +#endif
  50326. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub8.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub8.c
  50327. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub8.c 1970-01-01 01:00:00.000000000 +0100
  50328. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursub8.c 2016-08-08 20:37:53.570582300 +0200
  50329. @@ -0,0 +1,40 @@
  50330. +/* This is a test program for ursub8 instruction. */
  50331. +
  50332. +/* { dg-do run } */
  50333. +
  50334. +#include <nds32_intrinsic.h>
  50335. +#include <stdlib.h>
  50336. +
  50337. +#ifdef __NDS32_EXT_DSP__
  50338. +static __attribute__ ((noinline))
  50339. +unsigned int ursub8 (unsigned int ra, unsigned int rb)
  50340. +{
  50341. + return __nds32__ursub8 (ra, rb);
  50342. +}
  50343. +
  50344. +static __attribute__ ((noinline))
  50345. +uint8x4_t v_ursub8 (uint8x4_t ra, uint8x4_t rb)
  50346. +{
  50347. + return __nds32__v_ursub8 (ra, rb);
  50348. +}
  50349. +
  50350. +int
  50351. +main ()
  50352. +{
  50353. + unsigned int a = ursub8 (0x55667788, 0x11223344);
  50354. + uint8x4_t va = v_ursub8 ((uint8x4_t) {0x7f, 0x80, 0x80, 0xaa},
  50355. + (uint8x4_t) {0x80, 0x7f, 0x40, 0xaa});
  50356. +
  50357. + if (a != 0x22222222)
  50358. + abort ();
  50359. + else if (va[0] != 0xff
  50360. + || va[1] != 0
  50361. + || va[2] != 0x20
  50362. + || va[3] != 0)
  50363. + abort ();
  50364. + else
  50365. + exit (0);
  50366. +}
  50367. +#else
  50368. +int main(){return 0;}
  50369. +#endif
  50370. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursubw.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursubw.c
  50371. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursubw.c 1970-01-01 01:00:00.000000000 +0100
  50372. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-ursubw.c 2016-08-08 20:37:53.570582300 +0200
  50373. @@ -0,0 +1,27 @@
  50374. +/* This is a test program for ursubw instruction. */
  50375. +
  50376. +/* { dg-do run } */
  50377. +
  50378. +#include <nds32_intrinsic.h>
  50379. +#include <stdlib.h>
  50380. +
  50381. +#ifdef __NDS32_EXT_DSP__
  50382. +static __attribute__ ((noinline))
  50383. +unsigned int ursubw (unsigned int ra,unsigned int rb)
  50384. +{
  50385. + return __nds32__ursubw (ra, rb);
  50386. +}
  50387. +
  50388. +int
  50389. +main ()
  50390. +{
  50391. + unsigned int a = ursubw (0x80000000, 0x40000000);
  50392. +
  50393. + if (a != 0x20000000)
  50394. + abort ();
  50395. + else
  50396. + exit (0);
  50397. +}
  50398. +#else
  50399. +int main(){return 0;}
  50400. +#endif
  50401. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wext.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wext.c
  50402. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wext.c 1970-01-01 01:00:00.000000000 +0100
  50403. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wext.c 2016-08-08 20:37:53.570582300 +0200
  50404. @@ -0,0 +1,27 @@
  50405. +/* This is a test program for wext instruction. */
  50406. +
  50407. +/* { dg-do run } */
  50408. +
  50409. +#include <nds32_intrinsic.h>
  50410. +#include <stdlib.h>
  50411. +
  50412. +#ifdef __NDS32_EXT_DSP__
  50413. +static __attribute__ ((noinline))
  50414. +unsigned int wext (long long ra, unsigned int rb)
  50415. +{
  50416. + return __nds32__wext (ra, rb);
  50417. +}
  50418. +
  50419. +int
  50420. +main ()
  50421. +{
  50422. + unsigned int a = wext (0x1234ffff0000ll, 16);
  50423. +
  50424. + if (a != 0x1234ffff)
  50425. + abort ();
  50426. + else
  50427. + exit (0);
  50428. +}
  50429. +#else
  50430. +int main(){return 0;}
  50431. +#endif
  50432. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wexti.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wexti.c
  50433. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wexti.c 1970-01-01 01:00:00.000000000 +0100
  50434. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-wexti.c 2016-08-08 20:37:53.570582300 +0200
  50435. @@ -0,0 +1,27 @@
  50436. +/* This is a test program for wexti instruction. */
  50437. +
  50438. +/* { dg-do run } */
  50439. +
  50440. +#include <nds32_intrinsic.h>
  50441. +#include <stdlib.h>
  50442. +
  50443. +#ifdef __NDS32_EXT_DSP__
  50444. +static __attribute__ ((noinline))
  50445. +unsigned int wexti (long long ra)
  50446. +{
  50447. + return __nds32__wext (ra, 16);
  50448. +}
  50449. +
  50450. +int
  50451. +main ()
  50452. +{
  50453. + unsigned int a = wexti (0x1234ffff0000ll);
  50454. +
  50455. + if (a != 0x1234ffff)
  50456. + abort ();
  50457. + else
  50458. + exit (0);
  50459. +}
  50460. +#else
  50461. +int main(){return 0;}
  50462. +#endif
  50463. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd810.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd810.c
  50464. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd810.c 1970-01-01 01:00:00.000000000 +0100
  50465. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd810.c 2016-08-08 20:37:53.570582300 +0200
  50466. @@ -0,0 +1,43 @@
  50467. +/* This is a test program for zunpkd810 instruction. */
  50468. +
  50469. +/* { dg-do run } */
  50470. +
  50471. +#include <nds32_intrinsic.h>
  50472. +#include <stdlib.h>
  50473. +
  50474. +#ifdef __NDS32_EXT_DSP__
  50475. +static __attribute__ ((noinline))
  50476. +unsigned int zunpkd810 (unsigned int a)
  50477. +{
  50478. + return __nds32__zunpkd810 (a);
  50479. +}
  50480. +
  50481. +static __attribute__ ((noinline))
  50482. +uint16x2_t v_zunpkd810 (uint8x4_t a)
  50483. +{
  50484. + return __nds32__v_zunpkd810 (a);
  50485. +}
  50486. +
  50487. +int
  50488. +main ()
  50489. +{
  50490. +#ifdef __NDS32_EL__
  50491. + int16x2_t va_p = {0xf8, 0x56};
  50492. +#else
  50493. + int16x2_t va_p = {0, 0};
  50494. +#endif
  50495. +
  50496. + unsigned int a = zunpkd810 (0x000056f8);
  50497. + uint16x2_t va = v_zunpkd810 ((uint8x4_t) {0xf8, 0x56, 0, 0});
  50498. +
  50499. + if (a != 0x005600f8)
  50500. + abort ();
  50501. + else if (va[0] != va_p[0]
  50502. + || va[1] != va_p[1])
  50503. + abort ();
  50504. + else
  50505. + exit (0);
  50506. +}
  50507. +#else
  50508. +int main(){return 0;}
  50509. +#endif
  50510. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd820.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd820.c
  50511. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd820.c 1970-01-01 01:00:00.000000000 +0100
  50512. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd820.c 2016-08-08 20:37:53.570582300 +0200
  50513. @@ -0,0 +1,43 @@
  50514. +/* This is a test program for zunpkd820 instruction. */
  50515. +
  50516. +/* { dg-do run } */
  50517. +
  50518. +#include <nds32_intrinsic.h>
  50519. +#include <stdlib.h>
  50520. +
  50521. +#ifdef __NDS32_EXT_DSP__
  50522. +static __attribute__ ((noinline))
  50523. +unsigned int zunpkd820 (unsigned int a)
  50524. +{
  50525. + return __nds32__zunpkd820 (a);
  50526. +}
  50527. +
  50528. +static __attribute__ ((noinline))
  50529. +uint16x2_t v_zunpkd820 (uint8x4_t a)
  50530. +{
  50531. + return __nds32__v_zunpkd820 (a);
  50532. +}
  50533. +
  50534. +int
  50535. +main ()
  50536. +{
  50537. +#ifdef __NDS32_EL__
  50538. + int16x2_t va_p = {0xf8, 0x34};
  50539. +#else
  50540. + int16x2_t va_p = {0, 0};
  50541. +#endif
  50542. +
  50543. + unsigned int a = zunpkd820 (0x003400f8);
  50544. + uint16x2_t va = v_zunpkd820 ((uint8x4_t) {0xf8, 0, 0x34, 0});
  50545. +
  50546. + if (a != 0x003400f8)
  50547. + abort ();
  50548. + else if (va[0] != va_p[0]
  50549. + || va[1] != va_p[1])
  50550. + abort ();
  50551. + else
  50552. + exit (0);
  50553. +}
  50554. +#else
  50555. +int main(){return 0;}
  50556. +#endif
  50557. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd830.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd830.c
  50558. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd830.c 1970-01-01 01:00:00.000000000 +0100
  50559. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd830.c 2016-08-08 20:37:53.570582300 +0200
  50560. @@ -0,0 +1,37 @@
  50561. +/* This is a test program for zunpkd830 instruction. */
  50562. +
  50563. +/* { dg-do run } */
  50564. +
  50565. +#include <nds32_intrinsic.h>
  50566. +#include <stdlib.h>
  50567. +
  50568. +#ifdef __NDS32_EXT_DSP__
  50569. +static __attribute__ ((noinline))
  50570. +unsigned int zunpkd830 (unsigned int a)
  50571. +{
  50572. + return __nds32__zunpkd830 (a);
  50573. +}
  50574. +
  50575. +static __attribute__ ((noinline))
  50576. +uint16x2_t v_zunpkd830 (uint8x4_t a)
  50577. +{
  50578. + return __nds32__v_zunpkd830 (a);
  50579. +}
  50580. +
  50581. +int
  50582. +main ()
  50583. +{
  50584. + unsigned int a = zunpkd830 (0x120000f8);
  50585. + uint16x2_t va = v_zunpkd830 ((uint8x4_t) { 0xf8, 0x00, 0, 0x12});
  50586. +
  50587. + if (a != 0x001200f8)
  50588. + abort ();
  50589. + else if (va[0] != 0x00f8
  50590. + || va[1] != 0x0012)
  50591. + abort ();
  50592. + else
  50593. + exit (0);
  50594. +}
  50595. +#else
  50596. +int main(){return 0;}
  50597. +#endif
  50598. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd831.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd831.c
  50599. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd831.c 1970-01-01 01:00:00.000000000 +0100
  50600. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp/builtin-dsp-zunpkd831.c 2016-08-08 20:37:53.570582300 +0200
  50601. @@ -0,0 +1,43 @@
  50602. +/* This is a test program for zunpkd831 instruction. */
  50603. +
  50604. +/* { dg-do run } */
  50605. +
  50606. +#include <nds32_intrinsic.h>
  50607. +#include <stdlib.h>
  50608. +
  50609. +#ifdef __NDS32_EXT_DSP__
  50610. +static __attribute__ ((noinline))
  50611. +unsigned int zunpkd831 (unsigned int a)
  50612. +{
  50613. + return __nds32__zunpkd831 (a);
  50614. +}
  50615. +
  50616. +static __attribute__ ((noinline))
  50617. +uint16x2_t v_zunpkd831 (uint8x4_t a)
  50618. +{
  50619. + return __nds32__v_zunpkd831 (a);
  50620. +}
  50621. +
  50622. +int
  50623. +main ()
  50624. +{
  50625. +#ifdef __NDS32_EL__
  50626. + int16x2_t va_p = {0xf8, 0x12};
  50627. +#else
  50628. + int16x2_t va_p = {0, 0};
  50629. +#endif
  50630. +
  50631. + unsigned int a = zunpkd831 (0x1200f800);
  50632. + uint16x2_t va = v_zunpkd831 ((uint8x4_t) {0, 0xf8, 0, 0x12});
  50633. +
  50634. + if (a != 0x001200f8)
  50635. + abort ();
  50636. + else if (va[0] != va_p[0]
  50637. + || va[1] != va_p[1])
  50638. + abort ();
  50639. + else
  50640. + exit (0);
  50641. +}
  50642. +#else
  50643. +int main(){return 0;}
  50644. +#endif
  50645. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-add-sub.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-add-sub.c
  50646. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-add-sub.c 1970-01-01 01:00:00.000000000 +0100
  50647. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-add-sub.c 2016-08-08 20:37:53.570582300 +0200
  50648. @@ -0,0 +1,47 @@
  50649. +/* { dg-do compile } */
  50650. +/* { dg-options "-O2 -mext-dsp" } */
  50651. +/* { dg-final { scan-assembler "add8" } } */
  50652. +/* { dg-final { scan-assembler "add16" } } */
  50653. +/* { dg-final { scan-assembler "add64" } } */
  50654. +/* { dg-final { scan-assembler "sub8" } } */
  50655. +/* { dg-final { scan-assembler "sub16" } } */
  50656. +/* { dg-final { scan-assembler "sub64" } } */
  50657. +
  50658. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50659. +typedef short v2hi __attribute__ ((vector_size (4)));
  50660. +
  50661. +v4qi __attribute__ ((noinline))
  50662. +add8 (v4qi a, v4qi b)
  50663. +{
  50664. + return a + b;
  50665. +}
  50666. +
  50667. +v4qi __attribute__ ((noinline))
  50668. +sub8 (v4qi a, v4qi b)
  50669. +{
  50670. + return a - b;
  50671. +}
  50672. +
  50673. +v2hi __attribute__ ((noinline))
  50674. +add16 (v2hi a, v2hi b)
  50675. +{
  50676. + return a + b;
  50677. +}
  50678. +
  50679. +v2hi __attribute__ ((noinline))
  50680. +sub16 (v2hi a, v2hi b)
  50681. +{
  50682. + return a - b;
  50683. +}
  50684. +
  50685. +long long
  50686. +add64 (long long a, long long b)
  50687. +{
  50688. + return a + b;
  50689. +}
  50690. +
  50691. +long long
  50692. +sub64 (long long a, long long b)
  50693. +{
  50694. + return a - b;
  50695. +}
  50696. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-bpick.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-bpick.c
  50697. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-bpick.c 1970-01-01 01:00:00.000000000 +0100
  50698. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-bpick.c 2016-08-08 20:37:53.570582300 +0200
  50699. @@ -0,0 +1,8 @@
  50700. +/* { dg-do compile } */
  50701. +/* { dg-options "-O2 -mext-dsp" } */
  50702. +/* { dg-final { scan-assembler "bpick" } } */
  50703. +
  50704. +int bpick(int a, int b, int mask)
  50705. +{
  50706. + return (a & mask) | (b & ~mask);
  50707. +}
  50708. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-mmul.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-mmul.c
  50709. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-mmul.c 1970-01-01 01:00:00.000000000 +0100
  50710. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-mmul.c 2016-08-08 20:37:53.570582300 +0200
  50711. @@ -0,0 +1,12 @@
  50712. +/* { dg-do compile } */
  50713. +/* { dg-options "-O2 -mext-dsp" } */
  50714. +/* { dg-final { scan-assembler "smmul" } } */
  50715. +
  50716. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50717. +typedef short v2hi __attribute__ ((vector_size (4)));
  50718. +
  50719. +int smmul(int a, int b)
  50720. +{
  50721. + long long tmp = (long long)a * b;
  50722. + return (int)((tmp >> 32) & 0xffffffffll);
  50723. +}
  50724. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-mulhisi.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-mulhisi.c
  50725. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-mulhisi.c 1970-01-01 01:00:00.000000000 +0100
  50726. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-mulhisi.c 2016-08-08 20:37:53.570582300 +0200
  50727. @@ -0,0 +1,23 @@
  50728. +/* { dg-do compile } */
  50729. +/* { dg-options "-O2 -mext-dsp" } */
  50730. +/* { dg-final { scan-assembler "smbb" } } */
  50731. +/* { dg-final { scan-assembler "smbt" } } */
  50732. +/* { dg-final { scan-assembler "smtt" } } */
  50733. +
  50734. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50735. +typedef short v2hi __attribute__ ((vector_size (4)));
  50736. +
  50737. +int smbb(v2hi a, v2hi b)
  50738. +{
  50739. + return a[0] * b[0];
  50740. +}
  50741. +
  50742. +int smbt(v2hi a, v2hi b)
  50743. +{
  50744. + return a[0] * b[1];
  50745. +}
  50746. +
  50747. +int smtt(v2hi a, v2hi b)
  50748. +{
  50749. + return a[1] * b[1];
  50750. +}
  50751. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-raddsub.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-raddsub.c
  50752. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-raddsub.c 1970-01-01 01:00:00.000000000 +0100
  50753. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-raddsub.c 2016-08-08 20:37:53.570582300 +0200
  50754. @@ -0,0 +1,26 @@
  50755. +/* { dg-do compile } */
  50756. +/* { dg-options "-O2 -mext-dsp" } */
  50757. +/* { dg-final { scan-assembler "raddw" } } */
  50758. +/* { dg-final { scan-assembler "rsubw" } } */
  50759. +/* { dg-final { scan-assembler "uraddw" } } */
  50760. +/* { dg-final { scan-assembler "ursubw" } } */
  50761. +
  50762. +int raddw(int a, int b)
  50763. +{
  50764. + return (a + b) >> 1;
  50765. +}
  50766. +
  50767. +int rsubw(int a, int b)
  50768. +{
  50769. + return (a - b) >> 1;
  50770. +}
  50771. +
  50772. +unsigned uraddw(unsigned a, unsigned b)
  50773. +{
  50774. + return (a + b) >> 1;
  50775. +}
  50776. +
  50777. +unsigned ursubw(unsigned a, unsigned b)
  50778. +{
  50779. + return (a - b) >> 1;
  50780. +}
  50781. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-smals.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-smals.c
  50782. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-smals.c 1970-01-01 01:00:00.000000000 +0100
  50783. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-smals.c 2016-08-08 20:37:53.574582455 +0200
  50784. @@ -0,0 +1,30 @@
  50785. +/* { dg-do compile } */
  50786. +/* { dg-options "-O2 -mext-dsp" } */
  50787. +/* { dg-final { scan-assembler "smalbb" } } */
  50788. +/* { dg-final { scan-assembler "smalbt" } } */
  50789. +/* { dg-final { scan-assembler "smaltt" } } */
  50790. +/* { dg-final { scan-assembler "smal" } } */
  50791. +
  50792. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50793. +typedef short v2hi __attribute__ ((vector_size (4)));
  50794. +
  50795. +
  50796. +long long smalbb(long long acc, v2hi a, v2hi b)
  50797. +{
  50798. + return acc + a[0] * b[0];
  50799. +}
  50800. +
  50801. +long long smalbt(long long acc, v2hi a, v2hi b)
  50802. +{
  50803. + return acc + a[1] * b[0];
  50804. +}
  50805. +
  50806. +long long smaltt(long long acc, v2hi a, v2hi b)
  50807. +{
  50808. + return acc + a[1] * b[1];
  50809. +}
  50810. +
  50811. +long long smal(v2hi a, long long b)
  50812. +{
  50813. + return b + (long long)(a[0] * a[1]);
  50814. +}
  50815. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-smalxda.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-smalxda.c
  50816. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-smalxda.c 1970-01-01 01:00:00.000000000 +0100
  50817. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-smalxda.c 2016-08-08 20:37:53.574582455 +0200
  50818. @@ -0,0 +1,17 @@
  50819. +/* { dg-do compile } */
  50820. +/* { dg-options "-O2 -mext-dsp" } */
  50821. +/* { dg-final { scan-assembler "smalxda" } } */
  50822. +/* { dg-final { scan-assembler "smalxds" } } */
  50823. +
  50824. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50825. +typedef short v2hi __attribute__ ((vector_size (4)));
  50826. +
  50827. +long long smalxda(long long acc, v2hi a, v2hi b)
  50828. +{
  50829. + return acc + (a[0] * b[1] + a[1] * b[0]);
  50830. +}
  50831. +
  50832. +long long smalxds(long long acc, v2hi a, v2hi b)
  50833. +{
  50834. + return acc + (a[1] * b[0] - a[0] * b[1]);
  50835. +}
  50836. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-unpkd.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-unpkd.c
  50837. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-unpkd.c 1970-01-01 01:00:00.000000000 +0100
  50838. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-unpkd.c 2016-08-08 20:37:53.574582455 +0200
  50839. @@ -0,0 +1,79 @@
  50840. +/* { dg-do compile } */
  50841. +/* { dg-options "-O2 -mext-dsp" } */
  50842. +/* { dg-final { scan-assembler "sunpkd810" } } */
  50843. +/* { dg-final { scan-assembler "sunpkd820" } } */
  50844. +/* { dg-final { scan-assembler "sunpkd830" } } */
  50845. +/* { dg-final { scan-assembler "sunpkd831" } } */
  50846. +/* { dg-final { scan-assembler "zunpkd810" } } */
  50847. +/* { dg-final { scan-assembler "zunpkd820" } } */
  50848. +/* { dg-final { scan-assembler "zunpkd830" } } */
  50849. +/* { dg-final { scan-assembler "zunpkd831" } } */
  50850. +
  50851. +typedef signed char v4qi __attribute__ ((vector_size (4)));
  50852. +typedef short v2hi __attribute__ ((vector_size (4)));
  50853. +typedef unsigned char uv4qi __attribute__ ((vector_size (4)));
  50854. +typedef unsigned short uv2hi __attribute__ ((vector_size (4)));
  50855. +
  50856. +v2hi sunpkd810(v4qi v)
  50857. +{
  50858. + v2hi ret;
  50859. + ret[0] = v[0];
  50860. + ret[1] = v[1];
  50861. + return ret;
  50862. +}
  50863. +
  50864. +v2hi sunpkd820(v4qi v)
  50865. +{
  50866. + v2hi ret;
  50867. + ret[0] = v[0];
  50868. + ret[1] = v[2];
  50869. + return ret;
  50870. +}
  50871. +
  50872. +v2hi sunpkd830(v4qi v)
  50873. +{
  50874. + v2hi ret;
  50875. + ret[0] = v[0];
  50876. + ret[1] = v[3];
  50877. + return ret;
  50878. +}
  50879. +
  50880. +v2hi sunpkd831(v4qi v)
  50881. +{
  50882. + v2hi ret;
  50883. + ret[0] = v[1];
  50884. + ret[1] = v[3];
  50885. + return ret;
  50886. +}
  50887. +
  50888. +uv2hi zunpkd810(uv4qi v)
  50889. +{
  50890. + uv2hi ret;
  50891. + ret[0] = v[0];
  50892. + ret[1] = v[1];
  50893. + return ret;
  50894. +}
  50895. +
  50896. +uv2hi zunpkd820(uv4qi v)
  50897. +{
  50898. + uv2hi ret;
  50899. + ret[0] = v[0];
  50900. + ret[1] = v[2];
  50901. + return ret;
  50902. +}
  50903. +
  50904. +uv2hi zunpkd830(uv4qi v)
  50905. +{
  50906. + uv2hi ret;
  50907. + ret[0] = v[0];
  50908. + ret[1] = v[3];
  50909. + return ret;
  50910. +}
  50911. +
  50912. +uv2hi zunpkd831(uv4qi v)
  50913. +{
  50914. + uv2hi ret;
  50915. + ret[0] = v[1];
  50916. + ret[1] = v[3];
  50917. + return ret;
  50918. +}
  50919. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-v2hi-packing00.c gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-v2hi-packing00.c
  50920. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/dsp-v2hi-packing00.c 1970-01-01 01:00:00.000000000 +0100
  50921. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/dsp-v2hi-packing00.c 2016-08-08 20:37:53.574582455 +0200
  50922. @@ -0,0 +1,127 @@
  50923. +/* { dg-do run } */
  50924. +
  50925. +#include <nds32_intrinsic.h>
  50926. +
  50927. +int16x2_t packing01(int16x2_t x, int16x2_t y) __attribute__ ((noinline));
  50928. +int16x2_t packing01(int16x2_t x, int16x2_t y)
  50929. +{
  50930. + int16x2_t ret;
  50931. + ret[0] = x[0];
  50932. + ret[1] = y[1];
  50933. + return ret;
  50934. +}
  50935. +
  50936. +int16x2_t packing10(int16x2_t x, int16x2_t y) __attribute__ ((noinline));
  50937. +int16x2_t packing10(int16x2_t x, int16x2_t y)
  50938. +{
  50939. + int16x2_t ret;
  50940. + ret[0] = x[1];
  50941. + ret[1] = y[0];
  50942. + return ret;
  50943. +}
  50944. +
  50945. +int16x2_t packing00(int16x2_t x, int16x2_t y) __attribute__ ((noinline));
  50946. +int16x2_t packing00(int16x2_t x, int16x2_t y)
  50947. +{
  50948. + int16x2_t ret;
  50949. + ret[0] = x[0];
  50950. + ret[1] = y[0];
  50951. + return ret;
  50952. +}
  50953. +
  50954. +int16x2_t packing0cv0(int16x2_t x) __attribute__ ((noinline));
  50955. +int16x2_t packing0cv0(int16x2_t x)
  50956. +{
  50957. + int16x2_t ret = {0, 0};
  50958. + ret[0] = x[0];
  50959. + return ret;
  50960. +}
  50961. +
  50962. +int16x2_t packingcv00(int16x2_t x) __attribute__ ((noinline));
  50963. +int16x2_t packingcv00(int16x2_t x)
  50964. +{
  50965. + int16x2_t ret = {0, 0};
  50966. + ret[1] = x[0];
  50967. + return ret;
  50968. +}
  50969. +
  50970. +int16x2_t packing11(int16x2_t x, int16x2_t y) __attribute__ ((noinline));
  50971. +int16x2_t packing11(int16x2_t x, int16x2_t y)
  50972. +{
  50973. + int16x2_t ret;
  50974. + ret[0] = x[1];
  50975. + ret[1] = y[1];
  50976. + return ret;
  50977. +}
  50978. +int16x2_t packing1cv0(int16x2_t x) __attribute__ ((noinline));
  50979. +int16x2_t packing1cv0(int16x2_t x)
  50980. +{
  50981. + int16x2_t ret = {0, 0};
  50982. + ret[0] = x[1];
  50983. + return ret;
  50984. +}
  50985. +
  50986. +int16x2_t packingcv01(int16x2_t x) __attribute__ ((noinline));
  50987. +int16x2_t packingcv01(int16x2_t x)
  50988. +{
  50989. + int16x2_t ret = {0, 0};
  50990. + ret[1] = x[1];
  50991. + return ret;
  50992. +}
  50993. +
  50994. +int main() {
  50995. + int16x2_t a = {0x11, 0x22};
  50996. + int16x2_t b = {0x33, 0x44};
  50997. +
  50998. + int16x2_t ret00, ret01, ret10, ret11;
  50999. + int16x2_t ret0cv0, retcv00, ret1cv0, retcv01;
  51000. + ret00 = packing00 (a, b);
  51001. +
  51002. + if (ret00[0] != 0x11
  51003. + || ret00[1] != 0x33)
  51004. + return 1;
  51005. +
  51006. + ret0cv0 = packing0cv0 (a);
  51007. +
  51008. + if (ret0cv0[0] != 0x11
  51009. + || ret0cv0[1] != 0)
  51010. + return 1;
  51011. +
  51012. + retcv00 = packingcv00 (a);
  51013. +
  51014. + if (retcv00[0] != 0
  51015. + || retcv00[1] != 0x11)
  51016. + return 1;
  51017. +
  51018. + ret11 = packing11 (a, b);
  51019. +
  51020. + if (ret11[0] != 0x22
  51021. + || ret11[1] != 0x44)
  51022. + return 1;
  51023. +
  51024. + ret1cv0 = packing1cv0 (a);
  51025. +
  51026. + if (ret1cv0[0] != 0x22
  51027. + || ret1cv0[1] != 0)
  51028. + return 1;
  51029. +
  51030. + retcv01 = packingcv01 (a);
  51031. +
  51032. + if (retcv01[0] != 0
  51033. + || retcv01[1] != 0x22)
  51034. + return 1;
  51035. +
  51036. + ret01 = packing01 (a, b);
  51037. +
  51038. + if (ret01[0] != 0x11
  51039. + || ret01[1] != 0x44)
  51040. + return 1;
  51041. +
  51042. + ret10 = packing10 (a, b);
  51043. +
  51044. + if (ret10[0] != 0x22
  51045. + || ret10[1] != 0x33)
  51046. + return 1;
  51047. +
  51048. + return 0;
  51049. +}
  51050. diff -Nur gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/nds32.exp gcc-4.9.4/gcc/testsuite/gcc.target/nds32/nds32.exp
  51051. --- gcc-4.9.4.orig/gcc/testsuite/gcc.target/nds32/nds32.exp 2014-01-02 23:23:26.000000000 +0100
  51052. +++ gcc-4.9.4/gcc/testsuite/gcc.target/nds32/nds32.exp 2016-08-08 20:37:53.574582455 +0200
  51053. @@ -1,5 +1,5 @@
  51054. # Target test cases of Andes NDS32 cpu for GNU compiler
  51055. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  51056. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  51057. # Contributed by Andes Technology Corporation.
  51058. #
  51059. # This file is part of GCC.
  51060. @@ -40,6 +40,8 @@
  51061. # Main loop.
  51062. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
  51063. "" $DEFAULT_CFLAGS
  51064. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/dsp/*.\[cS\]]] \
  51065. + ""
  51066. # All done.
  51067. dg-finish
  51068. diff -Nur gcc-4.9.4.orig/gcc/testsuite/g++.dg/init/array15.C gcc-4.9.4/gcc/testsuite/g++.dg/init/array15.C
  51069. --- gcc-4.9.4.orig/gcc/testsuite/g++.dg/init/array15.C 2004-12-09 10:37:37.000000000 +0100
  51070. +++ gcc-4.9.4/gcc/testsuite/g++.dg/init/array15.C 2016-08-08 20:37:53.542581218 +0200
  51071. @@ -1,4 +1,6 @@
  51072. // { dg-do run }
  51073. +// { dg-require-effective-target nds32_full_addr_space { target nds32*-*-elf* } }
  51074. +// { dg-options "-mcmodel=large" { target nds32*-*-elf* } }
  51075. // Copyright (C) 2004 Free Software Foundation, Inc.
  51076. // Contributed by Nathan Sidwell 8 Dec 2004 <nathan@codesourcery.com>
  51077. diff -Nur gcc-4.9.4.orig/gcc/testsuite/g++.dg/init/array16.C gcc-4.9.4/gcc/testsuite/g++.dg/init/array16.C
  51078. --- gcc-4.9.4.orig/gcc/testsuite/g++.dg/init/array16.C 2010-08-11 04:00:15.000000000 +0200
  51079. +++ gcc-4.9.4/gcc/testsuite/g++.dg/init/array16.C 2016-08-08 20:37:53.542581218 +0200
  51080. @@ -2,6 +2,7 @@
  51081. // have "compile" for some targets and "run" for others.
  51082. // { dg-do run { target { ! mmix-*-* } } }
  51083. // { dg-options "-mstructure-size-boundary=8" { target arm*-*-* } }
  51084. +// { dg-skip-if "" { nds32_gp_direct } }
  51085. // Copyright (C) 2004 Free Software Foundation, Inc.
  51086. // Contributed by Nathan Sidwell 8 Dec 2004 <nathan@codesourcery.com>
  51087. diff -Nur gcc-4.9.4.orig/gcc/testsuite/g++.dg/torture/type-generic-1.C gcc-4.9.4/gcc/testsuite/g++.dg/torture/type-generic-1.C
  51088. --- gcc-4.9.4.orig/gcc/testsuite/g++.dg/torture/type-generic-1.C 2009-09-01 00:23:27.000000000 +0200
  51089. +++ gcc-4.9.4/gcc/testsuite/g++.dg/torture/type-generic-1.C 2016-08-08 20:37:53.546581373 +0200
  51090. @@ -4,6 +4,7 @@
  51091. /* { dg-do run } */
  51092. /* { dg-add-options ieee } */
  51093. /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
  51094. +/* { dg-skip-if "No Denormmalized support" { nds32_ext_fpu } } */
  51095. #include "../../gcc.dg/tg-tests.h"
  51096. diff -Nur gcc-4.9.4.orig/gcc/testsuite/lib/target-supports.exp gcc-4.9.4/gcc/testsuite/lib/target-supports.exp
  51097. --- gcc-4.9.4.orig/gcc/testsuite/lib/target-supports.exp 2016-05-22 10:53:32.000000000 +0200
  51098. +++ gcc-4.9.4/gcc/testsuite/lib/target-supports.exp 2016-08-08 20:37:53.574582455 +0200
  51099. @@ -453,6 +453,10 @@
  51100. || [istarget hppa64-hp-hpux11.23] } {
  51101. return 0;
  51102. }
  51103. + if { [istarget nds32*-*-*]
  51104. + && [check_effective_target_nds32_reduced_regs] } {
  51105. + return 0;
  51106. + }
  51107. return 1
  51108. }
  51109. @@ -3029,6 +3033,114 @@
  51110. } "-O2 -mthumb" ]
  51111. }
  51112. +# If board info says it only has 16M addressing space, return 0.
  51113. +# Otherwise, return 1.
  51114. +proc check_effective_target_nds32_full_addr_space { } {
  51115. + if [board_info target exists addr16m] {
  51116. + return 0
  51117. + }
  51118. + return 1;
  51119. +}
  51120. +
  51121. +# Return 1 if gp direct is enable by default.
  51122. +proc check_effective_target_nds32_gp_direct { } {
  51123. + return [check_no_compiler_messages gp_direct object {
  51124. + #ifdef __NDS32_GP_DIRECT__
  51125. + int dummy;
  51126. + #else
  51127. + #error no GP_DIRECT
  51128. + #endif
  51129. + }]
  51130. +}
  51131. +
  51132. +# Return 1 if this is a nds32 target supporting -mext-perf.
  51133. +proc check_effective_target_nds32_ext_perf { } {
  51134. + return [check_no_compiler_messages ext_perf object {
  51135. + #ifdef __NDS32_EXT_PERF__
  51136. + int dummy;
  51137. + #else
  51138. + #error no EXT_PERF
  51139. + #endif
  51140. + }]
  51141. +}
  51142. +
  51143. +# Return 1 if this is a nds32 target supporting -mext-perf2.
  51144. +proc check_effective_target_nds32_ext_perf2 { } {
  51145. + return [check_no_compiler_messages ext_perf2 object {
  51146. + #ifdef __NDS32_EXT_PERF2__
  51147. + int dummy;
  51148. + #else
  51149. + #error no EXT_PERF2
  51150. + #endif
  51151. + }]
  51152. +}
  51153. +
  51154. +# Return 1 if this is a nds32 target supporting -mext-string.
  51155. +proc check_effective_target_nds32_ext_string { } {
  51156. + return [check_no_compiler_messages ext_string object {
  51157. + #ifdef __NDS32_EXT_STRING__
  51158. + int dummy;
  51159. + #else
  51160. + #error no EXT_STRING
  51161. + #endif
  51162. + }]
  51163. +}
  51164. +
  51165. +# Return 1 if this is a nds32 target supporting -mext-fpu-sp or -mext-fpu-dp.
  51166. +proc check_effective_target_nds32_ext_fpu { } {
  51167. + return [check_no_compiler_messages ext_fpu object {
  51168. + #if defined(__NDS32_EXT_FPU_SP__) || defined(__NDS32_EXT_FPU_DP__)
  51169. + int dummy;
  51170. + #else
  51171. + #error no support FPU
  51172. + #endif
  51173. + }]
  51174. +}
  51175. +
  51176. +# Return 1 if this is a nds32 target supporting -mext-fpu-sp.
  51177. +proc check_effective_target_nds32_ext_fpu_sp { } {
  51178. + return [check_no_compiler_messages ext_fpu_sp object {
  51179. + #ifdef __NDS32_EXT_FPU_SP__
  51180. + int dummy;
  51181. + #else
  51182. + #error no EXT_FPU_SP
  51183. + #endif
  51184. + }]
  51185. +}
  51186. +
  51187. +# Return 1 if this is a nds32 target supporting -mext-fpu-dp.
  51188. +proc check_effective_target_nds32_ext_fpu_dp { } {
  51189. + return [check_no_compiler_messages ext_fpu_dp object {
  51190. + #ifdef __NDS32_EXT_FPU_DP__
  51191. + int dummy;
  51192. + #else
  51193. + #error no EXT_FPU_DP
  51194. + #endif
  51195. + }]
  51196. +}
  51197. +
  51198. +# Return 1 if this is a nds32 target supporting -mreduced-regs.
  51199. +proc check_effective_target_nds32_reduced_regs { } {
  51200. + return [check_no_compiler_messages reduced_regs object {
  51201. + #ifdef __NDS32_REDUCED_REGS__
  51202. + int dummy;
  51203. + #else
  51204. + #error no REDUCED_REGS
  51205. + #endif
  51206. + }]
  51207. +}
  51208. +
  51209. +# Return 1 if this is a nds32 target not supporting v3m ISA.
  51210. +proc check_effective_target_nds32_no_v3m { } {
  51211. + return [check_no_compiler_messages no_v3m object {
  51212. + #if !defined(__NDS32_BASELINE_V3M__)
  51213. + int dummy;
  51214. + #else
  51215. + #error Support V3M ISA
  51216. + #endif
  51217. + }]
  51218. +}
  51219. +
  51220. # Return 1 if this is a PowerPC target supporting -meabi.
  51221. proc check_effective_target_powerpc_eabi_ok { } {
  51222. @@ -5875,6 +5987,7 @@
  51223. || [istarget arc*-*-*]
  51224. || [istarget avr*-*-*]
  51225. || [istarget crisv32-*-*] || [istarget cris-*-*]
  51226. + || [istarget nds32*-*-*]
  51227. || [istarget s390*-*-*]
  51228. || [check_effective_target_arm_cortex_m] } {
  51229. return 1
  51230. diff -Nur gcc-4.9.4.orig/gcc/timevar.def gcc-4.9.4/gcc/timevar.def
  51231. --- gcc-4.9.4.orig/gcc/timevar.def 2014-01-02 23:23:26.000000000 +0100
  51232. +++ gcc-4.9.4/gcc/timevar.def 2016-08-08 20:37:53.574582455 +0200
  51233. @@ -167,6 +167,7 @@
  51234. DEFTIMEVAR (TV_SCEV_CONST , "scev constant prop")
  51235. DEFTIMEVAR (TV_TREE_LOOP_UNSWITCH , "tree loop unswitching")
  51236. DEFTIMEVAR (TV_COMPLETE_UNROLL , "complete unrolling")
  51237. +DEFTIMEVAR (TV_SWITCH_SHORTCUT , "switch statement shortcuts")
  51238. DEFTIMEVAR (TV_TREE_PARALLELIZE_LOOPS, "tree parallelize loops")
  51239. DEFTIMEVAR (TV_TREE_VECTORIZATION , "tree vectorization")
  51240. DEFTIMEVAR (TV_TREE_SLP_VECTORIZATION, "tree slp vectorization")
  51241. diff -Nur gcc-4.9.4.orig/gcc/tree-loop-distribution.c gcc-4.9.4/gcc/tree-loop-distribution.c
  51242. --- gcc-4.9.4.orig/gcc/tree-loop-distribution.c 2015-02-20 08:32:08.000000000 +0100
  51243. +++ gcc-4.9.4/gcc/tree-loop-distribution.c 2016-08-08 20:37:53.574582455 +0200
  51244. @@ -1067,7 +1067,7 @@
  51245. gimple_bb (DR_STMT (single_store))))
  51246. plus_one = true;
  51247. - if (single_store && !single_load)
  51248. + if (single_store && !single_load && !flag_no_builtin)
  51249. {
  51250. gimple stmt = DR_STMT (single_store);
  51251. tree rhs = gimple_assign_rhs1 (stmt);
  51252. @@ -1089,7 +1089,7 @@
  51253. partition->niter = nb_iter;
  51254. partition->plus_one = plus_one;
  51255. }
  51256. - else if (single_store && single_load)
  51257. + else if (single_store && single_load && !flag_no_builtin)
  51258. {
  51259. gimple store = DR_STMT (single_store);
  51260. gimple load = DR_STMT (single_load);
  51261. diff -Nur gcc-4.9.4.orig/gcc/tree-pass.h gcc-4.9.4/gcc/tree-pass.h
  51262. --- gcc-4.9.4.orig/gcc/tree-pass.h 2014-01-02 23:23:26.000000000 +0100
  51263. +++ gcc-4.9.4/gcc/tree-pass.h 2016-08-08 20:37:53.574582455 +0200
  51264. @@ -585,6 +585,7 @@
  51265. extern gimple_opt_pass *make_pass_inline_parameters (gcc::context *ctxt);
  51266. extern gimple_opt_pass *make_pass_update_address_taken (gcc::context *ctxt);
  51267. extern gimple_opt_pass *make_pass_convert_switch (gcc::context *ctxt);
  51268. +extern gimple_opt_pass *make_pass_switch_shortcut (gcc::context *ctxt);
  51269. /* Current optimization pass. */
  51270. extern opt_pass *current_pass;
  51271. diff -Nur gcc-4.9.4.orig/gcc/tree-switch-shortcut.c gcc-4.9.4/gcc/tree-switch-shortcut.c
  51272. --- gcc-4.9.4.orig/gcc/tree-switch-shortcut.c 1970-01-01 01:00:00.000000000 +0100
  51273. +++ gcc-4.9.4/gcc/tree-switch-shortcut.c 2016-08-08 20:37:53.574582455 +0200
  51274. @@ -0,0 +1,423 @@
  51275. +/* Switch shortcutting optimization for GNU C
  51276. + Copyright (C) 2013 Free Software Foundation, Inc.
  51277. + Contributed by Steve Ellcey (sellcey@imgtec.com).
  51278. +
  51279. +This file is part of GCC.
  51280. +
  51281. +GCC is free software; you can redistribute it and/or modify it under
  51282. +the terms of the GNU General Public License as published by the Free
  51283. +Software Foundation; either version 3, or (at your option) any later
  51284. +version.
  51285. +
  51286. +GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  51287. +WARRANTY; without even the implied warranty of MERCHANTABILITY or
  51288. +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  51289. +for more details.
  51290. +
  51291. +You should have received a copy of the GNU General Public License
  51292. +along with GCC; see the file COPYING3. If not see
  51293. +<http://www.gnu.org/licenses/>. */
  51294. +
  51295. +/* This file implements an optimization where, when a variable is set
  51296. + to a constant value and there is a path that leads from this definition
  51297. + to a switch statement that uses that variable as its controlling expression
  51298. + we duplicate the blocks on this path and change the switch goto to a
  51299. + direct goto to the label of the switch block that control would goto based
  51300. + on the value of the variable. */
  51301. +
  51302. +#include "config.h"
  51303. +#include "system.h"
  51304. +#include "coretypes.h"
  51305. +#include "tm.h"
  51306. +#include "line-map.h"
  51307. +#include "params.h"
  51308. +#include "flags.h"
  51309. +#include "tree.h"
  51310. +#include "varasm.h"
  51311. +#include "stor-layout.h"
  51312. +#include "basic-block.h"
  51313. +#include "tree-ssa-alias.h"
  51314. +#include "internal-fn.h"
  51315. +#include "gimple-expr.h"
  51316. +#include "is-a.h"
  51317. +#include "gimple.h"
  51318. +#include "gimplify.h"
  51319. +#include "gimple-iterator.h"
  51320. +#include "gimplify-me.h"
  51321. +#include "gimple-ssa.h"
  51322. +#include "cgraph.h"
  51323. +#include "tree-cfg.h"
  51324. +#include "tree-phinodes.h"
  51325. +#include "stringpool.h"
  51326. +#include "tree-ssanames.h"
  51327. +#include "tree-pass.h"
  51328. +#include "gimple-pretty-print.h"
  51329. +#include "cfgloop.h"
  51330. +#include "pointer-set.h"
  51331. +
  51332. +#include "tree-inline.h"
  51333. +#include "tree-ssa-alias.h"
  51334. +#include "tree-into-ssa.h"
  51335. +#include "tree-pass.h"
  51336. +
  51337. +#if 0
  51338. +#include "tree.h"
  51339. +#include "internal-fn.h"
  51340. +//#include "tree-flow.h"
  51341. +//#include "tree-flow-inline.h"
  51342. +#include "basic-block.h"
  51343. +#include "gimple.h"
  51344. +#include "cfgloop.h"
  51345. +#endif
  51346. +#include "params.h"
  51347. +
  51348. +/* Helper function for find_path, visited_bbs is used to make sure we don't
  51349. + fall into an infinite loop. */
  51350. +
  51351. +static int
  51352. +find_path_1(basic_block start_bb, basic_block end_bb, struct pointer_set_t *visited_bbs)
  51353. +{
  51354. + edge_iterator ei;
  51355. + edge e;
  51356. +
  51357. + if (start_bb == end_bb) return 1;
  51358. +
  51359. + if (!pointer_set_insert (visited_bbs, start_bb))
  51360. + {
  51361. + FOR_EACH_EDGE (e, ei, start_bb->succs)
  51362. + if (find_path_1 (e->dest, end_bb, visited_bbs))
  51363. + return 1;
  51364. + }
  51365. + return 0;
  51366. +}
  51367. +
  51368. +/* Return 1 if there is a path from start_bb to end_bb and 0 if there
  51369. + is not. There may be multiple paths from start_bb to end_bb. */
  51370. +
  51371. +static int
  51372. +find_path(basic_block start_bb, basic_block end_bb)
  51373. +{
  51374. + edge_iterator ei;
  51375. + edge e;
  51376. + struct pointer_set_t *visited_bbs;
  51377. + int p = 0;
  51378. +
  51379. + if (start_bb == end_bb) return 1;
  51380. +
  51381. + visited_bbs = pointer_set_create ();
  51382. + if (!pointer_set_insert (visited_bbs, start_bb))
  51383. + {
  51384. + FOR_EACH_EDGE (e, ei, start_bb->succs)
  51385. + if (find_path_1 (e->dest, end_bb, visited_bbs))
  51386. + {
  51387. + p = 1;
  51388. + break;
  51389. + }
  51390. + }
  51391. + pointer_set_destroy (visited_bbs);
  51392. + return p;
  51393. +}
  51394. +
  51395. +
  51396. +/* We save the paths we want to copy in bbs_list_array. n_bbs_list is the
  51397. + number of paths saved, bbs_list_array[i] is the list of basic blocks in
  51398. + one path. Each path starts with the block where a variable is assigned
  51399. + a constant value (bbs_list_array[i][0]) and ends with the switch statement
  51400. + block (bbs_list_array[i][bbs_list_size[i]-2]) and then the block that the
  51401. + switch statement is going to go to given the constant value of the
  51402. + variable (bbs_list_array[i][bbs_list_size[i]-1]). */
  51403. +
  51404. +static basic_block **bbs_list_array;
  51405. +static int *val_array;
  51406. +static int *bbs_list_size;
  51407. +static int max_path_count;
  51408. +static int max_insn_count;
  51409. +static int n_bbs_list;
  51410. +
  51411. +/* bbs_list[0] is the block with the switch statement,
  51412. + bbs_list[n-1] is the block where the switch statement variable is assigned
  51413. + a constant value,
  51414. + The entries in between make a (reverse) path between the two.
  51415. +
  51416. + We don't want to change bb_list, we want to leave that alone and
  51417. + and copy the path to bbs_list_array so that we wind up with a list (array)
  51418. + of paths that we want to update. We also want to add the block that the
  51419. + switch is going to go to on to the list so that we know which exit from
  51420. + the switch statement is important. */
  51421. +
  51422. +static void
  51423. +save_new_path (basic_block *bbs_list, int n, tree val)
  51424. +{
  51425. + int i;
  51426. + int insn_count;
  51427. + basic_block bb;
  51428. + edge switch_taken_edge;
  51429. + gimple_stmt_iterator gsi;
  51430. +
  51431. + if (n <= 1) return;
  51432. +
  51433. + if (n_bbs_list >= max_path_count)
  51434. + return;
  51435. +
  51436. + /* Put the blocks in 'correct' order and add in where we want to go after
  51437. + the switch statement, We want to leave bbs_list untouched for future
  51438. + calls. */
  51439. +
  51440. + bbs_list_array[n_bbs_list] = XNEWVEC (basic_block, n+1);
  51441. + for (i = 0; i < n; i++)
  51442. + bbs_list_array[n_bbs_list][i] = bbs_list[n-i-1];
  51443. +
  51444. + switch_taken_edge = find_taken_edge (bbs_list[0], val);
  51445. + bbs_list_array[n_bbs_list][n] = switch_taken_edge->dest;
  51446. +
  51447. + bbs_list_size[n_bbs_list] = n + 1;
  51448. + val_array[n_bbs_list] = (int) TREE_INT_CST_LOW (val);
  51449. +
  51450. + /* Count how many instructions are in the blocks we are going to
  51451. + duplicate and if there are too many do not save this path
  51452. + (return without incrementing n_bbs_list). */
  51453. +
  51454. + insn_count = 0;
  51455. + for (i = 1; i < n; i++)
  51456. + {
  51457. + bb = bbs_list_array[n_bbs_list][i];
  51458. + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
  51459. + insn_count += estimate_num_insns (gsi_stmt (gsi), &eni_size_weights);
  51460. + }
  51461. +
  51462. + if (insn_count > max_insn_count)
  51463. + return;
  51464. +
  51465. + n_bbs_list = n_bbs_list + 1;
  51466. +}
  51467. +
  51468. +/* switch_stmt is a switch statement whose switch index expression
  51469. + is the variable expr. We trace the value of the variable back
  51470. + through any phi nodes looking for places where it gets a constant
  51471. + value and save the path in bbs_list. Then we call save_new_path
  51472. + to create a list of such paths. */
  51473. +
  51474. +static void
  51475. +process_switch (tree expr, gimple switch_stmt,
  51476. + struct pointer_set_t *visited_phis,
  51477. + basic_block *bbs_list, int n)
  51478. +{
  51479. + gimple def_stmt;
  51480. + tree var;
  51481. + unsigned int i;
  51482. + edge e;
  51483. + edge_iterator ei;
  51484. + basic_block bbx;
  51485. + basic_block var_bb;
  51486. + int e_count;
  51487. +
  51488. + gcc_assert (gimple_code (switch_stmt) == GIMPLE_SWITCH);
  51489. + var = SSA_NAME_VAR (expr);
  51490. + def_stmt = SSA_NAME_DEF_STMT (expr);
  51491. + var_bb = gimple_bb (def_stmt);
  51492. +
  51493. + if (var == NULL || var_bb == NULL) return;
  51494. +
  51495. + /* We have a variable definition (var) that is defined in var_bb,
  51496. + We want to put the path from var_bb to the current bb into the
  51497. + bbs_list. If there is more then one path, skip this and don't
  51498. + try to do the optimization. */
  51499. +
  51500. + bbx = bbs_list[n-1];
  51501. + while (bbx != var_bb)
  51502. + {
  51503. + e_count = 0;
  51504. + FOR_EACH_EDGE (e, ei, bbx->preds)
  51505. + {
  51506. + if (find_path (var_bb, e->src))
  51507. + {
  51508. + bbs_list[n] = e->src;
  51509. + n = n + 1;
  51510. + e_count = e_count + 1;
  51511. + }
  51512. + }
  51513. + if (e_count != 1) return;
  51514. + bbx = bbs_list[n-1];
  51515. + }
  51516. +
  51517. + if ((gimple_code (def_stmt) == GIMPLE_PHI)
  51518. + && !pointer_set_insert (visited_phis, def_stmt))
  51519. + {
  51520. + for (i = 0; i < gimple_phi_num_args (def_stmt); i++)
  51521. + {
  51522. + tree arg = gimple_phi_arg_def (def_stmt, i);
  51523. + if (arg && (TREE_CODE (arg) == INTEGER_CST))
  51524. + {
  51525. + /* const char *name = IDENTIFIER_POINTER (DECL_NAME (var)); */
  51526. + bbs_list[n] = gimple_phi_arg_edge (def_stmt, i)->src;
  51527. + save_new_path(bbs_list, n + 1, arg);
  51528. + }
  51529. + else if (arg && (TREE_CODE (arg) == SSA_NAME))
  51530. + {
  51531. + bbs_list[n] = gimple_phi_arg_edge (def_stmt, i)->src;
  51532. + process_switch (arg, switch_stmt, visited_phis, bbs_list, n+1);
  51533. + }
  51534. + }
  51535. + }
  51536. +}
  51537. +
  51538. +/* Find paths that lead from blocks where a variable is assigned a constant
  51539. + value to a switch statement where that variable is used as the switch
  51540. + index. Save the paths in bbs_list_array so that they can be processed
  51541. + by copy_switch_paths. */
  51542. +
  51543. +static unsigned int
  51544. +find_switch_shortcuts (void)
  51545. +{
  51546. + basic_block bb;
  51547. + struct pointer_set_t *visited_phis;
  51548. + basic_block *bbs_list;
  51549. + int n = 1;
  51550. +
  51551. + bbs_list = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun));
  51552. + visited_phis = pointer_set_create ();
  51553. + FOR_EACH_BB_FN (bb, cfun)
  51554. + {
  51555. + gimple stmt = last_stmt (bb);
  51556. + if (stmt && gimple_code (stmt) == GIMPLE_SWITCH)
  51557. + {
  51558. + tree op = gimple_switch_index (stmt);
  51559. + tree var = SSA_NAME_VAR (op);
  51560. + if (var)
  51561. + {
  51562. + bbs_list[0] = bb;
  51563. + process_switch (op, stmt, visited_phis, bbs_list, n);
  51564. + }
  51565. + }
  51566. + }
  51567. + pointer_set_destroy (visited_phis);
  51568. + XDELETEVEC (bbs_list);
  51569. + return 0;
  51570. +}
  51571. +
  51572. +/* Call gimple_duplicate_sese_region to douplicate the blocks in bb_list.
  51573. + We free and recalculate all ssa and dominance information afterwords
  51574. + because the regsion being copied is not really SESE and so we cannot
  51575. + trust gimple_duplicate_sese_region to correctly update the dataflow
  51576. + information. */
  51577. +
  51578. +static void
  51579. +duplicate_blocks (basic_block *bb_list, int bb_count)
  51580. +{
  51581. + edge orig_edge, exit_edge;
  51582. +
  51583. + orig_edge = find_edge (bb_list[0], bb_list[1]);
  51584. + exit_edge = find_edge (bb_list[bb_count-2], bb_list[bb_count-1]);
  51585. + gimple_duplicate_sese_region (orig_edge, exit_edge, &bb_list[1], bb_count-2, NULL, true);
  51586. + free_dominance_info (CDI_DOMINATORS);
  51587. + update_ssa (TODO_update_ssa);
  51588. + calculate_dominance_info (CDI_DOMINATORS);
  51589. +}
  51590. +
  51591. +/* Go through the paths saved in bbs_list_array and make copies of them. */
  51592. +
  51593. +static void
  51594. +copy_switch_paths (void)
  51595. +{
  51596. + int i;
  51597. +
  51598. + /* Process each path in bbs_list_size. */
  51599. + for (i = 0; i < n_bbs_list; i++)
  51600. + {
  51601. + /* For each path in bbs_list_size loop through and copy each block in
  51602. + the path (except the first on where the constant is assigned and
  51603. + the final one where the switch statement goes to. */
  51604. +
  51605. + if (!single_pred_p (bbs_list_array[i][1]))
  51606. + duplicate_blocks (bbs_list_array[i], bbs_list_size[i]);
  51607. + }
  51608. +}
  51609. +
  51610. +static unsigned int
  51611. +do_switch_shortcut (void)
  51612. +{
  51613. + int i;
  51614. +
  51615. + n_bbs_list = 0;
  51616. + max_insn_count = PARAM_VALUE (PARAM_MAX_SWITCH_INSNS);
  51617. + max_path_count = PARAM_VALUE (PARAM_MAX_SWITCH_PATHS);
  51618. + val_array = XNEWVEC (int, max_path_count);
  51619. + bbs_list_size = XNEWVEC (int, max_path_count);
  51620. + bbs_list_array = XNEWVEC (basic_block *, max_path_count);
  51621. + find_switch_shortcuts ();
  51622. + copy_switch_paths ();
  51623. + XDELETEVEC (val_array);
  51624. + XDELETEVEC (bbs_list_size);
  51625. + for (i = 0; i < n_bbs_list; i++)
  51626. + XDELETEVEC (bbs_list_array[i]);
  51627. + XDELETEVEC (bbs_list_array);
  51628. + return 0;
  51629. +}
  51630. +
  51631. +/* The pass gate. */
  51632. +
  51633. +static bool
  51634. +gate_switch_shortcut (void)
  51635. +{
  51636. + return flag_tree_switch_shortcut;
  51637. +}
  51638. +
  51639. +namespace {
  51640. +#if 0
  51641. +struct gimple_opt_pass pass_switch_shortcut =
  51642. +{
  51643. + {
  51644. + GIMPLE_PASS,
  51645. + "switch_shortcut", /* name */
  51646. + OPTGROUP_NONE, /* optinfo_flags */
  51647. + gate_switch_shortcut, /* gate */
  51648. + do_switch_shortcut, /* execute */
  51649. + NULL, /* sub */
  51650. + NULL, /* next */
  51651. + 0, /* static_pass_number */
  51652. + TV_SWITCH_SHORTCUT, /* tv_id */
  51653. + PROP_cfg | PROP_ssa, /* properties_required */
  51654. + 0, /* properties_provided */
  51655. + 0, /* properties_destroyed */
  51656. + 0, /* todo_flags_start */
  51657. + TODO_cleanup_cfg | TODO_verify_all, /* todo_flags_finish */
  51658. + }
  51659. +};
  51660. +#endif
  51661. +
  51662. +const pass_data pass_data_switch_shortcut =
  51663. +{
  51664. + GIMPLE_PASS, /* type */
  51665. + "switch_shortcut", /* name */
  51666. + OPTGROUP_NONE, /* optinfo_flags */
  51667. + true, /* has_gate */
  51668. + true, /* has_execute */
  51669. + TV_SWITCH_SHORTCUT, /* tv_id */
  51670. + ( PROP_cfg | PROP_ssa ), /* properties_required */
  51671. + 0, /* properties_provided */
  51672. + 0, /* properties_destroyed */
  51673. + 0, /* todo_flags_start */
  51674. + ( TODO_cleanup_cfg | TODO_verify_all), /* todo_flags_finish */
  51675. +};
  51676. +
  51677. +class pass_switch_shortcut : public gimple_opt_pass
  51678. +{
  51679. +public:
  51680. + pass_switch_shortcut (gcc::context *ctxt)
  51681. + : gimple_opt_pass (pass_data_switch_shortcut, ctxt)
  51682. + {}
  51683. +
  51684. + /* opt_pass methods: */
  51685. + bool gate () { return gate_switch_shortcut (); }
  51686. + unsigned int execute () { return do_switch_shortcut (); }
  51687. +
  51688. +}; // class pass_convert_switch
  51689. +
  51690. +
  51691. +}
  51692. +
  51693. +gimple_opt_pass *
  51694. +make_pass_switch_shortcut (gcc::context *ctxt)
  51695. +{
  51696. + return new pass_switch_shortcut (ctxt);
  51697. +}
  51698. diff -Nur gcc-4.9.4.orig/gcc/tree-vrp.c gcc-4.9.4/gcc/tree-vrp.c
  51699. --- gcc-4.9.4.orig/gcc/tree-vrp.c 2016-02-11 10:22:21.000000000 +0100
  51700. +++ gcc-4.9.4/gcc/tree-vrp.c 2016-08-08 20:37:53.578582611 +0200
  51701. @@ -9009,6 +9009,7 @@
  51702. used for the comparison directly if we just massage the constant in the
  51703. comparison. */
  51704. if (TREE_CODE (op0) == SSA_NAME
  51705. + && has_single_use (op0)
  51706. && TREE_CODE (op1) == INTEGER_CST)
  51707. {
  51708. gimple def_stmt = SSA_NAME_DEF_STMT (op0);
  51709. diff -Nur gcc-4.9.4.orig/gcc/varasm.c gcc-4.9.4/gcc/varasm.c
  51710. --- gcc-4.9.4.orig/gcc/varasm.c 2015-05-26 22:16:17.000000000 +0200
  51711. +++ gcc-4.9.4/gcc/varasm.c 2016-08-08 20:37:53.578582611 +0200
  51712. @@ -3243,7 +3243,7 @@
  51713. TREE_CONSTANT_POOL_ADDRESS_P (symbol) = 1;
  51714. rtl = gen_const_mem (TYPE_MODE (TREE_TYPE (exp)), symbol);
  51715. - set_mem_attributes (rtl, exp, 1);
  51716. + set_mem_attributes (rtl, decl, 1);
  51717. set_mem_alias_set (rtl, 0);
  51718. /* We cannot share RTX'es in pool entries.
  51719. diff -Nur gcc-4.9.4.orig/libcpp/configure gcc-4.9.4/libcpp/configure
  51720. --- gcc-4.9.4.orig/libcpp/configure 2016-08-03 07:09:47.000000000 +0200
  51721. +++ gcc-4.9.4/libcpp/configure 2016-08-08 20:37:53.578582611 +0200
  51722. @@ -7162,6 +7162,7 @@
  51723. i[34567]86-*-* | x86_64-*-solaris2.1[0-9]* | \
  51724. mips*-*-* | \
  51725. mmix-*-* | \
  51726. + nds32*-*-* | \
  51727. powerpc*-*-* | \
  51728. rs6000*-*-* | \
  51729. s390*-*-* | \
  51730. diff -Nur gcc-4.9.4.orig/libcpp/configure.ac gcc-4.9.4/libcpp/configure.ac
  51731. --- gcc-4.9.4.orig/libcpp/configure.ac 2014-02-24 16:08:00.000000000 +0100
  51732. +++ gcc-4.9.4/libcpp/configure.ac 2016-08-08 20:37:53.578582611 +0200
  51733. @@ -191,6 +191,7 @@
  51734. i[34567]86-*-* | x86_64-*-solaris2.1[0-9]* | \
  51735. mips*-*-* | \
  51736. mmix-*-* | \
  51737. + nds32*-*-* | \
  51738. powerpc*-*-* | \
  51739. rs6000*-*-* | \
  51740. s390*-*-* | \
  51741. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/crtzero.S gcc-4.9.4/libgcc/config/nds32/crtzero.S
  51742. --- gcc-4.9.4.orig/libgcc/config/nds32/crtzero.S 2014-01-02 23:25:22.000000000 +0100
  51743. +++ gcc-4.9.4/libgcc/config/nds32/crtzero.S 1970-01-01 01:00:00.000000000 +0100
  51744. @@ -1,103 +0,0 @@
  51745. -/* The startup code sample of Andes NDS32 cpu for GNU compiler
  51746. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  51747. - Contributed by Andes Technology Corporation.
  51748. -
  51749. - This file is part of GCC.
  51750. -
  51751. - GCC is free software; you can redistribute it and/or modify it
  51752. - under the terms of the GNU General Public License as published
  51753. - by the Free Software Foundation; either version 3, or (at your
  51754. - option) any later version.
  51755. -
  51756. - GCC is distributed in the hope that it will be useful, but WITHOUT
  51757. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  51758. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  51759. - License for more details.
  51760. -
  51761. - Under Section 7 of GPL version 3, you are granted additional
  51762. - permissions described in the GCC Runtime Library Exception, version
  51763. - 3.1, as published by the Free Software Foundation.
  51764. -
  51765. - You should have received a copy of the GNU General Public License and
  51766. - a copy of the GCC Runtime Library Exception along with this program;
  51767. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  51768. - <http://www.gnu.org/licenses/>. */
  51769. -
  51770. -!!==============================================================================
  51771. -!!
  51772. -!! crtzero.S
  51773. -!!
  51774. -!! This is JUST A SAMPLE of nds32 startup code !!
  51775. -!! You can refer this content and implement
  51776. -!! the actual one in newlib/mculib.
  51777. -!!
  51778. -!!==============================================================================
  51779. -
  51780. -!!------------------------------------------------------------------------------
  51781. -!! Jump to start up code
  51782. -!!------------------------------------------------------------------------------
  51783. - .section .nds32_init, "ax"
  51784. - j _start
  51785. -
  51786. -!!------------------------------------------------------------------------------
  51787. -!! Startup code implementation
  51788. -!!------------------------------------------------------------------------------
  51789. - .section .text
  51790. - .global _start
  51791. - .weak _SDA_BASE_
  51792. - .weak _FP_BASE_
  51793. - .align 2
  51794. - .func _start
  51795. - .type _start, @function
  51796. -_start:
  51797. -.L_fp_gp_lp_init:
  51798. - la $fp, _FP_BASE_ ! init $fp
  51799. - la $gp, _SDA_BASE_ ! init $gp for small data access
  51800. - movi $lp, 0 ! init $lp
  51801. -
  51802. -.L_stack_init:
  51803. - la $sp, _stack ! init $sp
  51804. - movi $r0, -8 ! align $sp to 8-byte (use 0xfffffff8)
  51805. - and $sp, $sp, $r0 ! align $sp to 8-byte (filter out lower 3-bit)
  51806. -
  51807. -.L_bss_init:
  51808. - ! clear BSS, this process can be 4 time faster if data is 4 byte aligned
  51809. - ! if so, use swi.p instead of sbi.p
  51810. - ! the related stuff are defined in linker script
  51811. - la $r0, _edata ! get the starting addr of bss
  51812. - la $r2, _end ! get ending addr of bss
  51813. - beq $r0, $r2, .L_call_main ! if no bss just do nothing
  51814. - movi $r1, 0 ! should be cleared to 0
  51815. -.L_clear_bss:
  51816. - sbi.p $r1, [$r0], 1 ! Set 0 to bss
  51817. - bne $r0, $r2, .L_clear_bss ! Still bytes left to set
  51818. -
  51819. -!.L_stack_heap_check:
  51820. -! la $r0, _end ! init heap_end
  51821. -! s.w $r0, heap_end ! save it
  51822. -
  51823. -
  51824. -!.L_init_argc_argv:
  51825. -! ! argc/argv initialization if necessary; default implementation is in crt1.o
  51826. -! la $r9, _arg_init ! load address of _arg_init?
  51827. -! beqz $r9, .L4 ! has _arg_init? no, go check main()
  51828. -! addi $sp, $sp, -512 ! allocate space for command line + arguments
  51829. -! move $r6, $sp ! r6 = buffer addr of cmd line
  51830. -! move $r0, $r6 ! r0 = buffer addr of cmd line
  51831. -! syscall 6002 ! get cmd line
  51832. -! move $r0, $r6 ! r0 = buffer addr of cmd line
  51833. -! addi $r1, $r6, 256 ! r1 = argv
  51834. -! jral $r9 ! init argc/argv
  51835. -! addi $r1, $r6, 256 ! r1 = argv
  51836. -
  51837. -.L_call_main:
  51838. - ! call main() if main() is provided
  51839. - la $r15, main ! load address of main
  51840. - jral $r15 ! call main
  51841. -
  51842. -.L_terminate_program:
  51843. - syscall 0x1 ! use syscall 0x1 to terminate program
  51844. - .size _start, .-_start
  51845. - .end
  51846. -
  51847. -!! ------------------------------------------------------------------------
  51848. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/initfini.c gcc-4.9.4/libgcc/config/nds32/initfini.c
  51849. --- gcc-4.9.4.orig/libgcc/config/nds32/initfini.c 2014-01-02 23:25:22.000000000 +0100
  51850. +++ gcc-4.9.4/libgcc/config/nds32/initfini.c 2016-08-08 20:37:53.698587257 +0200
  51851. @@ -1,7 +1,7 @@
  51852. /* .init/.fini section handling + C++ global constructor/destructor
  51853. handling of Andes NDS32 cpu for GNU compiler.
  51854. This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
  51855. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  51856. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  51857. Contributed by Andes Technology Corporation.
  51858. This file is part of GCC.
  51859. @@ -25,6 +25,10 @@
  51860. see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  51861. <http://www.gnu.org/licenses/>. */
  51862. +#include <stddef.h>
  51863. +/* Need header file for `struct object' type. */
  51864. +#include "../libgcc/unwind-dw2-fde.h"
  51865. +
  51866. /* Declare a pointer to void function type. */
  51867. typedef void (*func_ptr) (void);
  51868. @@ -42,11 +46,59 @@
  51869. refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
  51870. symbol in crtinit.o, where they are defined. */
  51871. -static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
  51872. - = { (func_ptr) (-1) };
  51873. +static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used))
  51874. + = { (func_ptr) 0 };
  51875. +
  51876. +static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used))
  51877. + = { (func_ptr) 0 };
  51878. +
  51879. +
  51880. +#ifdef SUPPORT_UNWINDING_DWARF2
  51881. +/* Preparation of exception handling with dwar2 mechanism registration. */
  51882. +
  51883. +asm ("\n\
  51884. + .section .eh_frame,\"aw\",@progbits\n\
  51885. + .global __EH_FRAME_BEGIN__\n\
  51886. + .type __EH_FRAME_BEGIN__, @object\n\
  51887. + .align 2\n\
  51888. +__EH_FRAME_BEGIN__:\n\
  51889. + ! Beginning location of eh_frame section\n\
  51890. + .previous\n\
  51891. +");
  51892. +
  51893. +extern func_ptr __EH_FRAME_BEGIN__[];
  51894. +
  51895. -static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
  51896. - = { (func_ptr) (-1) };
  51897. +/* Note that the following two functions are going to be chained into
  51898. + constructor and destructor list, repectively. So these two declarations
  51899. + must be placed after __CTOR_LIST__ and __DTOR_LIST. */
  51900. +extern void __nds32_register_eh(void) __attribute__((constructor, used));
  51901. +extern void __nds32_deregister_eh(void) __attribute__((destructor, used));
  51902. +
  51903. +/* Register the exception handling table as the first constructor. */
  51904. +void
  51905. +__nds32_register_eh (void)
  51906. +{
  51907. + static struct object object;
  51908. + if (__register_frame_info)
  51909. + __register_frame_info (__EH_FRAME_BEGIN__, &object);
  51910. +}
  51911. +
  51912. +/* Unregister the exception handling table as a deconstructor. */
  51913. +void
  51914. +__nds32_deregister_eh (void)
  51915. +{
  51916. + static int completed = 0;
  51917. +
  51918. + if (completed)
  51919. + return;
  51920. +
  51921. + if (__deregister_frame_info)
  51922. + __deregister_frame_info (__EH_FRAME_BEGIN__);
  51923. +
  51924. + completed = 1;
  51925. +}
  51926. +#endif
  51927. /* Run all the global destructors on exit from the program. */
  51928. @@ -63,7 +115,7 @@
  51929. same particular root executable or shared library file. */
  51930. static void __do_global_dtors (void)
  51931. -asm ("__do_global_dtors") __attribute__ ((section (".text")));
  51932. +asm ("__do_global_dtors") __attribute__ ((section (".text"), used));
  51933. static void
  51934. __do_global_dtors (void)
  51935. @@ -116,23 +168,37 @@
  51936. last, these words naturally end up at the very ends of the two lists
  51937. contained in these two sections. */
  51938. -static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
  51939. +static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used))
  51940. = { (func_ptr) 0 };
  51941. -static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
  51942. +static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used))
  51943. = { (func_ptr) 0 };
  51944. +#ifdef SUPPORT_UNWINDING_DWARF2
  51945. +/* ZERO terminator in .eh_frame section. */
  51946. +asm ("\n\
  51947. + .section .eh_frame,\"aw\",@progbits\n\
  51948. + .global __EH_FRAME_END__\n\
  51949. + .type __EH_FRAME_END__, @object\n\
  51950. + .align 2\n\
  51951. +__EH_FRAME_END__:\n\
  51952. + ! End location of eh_frame section with ZERO terminator\n\
  51953. + .word 0\n\
  51954. + .previous\n\
  51955. +");
  51956. +#endif
  51957. +
  51958. /* Run all global constructors for the program.
  51959. Note that they are run in reverse order. */
  51960. static void __do_global_ctors (void)
  51961. -asm ("__do_global_ctors") __attribute__ ((section (".text")));
  51962. +asm ("__do_global_ctors") __attribute__ ((section (".text"), used));
  51963. static void
  51964. __do_global_ctors (void)
  51965. {
  51966. func_ptr *p;
  51967. - for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
  51968. + for (p = __CTOR_END__ - 1; *p; p--)
  51969. (*p) ();
  51970. }
  51971. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc gcc-4.9.4/libgcc/config/nds32/isr-library/adj_intr_lvl.inc
  51972. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2014-01-02 23:25:22.000000000 +0100
  51973. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/adj_intr_lvl.inc 2016-08-08 20:37:53.698587257 +0200
  51974. @@ -1,5 +1,5 @@
  51975. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  51976. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  51977. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  51978. Contributed by Andes Technology Corporation.
  51979. This file is part of GCC.
  51980. @@ -26,13 +26,26 @@
  51981. .macro ADJ_INTR_LVL
  51982. #if defined(NDS32_NESTED) /* Nested handler. */
  51983. mfsr $r3, $PSW
  51984. + /* By substracting 1 from $PSW, we can lower PSW.INTL
  51985. + and enable GIE simultaneously. */
  51986. addi $r3, $r3, #-0x1
  51987. + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
  51988. + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
  51989. + #endif
  51990. mtsr $r3, $PSW
  51991. #elif defined(NDS32_NESTED_READY) /* Nested ready handler. */
  51992. /* Save ipc and ipsw and lower INT level. */
  51993. mfsr $r3, $PSW
  51994. addi $r3, $r3, #-0x2
  51995. + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
  51996. + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
  51997. + #endif
  51998. mtsr $r3, $PSW
  51999. #else /* Not nested handler. */
  52000. + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
  52001. + mfsr $r3, $PSW
  52002. + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
  52003. + mtsr $r3, $PSW
  52004. + #endif
  52005. #endif
  52006. .endm
  52007. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/excp_isr_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/excp_isr_4b.S
  52008. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/excp_isr_4b.S 2014-01-02 23:25:22.000000000 +0100
  52009. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/excp_isr_4b.S 1970-01-01 01:00:00.000000000 +0100
  52010. @@ -1,133 +0,0 @@
  52011. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52012. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52013. - Contributed by Andes Technology Corporation.
  52014. -
  52015. - This file is part of GCC.
  52016. -
  52017. - GCC is free software; you can redistribute it and/or modify it
  52018. - under the terms of the GNU General Public License as published
  52019. - by the Free Software Foundation; either version 3, or (at your
  52020. - option) any later version.
  52021. -
  52022. - GCC is distributed in the hope that it will be useful, but WITHOUT
  52023. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  52024. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  52025. - License for more details.
  52026. -
  52027. - Under Section 7 of GPL version 3, you are granted additional
  52028. - permissions described in the GCC Runtime Library Exception, version
  52029. - 3.1, as published by the Free Software Foundation.
  52030. -
  52031. - You should have received a copy of the GNU General Public License and
  52032. - a copy of the GCC Runtime Library Exception along with this program;
  52033. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  52034. - <http://www.gnu.org/licenses/>. */
  52035. -
  52036. -#include "save_mac_regs.inc"
  52037. -#include "save_fpu_regs.inc"
  52038. -#include "save_fpu_regs_00.inc"
  52039. -#include "save_fpu_regs_01.inc"
  52040. -#include "save_fpu_regs_02.inc"
  52041. -#include "save_fpu_regs_03.inc"
  52042. -#include "save_all.inc"
  52043. -#include "save_partial.inc"
  52044. -#include "adj_intr_lvl.inc"
  52045. -#include "restore_mac_regs.inc"
  52046. -#include "restore_fpu_regs_00.inc"
  52047. -#include "restore_fpu_regs_01.inc"
  52048. -#include "restore_fpu_regs_02.inc"
  52049. -#include "restore_fpu_regs_03.inc"
  52050. -#include "restore_fpu_regs.inc"
  52051. -#include "restore_all.inc"
  52052. -#include "restore_partial.inc"
  52053. - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  52054. - .align 1
  52055. -/*
  52056. - First Level Handlers
  52057. - 1. First Level Handlers are invokded in vector section via jump instruction
  52058. - with specific names for different configurations.
  52059. - 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52060. - _nds32_i_SR_NT for interrupt handlers.
  52061. - 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52062. - 2.2 SR: Saved Registers
  52063. - sa: Save All regs (context)
  52064. - ps: Partial Save (all caller-saved regs)
  52065. - 2.3 NT: Nested Type
  52066. - ns: nested
  52067. - nn: not nested
  52068. - nr: nested ready
  52069. -*/
  52070. -
  52071. -/*
  52072. - This is 4-byte vector size version.
  52073. - The "_4b" postfix was added for 4-byte version symbol.
  52074. -*/
  52075. -#ifdef NDS32_SAVE_ALL_REGS
  52076. -#if defined(NDS32_NESTED)
  52077. - .globl _nds32_e_sa_ns_4b
  52078. - .type _nds32_e_sa_ns_4b, @function
  52079. -_nds32_e_sa_ns_4b:
  52080. -#elif defined(NDS32_NESTED_READY)
  52081. - .globl _nds32_e_sa_nr_4b
  52082. - .type _nds32_e_sa_nr_4b, @function
  52083. -_nds32_e_sa_nr_4b:
  52084. -#else /* Not nested handler. */
  52085. - .globl _nds32_e_sa_nn_4b
  52086. - .type _nds32_e_sa_nn_4b, @function
  52087. -_nds32_e_sa_nn_4b:
  52088. -#endif /* endif for Nest Type */
  52089. -#else /* not NDS32_SAVE_ALL_REGS */
  52090. -#if defined(NDS32_NESTED)
  52091. - .globl _nds32_e_ps_ns_4b
  52092. - .type _nds32_e_ps_ns_4b, @function
  52093. -_nds32_e_ps_ns_4b:
  52094. -#elif defined(NDS32_NESTED_READY)
  52095. - .globl _nds32_e_ps_nr_4b
  52096. - .type _nds32_e_ps_nr_4b, @function
  52097. -_nds32_e_ps_nr_4b:
  52098. -#else /* Not nested handler. */
  52099. - .globl _nds32_e_ps_nn_4b
  52100. - .type _nds32_e_ps_nn_4b, @function
  52101. -_nds32_e_ps_nn_4b:
  52102. -#endif /* endif for Nest Type */
  52103. -#endif /* not NDS32_SAVE_ALL_REGS */
  52104. -
  52105. -/*
  52106. - This is 4-byte vector size version.
  52107. - The vector id was restored into $lp in vector by compiler.
  52108. -*/
  52109. -#ifdef NDS32_SAVE_ALL_REGS
  52110. - SAVE_ALL_4B
  52111. -#else
  52112. - SAVE_PARTIAL_4B
  52113. -#endif
  52114. - /* Prepare to call 2nd level handler. */
  52115. - la $r2, _nds32_jmptbl_00
  52116. - lw $r2, [$r2 + $r0 << #2]
  52117. - ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
  52118. - jral $r2
  52119. - /* Restore used registers. */
  52120. -#ifdef NDS32_SAVE_ALL_REGS
  52121. - RESTORE_ALL
  52122. -#else
  52123. - RESTORE_PARTIAL
  52124. -#endif
  52125. - iret
  52126. -
  52127. -#ifdef NDS32_SAVE_ALL_REGS
  52128. -#if defined(NDS32_NESTED)
  52129. - .size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
  52130. -#elif defined(NDS32_NESTED_READY)
  52131. - .size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
  52132. -#else /* Not nested handler. */
  52133. - .size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
  52134. -#endif /* endif for Nest Type */
  52135. -#else /* not NDS32_SAVE_ALL_REGS */
  52136. -#if defined(NDS32_NESTED)
  52137. - .size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
  52138. -#elif defined(NDS32_NESTED_READY)
  52139. - .size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
  52140. -#else /* Not nested handler. */
  52141. - .size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
  52142. -#endif /* endif for Nest Type */
  52143. -#endif /* not NDS32_SAVE_ALL_REGS */
  52144. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/excp_isr.S gcc-4.9.4/libgcc/config/nds32/isr-library/excp_isr.S
  52145. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/excp_isr.S 2014-01-02 23:25:22.000000000 +0100
  52146. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/excp_isr.S 2016-08-08 20:37:53.698587257 +0200
  52147. @@ -1,5 +1,5 @@
  52148. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52149. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52150. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52151. Contributed by Andes Technology Corporation.
  52152. This file is part of GCC.
  52153. @@ -23,6 +23,7 @@
  52154. see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  52155. <http://www.gnu.org/licenses/>. */
  52156. +#include "save_usr_regs.inc"
  52157. #include "save_mac_regs.inc"
  52158. #include "save_fpu_regs.inc"
  52159. #include "save_fpu_regs_00.inc"
  52160. @@ -32,35 +33,33 @@
  52161. #include "save_all.inc"
  52162. #include "save_partial.inc"
  52163. #include "adj_intr_lvl.inc"
  52164. -#include "restore_mac_regs.inc"
  52165. #include "restore_fpu_regs_00.inc"
  52166. #include "restore_fpu_regs_01.inc"
  52167. #include "restore_fpu_regs_02.inc"
  52168. #include "restore_fpu_regs_03.inc"
  52169. #include "restore_fpu_regs.inc"
  52170. +#include "restore_mac_regs.inc"
  52171. +#include "restore_usr_regs.inc"
  52172. #include "restore_all.inc"
  52173. #include "restore_partial.inc"
  52174. +
  52175. .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  52176. .align 1
  52177. -/*
  52178. - First Level Handlers
  52179. - 1. First Level Handlers are invokded in vector section via jump instruction
  52180. - with specific names for different configurations.
  52181. - 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52182. - _nds32_i_SR_NT for interrupt handlers.
  52183. - 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52184. - 2.2 SR: Saved Registers
  52185. - sa: Save All regs (context)
  52186. - ps: Partial Save (all caller-saved regs)
  52187. - 2.3 NT: Nested Type
  52188. - ns: nested
  52189. - nn: not nested
  52190. - nr: nested ready
  52191. -*/
  52192. -
  52193. -/*
  52194. - This is original 16-byte vector size version.
  52195. -*/
  52196. +
  52197. +/* First Level Handlers
  52198. + 1. First Level Handlers are invokded in vector section via jump instruction
  52199. + with specific names for different configurations.
  52200. + 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52201. + _nds32_i_SR_NT for interrupt handlers.
  52202. + 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52203. + 2.2 SR -- Saved Registers
  52204. + sa: Save All regs (context)
  52205. + ps: Partial Save (all caller-saved regs)
  52206. + 2.3 NT -- Nested Type
  52207. + ns: nested
  52208. + nn: not nested
  52209. + nr: nested ready */
  52210. +
  52211. #ifdef NDS32_SAVE_ALL_REGS
  52212. #if defined(NDS32_NESTED)
  52213. .globl _nds32_e_sa_ns
  52214. @@ -91,21 +90,26 @@
  52215. #endif /* endif for Nest Type */
  52216. #endif /* not NDS32_SAVE_ALL_REGS */
  52217. -/*
  52218. - This is 16-byte vector size version.
  52219. - The vector id was restored into $r0 in vector by compiler.
  52220. -*/
  52221. +
  52222. +/* For 4-byte vector size version, the vector id is
  52223. + extracted from $ITYPE and is set into $r0 by library.
  52224. + For 16-byte vector size version, the vector id
  52225. + is set into $r0 in vector section by compiler. */
  52226. +
  52227. +/* Save used registers. */
  52228. #ifdef NDS32_SAVE_ALL_REGS
  52229. SAVE_ALL
  52230. #else
  52231. SAVE_PARTIAL
  52232. #endif
  52233. +
  52234. /* Prepare to call 2nd level handler. */
  52235. la $r2, _nds32_jmptbl_00
  52236. lw $r2, [$r2 + $r0 << #2]
  52237. ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
  52238. jral $r2
  52239. - /* Restore used registers. */
  52240. +
  52241. +/* Restore used registers. */
  52242. #ifdef NDS32_SAVE_ALL_REGS
  52243. RESTORE_ALL
  52244. #else
  52245. @@ -113,6 +117,7 @@
  52246. #endif
  52247. iret
  52248. +
  52249. #ifdef NDS32_SAVE_ALL_REGS
  52250. #if defined(NDS32_NESTED)
  52251. .size _nds32_e_sa_ns, .-_nds32_e_sa_ns
  52252. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/intr_isr_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/intr_isr_4b.S
  52253. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/intr_isr_4b.S 2014-01-02 23:25:22.000000000 +0100
  52254. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/intr_isr_4b.S 1970-01-01 01:00:00.000000000 +0100
  52255. @@ -1,134 +0,0 @@
  52256. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52257. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52258. - Contributed by Andes Technology Corporation.
  52259. -
  52260. - This file is part of GCC.
  52261. -
  52262. - GCC is free software; you can redistribute it and/or modify it
  52263. - under the terms of the GNU General Public License as published
  52264. - by the Free Software Foundation; either version 3, or (at your
  52265. - option) any later version.
  52266. -
  52267. - GCC is distributed in the hope that it will be useful, but WITHOUT
  52268. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  52269. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  52270. - License for more details.
  52271. -
  52272. - Under Section 7 of GPL version 3, you are granted additional
  52273. - permissions described in the GCC Runtime Library Exception, version
  52274. - 3.1, as published by the Free Software Foundation.
  52275. -
  52276. - You should have received a copy of the GNU General Public License and
  52277. - a copy of the GCC Runtime Library Exception along with this program;
  52278. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  52279. - <http://www.gnu.org/licenses/>. */
  52280. -
  52281. -#include "save_mac_regs.inc"
  52282. -#include "save_fpu_regs.inc"
  52283. -#include "save_fpu_regs_00.inc"
  52284. -#include "save_fpu_regs_01.inc"
  52285. -#include "save_fpu_regs_02.inc"
  52286. -#include "save_fpu_regs_03.inc"
  52287. -#include "save_all.inc"
  52288. -#include "save_partial.inc"
  52289. -#include "adj_intr_lvl.inc"
  52290. -#include "restore_mac_regs.inc"
  52291. -#include "restore_fpu_regs_00.inc"
  52292. -#include "restore_fpu_regs_01.inc"
  52293. -#include "restore_fpu_regs_02.inc"
  52294. -#include "restore_fpu_regs_03.inc"
  52295. -#include "restore_fpu_regs.inc"
  52296. -#include "restore_all.inc"
  52297. -#include "restore_partial.inc"
  52298. - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  52299. - .align 1
  52300. -/*
  52301. - First Level Handlers
  52302. - 1. First Level Handlers are invokded in vector section via jump instruction
  52303. - with specific names for different configurations.
  52304. - 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52305. - _nds32_i_SR_NT for interrupt handlers.
  52306. - 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52307. - 2.2 SR: Saved Registers
  52308. - sa: Save All regs (context)
  52309. - ps: Partial Save (all caller-saved regs)
  52310. - 2.3 NT: Nested Type
  52311. - ns: nested
  52312. - nn: not nested
  52313. - nr: nested ready
  52314. -*/
  52315. -
  52316. -/*
  52317. - This is 4-byte vector size version.
  52318. - The "_4b" postfix was added for 4-byte version symbol.
  52319. -*/
  52320. -#ifdef NDS32_SAVE_ALL_REGS
  52321. -#if defined(NDS32_NESTED)
  52322. - .globl _nds32_i_sa_ns_4b
  52323. - .type _nds32_i_sa_ns_4b, @function
  52324. -_nds32_i_sa_ns_4b:
  52325. -#elif defined(NDS32_NESTED_READY)
  52326. - .globl _nds32_i_sa_nr_4b
  52327. - .type _nds32_i_sa_nr_4b, @function
  52328. -_nds32_i_sa_nr_4b:
  52329. -#else /* Not nested handler. */
  52330. - .globl _nds32_i_sa_nn_4b
  52331. - .type _nds32_i_sa_nn_4b, @function
  52332. -_nds32_i_sa_nn_4b:
  52333. -#endif /* endif for Nest Type */
  52334. -#else /* not NDS32_SAVE_ALL_REGS */
  52335. -#if defined(NDS32_NESTED)
  52336. - .globl _nds32_i_ps_ns_4b
  52337. - .type _nds32_i_ps_ns_4b, @function
  52338. -_nds32_i_ps_ns_4b:
  52339. -#elif defined(NDS32_NESTED_READY)
  52340. - .globl _nds32_i_ps_nr_4b
  52341. - .type _nds32_i_ps_nr_4b, @function
  52342. -_nds32_i_ps_nr_4b:
  52343. -#else /* Not nested handler. */
  52344. - .globl _nds32_i_ps_nn_4b
  52345. - .type _nds32_i_ps_nn_4b, @function
  52346. -_nds32_i_ps_nn_4b:
  52347. -#endif /* endif for Nest Type */
  52348. -#endif /* not NDS32_SAVE_ALL_REGS */
  52349. -
  52350. -/*
  52351. - This is 4-byte vector size version.
  52352. - The vector id was restored into $lp in vector by compiler.
  52353. -*/
  52354. -#ifdef NDS32_SAVE_ALL_REGS
  52355. - SAVE_ALL_4B
  52356. -#else
  52357. - SAVE_PARTIAL_4B
  52358. -#endif
  52359. - /* Prepare to call 2nd level handler. */
  52360. - la $r2, _nds32_jmptbl_00
  52361. - lw $r2, [$r2 + $r0 << #2]
  52362. - addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
  52363. - ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
  52364. - jral $r2
  52365. - /* Restore used registers. */
  52366. -#ifdef NDS32_SAVE_ALL_REGS
  52367. - RESTORE_ALL
  52368. -#else
  52369. - RESTORE_PARTIAL
  52370. -#endif
  52371. - iret
  52372. -
  52373. -#ifdef NDS32_SAVE_ALL_REGS
  52374. -#if defined(NDS32_NESTED)
  52375. - .size _nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b
  52376. -#elif defined(NDS32_NESTED_READY)
  52377. - .size _nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b
  52378. -#else /* Not nested handler. */
  52379. - .size _nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b
  52380. -#endif /* endif for Nest Type */
  52381. -#else /* not NDS32_SAVE_ALL_REGS */
  52382. -#if defined(NDS32_NESTED)
  52383. - .size _nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b
  52384. -#elif defined(NDS32_NESTED_READY)
  52385. - .size _nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b
  52386. -#else /* Not nested handler. */
  52387. - .size _nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b
  52388. -#endif /* endif for Nest Type */
  52389. -#endif /* not NDS32_SAVE_ALL_REGS */
  52390. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/intr_isr.S gcc-4.9.4/libgcc/config/nds32/isr-library/intr_isr.S
  52391. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/intr_isr.S 2014-01-02 23:25:22.000000000 +0100
  52392. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/intr_isr.S 2016-08-08 20:37:53.698587257 +0200
  52393. @@ -1,5 +1,5 @@
  52394. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52395. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52396. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52397. Contributed by Andes Technology Corporation.
  52398. This file is part of GCC.
  52399. @@ -23,6 +23,7 @@
  52400. see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  52401. <http://www.gnu.org/licenses/>. */
  52402. +#include "save_usr_regs.inc"
  52403. #include "save_mac_regs.inc"
  52404. #include "save_fpu_regs.inc"
  52405. #include "save_fpu_regs_00.inc"
  52406. @@ -32,35 +33,33 @@
  52407. #include "save_all.inc"
  52408. #include "save_partial.inc"
  52409. #include "adj_intr_lvl.inc"
  52410. -#include "restore_mac_regs.inc"
  52411. #include "restore_fpu_regs_00.inc"
  52412. #include "restore_fpu_regs_01.inc"
  52413. #include "restore_fpu_regs_02.inc"
  52414. #include "restore_fpu_regs_03.inc"
  52415. #include "restore_fpu_regs.inc"
  52416. +#include "restore_mac_regs.inc"
  52417. +#include "restore_usr_regs.inc"
  52418. #include "restore_all.inc"
  52419. #include "restore_partial.inc"
  52420. +
  52421. .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  52422. .align 1
  52423. -/*
  52424. - First Level Handlers
  52425. - 1. First Level Handlers are invokded in vector section via jump instruction
  52426. - with specific names for different configurations.
  52427. - 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52428. - _nds32_i_SR_NT for interrupt handlers.
  52429. - 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52430. - 2.2 SR: Saved Registers
  52431. - sa: Save All regs (context)
  52432. - ps: Partial Save (all caller-saved regs)
  52433. - 2.3 NT: Nested Type
  52434. - ns: nested
  52435. - nn: not nested
  52436. - nr: nested ready
  52437. -*/
  52438. -
  52439. -/*
  52440. - This is original 16-byte vector size version.
  52441. -*/
  52442. +
  52443. +/* First Level Handlers
  52444. + 1. First Level Handlers are invokded in vector section via jump instruction
  52445. + with specific names for different configurations.
  52446. + 2. Naming Format: _nds32_e_SR_NT for exception handlers.
  52447. + _nds32_i_SR_NT for interrupt handlers.
  52448. + 2.1 All upper case letters are replaced with specific lower case letters encodings.
  52449. + 2.2 SR -- Saved Registers
  52450. + sa: Save All regs (context)
  52451. + ps: Partial Save (all caller-saved regs)
  52452. + 2.3 NT -- Nested Type
  52453. + ns: nested
  52454. + nn: not nested
  52455. + nr: nested ready */
  52456. +
  52457. #ifdef NDS32_SAVE_ALL_REGS
  52458. #if defined(NDS32_NESTED)
  52459. .globl _nds32_i_sa_ns
  52460. @@ -91,21 +90,36 @@
  52461. #endif /* endif for Nest Type */
  52462. #endif /* not NDS32_SAVE_ALL_REGS */
  52463. -/*
  52464. - This is 16-byte vector size version.
  52465. - The vector id was restored into $r0 in vector by compiler.
  52466. -*/
  52467. +
  52468. +/* For 4-byte vector size version, the vector id is
  52469. + extracted from $ITYPE and is set into $r0 by library.
  52470. + For 16-byte vector size version, the vector id
  52471. + is set into $r0 in vector section by compiler. */
  52472. +
  52473. +/* Save used registers first. */
  52474. #ifdef NDS32_SAVE_ALL_REGS
  52475. SAVE_ALL
  52476. #else
  52477. SAVE_PARTIAL
  52478. #endif
  52479. - /* Prepare to call 2nd level handler. */
  52480. +
  52481. +/* According to vector size, we need to have different implementation. */
  52482. +#if __NDS32_ISR_VECTOR_SIZE_4__
  52483. + /* Prepare to call 2nd level handler. */
  52484. + la $r2, _nds32_jmptbl_00
  52485. + lw $r2, [$r2 + $r0 << #2]
  52486. + addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
  52487. + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
  52488. + jral $r2
  52489. +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  52490. + /* Prepare to call 2nd level handler. */
  52491. la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
  52492. lw $r2, [$r2 + $r0 << #2]
  52493. ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
  52494. jral $r2
  52495. - /* Restore used registers. */
  52496. +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  52497. +
  52498. +/* Restore used registers. */
  52499. #ifdef NDS32_SAVE_ALL_REGS
  52500. RESTORE_ALL
  52501. #else
  52502. @@ -113,6 +127,7 @@
  52503. #endif
  52504. iret
  52505. +
  52506. #ifdef NDS32_SAVE_ALL_REGS
  52507. #if defined(NDS32_NESTED)
  52508. .size _nds32_i_sa_ns, .-_nds32_i_sa_ns
  52509. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid00.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid00.S
  52510. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid00.S 2014-01-02 23:25:22.000000000 +0100
  52511. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid00.S 2016-08-08 20:37:53.702587412 +0200
  52512. @@ -1,5 +1,5 @@
  52513. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52514. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52515. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52516. Contributed by Andes Technology Corporation.
  52517. This file is part of GCC.
  52518. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid01.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid01.S
  52519. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid01.S 2014-01-02 23:25:22.000000000 +0100
  52520. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid01.S 2016-08-08 20:37:53.702587412 +0200
  52521. @@ -1,5 +1,5 @@
  52522. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52523. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52524. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52525. Contributed by Andes Technology Corporation.
  52526. This file is part of GCC.
  52527. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid02.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid02.S
  52528. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid02.S 2014-01-02 23:25:22.000000000 +0100
  52529. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid02.S 2016-08-08 20:37:53.702587412 +0200
  52530. @@ -1,5 +1,5 @@
  52531. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52532. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52533. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52534. Contributed by Andes Technology Corporation.
  52535. This file is part of GCC.
  52536. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid03.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid03.S
  52537. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid03.S 2014-01-02 23:25:22.000000000 +0100
  52538. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid03.S 2016-08-08 20:37:53.702587412 +0200
  52539. @@ -1,5 +1,5 @@
  52540. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52541. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52542. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52543. Contributed by Andes Technology Corporation.
  52544. This file is part of GCC.
  52545. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid04.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid04.S
  52546. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid04.S 2014-01-02 23:25:22.000000000 +0100
  52547. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid04.S 2016-08-08 20:37:53.702587412 +0200
  52548. @@ -1,5 +1,5 @@
  52549. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52550. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52551. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52552. Contributed by Andes Technology Corporation.
  52553. This file is part of GCC.
  52554. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid05.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid05.S
  52555. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid05.S 2014-01-02 23:25:22.000000000 +0100
  52556. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid05.S 2016-08-08 20:37:53.702587412 +0200
  52557. @@ -1,5 +1,5 @@
  52558. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52559. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52560. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52561. Contributed by Andes Technology Corporation.
  52562. This file is part of GCC.
  52563. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid06.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid06.S
  52564. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid06.S 2014-01-02 23:25:22.000000000 +0100
  52565. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid06.S 2016-08-08 20:37:53.702587412 +0200
  52566. @@ -1,5 +1,5 @@
  52567. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52568. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52569. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52570. Contributed by Andes Technology Corporation.
  52571. This file is part of GCC.
  52572. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid07.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid07.S
  52573. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid07.S 2014-01-02 23:25:22.000000000 +0100
  52574. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid07.S 2016-08-08 20:37:53.702587412 +0200
  52575. @@ -1,5 +1,5 @@
  52576. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52577. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52578. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52579. Contributed by Andes Technology Corporation.
  52580. This file is part of GCC.
  52581. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid08.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid08.S
  52582. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid08.S 2014-01-02 23:25:22.000000000 +0100
  52583. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid08.S 2016-08-08 20:37:53.702587412 +0200
  52584. @@ -1,5 +1,5 @@
  52585. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52586. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52587. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52588. Contributed by Andes Technology Corporation.
  52589. This file is part of GCC.
  52590. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid09.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid09.S
  52591. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid09.S 2014-01-02 23:25:22.000000000 +0100
  52592. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid09.S 2016-08-08 20:37:53.702587412 +0200
  52593. @@ -1,5 +1,5 @@
  52594. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52595. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52596. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52597. Contributed by Andes Technology Corporation.
  52598. This file is part of GCC.
  52599. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid10.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid10.S
  52600. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid10.S 2014-01-02 23:25:22.000000000 +0100
  52601. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid10.S 2016-08-08 20:37:53.702587412 +0200
  52602. @@ -1,5 +1,5 @@
  52603. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52604. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52605. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52606. Contributed by Andes Technology Corporation.
  52607. This file is part of GCC.
  52608. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid11.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid11.S
  52609. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid11.S 2014-01-02 23:25:22.000000000 +0100
  52610. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid11.S 2016-08-08 20:37:53.702587412 +0200
  52611. @@ -1,5 +1,5 @@
  52612. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52613. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52614. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52615. Contributed by Andes Technology Corporation.
  52616. This file is part of GCC.
  52617. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid12.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid12.S
  52618. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid12.S 2014-01-02 23:25:22.000000000 +0100
  52619. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid12.S 2016-08-08 20:37:53.702587412 +0200
  52620. @@ -1,5 +1,5 @@
  52621. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52622. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52623. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52624. Contributed by Andes Technology Corporation.
  52625. This file is part of GCC.
  52626. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid13.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid13.S
  52627. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid13.S 2014-01-02 23:25:22.000000000 +0100
  52628. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid13.S 2016-08-08 20:37:53.702587412 +0200
  52629. @@ -1,5 +1,5 @@
  52630. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52631. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52632. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52633. Contributed by Andes Technology Corporation.
  52634. This file is part of GCC.
  52635. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid14.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid14.S
  52636. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid14.S 2014-01-02 23:25:22.000000000 +0100
  52637. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid14.S 2016-08-08 20:37:53.702587412 +0200
  52638. @@ -1,5 +1,5 @@
  52639. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52640. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52641. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52642. Contributed by Andes Technology Corporation.
  52643. This file is part of GCC.
  52644. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid15.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid15.S
  52645. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid15.S 2014-01-02 23:25:22.000000000 +0100
  52646. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid15.S 2016-08-08 20:37:53.702587412 +0200
  52647. @@ -1,5 +1,5 @@
  52648. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52649. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52650. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52651. Contributed by Andes Technology Corporation.
  52652. This file is part of GCC.
  52653. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid16.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid16.S
  52654. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid16.S 2014-01-02 23:25:22.000000000 +0100
  52655. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid16.S 2016-08-08 20:37:53.702587412 +0200
  52656. @@ -1,5 +1,5 @@
  52657. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52658. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52659. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52660. Contributed by Andes Technology Corporation.
  52661. This file is part of GCC.
  52662. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid17.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid17.S
  52663. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid17.S 2014-01-02 23:25:22.000000000 +0100
  52664. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid17.S 2016-08-08 20:37:53.702587412 +0200
  52665. @@ -1,5 +1,5 @@
  52666. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52667. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52668. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52669. Contributed by Andes Technology Corporation.
  52670. This file is part of GCC.
  52671. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid18.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid18.S
  52672. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid18.S 2014-01-02 23:25:22.000000000 +0100
  52673. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid18.S 2016-08-08 20:37:53.702587412 +0200
  52674. @@ -1,5 +1,5 @@
  52675. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52676. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52677. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52678. Contributed by Andes Technology Corporation.
  52679. This file is part of GCC.
  52680. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid19.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid19.S
  52681. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid19.S 2014-01-02 23:25:22.000000000 +0100
  52682. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid19.S 2016-08-08 20:37:53.702587412 +0200
  52683. @@ -1,5 +1,5 @@
  52684. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52685. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52686. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52687. Contributed by Andes Technology Corporation.
  52688. This file is part of GCC.
  52689. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid20.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid20.S
  52690. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid20.S 2014-01-02 23:25:22.000000000 +0100
  52691. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid20.S 2016-08-08 20:37:53.706587567 +0200
  52692. @@ -1,5 +1,5 @@
  52693. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52694. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52695. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52696. Contributed by Andes Technology Corporation.
  52697. This file is part of GCC.
  52698. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid21.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid21.S
  52699. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid21.S 2014-01-02 23:25:22.000000000 +0100
  52700. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid21.S 2016-08-08 20:37:53.706587567 +0200
  52701. @@ -1,5 +1,5 @@
  52702. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52703. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52704. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52705. Contributed by Andes Technology Corporation.
  52706. This file is part of GCC.
  52707. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid22.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid22.S
  52708. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid22.S 2014-01-02 23:25:22.000000000 +0100
  52709. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid22.S 2016-08-08 20:37:53.706587567 +0200
  52710. @@ -1,5 +1,5 @@
  52711. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52712. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52713. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52714. Contributed by Andes Technology Corporation.
  52715. This file is part of GCC.
  52716. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid23.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid23.S
  52717. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid23.S 2014-01-02 23:25:22.000000000 +0100
  52718. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid23.S 2016-08-08 20:37:53.706587567 +0200
  52719. @@ -1,5 +1,5 @@
  52720. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52721. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52722. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52723. Contributed by Andes Technology Corporation.
  52724. This file is part of GCC.
  52725. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid24.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid24.S
  52726. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid24.S 2014-01-02 23:25:22.000000000 +0100
  52727. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid24.S 2016-08-08 20:37:53.706587567 +0200
  52728. @@ -1,5 +1,5 @@
  52729. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52730. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52731. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52732. Contributed by Andes Technology Corporation.
  52733. This file is part of GCC.
  52734. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid25.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid25.S
  52735. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid25.S 2014-01-02 23:25:22.000000000 +0100
  52736. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid25.S 2016-08-08 20:37:53.706587567 +0200
  52737. @@ -1,5 +1,5 @@
  52738. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52739. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52740. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52741. Contributed by Andes Technology Corporation.
  52742. This file is part of GCC.
  52743. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid26.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid26.S
  52744. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid26.S 2014-01-02 23:25:22.000000000 +0100
  52745. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid26.S 2016-08-08 20:37:53.706587567 +0200
  52746. @@ -1,5 +1,5 @@
  52747. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52748. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52749. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52750. Contributed by Andes Technology Corporation.
  52751. This file is part of GCC.
  52752. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid27.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid27.S
  52753. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid27.S 2014-01-02 23:25:22.000000000 +0100
  52754. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid27.S 2016-08-08 20:37:53.706587567 +0200
  52755. @@ -1,5 +1,5 @@
  52756. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52757. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52758. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52759. Contributed by Andes Technology Corporation.
  52760. This file is part of GCC.
  52761. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid28.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid28.S
  52762. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid28.S 2014-01-02 23:25:22.000000000 +0100
  52763. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid28.S 2016-08-08 20:37:53.706587567 +0200
  52764. @@ -1,5 +1,5 @@
  52765. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52766. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52767. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52768. Contributed by Andes Technology Corporation.
  52769. This file is part of GCC.
  52770. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid29.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid29.S
  52771. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid29.S 2014-01-02 23:25:22.000000000 +0100
  52772. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid29.S 2016-08-08 20:37:53.706587567 +0200
  52773. @@ -1,5 +1,5 @@
  52774. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52775. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52776. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52777. Contributed by Andes Technology Corporation.
  52778. This file is part of GCC.
  52779. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid30.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid30.S
  52780. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid30.S 2014-01-02 23:25:22.000000000 +0100
  52781. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid30.S 2016-08-08 20:37:53.706587567 +0200
  52782. @@ -1,5 +1,5 @@
  52783. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52784. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52785. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52786. Contributed by Andes Technology Corporation.
  52787. This file is part of GCC.
  52788. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid31.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid31.S
  52789. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid31.S 2014-01-02 23:25:22.000000000 +0100
  52790. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid31.S 2016-08-08 20:37:53.706587567 +0200
  52791. @@ -1,5 +1,5 @@
  52792. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52793. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52794. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52795. Contributed by Andes Technology Corporation.
  52796. This file is part of GCC.
  52797. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid32.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid32.S
  52798. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid32.S 2014-01-02 23:25:22.000000000 +0100
  52799. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid32.S 2016-08-08 20:37:53.706587567 +0200
  52800. @@ -1,5 +1,5 @@
  52801. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52802. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52803. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52804. Contributed by Andes Technology Corporation.
  52805. This file is part of GCC.
  52806. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid33.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid33.S
  52807. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid33.S 2014-01-02 23:25:22.000000000 +0100
  52808. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid33.S 2016-08-08 20:37:53.706587567 +0200
  52809. @@ -1,5 +1,5 @@
  52810. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52811. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52812. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52813. Contributed by Andes Technology Corporation.
  52814. This file is part of GCC.
  52815. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid34.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid34.S
  52816. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid34.S 2014-01-02 23:25:22.000000000 +0100
  52817. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid34.S 2016-08-08 20:37:53.706587567 +0200
  52818. @@ -1,5 +1,5 @@
  52819. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52820. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52821. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52822. Contributed by Andes Technology Corporation.
  52823. This file is part of GCC.
  52824. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid35.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid35.S
  52825. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid35.S 2014-01-02 23:25:22.000000000 +0100
  52826. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid35.S 2016-08-08 20:37:53.706587567 +0200
  52827. @@ -1,5 +1,5 @@
  52828. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52829. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52830. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52831. Contributed by Andes Technology Corporation.
  52832. This file is part of GCC.
  52833. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid36.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid36.S
  52834. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid36.S 2014-01-02 23:25:22.000000000 +0100
  52835. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid36.S 2016-08-08 20:37:53.706587567 +0200
  52836. @@ -1,5 +1,5 @@
  52837. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52838. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52839. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52840. Contributed by Andes Technology Corporation.
  52841. This file is part of GCC.
  52842. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid37.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid37.S
  52843. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid37.S 2014-01-02 23:25:22.000000000 +0100
  52844. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid37.S 2016-08-08 20:37:53.706587567 +0200
  52845. @@ -1,5 +1,5 @@
  52846. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52847. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52848. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52849. Contributed by Andes Technology Corporation.
  52850. This file is part of GCC.
  52851. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid38.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid38.S
  52852. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid38.S 2014-01-02 23:25:22.000000000 +0100
  52853. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid38.S 2016-08-08 20:37:53.706587567 +0200
  52854. @@ -1,5 +1,5 @@
  52855. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52856. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52857. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52858. Contributed by Andes Technology Corporation.
  52859. This file is part of GCC.
  52860. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid39.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid39.S
  52861. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid39.S 2014-01-02 23:25:22.000000000 +0100
  52862. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid39.S 2016-08-08 20:37:53.706587567 +0200
  52863. @@ -1,5 +1,5 @@
  52864. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52865. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52866. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52867. Contributed by Andes Technology Corporation.
  52868. This file is part of GCC.
  52869. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid40.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid40.S
  52870. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid40.S 2014-01-02 23:25:22.000000000 +0100
  52871. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid40.S 2016-08-08 20:37:53.706587567 +0200
  52872. @@ -1,5 +1,5 @@
  52873. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52874. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52875. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52876. Contributed by Andes Technology Corporation.
  52877. This file is part of GCC.
  52878. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid41.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid41.S
  52879. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid41.S 2014-01-02 23:25:22.000000000 +0100
  52880. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid41.S 2016-08-08 20:37:53.710587722 +0200
  52881. @@ -1,5 +1,5 @@
  52882. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52883. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52884. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52885. Contributed by Andes Technology Corporation.
  52886. This file is part of GCC.
  52887. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid42.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid42.S
  52888. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid42.S 2014-01-02 23:25:22.000000000 +0100
  52889. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid42.S 2016-08-08 20:37:53.710587722 +0200
  52890. @@ -1,5 +1,5 @@
  52891. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52892. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52893. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52894. Contributed by Andes Technology Corporation.
  52895. This file is part of GCC.
  52896. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid43.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid43.S
  52897. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid43.S 2014-01-02 23:25:22.000000000 +0100
  52898. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid43.S 2016-08-08 20:37:53.710587722 +0200
  52899. @@ -1,5 +1,5 @@
  52900. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52901. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52902. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52903. Contributed by Andes Technology Corporation.
  52904. This file is part of GCC.
  52905. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid44.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid44.S
  52906. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid44.S 2014-01-02 23:25:22.000000000 +0100
  52907. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid44.S 2016-08-08 20:37:53.710587722 +0200
  52908. @@ -1,5 +1,5 @@
  52909. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52910. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52911. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52912. Contributed by Andes Technology Corporation.
  52913. This file is part of GCC.
  52914. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid45.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid45.S
  52915. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid45.S 2014-01-02 23:25:22.000000000 +0100
  52916. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid45.S 2016-08-08 20:37:53.710587722 +0200
  52917. @@ -1,5 +1,5 @@
  52918. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52919. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52920. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52921. Contributed by Andes Technology Corporation.
  52922. This file is part of GCC.
  52923. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid46.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid46.S
  52924. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid46.S 2014-01-02 23:25:22.000000000 +0100
  52925. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid46.S 2016-08-08 20:37:53.710587722 +0200
  52926. @@ -1,5 +1,5 @@
  52927. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52928. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52929. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52930. Contributed by Andes Technology Corporation.
  52931. This file is part of GCC.
  52932. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid47.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid47.S
  52933. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid47.S 2014-01-02 23:25:22.000000000 +0100
  52934. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid47.S 2016-08-08 20:37:53.710587722 +0200
  52935. @@ -1,5 +1,5 @@
  52936. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52937. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52938. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52939. Contributed by Andes Technology Corporation.
  52940. This file is part of GCC.
  52941. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid48.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid48.S
  52942. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid48.S 2014-01-02 23:25:22.000000000 +0100
  52943. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid48.S 2016-08-08 20:37:53.710587722 +0200
  52944. @@ -1,5 +1,5 @@
  52945. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52946. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52947. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52948. Contributed by Andes Technology Corporation.
  52949. This file is part of GCC.
  52950. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid49.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid49.S
  52951. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid49.S 2014-01-02 23:25:22.000000000 +0100
  52952. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid49.S 2016-08-08 20:37:53.710587722 +0200
  52953. @@ -1,5 +1,5 @@
  52954. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52955. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52956. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52957. Contributed by Andes Technology Corporation.
  52958. This file is part of GCC.
  52959. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid50.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid50.S
  52960. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid50.S 2014-01-02 23:25:22.000000000 +0100
  52961. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid50.S 2016-08-08 20:37:53.710587722 +0200
  52962. @@ -1,5 +1,5 @@
  52963. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52964. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52965. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52966. Contributed by Andes Technology Corporation.
  52967. This file is part of GCC.
  52968. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid51.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid51.S
  52969. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid51.S 2014-01-02 23:25:22.000000000 +0100
  52970. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid51.S 2016-08-08 20:37:53.710587722 +0200
  52971. @@ -1,5 +1,5 @@
  52972. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52973. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52974. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52975. Contributed by Andes Technology Corporation.
  52976. This file is part of GCC.
  52977. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid52.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid52.S
  52978. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid52.S 2014-01-02 23:25:22.000000000 +0100
  52979. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid52.S 2016-08-08 20:37:53.710587722 +0200
  52980. @@ -1,5 +1,5 @@
  52981. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52982. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52983. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52984. Contributed by Andes Technology Corporation.
  52985. This file is part of GCC.
  52986. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid53.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid53.S
  52987. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid53.S 2014-01-02 23:25:22.000000000 +0100
  52988. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid53.S 2016-08-08 20:37:53.710587722 +0200
  52989. @@ -1,5 +1,5 @@
  52990. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  52991. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  52992. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  52993. Contributed by Andes Technology Corporation.
  52994. This file is part of GCC.
  52995. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid54.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid54.S
  52996. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid54.S 2014-01-02 23:25:22.000000000 +0100
  52997. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid54.S 2016-08-08 20:37:53.710587722 +0200
  52998. @@ -1,5 +1,5 @@
  52999. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53000. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53001. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53002. Contributed by Andes Technology Corporation.
  53003. This file is part of GCC.
  53004. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid55.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid55.S
  53005. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid55.S 2014-01-02 23:25:22.000000000 +0100
  53006. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid55.S 2016-08-08 20:37:53.710587722 +0200
  53007. @@ -1,5 +1,5 @@
  53008. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53009. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53010. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53011. Contributed by Andes Technology Corporation.
  53012. This file is part of GCC.
  53013. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid56.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid56.S
  53014. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid56.S 2014-01-02 23:25:22.000000000 +0100
  53015. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid56.S 2016-08-08 20:37:53.710587722 +0200
  53016. @@ -1,5 +1,5 @@
  53017. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53018. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53019. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53020. Contributed by Andes Technology Corporation.
  53021. This file is part of GCC.
  53022. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid57.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid57.S
  53023. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid57.S 2014-01-02 23:25:22.000000000 +0100
  53024. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid57.S 2016-08-08 20:37:53.710587722 +0200
  53025. @@ -1,5 +1,5 @@
  53026. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53027. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53028. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53029. Contributed by Andes Technology Corporation.
  53030. This file is part of GCC.
  53031. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid58.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid58.S
  53032. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid58.S 2014-01-02 23:25:22.000000000 +0100
  53033. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid58.S 2016-08-08 20:37:53.710587722 +0200
  53034. @@ -1,5 +1,5 @@
  53035. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53036. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53037. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53038. Contributed by Andes Technology Corporation.
  53039. This file is part of GCC.
  53040. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid59.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid59.S
  53041. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid59.S 2014-01-02 23:25:22.000000000 +0100
  53042. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid59.S 2016-08-08 20:37:53.710587722 +0200
  53043. @@ -1,5 +1,5 @@
  53044. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53045. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53046. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53047. Contributed by Andes Technology Corporation.
  53048. This file is part of GCC.
  53049. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid60.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid60.S
  53050. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid60.S 2014-01-02 23:25:22.000000000 +0100
  53051. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid60.S 2016-08-08 20:37:53.710587722 +0200
  53052. @@ -1,5 +1,5 @@
  53053. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53054. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53055. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53056. Contributed by Andes Technology Corporation.
  53057. This file is part of GCC.
  53058. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid61.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid61.S
  53059. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid61.S 2014-01-02 23:25:22.000000000 +0100
  53060. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid61.S 2016-08-08 20:37:53.710587722 +0200
  53061. @@ -1,5 +1,5 @@
  53062. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53063. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53064. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53065. Contributed by Andes Technology Corporation.
  53066. This file is part of GCC.
  53067. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid62.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid62.S
  53068. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid62.S 2014-01-02 23:25:22.000000000 +0100
  53069. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid62.S 2016-08-08 20:37:53.714587877 +0200
  53070. @@ -1,5 +1,5 @@
  53071. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53072. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53073. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53074. Contributed by Andes Technology Corporation.
  53075. This file is part of GCC.
  53076. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid63.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid63.S
  53077. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid63.S 2014-01-02 23:25:22.000000000 +0100
  53078. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid63.S 2016-08-08 20:37:53.714587877 +0200
  53079. @@ -1,5 +1,5 @@
  53080. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53081. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53082. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53083. Contributed by Andes Technology Corporation.
  53084. This file is part of GCC.
  53085. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid64.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid64.S
  53086. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid64.S 2014-01-02 23:25:22.000000000 +0100
  53087. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid64.S 2016-08-08 20:37:53.714587877 +0200
  53088. @@ -1,5 +1,5 @@
  53089. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53090. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53091. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53092. Contributed by Andes Technology Corporation.
  53093. This file is part of GCC.
  53094. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid65.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid65.S
  53095. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid65.S 2014-01-02 23:25:22.000000000 +0100
  53096. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid65.S 2016-08-08 20:37:53.714587877 +0200
  53097. @@ -1,5 +1,5 @@
  53098. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53099. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53100. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53101. Contributed by Andes Technology Corporation.
  53102. This file is part of GCC.
  53103. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid66.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid66.S
  53104. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid66.S 2014-01-02 23:25:22.000000000 +0100
  53105. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid66.S 2016-08-08 20:37:53.714587877 +0200
  53106. @@ -1,5 +1,5 @@
  53107. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53108. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53109. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53110. Contributed by Andes Technology Corporation.
  53111. This file is part of GCC.
  53112. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid67.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid67.S
  53113. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid67.S 2014-01-02 23:25:22.000000000 +0100
  53114. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid67.S 2016-08-08 20:37:53.714587877 +0200
  53115. @@ -1,5 +1,5 @@
  53116. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53117. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53118. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53119. Contributed by Andes Technology Corporation.
  53120. This file is part of GCC.
  53121. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid68.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid68.S
  53122. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid68.S 2014-01-02 23:25:22.000000000 +0100
  53123. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid68.S 2016-08-08 20:37:53.714587877 +0200
  53124. @@ -1,5 +1,5 @@
  53125. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53126. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53127. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53128. Contributed by Andes Technology Corporation.
  53129. This file is part of GCC.
  53130. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid69.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid69.S
  53131. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid69.S 2014-01-02 23:25:22.000000000 +0100
  53132. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid69.S 2016-08-08 20:37:53.714587877 +0200
  53133. @@ -1,5 +1,5 @@
  53134. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53135. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53136. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53137. Contributed by Andes Technology Corporation.
  53138. This file is part of GCC.
  53139. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid70.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid70.S
  53140. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid70.S 2014-01-02 23:25:22.000000000 +0100
  53141. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid70.S 2016-08-08 20:37:53.714587877 +0200
  53142. @@ -1,5 +1,5 @@
  53143. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53144. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53145. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53146. Contributed by Andes Technology Corporation.
  53147. This file is part of GCC.
  53148. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid71.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid71.S
  53149. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid71.S 2014-01-02 23:25:22.000000000 +0100
  53150. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid71.S 2016-08-08 20:37:53.714587877 +0200
  53151. @@ -1,5 +1,5 @@
  53152. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53153. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53154. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53155. Contributed by Andes Technology Corporation.
  53156. This file is part of GCC.
  53157. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid72.S gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid72.S
  53158. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/jmptbl_vid72.S 2014-01-02 23:25:22.000000000 +0100
  53159. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/jmptbl_vid72.S 2016-08-08 20:37:53.714587877 +0200
  53160. @@ -1,5 +1,5 @@
  53161. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53162. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53163. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53164. Contributed by Andes Technology Corporation.
  53165. This file is part of GCC.
  53166. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/nmih.S gcc-4.9.4/libgcc/config/nds32/isr-library/nmih.S
  53167. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/nmih.S 2014-01-02 23:25:22.000000000 +0100
  53168. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/nmih.S 2016-08-08 20:37:53.714587877 +0200
  53169. @@ -1,5 +1,5 @@
  53170. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53171. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53172. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53173. Contributed by Andes Technology Corporation.
  53174. This file is part of GCC.
  53175. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/reset_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/reset_4b.S
  53176. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/reset_4b.S 2014-01-02 23:25:22.000000000 +0100
  53177. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/reset_4b.S 1970-01-01 01:00:00.000000000 +0100
  53178. @@ -1,131 +0,0 @@
  53179. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53180. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53181. - Contributed by Andes Technology Corporation.
  53182. -
  53183. - This file is part of GCC.
  53184. -
  53185. - GCC is free software; you can redistribute it and/or modify it
  53186. - under the terms of the GNU General Public License as published
  53187. - by the Free Software Foundation; either version 3, or (at your
  53188. - option) any later version.
  53189. -
  53190. - GCC is distributed in the hope that it will be useful, but WITHOUT
  53191. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  53192. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53193. - License for more details.
  53194. -
  53195. - Under Section 7 of GPL version 3, you are granted additional
  53196. - permissions described in the GCC Runtime Library Exception, version
  53197. - 3.1, as published by the Free Software Foundation.
  53198. -
  53199. - You should have received a copy of the GNU General Public License and
  53200. - a copy of the GCC Runtime Library Exception along with this program;
  53201. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53202. - <http://www.gnu.org/licenses/>. */
  53203. -
  53204. - .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  53205. - .align 1
  53206. - .weak _SDA_BASE_ /* For reset handler only. */
  53207. - .weak _FP_BASE_ /* For reset handler only. */
  53208. - .weak _nds32_init_mem /* User defined memory initialization function. */
  53209. - .globl _start
  53210. - .globl _nds32_reset_4b
  53211. - .type _nds32_reset_4b, @function
  53212. -_nds32_reset_4b:
  53213. -_start:
  53214. -#ifdef NDS32_EXT_EX9
  53215. - .no_ex9_begin
  53216. -#endif
  53217. - /* Handle NMI and warm boot if any of them exists. */
  53218. - beqz $sp, 1f /* Reset, NMI or warm boot? */
  53219. - /* Either NMI or warm boot; save all regs. */
  53220. -
  53221. - /* Preserve registers for context-switching. */
  53222. -#ifdef __NDS32_REDUCED_REGS__
  53223. - /* For 16-reg mode. */
  53224. - smw.adm $r0, [$sp], $r10, #0x0
  53225. - smw.adm $r15, [$sp], $r15, #0xf
  53226. -#else
  53227. - /* For 32-reg mode. */
  53228. - smw.adm $r0, [$sp], $r27, #0xf
  53229. -#endif
  53230. -#ifdef NDS32_EXT_IFC
  53231. - mfusr $r1, $IFC_LP
  53232. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53233. - stack 8-byte alignment. */
  53234. -#endif
  53235. -
  53236. - la $gp, _SDA_BASE_ /* Init GP for small data access. */
  53237. - move $r0, $sp /* Init parameter. */
  53238. - mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */
  53239. - andi $r1, $r1, #0xf
  53240. - addi $r1, $r1, #-1
  53241. - beqz $r1, 2f /* Warm boot if true. */
  53242. - l.w $r15, _nds32_nmih /* Load NMI handler. */
  53243. - j 3f
  53244. -2:
  53245. - l.w $r15, _nds32_wrh /* Load warm boot handler. */
  53246. -3:
  53247. - beqz $r15, 1f /* If no handler, do cold boot. */
  53248. - jral $r15 /* Call handler. */
  53249. - bnez $r0, 1f /* If fail to resume, do cold boot. */
  53250. -
  53251. - /* Restore registers for context-switching. */
  53252. -#ifdef NDS32_EXT_IFC
  53253. - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
  53254. - stack 8-byte alignment. */
  53255. - mtusr $r1, $IFC_LP
  53256. -#endif
  53257. -#ifdef __NDS32_REDUCED_REGS__
  53258. - /* For 16-reg mode. */
  53259. - lmw.bim $r15, [$sp], $r15, #0xf
  53260. - lmw.bim $r0, [$sp], $r10, #0x0
  53261. -#else
  53262. - /* For 32-reg mode. */
  53263. - lmw.bim $r0, [$sp], $r27, #0xf
  53264. -#endif
  53265. - iret /* Resume operation. */
  53266. -
  53267. -
  53268. -1: /* Cold boot. */
  53269. - /* With vector ID feature, set default vector size to 4B. */
  53270. - /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
  53271. - mfsr $r0, $IVB
  53272. - li $r1, #0xc000
  53273. - or $r0, $r0, $r1
  53274. - xor $r0, $r0, $r1
  53275. - mtsr $r0, $IVB
  53276. - dsb
  53277. -
  53278. - la $gp, _SDA_BASE_ /* Init $gp. */
  53279. - la $fp, _FP_BASE_ /* Init $fp. */
  53280. - la $sp, _stack /* Init $sp. */
  53281. -#ifdef NDS32_EXT_EX9
  53282. -/*
  53283. - * Initialize the table base of EX9 instruction
  53284. - * ex9 generation needs to disable before the ITB is set
  53285. - */
  53286. - mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
  53287. - srli $r0, $r0, 24
  53288. - andi $r0, $r0, 0x1
  53289. - beqz $r0, 4f /* Zero means HW does not support EX9. */
  53290. - la $r0, _ITB_BASE_ /* Init $ITB. */
  53291. - mtusr $r0, $ITB
  53292. - .no_ex9_end
  53293. -4:
  53294. -#endif
  53295. - la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
  53296. - may written by C language. */
  53297. - beqz $r15, 6f
  53298. - jral $r15
  53299. -6:
  53300. - l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
  53301. - jral $r15
  53302. -/* Reset handler() should never return in a RTOS or non-OS system.
  53303. - In case it does return, an exception will be generated.
  53304. - This exception will be caught either by default break handler or by EDM.
  53305. - Default break handle may just do an infinite loop.
  53306. - EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
  53307. -5:
  53308. - break #0x7fff
  53309. - .size _nds32_reset_4b, .-_nds32_reset_4b
  53310. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/reset.S gcc-4.9.4/libgcc/config/nds32/isr-library/reset.S
  53311. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/reset.S 2014-01-02 23:25:22.000000000 +0100
  53312. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/reset.S 2016-08-08 20:37:53.714587877 +0200
  53313. @@ -26,22 +26,18 @@
  53314. .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
  53315. .align 1
  53316. .weak _SDA_BASE_ /* For reset handler only. */
  53317. - .weak _FP_BASE_ /* For reset handler only. */
  53318. .weak _nds32_init_mem /* User defined memory initialization function. */
  53319. .globl _start
  53320. .globl _nds32_reset
  53321. .type _nds32_reset, @function
  53322. _nds32_reset:
  53323. _start:
  53324. -#ifdef NDS32_EXT_EX9
  53325. - .no_ex9_begin
  53326. -#endif
  53327. /* Handle NMI and warm boot if any of them exists. */
  53328. beqz $sp, 1f /* Reset, NMI or warm boot? */
  53329. /* Either NMI or warm boot; save all regs. */
  53330. /* Preserve registers for context-switching. */
  53331. -#ifdef __NDS32_REDUCED_REGS__
  53332. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53333. /* For 16-reg mode. */
  53334. smw.adm $r0, [$sp], $r10, #0x0
  53335. smw.adm $r15, [$sp], $r15, #0xf
  53336. @@ -49,10 +45,9 @@
  53337. /* For 32-reg mode. */
  53338. smw.adm $r0, [$sp], $r27, #0xf
  53339. #endif
  53340. -#ifdef NDS32_EXT_IFC
  53341. +#if __NDS32_EXT_IFC__
  53342. mfusr $r1, $IFC_LP
  53343. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53344. - stack 8-byte alignment. */
  53345. + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */
  53346. #endif
  53347. la $gp, _SDA_BASE_ /* Init GP for small data access. */
  53348. @@ -71,12 +66,11 @@
  53349. bnez $r0, 1f /* If fail to resume, do cold boot. */
  53350. /* Restore registers for context-switching. */
  53351. -#ifdef NDS32_EXT_IFC
  53352. - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
  53353. - stack 8-byte alignment. */
  53354. +#if __NDS32_EXT_IFC__
  53355. + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */
  53356. mtusr $r1, $IFC_LP
  53357. #endif
  53358. -#ifdef __NDS32_REDUCED_REGS__
  53359. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53360. /* For 16-reg mode. */
  53361. lmw.bim $r15, [$sp], $r15, #0xf
  53362. lmw.bim $r0, [$sp], $r10, #0x0
  53363. @@ -88,6 +82,17 @@
  53364. 1: /* Cold boot. */
  53365. +#if __NDS32_ISR_VECTOR_SIZE_4__
  53366. + /* With vector ID feature for v3 architecture, default vector size is 4-byte. */
  53367. + /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
  53368. + mfsr $r0, $IVB
  53369. + li $r1, #0xc000
  53370. + or $r0, $r0, $r1
  53371. + xor $r0, $r0, $r1
  53372. + mtsr $r0, $IVB
  53373. + dsb
  53374. +#else
  53375. + /* There is no vector ID feature, so the vector size must be 16-byte. */
  53376. /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */
  53377. mfsr $r0, $IVB
  53378. li $r1, #0xffff3fff
  53379. @@ -95,36 +100,54 @@
  53380. ori $r0, $r0, #0x4000
  53381. mtsr $r0, $IVB
  53382. dsb
  53383. +#endif
  53384. la $gp, _SDA_BASE_ /* Init $gp. */
  53385. - la $fp, _FP_BASE_ /* Init $fp. */
  53386. la $sp, _stack /* Init $sp. */
  53387. -#ifdef NDS32_EXT_EX9
  53388. -/*
  53389. - * Initialize the table base of EX9 instruction
  53390. - * ex9 generation needs to disable before the ITB is set
  53391. - */
  53392. - mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
  53393. +
  53394. +#if __NDS32_EXT_EX9__
  53395. +.L_init_itb:
  53396. + /* Initialization for Instruction Table Base (ITB).
  53397. + The symbol _ITB_BASE_ is determined by Linker.
  53398. + Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */
  53399. + mfsr $r0, $MSC_CFG
  53400. srli $r0, $r0, 24
  53401. andi $r0, $r0, 0x1
  53402. - beqz $r0, 4f /* Zero means HW does not support EX9. */
  53403. - la $r0, _ITB_BASE_ /* Init $ITB. */
  53404. + beqz $r0, 4f /* Fall through ? */
  53405. + la $r0, _ITB_BASE_
  53406. mtusr $r0, $ITB
  53407. - .no_ex9_end
  53408. 4:
  53409. #endif
  53410. - la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
  53411. - may written by C language. */
  53412. +
  53413. +#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
  53414. +.L_init_fpu:
  53415. + /* Initialize FPU
  53416. + Set FUCOP_CTL.CP0EN (fucpr.b'0). */
  53417. + mfsr $r0, $FUCOP_CTL
  53418. + ori $r0, $r0, 0x1
  53419. + mtsr $r0, $FUCOP_CTL
  53420. + dsb
  53421. + /* According to [bugzilla #9425], set flush-to-zero mode.
  53422. + That is, set $FPCSR.DNZ(b'12) = 1. */
  53423. + FMFCSR $r0
  53424. + ori $r0, $r0, 0x1000
  53425. + FMTCSR $r0
  53426. + dsb
  53427. +#endif
  53428. +
  53429. + /* Call DRAM init. _nds32_init_mem may written by C language. */
  53430. + la $r15, _nds32_init_mem
  53431. beqz $r15, 6f
  53432. jral $r15
  53433. 6:
  53434. l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
  53435. jral $r15
  53436. -/* Reset handler() should never return in a RTOS or non-OS system.
  53437. - In case it does return, an exception will be generated.
  53438. - This exception will be caught either by default break handler or by EDM.
  53439. - Default break handle may just do an infinite loop.
  53440. - EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
  53441. +
  53442. + /* Reset handler() should never return in a RTOS or non-OS system.
  53443. + In case it does return, an exception will be generated.
  53444. + This exception will be caught either by default break handler or by EDM.
  53445. + Default break handle may just do an infinite loop.
  53446. + EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
  53447. 5:
  53448. break #0x7fff
  53449. .size _nds32_reset, .-_nds32_reset
  53450. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_all.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_all.inc
  53451. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_all.inc 2014-01-02 23:25:22.000000000 +0100
  53452. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_all.inc 2016-08-08 20:37:53.714587877 +0200
  53453. @@ -1,5 +1,5 @@
  53454. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53455. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53456. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53457. Contributed by Andes Technology Corporation.
  53458. This file is part of GCC.
  53459. @@ -31,15 +31,11 @@
  53460. mtsr $r2, $IPSW
  53461. RESTORE_FPU_REGS
  53462. RESTORE_MAC_REGS
  53463. -#ifdef NDS32_EXT_IFC
  53464. - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
  53465. - stack 8-byte alignment. */
  53466. - mtusr $r1, $IFC_LP
  53467. -#endif
  53468. -#ifdef __NDS32_REDUCED_REGS__
  53469. + RESTORE_USR_REGS
  53470. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53471. lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */
  53472. lmw.bim $r15, [$sp], $r15, #0xf
  53473. -#else /* not __NDS32_REDUCED_REGS__ */
  53474. +#else
  53475. lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */
  53476. #endif
  53477. .endm
  53478. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc
  53479. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc 2014-01-02 23:25:22.000000000 +0100
  53480. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc 2016-08-08 20:37:53.714587877 +0200
  53481. @@ -1,5 +1,5 @@
  53482. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53483. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53484. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53485. Contributed by Andes Technology Corporation.
  53486. This file is part of GCC.
  53487. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc
  53488. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc 2014-01-02 23:25:22.000000000 +0100
  53489. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc 2016-08-08 20:37:53.714587877 +0200
  53490. @@ -1,5 +1,5 @@
  53491. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53492. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53493. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53494. Contributed by Andes Technology Corporation.
  53495. This file is part of GCC.
  53496. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc
  53497. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc 2014-01-02 23:25:22.000000000 +0100
  53498. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc 2016-08-08 20:37:53.714587877 +0200
  53499. @@ -1,5 +1,5 @@
  53500. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53501. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53502. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53503. Contributed by Andes Technology Corporation.
  53504. This file is part of GCC.
  53505. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc
  53506. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc 2014-01-02 23:25:22.000000000 +0100
  53507. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc 2016-08-08 20:37:53.718588032 +0200
  53508. @@ -1,5 +1,5 @@
  53509. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53510. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53511. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53512. Contributed by Andes Technology Corporation.
  53513. This file is part of GCC.
  53514. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs.inc
  53515. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_fpu_regs.inc 2014-01-02 23:25:22.000000000 +0100
  53516. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_fpu_regs.inc 2016-08-08 20:37:53.714587877 +0200
  53517. @@ -1,5 +1,5 @@
  53518. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53519. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53520. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53521. Contributed by Andes Technology Corporation.
  53522. This file is part of GCC.
  53523. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_mac_regs.inc
  53524. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2014-01-02 23:25:22.000000000 +0100
  53525. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_mac_regs.inc 2016-08-08 20:37:53.718588032 +0200
  53526. @@ -1,5 +1,5 @@
  53527. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53528. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53529. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53530. Contributed by Andes Technology Corporation.
  53531. This file is part of GCC.
  53532. @@ -24,7 +24,7 @@
  53533. <http://www.gnu.org/licenses/>. */
  53534. .macro RESTORE_MAC_REGS
  53535. -#ifdef NDS32_DX_REGS
  53536. +#if __NDS32_DX_REGS__
  53537. lmw.bim $r1, [$sp], $r4, #0x0
  53538. mtusr $r1, $d0.lo
  53539. mtusr $r2, $d0.hi
  53540. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_partial.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_partial.inc
  53541. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_partial.inc 2014-01-02 23:25:22.000000000 +0100
  53542. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_partial.inc 2016-08-08 20:37:53.718588032 +0200
  53543. @@ -1,5 +1,5 @@
  53544. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53545. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53546. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53547. Contributed by Andes Technology Corporation.
  53548. This file is part of GCC.
  53549. @@ -31,15 +31,11 @@
  53550. mtsr $r1, $IPC /* Set IPC. */
  53551. mtsr $r2, $IPSW /* Set IPSW. */
  53552. #endif
  53553. - RESTORE_FPU_REGS
  53554. - RESTORE_MAC_REGS
  53555. -#ifdef NDS32_EXT_IFC
  53556. - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
  53557. - stack 8-byte alignment. */
  53558. - mtusr $r1, $IFC_LP
  53559. -#endif
  53560. + RESTORE_FPU_REGS
  53561. + RESTORE_MAC_REGS
  53562. + RESTORE_USR_REGS
  53563. lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */
  53564. -#ifdef __NDS32_REDUCED_REGS__
  53565. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53566. lmw.bim $r15, [$sp], $r15, #0x2
  53567. #else
  53568. lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */
  53569. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/restore_usr_regs.inc
  53570. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/restore_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100
  53571. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/restore_usr_regs.inc 2016-08-08 20:37:53.718588032 +0200
  53572. @@ -0,0 +1,42 @@
  53573. +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53574. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53575. + Contributed by Andes Technology Corporation.
  53576. +
  53577. + This file is part of GCC.
  53578. +
  53579. + GCC is free software; you can redistribute it and/or modify it
  53580. + under the terms of the GNU General Public License as published
  53581. + by the Free Software Foundation; either version 3, or (at your
  53582. + option) any later version.
  53583. +
  53584. + GCC is distributed in the hope that it will be useful, but WITHOUT
  53585. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  53586. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53587. + License for more details.
  53588. +
  53589. + Under Section 7 of GPL version 3, you are granted additional
  53590. + permissions described in the GCC Runtime Library Exception, version
  53591. + 3.1, as published by the Free Software Foundation.
  53592. +
  53593. + You should have received a copy of the GNU General Public License and
  53594. + a copy of the GCC Runtime Library Exception along with this program;
  53595. + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53596. + <http://www.gnu.org/licenses/>. */
  53597. +
  53598. +.macro RESTORE_USR_REGS
  53599. +#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
  53600. + lmw.bim $r1, [$sp], $r4, #0x0
  53601. + mtusr $r1, $IFC_LP
  53602. + mtusr $r2, $LB
  53603. + mtusr $r3, $LE
  53604. + mtusr $r4, $LC
  53605. +#elif __NDS32_EXT_IFC__
  53606. + lmw.bim $r1, [$sp], $r2, #0x0
  53607. + mtusr $r1, $IFC_LP
  53608. +#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
  53609. + lmw.bim $r1, [$sp], $r4, #0x0
  53610. + mtusr $r1, $LB
  53611. + mtusr $r2, $LE
  53612. + mtusr $r3, $LC
  53613. +#endif
  53614. +.endm
  53615. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_all.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_all.inc
  53616. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_all.inc 2014-01-02 23:25:22.000000000 +0100
  53617. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_all.inc 2016-08-08 20:37:53.718588032 +0200
  53618. @@ -1,5 +1,5 @@
  53619. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53620. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53621. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53622. Contributed by Andes Technology Corporation.
  53623. This file is part of GCC.
  53624. @@ -23,45 +23,42 @@
  53625. see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53626. <http://www.gnu.org/licenses/>. */
  53627. -.macro SAVE_ALL_4B
  53628. -#ifdef __NDS32_REDUCED_REGS__
  53629. +#if __NDS32_ISR_VECTOR_SIZE_4__
  53630. +
  53631. +/* If vector size is 4-byte, we have to save registers
  53632. + in the macro implementation. */
  53633. +.macro SAVE_ALL
  53634. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53635. smw.adm $r15, [$sp], $r15, #0xf
  53636. smw.adm $r0, [$sp], $r10, #0x0
  53637. -#else /* not __NDS32_REDUCED_REGS__ */
  53638. +#else
  53639. smw.adm $r0, [$sp], $r27, #0xf
  53640. -#endif /* not __NDS32_REDUCED_REGS__ */
  53641. -#ifdef NDS32_EXT_IFC
  53642. - mfusr $r1, $IFC_LP
  53643. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53644. - stack 8-byte alignment. */
  53645. #endif
  53646. - SAVE_MAC_REGS
  53647. - SAVE_FPU_REGS
  53648. + SAVE_USR_REGS
  53649. + SAVE_MAC_REGS
  53650. + SAVE_FPU_REGS
  53651. mfsr $r1, $IPC /* Get IPC. */
  53652. mfsr $r2, $IPSW /* Get IPSW. */
  53653. smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
  53654. move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
  53655. mfsr $r0, $ITYPE /* Get VID to $r0. */
  53656. srli $r0, $r0, #5
  53657. -#ifdef __NDS32_ISA_V2__
  53658. andi $r0, $r0, #127
  53659. -#else
  53660. - fexti33 $r0, #6
  53661. -#endif
  53662. .endm
  53663. +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  53664. +
  53665. +/* If vector size is 16-byte, some works can be done in
  53666. + the vector section generated by compiler, so that we
  53667. + can implement less in the macro. */
  53668. .macro SAVE_ALL
  53669. -/* SAVE_REG_TBL code has been moved to
  53670. - vector table generated by compiler. */
  53671. -#ifdef NDS32_EXT_IFC
  53672. - mfusr $r1, $IFC_LP
  53673. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53674. - stack 8-byte alignment. */
  53675. -#endif
  53676. - SAVE_MAC_REGS
  53677. - SAVE_FPU_REGS
  53678. + SAVE_USR_REGS
  53679. + SAVE_MAC_REGS
  53680. + SAVE_FPU_REGS
  53681. mfsr $r1, $IPC /* Get IPC. */
  53682. mfsr $r2, $IPSW /* Get IPSW. */
  53683. smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
  53684. move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
  53685. .endm
  53686. +
  53687. +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  53688. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc
  53689. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc 2014-01-02 23:25:22.000000000 +0100
  53690. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc 2016-08-08 20:37:53.718588032 +0200
  53691. @@ -1,5 +1,5 @@
  53692. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53693. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53694. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53695. Contributed by Andes Technology Corporation.
  53696. This file is part of GCC.
  53697. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc
  53698. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc 2014-01-02 23:25:22.000000000 +0100
  53699. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc 2016-08-08 20:37:53.718588032 +0200
  53700. @@ -1,5 +1,5 @@
  53701. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53702. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53703. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53704. Contributed by Andes Technology Corporation.
  53705. This file is part of GCC.
  53706. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc
  53707. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc 2014-01-02 23:25:22.000000000 +0100
  53708. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc 2016-08-08 20:37:53.718588032 +0200
  53709. @@ -1,5 +1,5 @@
  53710. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53711. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53712. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53713. Contributed by Andes Technology Corporation.
  53714. This file is part of GCC.
  53715. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc
  53716. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc 2014-01-02 23:25:22.000000000 +0100
  53717. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc 2016-08-08 20:37:53.718588032 +0200
  53718. @@ -1,5 +1,5 @@
  53719. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53720. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53721. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53722. Contributed by Andes Technology Corporation.
  53723. This file is part of GCC.
  53724. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs.inc
  53725. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_fpu_regs.inc 2014-01-02 23:25:22.000000000 +0100
  53726. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_fpu_regs.inc 2016-08-08 20:37:53.718588032 +0200
  53727. @@ -1,5 +1,5 @@
  53728. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53729. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53730. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53731. Contributed by Andes Technology Corporation.
  53732. This file is part of GCC.
  53733. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_mac_regs.inc
  53734. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_mac_regs.inc 2014-01-02 23:25:22.000000000 +0100
  53735. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_mac_regs.inc 2016-08-08 20:37:53.718588032 +0200
  53736. @@ -1,5 +1,5 @@
  53737. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53738. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53739. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53740. Contributed by Andes Technology Corporation.
  53741. This file is part of GCC.
  53742. @@ -24,7 +24,7 @@
  53743. <http://www.gnu.org/licenses/>. */
  53744. .macro SAVE_MAC_REGS
  53745. -#ifdef NDS32_DX_REGS
  53746. +#if __NDS32_DX_REGS__
  53747. mfusr $r1, $d0.lo
  53748. mfusr $r2, $d0.hi
  53749. mfusr $r3, $d1.lo
  53750. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_partial.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_partial.inc
  53751. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_partial.inc 2014-01-02 23:25:22.000000000 +0100
  53752. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_partial.inc 2016-08-08 20:37:53.718588032 +0200
  53753. @@ -1,5 +1,5 @@
  53754. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53755. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53756. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53757. Contributed by Andes Technology Corporation.
  53758. This file is part of GCC.
  53759. @@ -23,20 +23,20 @@
  53760. see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53761. <http://www.gnu.org/licenses/>. */
  53762. -.macro SAVE_PARTIAL_4B
  53763. -#ifdef __NDS32_REDUCED_REGS__
  53764. +#if __NDS32_ISR_VECTOR_SIZE_4__
  53765. +
  53766. +/* If vector size is 4-byte, we have to save registers
  53767. + in the macro implementation. */
  53768. +.macro SAVE_PARTIAL
  53769. +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
  53770. smw.adm $r15, [$sp], $r15, #0x2
  53771. -#else /* not __NDS32_REDUCED_REGS__ */
  53772. +#else
  53773. smw.adm $r15, [$sp], $r27, #0x2
  53774. -#endif /* not __NDS32_REDUCED_REGS__ */
  53775. - smw.adm $r0, [$sp], $r5, #0x0
  53776. -#ifdef NDS32_EXT_IFC
  53777. - mfusr $r1, $IFC_LP
  53778. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53779. - stack 8-byte alignment. */
  53780. #endif
  53781. - SAVE_MAC_REGS
  53782. - SAVE_FPU_REGS
  53783. + smw.adm $r0, [$sp], $r5, #0x0
  53784. + SAVE_USR_REGS
  53785. + SAVE_MAC_REGS
  53786. + SAVE_FPU_REGS
  53787. #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
  53788. mfsr $r1, $IPC /* Get IPC. */
  53789. mfsr $r2, $IPSW /* Get IPSW. */
  53790. @@ -44,26 +44,24 @@
  53791. #endif
  53792. mfsr $r0, $ITYPE /* Get VID to $r0. */
  53793. srli $r0, $r0, #5
  53794. -#ifdef __NDS32_ISA_V2__
  53795. andi $r0, $r0, #127
  53796. -#else
  53797. - fexti33 $r0, #6
  53798. -#endif
  53799. .endm
  53800. +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  53801. +
  53802. +/* If vector size is 16-byte, some works can be done in
  53803. + the vector section generated by compiler, so that we
  53804. + can implement less in the macro. */
  53805. +
  53806. .macro SAVE_PARTIAL
  53807. -/* SAVE_CALLER_REGS code has been moved to
  53808. - vector table generated by compiler. */
  53809. -#ifdef NDS32_EXT_IFC
  53810. - mfusr $r1, $IFC_LP
  53811. - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
  53812. - stack 8-byte alignment. */
  53813. -#endif
  53814. - SAVE_MAC_REGS
  53815. - SAVE_FPU_REGS
  53816. + SAVE_USR_REGS
  53817. + SAVE_MAC_REGS
  53818. + SAVE_FPU_REGS
  53819. #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
  53820. mfsr $r1, $IPC /* Get IPC. */
  53821. mfsr $r2, $IPSW /* Get IPSW. */
  53822. smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
  53823. #endif
  53824. .endm
  53825. +
  53826. +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
  53827. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc gcc-4.9.4/libgcc/config/nds32/isr-library/save_usr_regs.inc
  53828. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/save_usr_regs.inc 1970-01-01 01:00:00.000000000 +0100
  53829. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/save_usr_regs.inc 2016-08-08 20:37:53.718588032 +0200
  53830. @@ -0,0 +1,44 @@
  53831. +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53832. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53833. + Contributed by Andes Technology Corporation.
  53834. +
  53835. + This file is part of GCC.
  53836. +
  53837. + GCC is free software; you can redistribute it and/or modify it
  53838. + under the terms of the GNU General Public License as published
  53839. + by the Free Software Foundation; either version 3, or (at your
  53840. + option) any later version.
  53841. +
  53842. + GCC is distributed in the hope that it will be useful, but WITHOUT
  53843. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  53844. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53845. + License for more details.
  53846. +
  53847. + Under Section 7 of GPL version 3, you are granted additional
  53848. + permissions described in the GCC Runtime Library Exception, version
  53849. + 3.1, as published by the Free Software Foundation.
  53850. +
  53851. + You should have received a copy of the GNU General Public License and
  53852. + a copy of the GCC Runtime Library Exception along with this program;
  53853. + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53854. + <http://www.gnu.org/licenses/>. */
  53855. +
  53856. +.macro SAVE_USR_REGS
  53857. +/* Store User Special Registers according to supported ISA extension
  53858. + !!! WATCH OUT !!! Take care of 8-byte alignment issue. */
  53859. +#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
  53860. + mfusr $r1, $IFC_LP
  53861. + mfusr $r2, $LB
  53862. + mfusr $r3, $LE
  53863. + mfusr $r4, $LC
  53864. + smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */
  53865. +#elif __NDS32_EXT_IFC__
  53866. + mfusr $r1, $IFC_LP
  53867. + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */
  53868. +#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
  53869. + mfusr $r1, $LB
  53870. + mfusr $r2, $LE
  53871. + mfusr $r3, $LC
  53872. + smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */
  53873. +#endif
  53874. +.endm
  53875. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid00_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid00_4b.S
  53876. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid00_4b.S 2014-01-02 23:25:22.000000000 +0100
  53877. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid00_4b.S 1970-01-01 01:00:00.000000000 +0100
  53878. @@ -1,34 +0,0 @@
  53879. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53880. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53881. - Contributed by Andes Technology Corporation.
  53882. -
  53883. - This file is part of GCC.
  53884. -
  53885. - GCC is free software; you can redistribute it and/or modify it
  53886. - under the terms of the GNU General Public License as published
  53887. - by the Free Software Foundation; either version 3, or (at your
  53888. - option) any later version.
  53889. -
  53890. - GCC is distributed in the hope that it will be useful, but WITHOUT
  53891. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  53892. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53893. - License for more details.
  53894. -
  53895. - Under Section 7 of GPL version 3, you are granted additional
  53896. - permissions described in the GCC Runtime Library Exception, version
  53897. - 3.1, as published by the Free Software Foundation.
  53898. -
  53899. - You should have received a copy of the GNU General Public License and
  53900. - a copy of the GCC Runtime Library Exception along with this program;
  53901. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53902. - <http://www.gnu.org/licenses/>. */
  53903. -
  53904. - .section .nds32_vector.00, "ax"
  53905. - .vec_size 4
  53906. - .align 2
  53907. - .weak _nds32_vector_00_4b
  53908. - .type _nds32_vector_00_4b, @function
  53909. -_nds32_vector_00_4b:
  53910. -1:
  53911. - j 1b
  53912. - .size _nds32_vector_00_4b, .-_nds32_vector_00_4b
  53913. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid00.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid00.S
  53914. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid00.S 2014-01-02 23:25:22.000000000 +0100
  53915. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid00.S 2016-08-08 20:37:53.718588032 +0200
  53916. @@ -1,5 +1,5 @@
  53917. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53918. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53919. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53920. Contributed by Andes Technology Corporation.
  53921. This file is part of GCC.
  53922. @@ -24,8 +24,15 @@
  53923. <http://www.gnu.org/licenses/>. */
  53924. .section .nds32_vector.00, "ax"
  53925. +#if __NDS32_ISR_VECTOR_SIZE_4__
  53926. + /* The vector size is default 4-byte for v3 architecture. */
  53927. + .vec_size 4
  53928. + .align 2
  53929. +#else
  53930. + /* The vector size is default 16-byte for other architectures. */
  53931. .vec_size 16
  53932. .align 4
  53933. +#endif
  53934. .weak _nds32_vector_00
  53935. .type _nds32_vector_00, @function
  53936. _nds32_vector_00:
  53937. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid01_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid01_4b.S
  53938. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid01_4b.S 2014-01-02 23:25:22.000000000 +0100
  53939. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid01_4b.S 1970-01-01 01:00:00.000000000 +0100
  53940. @@ -1,34 +0,0 @@
  53941. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53942. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53943. - Contributed by Andes Technology Corporation.
  53944. -
  53945. - This file is part of GCC.
  53946. -
  53947. - GCC is free software; you can redistribute it and/or modify it
  53948. - under the terms of the GNU General Public License as published
  53949. - by the Free Software Foundation; either version 3, or (at your
  53950. - option) any later version.
  53951. -
  53952. - GCC is distributed in the hope that it will be useful, but WITHOUT
  53953. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  53954. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  53955. - License for more details.
  53956. -
  53957. - Under Section 7 of GPL version 3, you are granted additional
  53958. - permissions described in the GCC Runtime Library Exception, version
  53959. - 3.1, as published by the Free Software Foundation.
  53960. -
  53961. - You should have received a copy of the GNU General Public License and
  53962. - a copy of the GCC Runtime Library Exception along with this program;
  53963. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  53964. - <http://www.gnu.org/licenses/>. */
  53965. -
  53966. - .section .nds32_vector.01, "ax"
  53967. - .vec_size 4
  53968. - .align 2
  53969. - .weak _nds32_vector_01_4b
  53970. - .type _nds32_vector_01_4b, @function
  53971. -_nds32_vector_01_4b:
  53972. -1:
  53973. - j 1b
  53974. - .size _nds32_vector_01_4b, .-_nds32_vector_01_4b
  53975. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid01.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid01.S
  53976. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid01.S 2014-01-02 23:25:22.000000000 +0100
  53977. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid01.S 2016-08-08 20:37:53.718588032 +0200
  53978. @@ -1,5 +1,5 @@
  53979. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  53980. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  53981. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  53982. Contributed by Andes Technology Corporation.
  53983. This file is part of GCC.
  53984. @@ -24,8 +24,15 @@
  53985. <http://www.gnu.org/licenses/>. */
  53986. .section .nds32_vector.01, "ax"
  53987. +#if __NDS32_ISR_VECTOR_SIZE_4__
  53988. + /* The vector size is default 4-byte for v3 architecture. */
  53989. + .vec_size 4
  53990. + .align 2
  53991. +#else
  53992. + /* The vector size is default 16-byte for other architectures. */
  53993. .vec_size 16
  53994. .align 4
  53995. +#endif
  53996. .weak _nds32_vector_01
  53997. .type _nds32_vector_01, @function
  53998. _nds32_vector_01:
  53999. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid02_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid02_4b.S
  54000. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid02_4b.S 2014-01-02 23:25:22.000000000 +0100
  54001. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid02_4b.S 1970-01-01 01:00:00.000000000 +0100
  54002. @@ -1,34 +0,0 @@
  54003. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54004. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54005. - Contributed by Andes Technology Corporation.
  54006. -
  54007. - This file is part of GCC.
  54008. -
  54009. - GCC is free software; you can redistribute it and/or modify it
  54010. - under the terms of the GNU General Public License as published
  54011. - by the Free Software Foundation; either version 3, or (at your
  54012. - option) any later version.
  54013. -
  54014. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54015. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54016. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54017. - License for more details.
  54018. -
  54019. - Under Section 7 of GPL version 3, you are granted additional
  54020. - permissions described in the GCC Runtime Library Exception, version
  54021. - 3.1, as published by the Free Software Foundation.
  54022. -
  54023. - You should have received a copy of the GNU General Public License and
  54024. - a copy of the GCC Runtime Library Exception along with this program;
  54025. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54026. - <http://www.gnu.org/licenses/>. */
  54027. -
  54028. - .section .nds32_vector.02, "ax"
  54029. - .vec_size 4
  54030. - .align 2
  54031. - .weak _nds32_vector_02_4b
  54032. - .type _nds32_vector_02_4b, @function
  54033. -_nds32_vector_02_4b:
  54034. -1:
  54035. - j 1b
  54036. - .size _nds32_vector_02_4b, .-_nds32_vector_02_4b
  54037. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid02.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid02.S
  54038. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid02.S 2014-01-02 23:25:22.000000000 +0100
  54039. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid02.S 2016-08-08 20:37:53.718588032 +0200
  54040. @@ -1,5 +1,5 @@
  54041. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54042. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54043. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54044. Contributed by Andes Technology Corporation.
  54045. This file is part of GCC.
  54046. @@ -24,8 +24,15 @@
  54047. <http://www.gnu.org/licenses/>. */
  54048. .section .nds32_vector.02, "ax"
  54049. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54050. + /* The vector size is default 4-byte for v3 architecture. */
  54051. + .vec_size 4
  54052. + .align 2
  54053. +#else
  54054. + /* The vector size is default 16-byte for other architectures. */
  54055. .vec_size 16
  54056. .align 4
  54057. +#endif
  54058. .weak _nds32_vector_02
  54059. .type _nds32_vector_02, @function
  54060. _nds32_vector_02:
  54061. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid03_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid03_4b.S
  54062. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid03_4b.S 2014-01-02 23:25:22.000000000 +0100
  54063. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid03_4b.S 1970-01-01 01:00:00.000000000 +0100
  54064. @@ -1,34 +0,0 @@
  54065. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54066. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54067. - Contributed by Andes Technology Corporation.
  54068. -
  54069. - This file is part of GCC.
  54070. -
  54071. - GCC is free software; you can redistribute it and/or modify it
  54072. - under the terms of the GNU General Public License as published
  54073. - by the Free Software Foundation; either version 3, or (at your
  54074. - option) any later version.
  54075. -
  54076. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54077. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54078. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54079. - License for more details.
  54080. -
  54081. - Under Section 7 of GPL version 3, you are granted additional
  54082. - permissions described in the GCC Runtime Library Exception, version
  54083. - 3.1, as published by the Free Software Foundation.
  54084. -
  54085. - You should have received a copy of the GNU General Public License and
  54086. - a copy of the GCC Runtime Library Exception along with this program;
  54087. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54088. - <http://www.gnu.org/licenses/>. */
  54089. -
  54090. - .section .nds32_vector.03, "ax"
  54091. - .vec_size 4
  54092. - .align 2
  54093. - .weak _nds32_vector_03_4b
  54094. - .type _nds32_vector_03_4b, @function
  54095. -_nds32_vector_03_4b:
  54096. -1:
  54097. - j 1b
  54098. - .size _nds32_vector_03_4b, .-_nds32_vector_03_4b
  54099. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid03.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid03.S
  54100. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid03.S 2014-01-02 23:25:22.000000000 +0100
  54101. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid03.S 2016-08-08 20:37:53.718588032 +0200
  54102. @@ -1,5 +1,5 @@
  54103. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54104. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54105. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54106. Contributed by Andes Technology Corporation.
  54107. This file is part of GCC.
  54108. @@ -24,8 +24,15 @@
  54109. <http://www.gnu.org/licenses/>. */
  54110. .section .nds32_vector.03, "ax"
  54111. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54112. + /* The vector size is default 4-byte for v3 architecture. */
  54113. + .vec_size 4
  54114. + .align 2
  54115. +#else
  54116. + /* The vector size is default 16-byte for other architectures. */
  54117. .vec_size 16
  54118. .align 4
  54119. +#endif
  54120. .weak _nds32_vector_03
  54121. .type _nds32_vector_03, @function
  54122. _nds32_vector_03:
  54123. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid04_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid04_4b.S
  54124. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid04_4b.S 2014-01-02 23:25:22.000000000 +0100
  54125. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid04_4b.S 1970-01-01 01:00:00.000000000 +0100
  54126. @@ -1,34 +0,0 @@
  54127. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54128. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54129. - Contributed by Andes Technology Corporation.
  54130. -
  54131. - This file is part of GCC.
  54132. -
  54133. - GCC is free software; you can redistribute it and/or modify it
  54134. - under the terms of the GNU General Public License as published
  54135. - by the Free Software Foundation; either version 3, or (at your
  54136. - option) any later version.
  54137. -
  54138. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54139. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54140. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54141. - License for more details.
  54142. -
  54143. - Under Section 7 of GPL version 3, you are granted additional
  54144. - permissions described in the GCC Runtime Library Exception, version
  54145. - 3.1, as published by the Free Software Foundation.
  54146. -
  54147. - You should have received a copy of the GNU General Public License and
  54148. - a copy of the GCC Runtime Library Exception along with this program;
  54149. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54150. - <http://www.gnu.org/licenses/>. */
  54151. -
  54152. - .section .nds32_vector.04, "ax"
  54153. - .vec_size 4
  54154. - .align 2
  54155. - .weak _nds32_vector_04_4b
  54156. - .type _nds32_vector_04_4b, @function
  54157. -_nds32_vector_04_4b:
  54158. -1:
  54159. - j 1b
  54160. - .size _nds32_vector_04_4b, .-_nds32_vector_04_4b
  54161. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid04.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid04.S
  54162. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid04.S 2014-01-02 23:25:22.000000000 +0100
  54163. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid04.S 2016-08-08 20:37:53.722588187 +0200
  54164. @@ -1,5 +1,5 @@
  54165. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54166. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54167. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54168. Contributed by Andes Technology Corporation.
  54169. This file is part of GCC.
  54170. @@ -24,8 +24,15 @@
  54171. <http://www.gnu.org/licenses/>. */
  54172. .section .nds32_vector.04, "ax"
  54173. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54174. + /* The vector size is default 4-byte for v3 architecture. */
  54175. + .vec_size 4
  54176. + .align 2
  54177. +#else
  54178. + /* The vector size is default 16-byte for other architectures. */
  54179. .vec_size 16
  54180. .align 4
  54181. +#endif
  54182. .weak _nds32_vector_04
  54183. .type _nds32_vector_04, @function
  54184. _nds32_vector_04:
  54185. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid05_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid05_4b.S
  54186. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid05_4b.S 2014-01-02 23:25:22.000000000 +0100
  54187. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid05_4b.S 1970-01-01 01:00:00.000000000 +0100
  54188. @@ -1,34 +0,0 @@
  54189. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54190. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54191. - Contributed by Andes Technology Corporation.
  54192. -
  54193. - This file is part of GCC.
  54194. -
  54195. - GCC is free software; you can redistribute it and/or modify it
  54196. - under the terms of the GNU General Public License as published
  54197. - by the Free Software Foundation; either version 3, or (at your
  54198. - option) any later version.
  54199. -
  54200. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54201. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54202. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54203. - License for more details.
  54204. -
  54205. - Under Section 7 of GPL version 3, you are granted additional
  54206. - permissions described in the GCC Runtime Library Exception, version
  54207. - 3.1, as published by the Free Software Foundation.
  54208. -
  54209. - You should have received a copy of the GNU General Public License and
  54210. - a copy of the GCC Runtime Library Exception along with this program;
  54211. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54212. - <http://www.gnu.org/licenses/>. */
  54213. -
  54214. - .section .nds32_vector.05, "ax"
  54215. - .vec_size 4
  54216. - .align 2
  54217. - .weak _nds32_vector_05_4b
  54218. - .type _nds32_vector_05_4b, @function
  54219. -_nds32_vector_05_4b:
  54220. -1:
  54221. - j 1b
  54222. - .size _nds32_vector_05_4b, .-_nds32_vector_05_4b
  54223. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid05.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid05.S
  54224. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid05.S 2014-01-02 23:25:22.000000000 +0100
  54225. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid05.S 2016-08-08 20:37:53.722588187 +0200
  54226. @@ -1,5 +1,5 @@
  54227. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54228. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54229. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54230. Contributed by Andes Technology Corporation.
  54231. This file is part of GCC.
  54232. @@ -24,8 +24,15 @@
  54233. <http://www.gnu.org/licenses/>. */
  54234. .section .nds32_vector.05, "ax"
  54235. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54236. + /* The vector size is default 4-byte for v3 architecture. */
  54237. + .vec_size 4
  54238. + .align 2
  54239. +#else
  54240. + /* The vector size is default 16-byte for other architectures. */
  54241. .vec_size 16
  54242. .align 4
  54243. +#endif
  54244. .weak _nds32_vector_05
  54245. .type _nds32_vector_05, @function
  54246. _nds32_vector_05:
  54247. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid06_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid06_4b.S
  54248. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid06_4b.S 2014-01-02 23:25:22.000000000 +0100
  54249. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid06_4b.S 1970-01-01 01:00:00.000000000 +0100
  54250. @@ -1,34 +0,0 @@
  54251. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54252. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54253. - Contributed by Andes Technology Corporation.
  54254. -
  54255. - This file is part of GCC.
  54256. -
  54257. - GCC is free software; you can redistribute it and/or modify it
  54258. - under the terms of the GNU General Public License as published
  54259. - by the Free Software Foundation; either version 3, or (at your
  54260. - option) any later version.
  54261. -
  54262. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54263. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54264. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54265. - License for more details.
  54266. -
  54267. - Under Section 7 of GPL version 3, you are granted additional
  54268. - permissions described in the GCC Runtime Library Exception, version
  54269. - 3.1, as published by the Free Software Foundation.
  54270. -
  54271. - You should have received a copy of the GNU General Public License and
  54272. - a copy of the GCC Runtime Library Exception along with this program;
  54273. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54274. - <http://www.gnu.org/licenses/>. */
  54275. -
  54276. - .section .nds32_vector.06, "ax"
  54277. - .vec_size 4
  54278. - .align 2
  54279. - .weak _nds32_vector_06_4b
  54280. - .type _nds32_vector_06_4b, @function
  54281. -_nds32_vector_06_4b:
  54282. -1:
  54283. - j 1b
  54284. - .size _nds32_vector_06_4b, .-_nds32_vector_06_4b
  54285. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid06.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid06.S
  54286. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid06.S 2014-01-02 23:25:22.000000000 +0100
  54287. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid06.S 2016-08-08 20:37:53.722588187 +0200
  54288. @@ -1,5 +1,5 @@
  54289. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54290. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54291. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54292. Contributed by Andes Technology Corporation.
  54293. This file is part of GCC.
  54294. @@ -24,8 +24,15 @@
  54295. <http://www.gnu.org/licenses/>. */
  54296. .section .nds32_vector.06, "ax"
  54297. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54298. + /* The vector size is default 4-byte for v3 architecture. */
  54299. + .vec_size 4
  54300. + .align 2
  54301. +#else
  54302. + /* The vector size is default 16-byte for other architectures. */
  54303. .vec_size 16
  54304. .align 4
  54305. +#endif
  54306. .weak _nds32_vector_06
  54307. .type _nds32_vector_06, @function
  54308. _nds32_vector_06:
  54309. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid07_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid07_4b.S
  54310. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid07_4b.S 2014-01-02 23:25:22.000000000 +0100
  54311. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid07_4b.S 1970-01-01 01:00:00.000000000 +0100
  54312. @@ -1,34 +0,0 @@
  54313. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54314. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54315. - Contributed by Andes Technology Corporation.
  54316. -
  54317. - This file is part of GCC.
  54318. -
  54319. - GCC is free software; you can redistribute it and/or modify it
  54320. - under the terms of the GNU General Public License as published
  54321. - by the Free Software Foundation; either version 3, or (at your
  54322. - option) any later version.
  54323. -
  54324. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54325. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54326. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54327. - License for more details.
  54328. -
  54329. - Under Section 7 of GPL version 3, you are granted additional
  54330. - permissions described in the GCC Runtime Library Exception, version
  54331. - 3.1, as published by the Free Software Foundation.
  54332. -
  54333. - You should have received a copy of the GNU General Public License and
  54334. - a copy of the GCC Runtime Library Exception along with this program;
  54335. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54336. - <http://www.gnu.org/licenses/>. */
  54337. -
  54338. - .section .nds32_vector.07, "ax"
  54339. - .vec_size 4
  54340. - .align 2
  54341. - .weak _nds32_vector_07_4b
  54342. - .type _nds32_vector_07_4b, @function
  54343. -_nds32_vector_07_4b:
  54344. -1:
  54345. - j 1b
  54346. - .size _nds32_vector_07_4b, .-_nds32_vector_07_4b
  54347. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid07.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid07.S
  54348. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid07.S 2014-01-02 23:25:22.000000000 +0100
  54349. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid07.S 2016-08-08 20:37:53.722588187 +0200
  54350. @@ -1,5 +1,5 @@
  54351. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54352. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54353. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54354. Contributed by Andes Technology Corporation.
  54355. This file is part of GCC.
  54356. @@ -24,8 +24,15 @@
  54357. <http://www.gnu.org/licenses/>. */
  54358. .section .nds32_vector.07, "ax"
  54359. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54360. + /* The vector size is default 4-byte for v3 architecture. */
  54361. + .vec_size 4
  54362. + .align 2
  54363. +#else
  54364. + /* The vector size is default 16-byte for other architectures. */
  54365. .vec_size 16
  54366. .align 4
  54367. +#endif
  54368. .weak _nds32_vector_07
  54369. .type _nds32_vector_07, @function
  54370. _nds32_vector_07:
  54371. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid08_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid08_4b.S
  54372. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid08_4b.S 2014-01-02 23:25:22.000000000 +0100
  54373. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid08_4b.S 1970-01-01 01:00:00.000000000 +0100
  54374. @@ -1,34 +0,0 @@
  54375. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54376. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54377. - Contributed by Andes Technology Corporation.
  54378. -
  54379. - This file is part of GCC.
  54380. -
  54381. - GCC is free software; you can redistribute it and/or modify it
  54382. - under the terms of the GNU General Public License as published
  54383. - by the Free Software Foundation; either version 3, or (at your
  54384. - option) any later version.
  54385. -
  54386. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54387. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54388. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54389. - License for more details.
  54390. -
  54391. - Under Section 7 of GPL version 3, you are granted additional
  54392. - permissions described in the GCC Runtime Library Exception, version
  54393. - 3.1, as published by the Free Software Foundation.
  54394. -
  54395. - You should have received a copy of the GNU General Public License and
  54396. - a copy of the GCC Runtime Library Exception along with this program;
  54397. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54398. - <http://www.gnu.org/licenses/>. */
  54399. -
  54400. - .section .nds32_vector.08, "ax"
  54401. - .vec_size 4
  54402. - .align 2
  54403. - .weak _nds32_vector_08_4b
  54404. - .type _nds32_vector_08_4b, @function
  54405. -_nds32_vector_08_4b:
  54406. -1:
  54407. - j 1b
  54408. - .size _nds32_vector_08_4b, .-_nds32_vector_08_4b
  54409. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid08.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid08.S
  54410. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid08.S 2014-01-02 23:25:22.000000000 +0100
  54411. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid08.S 2016-08-08 20:37:53.722588187 +0200
  54412. @@ -1,5 +1,5 @@
  54413. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54414. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54415. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54416. Contributed by Andes Technology Corporation.
  54417. This file is part of GCC.
  54418. @@ -24,8 +24,15 @@
  54419. <http://www.gnu.org/licenses/>. */
  54420. .section .nds32_vector.08, "ax"
  54421. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54422. + /* The vector size is default 4-byte for v3 architecture. */
  54423. + .vec_size 4
  54424. + .align 2
  54425. +#else
  54426. + /* The vector size is default 16-byte for other architectures. */
  54427. .vec_size 16
  54428. .align 4
  54429. +#endif
  54430. .weak _nds32_vector_08
  54431. .type _nds32_vector_08, @function
  54432. _nds32_vector_08:
  54433. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid09_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid09_4b.S
  54434. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid09_4b.S 2014-01-02 23:25:22.000000000 +0100
  54435. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid09_4b.S 1970-01-01 01:00:00.000000000 +0100
  54436. @@ -1,34 +0,0 @@
  54437. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54438. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54439. - Contributed by Andes Technology Corporation.
  54440. -
  54441. - This file is part of GCC.
  54442. -
  54443. - GCC is free software; you can redistribute it and/or modify it
  54444. - under the terms of the GNU General Public License as published
  54445. - by the Free Software Foundation; either version 3, or (at your
  54446. - option) any later version.
  54447. -
  54448. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54449. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54450. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54451. - License for more details.
  54452. -
  54453. - Under Section 7 of GPL version 3, you are granted additional
  54454. - permissions described in the GCC Runtime Library Exception, version
  54455. - 3.1, as published by the Free Software Foundation.
  54456. -
  54457. - You should have received a copy of the GNU General Public License and
  54458. - a copy of the GCC Runtime Library Exception along with this program;
  54459. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54460. - <http://www.gnu.org/licenses/>. */
  54461. -
  54462. - .section .nds32_vector.09, "ax"
  54463. - .vec_size 4
  54464. - .align 2
  54465. - .weak _nds32_vector_09_4b
  54466. - .type _nds32_vector_09_4b, @function
  54467. -_nds32_vector_09_4b:
  54468. -1:
  54469. - j 1b
  54470. - .size _nds32_vector_09_4b, .-_nds32_vector_09_4b
  54471. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid09.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid09.S
  54472. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid09.S 2014-01-02 23:25:22.000000000 +0100
  54473. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid09.S 2016-08-08 20:37:53.722588187 +0200
  54474. @@ -1,5 +1,5 @@
  54475. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54476. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54477. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54478. Contributed by Andes Technology Corporation.
  54479. This file is part of GCC.
  54480. @@ -24,8 +24,15 @@
  54481. <http://www.gnu.org/licenses/>. */
  54482. .section .nds32_vector.09, "ax"
  54483. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54484. + /* The vector size is default 4-byte for v3 architecture. */
  54485. + .vec_size 4
  54486. + .align 2
  54487. +#else
  54488. + /* The vector size is default 16-byte for other architectures. */
  54489. .vec_size 16
  54490. .align 4
  54491. +#endif
  54492. .weak _nds32_vector_09
  54493. .type _nds32_vector_09, @function
  54494. _nds32_vector_09:
  54495. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid10_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid10_4b.S
  54496. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid10_4b.S 2014-01-02 23:25:22.000000000 +0100
  54497. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid10_4b.S 1970-01-01 01:00:00.000000000 +0100
  54498. @@ -1,34 +0,0 @@
  54499. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54500. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54501. - Contributed by Andes Technology Corporation.
  54502. -
  54503. - This file is part of GCC.
  54504. -
  54505. - GCC is free software; you can redistribute it and/or modify it
  54506. - under the terms of the GNU General Public License as published
  54507. - by the Free Software Foundation; either version 3, or (at your
  54508. - option) any later version.
  54509. -
  54510. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54511. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54512. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54513. - License for more details.
  54514. -
  54515. - Under Section 7 of GPL version 3, you are granted additional
  54516. - permissions described in the GCC Runtime Library Exception, version
  54517. - 3.1, as published by the Free Software Foundation.
  54518. -
  54519. - You should have received a copy of the GNU General Public License and
  54520. - a copy of the GCC Runtime Library Exception along with this program;
  54521. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54522. - <http://www.gnu.org/licenses/>. */
  54523. -
  54524. - .section .nds32_vector.10, "ax"
  54525. - .vec_size 4
  54526. - .align 2
  54527. - .weak _nds32_vector_10_4b
  54528. - .type _nds32_vector_10_4b, @function
  54529. -_nds32_vector_10_4b:
  54530. -1:
  54531. - j 1b
  54532. - .size _nds32_vector_10_4b, .-_nds32_vector_10_4b
  54533. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid10.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid10.S
  54534. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid10.S 2014-01-02 23:25:22.000000000 +0100
  54535. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid10.S 2016-08-08 20:37:53.722588187 +0200
  54536. @@ -1,5 +1,5 @@
  54537. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54538. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54539. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54540. Contributed by Andes Technology Corporation.
  54541. This file is part of GCC.
  54542. @@ -24,8 +24,15 @@
  54543. <http://www.gnu.org/licenses/>. */
  54544. .section .nds32_vector.10, "ax"
  54545. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54546. + /* The vector size is default 4-byte for v3 architecture. */
  54547. + .vec_size 4
  54548. + .align 2
  54549. +#else
  54550. + /* The vector size is default 16-byte for other architectures. */
  54551. .vec_size 16
  54552. .align 4
  54553. +#endif
  54554. .weak _nds32_vector_10
  54555. .type _nds32_vector_10, @function
  54556. _nds32_vector_10:
  54557. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid11_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid11_4b.S
  54558. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid11_4b.S 2014-01-02 23:25:22.000000000 +0100
  54559. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid11_4b.S 1970-01-01 01:00:00.000000000 +0100
  54560. @@ -1,34 +0,0 @@
  54561. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54562. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54563. - Contributed by Andes Technology Corporation.
  54564. -
  54565. - This file is part of GCC.
  54566. -
  54567. - GCC is free software; you can redistribute it and/or modify it
  54568. - under the terms of the GNU General Public License as published
  54569. - by the Free Software Foundation; either version 3, or (at your
  54570. - option) any later version.
  54571. -
  54572. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54573. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54574. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54575. - License for more details.
  54576. -
  54577. - Under Section 7 of GPL version 3, you are granted additional
  54578. - permissions described in the GCC Runtime Library Exception, version
  54579. - 3.1, as published by the Free Software Foundation.
  54580. -
  54581. - You should have received a copy of the GNU General Public License and
  54582. - a copy of the GCC Runtime Library Exception along with this program;
  54583. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54584. - <http://www.gnu.org/licenses/>. */
  54585. -
  54586. - .section .nds32_vector.11, "ax"
  54587. - .vec_size 4
  54588. - .align 2
  54589. - .weak _nds32_vector_11_4b
  54590. - .type _nds32_vector_11_4b, @function
  54591. -_nds32_vector_11_4b:
  54592. -1:
  54593. - j 1b
  54594. - .size _nds32_vector_11_4b, .-_nds32_vector_11_4b
  54595. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid11.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid11.S
  54596. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid11.S 2014-01-02 23:25:22.000000000 +0100
  54597. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid11.S 2016-08-08 20:37:53.722588187 +0200
  54598. @@ -1,5 +1,5 @@
  54599. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54600. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54601. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54602. Contributed by Andes Technology Corporation.
  54603. This file is part of GCC.
  54604. @@ -24,8 +24,15 @@
  54605. <http://www.gnu.org/licenses/>. */
  54606. .section .nds32_vector.11, "ax"
  54607. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54608. + /* The vector size is default 4-byte for v3 architecture. */
  54609. + .vec_size 4
  54610. + .align 2
  54611. +#else
  54612. + /* The vector size is default 16-byte for other architectures. */
  54613. .vec_size 16
  54614. .align 4
  54615. +#endif
  54616. .weak _nds32_vector_11
  54617. .type _nds32_vector_11, @function
  54618. _nds32_vector_11:
  54619. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid12_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid12_4b.S
  54620. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid12_4b.S 2014-01-02 23:25:22.000000000 +0100
  54621. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid12_4b.S 1970-01-01 01:00:00.000000000 +0100
  54622. @@ -1,34 +0,0 @@
  54623. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54624. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54625. - Contributed by Andes Technology Corporation.
  54626. -
  54627. - This file is part of GCC.
  54628. -
  54629. - GCC is free software; you can redistribute it and/or modify it
  54630. - under the terms of the GNU General Public License as published
  54631. - by the Free Software Foundation; either version 3, or (at your
  54632. - option) any later version.
  54633. -
  54634. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54635. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54636. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54637. - License for more details.
  54638. -
  54639. - Under Section 7 of GPL version 3, you are granted additional
  54640. - permissions described in the GCC Runtime Library Exception, version
  54641. - 3.1, as published by the Free Software Foundation.
  54642. -
  54643. - You should have received a copy of the GNU General Public License and
  54644. - a copy of the GCC Runtime Library Exception along with this program;
  54645. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54646. - <http://www.gnu.org/licenses/>. */
  54647. -
  54648. - .section .nds32_vector.12, "ax"
  54649. - .vec_size 4
  54650. - .align 2
  54651. - .weak _nds32_vector_12_4b
  54652. - .type _nds32_vector_12_4b, @function
  54653. -_nds32_vector_12_4b:
  54654. -1:
  54655. - j 1b
  54656. - .size _nds32_vector_12_4b, .-_nds32_vector_12_4b
  54657. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid12.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid12.S
  54658. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid12.S 2014-01-02 23:25:22.000000000 +0100
  54659. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid12.S 2016-08-08 20:37:53.722588187 +0200
  54660. @@ -1,5 +1,5 @@
  54661. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54662. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54663. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54664. Contributed by Andes Technology Corporation.
  54665. This file is part of GCC.
  54666. @@ -24,8 +24,15 @@
  54667. <http://www.gnu.org/licenses/>. */
  54668. .section .nds32_vector.12, "ax"
  54669. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54670. + /* The vector size is default 4-byte for v3 architecture. */
  54671. + .vec_size 4
  54672. + .align 2
  54673. +#else
  54674. + /* The vector size is default 16-byte for other architectures. */
  54675. .vec_size 16
  54676. .align 4
  54677. +#endif
  54678. .weak _nds32_vector_12
  54679. .type _nds32_vector_12, @function
  54680. _nds32_vector_12:
  54681. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid13_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid13_4b.S
  54682. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid13_4b.S 2014-01-02 23:25:22.000000000 +0100
  54683. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid13_4b.S 1970-01-01 01:00:00.000000000 +0100
  54684. @@ -1,34 +0,0 @@
  54685. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54686. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54687. - Contributed by Andes Technology Corporation.
  54688. -
  54689. - This file is part of GCC.
  54690. -
  54691. - GCC is free software; you can redistribute it and/or modify it
  54692. - under the terms of the GNU General Public License as published
  54693. - by the Free Software Foundation; either version 3, or (at your
  54694. - option) any later version.
  54695. -
  54696. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54697. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54698. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54699. - License for more details.
  54700. -
  54701. - Under Section 7 of GPL version 3, you are granted additional
  54702. - permissions described in the GCC Runtime Library Exception, version
  54703. - 3.1, as published by the Free Software Foundation.
  54704. -
  54705. - You should have received a copy of the GNU General Public License and
  54706. - a copy of the GCC Runtime Library Exception along with this program;
  54707. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54708. - <http://www.gnu.org/licenses/>. */
  54709. -
  54710. - .section .nds32_vector.13, "ax"
  54711. - .vec_size 4
  54712. - .align 2
  54713. - .weak _nds32_vector_13_4b
  54714. - .type _nds32_vector_13_4b, @function
  54715. -_nds32_vector_13_4b:
  54716. -1:
  54717. - j 1b
  54718. - .size _nds32_vector_13_4b, .-_nds32_vector_13_4b
  54719. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid13.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid13.S
  54720. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid13.S 2014-01-02 23:25:22.000000000 +0100
  54721. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid13.S 2016-08-08 20:37:53.722588187 +0200
  54722. @@ -1,5 +1,5 @@
  54723. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54724. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54725. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54726. Contributed by Andes Technology Corporation.
  54727. This file is part of GCC.
  54728. @@ -24,8 +24,15 @@
  54729. <http://www.gnu.org/licenses/>. */
  54730. .section .nds32_vector.13, "ax"
  54731. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54732. + /* The vector size is default 4-byte for v3 architecture. */
  54733. + .vec_size 4
  54734. + .align 2
  54735. +#else
  54736. + /* The vector size is default 16-byte for other architectures. */
  54737. .vec_size 16
  54738. .align 4
  54739. +#endif
  54740. .weak _nds32_vector_13
  54741. .type _nds32_vector_13, @function
  54742. _nds32_vector_13:
  54743. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid14_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid14_4b.S
  54744. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid14_4b.S 2014-01-02 23:25:22.000000000 +0100
  54745. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid14_4b.S 1970-01-01 01:00:00.000000000 +0100
  54746. @@ -1,34 +0,0 @@
  54747. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54748. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54749. - Contributed by Andes Technology Corporation.
  54750. -
  54751. - This file is part of GCC.
  54752. -
  54753. - GCC is free software; you can redistribute it and/or modify it
  54754. - under the terms of the GNU General Public License as published
  54755. - by the Free Software Foundation; either version 3, or (at your
  54756. - option) any later version.
  54757. -
  54758. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54759. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54760. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54761. - License for more details.
  54762. -
  54763. - Under Section 7 of GPL version 3, you are granted additional
  54764. - permissions described in the GCC Runtime Library Exception, version
  54765. - 3.1, as published by the Free Software Foundation.
  54766. -
  54767. - You should have received a copy of the GNU General Public License and
  54768. - a copy of the GCC Runtime Library Exception along with this program;
  54769. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54770. - <http://www.gnu.org/licenses/>. */
  54771. -
  54772. - .section .nds32_vector.14, "ax"
  54773. - .vec_size 4
  54774. - .align 2
  54775. - .weak _nds32_vector_14_4b
  54776. - .type _nds32_vector_14_4b, @function
  54777. -_nds32_vector_14_4b:
  54778. -1:
  54779. - j 1b
  54780. - .size _nds32_vector_14_4b, .-_nds32_vector_14_4b
  54781. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid14.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid14.S
  54782. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid14.S 2014-01-02 23:25:22.000000000 +0100
  54783. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid14.S 2016-08-08 20:37:53.722588187 +0200
  54784. @@ -1,5 +1,5 @@
  54785. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54786. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54787. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54788. Contributed by Andes Technology Corporation.
  54789. This file is part of GCC.
  54790. @@ -24,8 +24,15 @@
  54791. <http://www.gnu.org/licenses/>. */
  54792. .section .nds32_vector.14, "ax"
  54793. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54794. + /* The vector size is default 4-byte for v3 architecture. */
  54795. + .vec_size 4
  54796. + .align 2
  54797. +#else
  54798. + /* The vector size is default 16-byte for other architectures. */
  54799. .vec_size 16
  54800. .align 4
  54801. +#endif
  54802. .weak _nds32_vector_14
  54803. .type _nds32_vector_14, @function
  54804. _nds32_vector_14:
  54805. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid15_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid15_4b.S
  54806. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid15_4b.S 2014-01-02 23:25:22.000000000 +0100
  54807. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid15_4b.S 1970-01-01 01:00:00.000000000 +0100
  54808. @@ -1,34 +0,0 @@
  54809. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54810. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54811. - Contributed by Andes Technology Corporation.
  54812. -
  54813. - This file is part of GCC.
  54814. -
  54815. - GCC is free software; you can redistribute it and/or modify it
  54816. - under the terms of the GNU General Public License as published
  54817. - by the Free Software Foundation; either version 3, or (at your
  54818. - option) any later version.
  54819. -
  54820. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54821. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54822. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54823. - License for more details.
  54824. -
  54825. - Under Section 7 of GPL version 3, you are granted additional
  54826. - permissions described in the GCC Runtime Library Exception, version
  54827. - 3.1, as published by the Free Software Foundation.
  54828. -
  54829. - You should have received a copy of the GNU General Public License and
  54830. - a copy of the GCC Runtime Library Exception along with this program;
  54831. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54832. - <http://www.gnu.org/licenses/>. */
  54833. -
  54834. - .section .nds32_vector.15, "ax"
  54835. - .vec_size 4
  54836. - .align 2
  54837. - .weak _nds32_vector_15_4b
  54838. - .type _nds32_vector_15_4b, @function
  54839. -_nds32_vector_15_4b:
  54840. -1:
  54841. - j 1b
  54842. - .size _nds32_vector_15_4b, .-_nds32_vector_15_4b
  54843. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid15.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid15.S
  54844. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid15.S 2014-01-02 23:25:22.000000000 +0100
  54845. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid15.S 2016-08-08 20:37:53.726588342 +0200
  54846. @@ -1,5 +1,5 @@
  54847. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54848. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54849. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54850. Contributed by Andes Technology Corporation.
  54851. This file is part of GCC.
  54852. @@ -24,8 +24,15 @@
  54853. <http://www.gnu.org/licenses/>. */
  54854. .section .nds32_vector.15, "ax"
  54855. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54856. + /* The vector size is default 4-byte for v3 architecture. */
  54857. + .vec_size 4
  54858. + .align 2
  54859. +#else
  54860. + /* The vector size is default 16-byte for other architectures. */
  54861. .vec_size 16
  54862. .align 4
  54863. +#endif
  54864. .weak _nds32_vector_15
  54865. .type _nds32_vector_15, @function
  54866. _nds32_vector_15:
  54867. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid16_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid16_4b.S
  54868. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid16_4b.S 2014-01-02 23:25:22.000000000 +0100
  54869. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid16_4b.S 1970-01-01 01:00:00.000000000 +0100
  54870. @@ -1,34 +0,0 @@
  54871. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54872. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54873. - Contributed by Andes Technology Corporation.
  54874. -
  54875. - This file is part of GCC.
  54876. -
  54877. - GCC is free software; you can redistribute it and/or modify it
  54878. - under the terms of the GNU General Public License as published
  54879. - by the Free Software Foundation; either version 3, or (at your
  54880. - option) any later version.
  54881. -
  54882. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54883. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54884. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54885. - License for more details.
  54886. -
  54887. - Under Section 7 of GPL version 3, you are granted additional
  54888. - permissions described in the GCC Runtime Library Exception, version
  54889. - 3.1, as published by the Free Software Foundation.
  54890. -
  54891. - You should have received a copy of the GNU General Public License and
  54892. - a copy of the GCC Runtime Library Exception along with this program;
  54893. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54894. - <http://www.gnu.org/licenses/>. */
  54895. -
  54896. - .section .nds32_vector.16, "ax"
  54897. - .vec_size 4
  54898. - .align 2
  54899. - .weak _nds32_vector_16_4b
  54900. - .type _nds32_vector_16_4b, @function
  54901. -_nds32_vector_16_4b:
  54902. -1:
  54903. - j 1b
  54904. - .size _nds32_vector_16_4b, .-_nds32_vector_16_4b
  54905. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid16.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid16.S
  54906. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid16.S 2014-01-02 23:25:22.000000000 +0100
  54907. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid16.S 2016-08-08 20:37:53.726588342 +0200
  54908. @@ -1,5 +1,5 @@
  54909. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54910. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54911. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54912. Contributed by Andes Technology Corporation.
  54913. This file is part of GCC.
  54914. @@ -24,8 +24,15 @@
  54915. <http://www.gnu.org/licenses/>. */
  54916. .section .nds32_vector.16, "ax"
  54917. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54918. + /* The vector size is default 4-byte for v3 architecture. */
  54919. + .vec_size 4
  54920. + .align 2
  54921. +#else
  54922. + /* The vector size is default 16-byte for other architectures. */
  54923. .vec_size 16
  54924. .align 4
  54925. +#endif
  54926. .weak _nds32_vector_16
  54927. .type _nds32_vector_16, @function
  54928. _nds32_vector_16:
  54929. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid17_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid17_4b.S
  54930. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid17_4b.S 2014-01-02 23:25:22.000000000 +0100
  54931. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid17_4b.S 1970-01-01 01:00:00.000000000 +0100
  54932. @@ -1,34 +0,0 @@
  54933. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54934. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54935. - Contributed by Andes Technology Corporation.
  54936. -
  54937. - This file is part of GCC.
  54938. -
  54939. - GCC is free software; you can redistribute it and/or modify it
  54940. - under the terms of the GNU General Public License as published
  54941. - by the Free Software Foundation; either version 3, or (at your
  54942. - option) any later version.
  54943. -
  54944. - GCC is distributed in the hope that it will be useful, but WITHOUT
  54945. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  54946. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  54947. - License for more details.
  54948. -
  54949. - Under Section 7 of GPL version 3, you are granted additional
  54950. - permissions described in the GCC Runtime Library Exception, version
  54951. - 3.1, as published by the Free Software Foundation.
  54952. -
  54953. - You should have received a copy of the GNU General Public License and
  54954. - a copy of the GCC Runtime Library Exception along with this program;
  54955. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  54956. - <http://www.gnu.org/licenses/>. */
  54957. -
  54958. - .section .nds32_vector.17, "ax"
  54959. - .vec_size 4
  54960. - .align 2
  54961. - .weak _nds32_vector_17_4b
  54962. - .type _nds32_vector_17_4b, @function
  54963. -_nds32_vector_17_4b:
  54964. -1:
  54965. - j 1b
  54966. - .size _nds32_vector_17_4b, .-_nds32_vector_17_4b
  54967. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid17.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid17.S
  54968. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid17.S 2014-01-02 23:25:22.000000000 +0100
  54969. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid17.S 2016-08-08 20:37:53.726588342 +0200
  54970. @@ -1,5 +1,5 @@
  54971. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54972. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54973. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  54974. Contributed by Andes Technology Corporation.
  54975. This file is part of GCC.
  54976. @@ -24,8 +24,15 @@
  54977. <http://www.gnu.org/licenses/>. */
  54978. .section .nds32_vector.17, "ax"
  54979. +#if __NDS32_ISR_VECTOR_SIZE_4__
  54980. + /* The vector size is default 4-byte for v3 architecture. */
  54981. + .vec_size 4
  54982. + .align 2
  54983. +#else
  54984. + /* The vector size is default 16-byte for other architectures. */
  54985. .vec_size 16
  54986. .align 4
  54987. +#endif
  54988. .weak _nds32_vector_17
  54989. .type _nds32_vector_17, @function
  54990. _nds32_vector_17:
  54991. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid18_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid18_4b.S
  54992. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid18_4b.S 2014-01-02 23:25:22.000000000 +0100
  54993. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid18_4b.S 1970-01-01 01:00:00.000000000 +0100
  54994. @@ -1,34 +0,0 @@
  54995. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  54996. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  54997. - Contributed by Andes Technology Corporation.
  54998. -
  54999. - This file is part of GCC.
  55000. -
  55001. - GCC is free software; you can redistribute it and/or modify it
  55002. - under the terms of the GNU General Public License as published
  55003. - by the Free Software Foundation; either version 3, or (at your
  55004. - option) any later version.
  55005. -
  55006. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55007. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55008. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55009. - License for more details.
  55010. -
  55011. - Under Section 7 of GPL version 3, you are granted additional
  55012. - permissions described in the GCC Runtime Library Exception, version
  55013. - 3.1, as published by the Free Software Foundation.
  55014. -
  55015. - You should have received a copy of the GNU General Public License and
  55016. - a copy of the GCC Runtime Library Exception along with this program;
  55017. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55018. - <http://www.gnu.org/licenses/>. */
  55019. -
  55020. - .section .nds32_vector.18, "ax"
  55021. - .vec_size 4
  55022. - .align 2
  55023. - .weak _nds32_vector_18_4b
  55024. - .type _nds32_vector_18_4b, @function
  55025. -_nds32_vector_18_4b:
  55026. -1:
  55027. - j 1b
  55028. - .size _nds32_vector_18_4b, .-_nds32_vector_18_4b
  55029. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid18.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid18.S
  55030. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid18.S 2014-01-02 23:25:22.000000000 +0100
  55031. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid18.S 2016-08-08 20:37:53.726588342 +0200
  55032. @@ -1,5 +1,5 @@
  55033. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55034. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55035. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55036. Contributed by Andes Technology Corporation.
  55037. This file is part of GCC.
  55038. @@ -24,8 +24,15 @@
  55039. <http://www.gnu.org/licenses/>. */
  55040. .section .nds32_vector.18, "ax"
  55041. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55042. + /* The vector size is default 4-byte for v3 architecture. */
  55043. + .vec_size 4
  55044. + .align 2
  55045. +#else
  55046. + /* The vector size is default 16-byte for other architectures. */
  55047. .vec_size 16
  55048. .align 4
  55049. +#endif
  55050. .weak _nds32_vector_18
  55051. .type _nds32_vector_18, @function
  55052. _nds32_vector_18:
  55053. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid19_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid19_4b.S
  55054. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid19_4b.S 2014-01-02 23:25:22.000000000 +0100
  55055. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid19_4b.S 1970-01-01 01:00:00.000000000 +0100
  55056. @@ -1,34 +0,0 @@
  55057. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55058. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55059. - Contributed by Andes Technology Corporation.
  55060. -
  55061. - This file is part of GCC.
  55062. -
  55063. - GCC is free software; you can redistribute it and/or modify it
  55064. - under the terms of the GNU General Public License as published
  55065. - by the Free Software Foundation; either version 3, or (at your
  55066. - option) any later version.
  55067. -
  55068. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55069. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55070. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55071. - License for more details.
  55072. -
  55073. - Under Section 7 of GPL version 3, you are granted additional
  55074. - permissions described in the GCC Runtime Library Exception, version
  55075. - 3.1, as published by the Free Software Foundation.
  55076. -
  55077. - You should have received a copy of the GNU General Public License and
  55078. - a copy of the GCC Runtime Library Exception along with this program;
  55079. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55080. - <http://www.gnu.org/licenses/>. */
  55081. -
  55082. - .section .nds32_vector.19, "ax"
  55083. - .vec_size 4
  55084. - .align 2
  55085. - .weak _nds32_vector_19_4b
  55086. - .type _nds32_vector_19_4b, @function
  55087. -_nds32_vector_19_4b:
  55088. -1:
  55089. - j 1b
  55090. - .size _nds32_vector_19_4b, .-_nds32_vector_19_4b
  55091. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid19.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid19.S
  55092. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid19.S 2014-01-02 23:25:22.000000000 +0100
  55093. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid19.S 2016-08-08 20:37:53.726588342 +0200
  55094. @@ -1,5 +1,5 @@
  55095. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55096. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55097. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55098. Contributed by Andes Technology Corporation.
  55099. This file is part of GCC.
  55100. @@ -24,8 +24,15 @@
  55101. <http://www.gnu.org/licenses/>. */
  55102. .section .nds32_vector.19, "ax"
  55103. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55104. + /* The vector size is default 4-byte for v3 architecture. */
  55105. + .vec_size 4
  55106. + .align 2
  55107. +#else
  55108. + /* The vector size is default 16-byte for other architectures. */
  55109. .vec_size 16
  55110. .align 4
  55111. +#endif
  55112. .weak _nds32_vector_19
  55113. .type _nds32_vector_19, @function
  55114. _nds32_vector_19:
  55115. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid20_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid20_4b.S
  55116. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid20_4b.S 2014-01-02 23:25:22.000000000 +0100
  55117. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid20_4b.S 1970-01-01 01:00:00.000000000 +0100
  55118. @@ -1,34 +0,0 @@
  55119. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55120. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55121. - Contributed by Andes Technology Corporation.
  55122. -
  55123. - This file is part of GCC.
  55124. -
  55125. - GCC is free software; you can redistribute it and/or modify it
  55126. - under the terms of the GNU General Public License as published
  55127. - by the Free Software Foundation; either version 3, or (at your
  55128. - option) any later version.
  55129. -
  55130. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55131. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55132. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55133. - License for more details.
  55134. -
  55135. - Under Section 7 of GPL version 3, you are granted additional
  55136. - permissions described in the GCC Runtime Library Exception, version
  55137. - 3.1, as published by the Free Software Foundation.
  55138. -
  55139. - You should have received a copy of the GNU General Public License and
  55140. - a copy of the GCC Runtime Library Exception along with this program;
  55141. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55142. - <http://www.gnu.org/licenses/>. */
  55143. -
  55144. - .section .nds32_vector.20, "ax"
  55145. - .vec_size 4
  55146. - .align 2
  55147. - .weak _nds32_vector_20_4b
  55148. - .type _nds32_vector_20_4b, @function
  55149. -_nds32_vector_20_4b:
  55150. -1:
  55151. - j 1b
  55152. - .size _nds32_vector_20_4b, .-_nds32_vector_20_4b
  55153. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid20.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid20.S
  55154. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid20.S 2014-01-02 23:25:22.000000000 +0100
  55155. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid20.S 2016-08-08 20:37:53.726588342 +0200
  55156. @@ -1,5 +1,5 @@
  55157. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55158. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55159. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55160. Contributed by Andes Technology Corporation.
  55161. This file is part of GCC.
  55162. @@ -24,8 +24,15 @@
  55163. <http://www.gnu.org/licenses/>. */
  55164. .section .nds32_vector.20, "ax"
  55165. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55166. + /* The vector size is default 4-byte for v3 architecture. */
  55167. + .vec_size 4
  55168. + .align 2
  55169. +#else
  55170. + /* The vector size is default 16-byte for other architectures. */
  55171. .vec_size 16
  55172. .align 4
  55173. +#endif
  55174. .weak _nds32_vector_20
  55175. .type _nds32_vector_20, @function
  55176. _nds32_vector_20:
  55177. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid21_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid21_4b.S
  55178. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid21_4b.S 2014-01-02 23:25:22.000000000 +0100
  55179. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid21_4b.S 1970-01-01 01:00:00.000000000 +0100
  55180. @@ -1,34 +0,0 @@
  55181. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55182. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55183. - Contributed by Andes Technology Corporation.
  55184. -
  55185. - This file is part of GCC.
  55186. -
  55187. - GCC is free software; you can redistribute it and/or modify it
  55188. - under the terms of the GNU General Public License as published
  55189. - by the Free Software Foundation; either version 3, or (at your
  55190. - option) any later version.
  55191. -
  55192. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55193. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55194. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55195. - License for more details.
  55196. -
  55197. - Under Section 7 of GPL version 3, you are granted additional
  55198. - permissions described in the GCC Runtime Library Exception, version
  55199. - 3.1, as published by the Free Software Foundation.
  55200. -
  55201. - You should have received a copy of the GNU General Public License and
  55202. - a copy of the GCC Runtime Library Exception along with this program;
  55203. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55204. - <http://www.gnu.org/licenses/>. */
  55205. -
  55206. - .section .nds32_vector.21, "ax"
  55207. - .vec_size 4
  55208. - .align 2
  55209. - .weak _nds32_vector_21_4b
  55210. - .type _nds32_vector_21_4b, @function
  55211. -_nds32_vector_21_4b:
  55212. -1:
  55213. - j 1b
  55214. - .size _nds32_vector_21_4b, .-_nds32_vector_21_4b
  55215. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid21.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid21.S
  55216. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid21.S 2014-01-02 23:25:22.000000000 +0100
  55217. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid21.S 2016-08-08 20:37:53.726588342 +0200
  55218. @@ -1,5 +1,5 @@
  55219. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55220. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55221. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55222. Contributed by Andes Technology Corporation.
  55223. This file is part of GCC.
  55224. @@ -24,8 +24,15 @@
  55225. <http://www.gnu.org/licenses/>. */
  55226. .section .nds32_vector.21, "ax"
  55227. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55228. + /* The vector size is default 4-byte for v3 architecture. */
  55229. + .vec_size 4
  55230. + .align 2
  55231. +#else
  55232. + /* The vector size is default 16-byte for other architectures. */
  55233. .vec_size 16
  55234. .align 4
  55235. +#endif
  55236. .weak _nds32_vector_21
  55237. .type _nds32_vector_21, @function
  55238. _nds32_vector_21:
  55239. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid22_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid22_4b.S
  55240. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid22_4b.S 2014-01-02 23:25:22.000000000 +0100
  55241. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid22_4b.S 1970-01-01 01:00:00.000000000 +0100
  55242. @@ -1,34 +0,0 @@
  55243. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55244. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55245. - Contributed by Andes Technology Corporation.
  55246. -
  55247. - This file is part of GCC.
  55248. -
  55249. - GCC is free software; you can redistribute it and/or modify it
  55250. - under the terms of the GNU General Public License as published
  55251. - by the Free Software Foundation; either version 3, or (at your
  55252. - option) any later version.
  55253. -
  55254. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55255. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55256. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55257. - License for more details.
  55258. -
  55259. - Under Section 7 of GPL version 3, you are granted additional
  55260. - permissions described in the GCC Runtime Library Exception, version
  55261. - 3.1, as published by the Free Software Foundation.
  55262. -
  55263. - You should have received a copy of the GNU General Public License and
  55264. - a copy of the GCC Runtime Library Exception along with this program;
  55265. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55266. - <http://www.gnu.org/licenses/>. */
  55267. -
  55268. - .section .nds32_vector.22, "ax"
  55269. - .vec_size 4
  55270. - .align 2
  55271. - .weak _nds32_vector_22_4b
  55272. - .type _nds32_vector_22_4b, @function
  55273. -_nds32_vector_22_4b:
  55274. -1:
  55275. - j 1b
  55276. - .size _nds32_vector_22_4b, .-_nds32_vector_22_4b
  55277. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid22.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid22.S
  55278. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid22.S 2014-01-02 23:25:22.000000000 +0100
  55279. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid22.S 2016-08-08 20:37:53.726588342 +0200
  55280. @@ -1,5 +1,5 @@
  55281. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55282. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55283. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55284. Contributed by Andes Technology Corporation.
  55285. This file is part of GCC.
  55286. @@ -24,8 +24,15 @@
  55287. <http://www.gnu.org/licenses/>. */
  55288. .section .nds32_vector.22, "ax"
  55289. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55290. + /* The vector size is default 4-byte for v3 architecture. */
  55291. + .vec_size 4
  55292. + .align 2
  55293. +#else
  55294. + /* The vector size is default 16-byte for other architectures. */
  55295. .vec_size 16
  55296. .align 4
  55297. +#endif
  55298. .weak _nds32_vector_22
  55299. .type _nds32_vector_22, @function
  55300. _nds32_vector_22:
  55301. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid23_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid23_4b.S
  55302. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid23_4b.S 2014-01-02 23:25:22.000000000 +0100
  55303. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid23_4b.S 1970-01-01 01:00:00.000000000 +0100
  55304. @@ -1,34 +0,0 @@
  55305. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55306. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55307. - Contributed by Andes Technology Corporation.
  55308. -
  55309. - This file is part of GCC.
  55310. -
  55311. - GCC is free software; you can redistribute it and/or modify it
  55312. - under the terms of the GNU General Public License as published
  55313. - by the Free Software Foundation; either version 3, or (at your
  55314. - option) any later version.
  55315. -
  55316. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55317. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55318. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55319. - License for more details.
  55320. -
  55321. - Under Section 7 of GPL version 3, you are granted additional
  55322. - permissions described in the GCC Runtime Library Exception, version
  55323. - 3.1, as published by the Free Software Foundation.
  55324. -
  55325. - You should have received a copy of the GNU General Public License and
  55326. - a copy of the GCC Runtime Library Exception along with this program;
  55327. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55328. - <http://www.gnu.org/licenses/>. */
  55329. -
  55330. - .section .nds32_vector.23, "ax"
  55331. - .vec_size 4
  55332. - .align 2
  55333. - .weak _nds32_vector_23_4b
  55334. - .type _nds32_vector_23_4b, @function
  55335. -_nds32_vector_23_4b:
  55336. -1:
  55337. - j 1b
  55338. - .size _nds32_vector_23_4b, .-_nds32_vector_23_4b
  55339. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid23.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid23.S
  55340. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid23.S 2014-01-02 23:25:22.000000000 +0100
  55341. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid23.S 2016-08-08 20:37:53.726588342 +0200
  55342. @@ -1,5 +1,5 @@
  55343. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55344. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55345. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55346. Contributed by Andes Technology Corporation.
  55347. This file is part of GCC.
  55348. @@ -24,8 +24,15 @@
  55349. <http://www.gnu.org/licenses/>. */
  55350. .section .nds32_vector.23, "ax"
  55351. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55352. + /* The vector size is default 4-byte for v3 architecture. */
  55353. + .vec_size 4
  55354. + .align 2
  55355. +#else
  55356. + /* The vector size is default 16-byte for other architectures. */
  55357. .vec_size 16
  55358. .align 4
  55359. +#endif
  55360. .weak _nds32_vector_23
  55361. .type _nds32_vector_23, @function
  55362. _nds32_vector_23:
  55363. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid24_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid24_4b.S
  55364. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid24_4b.S 2014-01-02 23:25:22.000000000 +0100
  55365. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid24_4b.S 1970-01-01 01:00:00.000000000 +0100
  55366. @@ -1,34 +0,0 @@
  55367. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55368. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55369. - Contributed by Andes Technology Corporation.
  55370. -
  55371. - This file is part of GCC.
  55372. -
  55373. - GCC is free software; you can redistribute it and/or modify it
  55374. - under the terms of the GNU General Public License as published
  55375. - by the Free Software Foundation; either version 3, or (at your
  55376. - option) any later version.
  55377. -
  55378. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55379. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55380. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55381. - License for more details.
  55382. -
  55383. - Under Section 7 of GPL version 3, you are granted additional
  55384. - permissions described in the GCC Runtime Library Exception, version
  55385. - 3.1, as published by the Free Software Foundation.
  55386. -
  55387. - You should have received a copy of the GNU General Public License and
  55388. - a copy of the GCC Runtime Library Exception along with this program;
  55389. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55390. - <http://www.gnu.org/licenses/>. */
  55391. -
  55392. - .section .nds32_vector.24, "ax"
  55393. - .vec_size 4
  55394. - .align 2
  55395. - .weak _nds32_vector_24_4b
  55396. - .type _nds32_vector_24_4b, @function
  55397. -_nds32_vector_24_4b:
  55398. -1:
  55399. - j 1b
  55400. - .size _nds32_vector_24_4b, .-_nds32_vector_24_4b
  55401. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid24.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid24.S
  55402. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid24.S 2014-01-02 23:25:22.000000000 +0100
  55403. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid24.S 2016-08-08 20:37:53.726588342 +0200
  55404. @@ -1,5 +1,5 @@
  55405. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55406. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55407. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55408. Contributed by Andes Technology Corporation.
  55409. This file is part of GCC.
  55410. @@ -24,8 +24,15 @@
  55411. <http://www.gnu.org/licenses/>. */
  55412. .section .nds32_vector.24, "ax"
  55413. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55414. + /* The vector size is default 4-byte for v3 architecture. */
  55415. + .vec_size 4
  55416. + .align 2
  55417. +#else
  55418. + /* The vector size is default 16-byte for other architectures. */
  55419. .vec_size 16
  55420. .align 4
  55421. +#endif
  55422. .weak _nds32_vector_24
  55423. .type _nds32_vector_24, @function
  55424. _nds32_vector_24:
  55425. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid25_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid25_4b.S
  55426. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid25_4b.S 2014-01-02 23:25:22.000000000 +0100
  55427. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid25_4b.S 1970-01-01 01:00:00.000000000 +0100
  55428. @@ -1,34 +0,0 @@
  55429. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55430. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55431. - Contributed by Andes Technology Corporation.
  55432. -
  55433. - This file is part of GCC.
  55434. -
  55435. - GCC is free software; you can redistribute it and/or modify it
  55436. - under the terms of the GNU General Public License as published
  55437. - by the Free Software Foundation; either version 3, or (at your
  55438. - option) any later version.
  55439. -
  55440. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55441. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55442. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55443. - License for more details.
  55444. -
  55445. - Under Section 7 of GPL version 3, you are granted additional
  55446. - permissions described in the GCC Runtime Library Exception, version
  55447. - 3.1, as published by the Free Software Foundation.
  55448. -
  55449. - You should have received a copy of the GNU General Public License and
  55450. - a copy of the GCC Runtime Library Exception along with this program;
  55451. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55452. - <http://www.gnu.org/licenses/>. */
  55453. -
  55454. - .section .nds32_vector.25, "ax"
  55455. - .vec_size 4
  55456. - .align 2
  55457. - .weak _nds32_vector_25_4b
  55458. - .type _nds32_vector_25_4b, @function
  55459. -_nds32_vector_25_4b:
  55460. -1:
  55461. - j 1b
  55462. - .size _nds32_vector_25_4b, .-_nds32_vector_25_4b
  55463. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid25.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid25.S
  55464. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid25.S 2014-01-02 23:25:22.000000000 +0100
  55465. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid25.S 2016-08-08 20:37:53.726588342 +0200
  55466. @@ -1,5 +1,5 @@
  55467. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55468. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55469. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55470. Contributed by Andes Technology Corporation.
  55471. This file is part of GCC.
  55472. @@ -24,8 +24,15 @@
  55473. <http://www.gnu.org/licenses/>. */
  55474. .section .nds32_vector.25, "ax"
  55475. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55476. + /* The vector size is default 4-byte for v3 architecture. */
  55477. + .vec_size 4
  55478. + .align 2
  55479. +#else
  55480. + /* The vector size is default 16-byte for other architectures. */
  55481. .vec_size 16
  55482. .align 4
  55483. +#endif
  55484. .weak _nds32_vector_25
  55485. .type _nds32_vector_25, @function
  55486. _nds32_vector_25:
  55487. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid26_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid26_4b.S
  55488. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid26_4b.S 2014-01-02 23:25:22.000000000 +0100
  55489. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid26_4b.S 1970-01-01 01:00:00.000000000 +0100
  55490. @@ -1,34 +0,0 @@
  55491. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55492. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55493. - Contributed by Andes Technology Corporation.
  55494. -
  55495. - This file is part of GCC.
  55496. -
  55497. - GCC is free software; you can redistribute it and/or modify it
  55498. - under the terms of the GNU General Public License as published
  55499. - by the Free Software Foundation; either version 3, or (at your
  55500. - option) any later version.
  55501. -
  55502. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55503. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55504. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55505. - License for more details.
  55506. -
  55507. - Under Section 7 of GPL version 3, you are granted additional
  55508. - permissions described in the GCC Runtime Library Exception, version
  55509. - 3.1, as published by the Free Software Foundation.
  55510. -
  55511. - You should have received a copy of the GNU General Public License and
  55512. - a copy of the GCC Runtime Library Exception along with this program;
  55513. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55514. - <http://www.gnu.org/licenses/>. */
  55515. -
  55516. - .section .nds32_vector.26, "ax"
  55517. - .vec_size 4
  55518. - .align 2
  55519. - .weak _nds32_vector_26_4b
  55520. - .type _nds32_vector_26_4b, @function
  55521. -_nds32_vector_26_4b:
  55522. -1:
  55523. - j 1b
  55524. - .size _nds32_vector_26_4b, .-_nds32_vector_26_4b
  55525. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid26.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid26.S
  55526. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid26.S 2014-01-02 23:25:22.000000000 +0100
  55527. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid26.S 2016-08-08 20:37:53.730588496 +0200
  55528. @@ -1,5 +1,5 @@
  55529. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55530. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55531. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55532. Contributed by Andes Technology Corporation.
  55533. This file is part of GCC.
  55534. @@ -24,8 +24,15 @@
  55535. <http://www.gnu.org/licenses/>. */
  55536. .section .nds32_vector.26, "ax"
  55537. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55538. + /* The vector size is default 4-byte for v3 architecture. */
  55539. + .vec_size 4
  55540. + .align 2
  55541. +#else
  55542. + /* The vector size is default 16-byte for other architectures. */
  55543. .vec_size 16
  55544. .align 4
  55545. +#endif
  55546. .weak _nds32_vector_26
  55547. .type _nds32_vector_26, @function
  55548. _nds32_vector_26:
  55549. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid27_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid27_4b.S
  55550. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid27_4b.S 2014-01-02 23:25:22.000000000 +0100
  55551. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid27_4b.S 1970-01-01 01:00:00.000000000 +0100
  55552. @@ -1,34 +0,0 @@
  55553. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55554. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55555. - Contributed by Andes Technology Corporation.
  55556. -
  55557. - This file is part of GCC.
  55558. -
  55559. - GCC is free software; you can redistribute it and/or modify it
  55560. - under the terms of the GNU General Public License as published
  55561. - by the Free Software Foundation; either version 3, or (at your
  55562. - option) any later version.
  55563. -
  55564. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55565. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55566. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55567. - License for more details.
  55568. -
  55569. - Under Section 7 of GPL version 3, you are granted additional
  55570. - permissions described in the GCC Runtime Library Exception, version
  55571. - 3.1, as published by the Free Software Foundation.
  55572. -
  55573. - You should have received a copy of the GNU General Public License and
  55574. - a copy of the GCC Runtime Library Exception along with this program;
  55575. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55576. - <http://www.gnu.org/licenses/>. */
  55577. -
  55578. - .section .nds32_vector.27, "ax"
  55579. - .vec_size 4
  55580. - .align 2
  55581. - .weak _nds32_vector_27_4b
  55582. - .type _nds32_vector_27_4b, @function
  55583. -_nds32_vector_27_4b:
  55584. -1:
  55585. - j 1b
  55586. - .size _nds32_vector_27_4b, .-_nds32_vector_27_4b
  55587. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid27.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid27.S
  55588. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid27.S 2014-01-02 23:25:22.000000000 +0100
  55589. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid27.S 2016-08-08 20:37:53.730588496 +0200
  55590. @@ -1,5 +1,5 @@
  55591. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55592. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55593. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55594. Contributed by Andes Technology Corporation.
  55595. This file is part of GCC.
  55596. @@ -24,8 +24,15 @@
  55597. <http://www.gnu.org/licenses/>. */
  55598. .section .nds32_vector.27, "ax"
  55599. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55600. + /* The vector size is default 4-byte for v3 architecture. */
  55601. + .vec_size 4
  55602. + .align 2
  55603. +#else
  55604. + /* The vector size is default 16-byte for other architectures. */
  55605. .vec_size 16
  55606. .align 4
  55607. +#endif
  55608. .weak _nds32_vector_27
  55609. .type _nds32_vector_27, @function
  55610. _nds32_vector_27:
  55611. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid28_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid28_4b.S
  55612. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid28_4b.S 2014-01-02 23:25:22.000000000 +0100
  55613. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid28_4b.S 1970-01-01 01:00:00.000000000 +0100
  55614. @@ -1,34 +0,0 @@
  55615. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55616. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55617. - Contributed by Andes Technology Corporation.
  55618. -
  55619. - This file is part of GCC.
  55620. -
  55621. - GCC is free software; you can redistribute it and/or modify it
  55622. - under the terms of the GNU General Public License as published
  55623. - by the Free Software Foundation; either version 3, or (at your
  55624. - option) any later version.
  55625. -
  55626. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55627. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55628. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55629. - License for more details.
  55630. -
  55631. - Under Section 7 of GPL version 3, you are granted additional
  55632. - permissions described in the GCC Runtime Library Exception, version
  55633. - 3.1, as published by the Free Software Foundation.
  55634. -
  55635. - You should have received a copy of the GNU General Public License and
  55636. - a copy of the GCC Runtime Library Exception along with this program;
  55637. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55638. - <http://www.gnu.org/licenses/>. */
  55639. -
  55640. - .section .nds32_vector.28, "ax"
  55641. - .vec_size 4
  55642. - .align 2
  55643. - .weak _nds32_vector_28_4b
  55644. - .type _nds32_vector_28_4b, @function
  55645. -_nds32_vector_28_4b:
  55646. -1:
  55647. - j 1b
  55648. - .size _nds32_vector_28_4b, .-_nds32_vector_28_4b
  55649. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid28.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid28.S
  55650. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid28.S 2014-01-02 23:25:22.000000000 +0100
  55651. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid28.S 2016-08-08 20:37:53.730588496 +0200
  55652. @@ -1,5 +1,5 @@
  55653. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55654. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55655. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55656. Contributed by Andes Technology Corporation.
  55657. This file is part of GCC.
  55658. @@ -24,8 +24,15 @@
  55659. <http://www.gnu.org/licenses/>. */
  55660. .section .nds32_vector.28, "ax"
  55661. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55662. + /* The vector size is default 4-byte for v3 architecture. */
  55663. + .vec_size 4
  55664. + .align 2
  55665. +#else
  55666. + /* The vector size is default 16-byte for other architectures. */
  55667. .vec_size 16
  55668. .align 4
  55669. +#endif
  55670. .weak _nds32_vector_28
  55671. .type _nds32_vector_28, @function
  55672. _nds32_vector_28:
  55673. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid29_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid29_4b.S
  55674. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid29_4b.S 2014-01-02 23:25:22.000000000 +0100
  55675. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid29_4b.S 1970-01-01 01:00:00.000000000 +0100
  55676. @@ -1,34 +0,0 @@
  55677. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55678. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55679. - Contributed by Andes Technology Corporation.
  55680. -
  55681. - This file is part of GCC.
  55682. -
  55683. - GCC is free software; you can redistribute it and/or modify it
  55684. - under the terms of the GNU General Public License as published
  55685. - by the Free Software Foundation; either version 3, or (at your
  55686. - option) any later version.
  55687. -
  55688. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55689. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55690. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55691. - License for more details.
  55692. -
  55693. - Under Section 7 of GPL version 3, you are granted additional
  55694. - permissions described in the GCC Runtime Library Exception, version
  55695. - 3.1, as published by the Free Software Foundation.
  55696. -
  55697. - You should have received a copy of the GNU General Public License and
  55698. - a copy of the GCC Runtime Library Exception along with this program;
  55699. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55700. - <http://www.gnu.org/licenses/>. */
  55701. -
  55702. - .section .nds32_vector.29, "ax"
  55703. - .vec_size 4
  55704. - .align 2
  55705. - .weak _nds32_vector_29_4b
  55706. - .type _nds32_vector_29_4b, @function
  55707. -_nds32_vector_29_4b:
  55708. -1:
  55709. - j 1b
  55710. - .size _nds32_vector_29_4b, .-_nds32_vector_29_4b
  55711. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid29.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid29.S
  55712. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid29.S 2014-01-02 23:25:22.000000000 +0100
  55713. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid29.S 2016-08-08 20:37:53.730588496 +0200
  55714. @@ -1,5 +1,5 @@
  55715. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55716. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55717. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55718. Contributed by Andes Technology Corporation.
  55719. This file is part of GCC.
  55720. @@ -24,8 +24,15 @@
  55721. <http://www.gnu.org/licenses/>. */
  55722. .section .nds32_vector.29, "ax"
  55723. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55724. + /* The vector size is default 4-byte for v3 architecture. */
  55725. + .vec_size 4
  55726. + .align 2
  55727. +#else
  55728. + /* The vector size is default 16-byte for other architectures. */
  55729. .vec_size 16
  55730. .align 4
  55731. +#endif
  55732. .weak _nds32_vector_29
  55733. .type _nds32_vector_29, @function
  55734. _nds32_vector_29:
  55735. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid30_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid30_4b.S
  55736. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid30_4b.S 2014-01-02 23:25:22.000000000 +0100
  55737. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid30_4b.S 1970-01-01 01:00:00.000000000 +0100
  55738. @@ -1,34 +0,0 @@
  55739. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55740. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55741. - Contributed by Andes Technology Corporation.
  55742. -
  55743. - This file is part of GCC.
  55744. -
  55745. - GCC is free software; you can redistribute it and/or modify it
  55746. - under the terms of the GNU General Public License as published
  55747. - by the Free Software Foundation; either version 3, or (at your
  55748. - option) any later version.
  55749. -
  55750. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55751. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55752. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55753. - License for more details.
  55754. -
  55755. - Under Section 7 of GPL version 3, you are granted additional
  55756. - permissions described in the GCC Runtime Library Exception, version
  55757. - 3.1, as published by the Free Software Foundation.
  55758. -
  55759. - You should have received a copy of the GNU General Public License and
  55760. - a copy of the GCC Runtime Library Exception along with this program;
  55761. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55762. - <http://www.gnu.org/licenses/>. */
  55763. -
  55764. - .section .nds32_vector.30, "ax"
  55765. - .vec_size 4
  55766. - .align 2
  55767. - .weak _nds32_vector_30_4b
  55768. - .type _nds32_vector_30_4b, @function
  55769. -_nds32_vector_30_4b:
  55770. -1:
  55771. - j 1b
  55772. - .size _nds32_vector_30_4b, .-_nds32_vector_30_4b
  55773. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid30.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid30.S
  55774. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid30.S 2014-01-02 23:25:22.000000000 +0100
  55775. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid30.S 2016-08-08 20:37:53.730588496 +0200
  55776. @@ -1,5 +1,5 @@
  55777. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55778. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55779. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55780. Contributed by Andes Technology Corporation.
  55781. This file is part of GCC.
  55782. @@ -24,8 +24,15 @@
  55783. <http://www.gnu.org/licenses/>. */
  55784. .section .nds32_vector.30, "ax"
  55785. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55786. + /* The vector size is default 4-byte for v3 architecture. */
  55787. + .vec_size 4
  55788. + .align 2
  55789. +#else
  55790. + /* The vector size is default 16-byte for other architectures. */
  55791. .vec_size 16
  55792. .align 4
  55793. +#endif
  55794. .weak _nds32_vector_30
  55795. .type _nds32_vector_30, @function
  55796. _nds32_vector_30:
  55797. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid31_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid31_4b.S
  55798. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid31_4b.S 2014-01-02 23:25:22.000000000 +0100
  55799. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid31_4b.S 1970-01-01 01:00:00.000000000 +0100
  55800. @@ -1,34 +0,0 @@
  55801. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55802. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55803. - Contributed by Andes Technology Corporation.
  55804. -
  55805. - This file is part of GCC.
  55806. -
  55807. - GCC is free software; you can redistribute it and/or modify it
  55808. - under the terms of the GNU General Public License as published
  55809. - by the Free Software Foundation; either version 3, or (at your
  55810. - option) any later version.
  55811. -
  55812. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55813. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55814. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55815. - License for more details.
  55816. -
  55817. - Under Section 7 of GPL version 3, you are granted additional
  55818. - permissions described in the GCC Runtime Library Exception, version
  55819. - 3.1, as published by the Free Software Foundation.
  55820. -
  55821. - You should have received a copy of the GNU General Public License and
  55822. - a copy of the GCC Runtime Library Exception along with this program;
  55823. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55824. - <http://www.gnu.org/licenses/>. */
  55825. -
  55826. - .section .nds32_vector.31, "ax"
  55827. - .vec_size 4
  55828. - .align 2
  55829. - .weak _nds32_vector_31_4b
  55830. - .type _nds32_vector_31_4b, @function
  55831. -_nds32_vector_31_4b:
  55832. -1:
  55833. - j 1b
  55834. - .size _nds32_vector_31_4b, .-_nds32_vector_31_4b
  55835. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid31.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid31.S
  55836. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid31.S 2014-01-02 23:25:22.000000000 +0100
  55837. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid31.S 2016-08-08 20:37:53.730588496 +0200
  55838. @@ -1,5 +1,5 @@
  55839. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55840. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55841. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55842. Contributed by Andes Technology Corporation.
  55843. This file is part of GCC.
  55844. @@ -24,8 +24,15 @@
  55845. <http://www.gnu.org/licenses/>. */
  55846. .section .nds32_vector.31, "ax"
  55847. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55848. + /* The vector size is default 4-byte for v3 architecture. */
  55849. + .vec_size 4
  55850. + .align 2
  55851. +#else
  55852. + /* The vector size is default 16-byte for other architectures. */
  55853. .vec_size 16
  55854. .align 4
  55855. +#endif
  55856. .weak _nds32_vector_31
  55857. .type _nds32_vector_31, @function
  55858. _nds32_vector_31:
  55859. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid32_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid32_4b.S
  55860. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid32_4b.S 2014-01-02 23:25:22.000000000 +0100
  55861. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid32_4b.S 1970-01-01 01:00:00.000000000 +0100
  55862. @@ -1,34 +0,0 @@
  55863. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55864. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55865. - Contributed by Andes Technology Corporation.
  55866. -
  55867. - This file is part of GCC.
  55868. -
  55869. - GCC is free software; you can redistribute it and/or modify it
  55870. - under the terms of the GNU General Public License as published
  55871. - by the Free Software Foundation; either version 3, or (at your
  55872. - option) any later version.
  55873. -
  55874. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55875. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55876. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55877. - License for more details.
  55878. -
  55879. - Under Section 7 of GPL version 3, you are granted additional
  55880. - permissions described in the GCC Runtime Library Exception, version
  55881. - 3.1, as published by the Free Software Foundation.
  55882. -
  55883. - You should have received a copy of the GNU General Public License and
  55884. - a copy of the GCC Runtime Library Exception along with this program;
  55885. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55886. - <http://www.gnu.org/licenses/>. */
  55887. -
  55888. - .section .nds32_vector.32, "ax"
  55889. - .vec_size 4
  55890. - .align 2
  55891. - .weak _nds32_vector_32_4b
  55892. - .type _nds32_vector_32_4b, @function
  55893. -_nds32_vector_32_4b:
  55894. -1:
  55895. - j 1b
  55896. - .size _nds32_vector_32_4b, .-_nds32_vector_32_4b
  55897. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid32.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid32.S
  55898. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid32.S 2014-01-02 23:25:22.000000000 +0100
  55899. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid32.S 2016-08-08 20:37:53.730588496 +0200
  55900. @@ -1,5 +1,5 @@
  55901. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55902. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55903. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55904. Contributed by Andes Technology Corporation.
  55905. This file is part of GCC.
  55906. @@ -24,8 +24,15 @@
  55907. <http://www.gnu.org/licenses/>. */
  55908. .section .nds32_vector.32, "ax"
  55909. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55910. + /* The vector size is default 4-byte for v3 architecture. */
  55911. + .vec_size 4
  55912. + .align 2
  55913. +#else
  55914. + /* The vector size is default 16-byte for other architectures. */
  55915. .vec_size 16
  55916. .align 4
  55917. +#endif
  55918. .weak _nds32_vector_32
  55919. .type _nds32_vector_32, @function
  55920. _nds32_vector_32:
  55921. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid33_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid33_4b.S
  55922. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid33_4b.S 2014-01-02 23:25:22.000000000 +0100
  55923. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid33_4b.S 1970-01-01 01:00:00.000000000 +0100
  55924. @@ -1,34 +0,0 @@
  55925. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55926. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55927. - Contributed by Andes Technology Corporation.
  55928. -
  55929. - This file is part of GCC.
  55930. -
  55931. - GCC is free software; you can redistribute it and/or modify it
  55932. - under the terms of the GNU General Public License as published
  55933. - by the Free Software Foundation; either version 3, or (at your
  55934. - option) any later version.
  55935. -
  55936. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55937. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  55938. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  55939. - License for more details.
  55940. -
  55941. - Under Section 7 of GPL version 3, you are granted additional
  55942. - permissions described in the GCC Runtime Library Exception, version
  55943. - 3.1, as published by the Free Software Foundation.
  55944. -
  55945. - You should have received a copy of the GNU General Public License and
  55946. - a copy of the GCC Runtime Library Exception along with this program;
  55947. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  55948. - <http://www.gnu.org/licenses/>. */
  55949. -
  55950. - .section .nds32_vector.33, "ax"
  55951. - .vec_size 4
  55952. - .align 2
  55953. - .weak _nds32_vector_33_4b
  55954. - .type _nds32_vector_33_4b, @function
  55955. -_nds32_vector_33_4b:
  55956. -1:
  55957. - j 1b
  55958. - .size _nds32_vector_33_4b, .-_nds32_vector_33_4b
  55959. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid33.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid33.S
  55960. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid33.S 2014-01-02 23:25:22.000000000 +0100
  55961. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid33.S 2016-08-08 20:37:53.730588496 +0200
  55962. @@ -1,5 +1,5 @@
  55963. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55964. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55965. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  55966. Contributed by Andes Technology Corporation.
  55967. This file is part of GCC.
  55968. @@ -24,8 +24,15 @@
  55969. <http://www.gnu.org/licenses/>. */
  55970. .section .nds32_vector.33, "ax"
  55971. +#if __NDS32_ISR_VECTOR_SIZE_4__
  55972. + /* The vector size is default 4-byte for v3 architecture. */
  55973. + .vec_size 4
  55974. + .align 2
  55975. +#else
  55976. + /* The vector size is default 16-byte for other architectures. */
  55977. .vec_size 16
  55978. .align 4
  55979. +#endif
  55980. .weak _nds32_vector_33
  55981. .type _nds32_vector_33, @function
  55982. _nds32_vector_33:
  55983. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid34_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid34_4b.S
  55984. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid34_4b.S 2014-01-02 23:25:22.000000000 +0100
  55985. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid34_4b.S 1970-01-01 01:00:00.000000000 +0100
  55986. @@ -1,34 +0,0 @@
  55987. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  55988. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  55989. - Contributed by Andes Technology Corporation.
  55990. -
  55991. - This file is part of GCC.
  55992. -
  55993. - GCC is free software; you can redistribute it and/or modify it
  55994. - under the terms of the GNU General Public License as published
  55995. - by the Free Software Foundation; either version 3, or (at your
  55996. - option) any later version.
  55997. -
  55998. - GCC is distributed in the hope that it will be useful, but WITHOUT
  55999. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56000. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56001. - License for more details.
  56002. -
  56003. - Under Section 7 of GPL version 3, you are granted additional
  56004. - permissions described in the GCC Runtime Library Exception, version
  56005. - 3.1, as published by the Free Software Foundation.
  56006. -
  56007. - You should have received a copy of the GNU General Public License and
  56008. - a copy of the GCC Runtime Library Exception along with this program;
  56009. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56010. - <http://www.gnu.org/licenses/>. */
  56011. -
  56012. - .section .nds32_vector.34, "ax"
  56013. - .vec_size 4
  56014. - .align 2
  56015. - .weak _nds32_vector_34_4b
  56016. - .type _nds32_vector_34_4b, @function
  56017. -_nds32_vector_34_4b:
  56018. -1:
  56019. - j 1b
  56020. - .size _nds32_vector_34_4b, .-_nds32_vector_34_4b
  56021. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid34.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid34.S
  56022. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid34.S 2014-01-02 23:25:22.000000000 +0100
  56023. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid34.S 2016-08-08 20:37:53.730588496 +0200
  56024. @@ -1,5 +1,5 @@
  56025. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56026. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56027. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56028. Contributed by Andes Technology Corporation.
  56029. This file is part of GCC.
  56030. @@ -24,8 +24,15 @@
  56031. <http://www.gnu.org/licenses/>. */
  56032. .section .nds32_vector.34, "ax"
  56033. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56034. + /* The vector size is default 4-byte for v3 architecture. */
  56035. + .vec_size 4
  56036. + .align 2
  56037. +#else
  56038. + /* The vector size is default 16-byte for other architectures. */
  56039. .vec_size 16
  56040. .align 4
  56041. +#endif
  56042. .weak _nds32_vector_34
  56043. .type _nds32_vector_34, @function
  56044. _nds32_vector_34:
  56045. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid35_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid35_4b.S
  56046. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid35_4b.S 2014-01-02 23:25:22.000000000 +0100
  56047. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid35_4b.S 1970-01-01 01:00:00.000000000 +0100
  56048. @@ -1,34 +0,0 @@
  56049. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56050. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56051. - Contributed by Andes Technology Corporation.
  56052. -
  56053. - This file is part of GCC.
  56054. -
  56055. - GCC is free software; you can redistribute it and/or modify it
  56056. - under the terms of the GNU General Public License as published
  56057. - by the Free Software Foundation; either version 3, or (at your
  56058. - option) any later version.
  56059. -
  56060. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56061. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56062. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56063. - License for more details.
  56064. -
  56065. - Under Section 7 of GPL version 3, you are granted additional
  56066. - permissions described in the GCC Runtime Library Exception, version
  56067. - 3.1, as published by the Free Software Foundation.
  56068. -
  56069. - You should have received a copy of the GNU General Public License and
  56070. - a copy of the GCC Runtime Library Exception along with this program;
  56071. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56072. - <http://www.gnu.org/licenses/>. */
  56073. -
  56074. - .section .nds32_vector.35, "ax"
  56075. - .vec_size 4
  56076. - .align 2
  56077. - .weak _nds32_vector_35_4b
  56078. - .type _nds32_vector_35_4b, @function
  56079. -_nds32_vector_35_4b:
  56080. -1:
  56081. - j 1b
  56082. - .size _nds32_vector_35_4b, .-_nds32_vector_35_4b
  56083. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid35.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid35.S
  56084. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid35.S 2014-01-02 23:25:22.000000000 +0100
  56085. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid35.S 2016-08-08 20:37:53.730588496 +0200
  56086. @@ -1,5 +1,5 @@
  56087. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56088. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56089. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56090. Contributed by Andes Technology Corporation.
  56091. This file is part of GCC.
  56092. @@ -24,8 +24,15 @@
  56093. <http://www.gnu.org/licenses/>. */
  56094. .section .nds32_vector.35, "ax"
  56095. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56096. + /* The vector size is default 4-byte for v3 architecture. */
  56097. + .vec_size 4
  56098. + .align 2
  56099. +#else
  56100. + /* The vector size is default 16-byte for other architectures. */
  56101. .vec_size 16
  56102. .align 4
  56103. +#endif
  56104. .weak _nds32_vector_35
  56105. .type _nds32_vector_35, @function
  56106. _nds32_vector_35:
  56107. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid36_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid36_4b.S
  56108. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid36_4b.S 2014-01-02 23:25:22.000000000 +0100
  56109. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid36_4b.S 1970-01-01 01:00:00.000000000 +0100
  56110. @@ -1,34 +0,0 @@
  56111. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56112. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56113. - Contributed by Andes Technology Corporation.
  56114. -
  56115. - This file is part of GCC.
  56116. -
  56117. - GCC is free software; you can redistribute it and/or modify it
  56118. - under the terms of the GNU General Public License as published
  56119. - by the Free Software Foundation; either version 3, or (at your
  56120. - option) any later version.
  56121. -
  56122. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56123. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56124. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56125. - License for more details.
  56126. -
  56127. - Under Section 7 of GPL version 3, you are granted additional
  56128. - permissions described in the GCC Runtime Library Exception, version
  56129. - 3.1, as published by the Free Software Foundation.
  56130. -
  56131. - You should have received a copy of the GNU General Public License and
  56132. - a copy of the GCC Runtime Library Exception along with this program;
  56133. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56134. - <http://www.gnu.org/licenses/>. */
  56135. -
  56136. - .section .nds32_vector.36, "ax"
  56137. - .vec_size 4
  56138. - .align 2
  56139. - .weak _nds32_vector_36_4b
  56140. - .type _nds32_vector_36_4b, @function
  56141. -_nds32_vector_36_4b:
  56142. -1:
  56143. - j 1b
  56144. - .size _nds32_vector_36_4b, .-_nds32_vector_36_4b
  56145. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid36.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid36.S
  56146. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid36.S 2014-01-02 23:25:22.000000000 +0100
  56147. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid36.S 2016-08-08 20:37:53.730588496 +0200
  56148. @@ -1,5 +1,5 @@
  56149. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56150. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56151. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56152. Contributed by Andes Technology Corporation.
  56153. This file is part of GCC.
  56154. @@ -24,8 +24,15 @@
  56155. <http://www.gnu.org/licenses/>. */
  56156. .section .nds32_vector.36, "ax"
  56157. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56158. + /* The vector size is default 4-byte for v3 architecture. */
  56159. + .vec_size 4
  56160. + .align 2
  56161. +#else
  56162. + /* The vector size is default 16-byte for other architectures. */
  56163. .vec_size 16
  56164. .align 4
  56165. +#endif
  56166. .weak _nds32_vector_36
  56167. .type _nds32_vector_36, @function
  56168. _nds32_vector_36:
  56169. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid37_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid37_4b.S
  56170. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid37_4b.S 2014-01-02 23:25:22.000000000 +0100
  56171. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid37_4b.S 1970-01-01 01:00:00.000000000 +0100
  56172. @@ -1,34 +0,0 @@
  56173. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56174. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56175. - Contributed by Andes Technology Corporation.
  56176. -
  56177. - This file is part of GCC.
  56178. -
  56179. - GCC is free software; you can redistribute it and/or modify it
  56180. - under the terms of the GNU General Public License as published
  56181. - by the Free Software Foundation; either version 3, or (at your
  56182. - option) any later version.
  56183. -
  56184. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56185. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56186. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56187. - License for more details.
  56188. -
  56189. - Under Section 7 of GPL version 3, you are granted additional
  56190. - permissions described in the GCC Runtime Library Exception, version
  56191. - 3.1, as published by the Free Software Foundation.
  56192. -
  56193. - You should have received a copy of the GNU General Public License and
  56194. - a copy of the GCC Runtime Library Exception along with this program;
  56195. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56196. - <http://www.gnu.org/licenses/>. */
  56197. -
  56198. - .section .nds32_vector.37, "ax"
  56199. - .vec_size 4
  56200. - .align 2
  56201. - .weak _nds32_vector_37_4b
  56202. - .type _nds32_vector_37_4b, @function
  56203. -_nds32_vector_37_4b:
  56204. -1:
  56205. - j 1b
  56206. - .size _nds32_vector_37_4b, .-_nds32_vector_37_4b
  56207. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid37.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid37.S
  56208. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid37.S 2014-01-02 23:25:22.000000000 +0100
  56209. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid37.S 2016-08-08 20:37:53.734588650 +0200
  56210. @@ -1,5 +1,5 @@
  56211. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56212. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56213. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56214. Contributed by Andes Technology Corporation.
  56215. This file is part of GCC.
  56216. @@ -24,8 +24,15 @@
  56217. <http://www.gnu.org/licenses/>. */
  56218. .section .nds32_vector.37, "ax"
  56219. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56220. + /* The vector size is default 4-byte for v3 architecture. */
  56221. + .vec_size 4
  56222. + .align 2
  56223. +#else
  56224. + /* The vector size is default 16-byte for other architectures. */
  56225. .vec_size 16
  56226. .align 4
  56227. +#endif
  56228. .weak _nds32_vector_37
  56229. .type _nds32_vector_37, @function
  56230. _nds32_vector_37:
  56231. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid38_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid38_4b.S
  56232. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid38_4b.S 2014-01-02 23:25:22.000000000 +0100
  56233. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid38_4b.S 1970-01-01 01:00:00.000000000 +0100
  56234. @@ -1,34 +0,0 @@
  56235. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56236. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56237. - Contributed by Andes Technology Corporation.
  56238. -
  56239. - This file is part of GCC.
  56240. -
  56241. - GCC is free software; you can redistribute it and/or modify it
  56242. - under the terms of the GNU General Public License as published
  56243. - by the Free Software Foundation; either version 3, or (at your
  56244. - option) any later version.
  56245. -
  56246. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56247. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56248. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56249. - License for more details.
  56250. -
  56251. - Under Section 7 of GPL version 3, you are granted additional
  56252. - permissions described in the GCC Runtime Library Exception, version
  56253. - 3.1, as published by the Free Software Foundation.
  56254. -
  56255. - You should have received a copy of the GNU General Public License and
  56256. - a copy of the GCC Runtime Library Exception along with this program;
  56257. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56258. - <http://www.gnu.org/licenses/>. */
  56259. -
  56260. - .section .nds32_vector.38, "ax"
  56261. - .vec_size 4
  56262. - .align 2
  56263. - .weak _nds32_vector_38_4b
  56264. - .type _nds32_vector_38_4b, @function
  56265. -_nds32_vector_38_4b:
  56266. -1:
  56267. - j 1b
  56268. - .size _nds32_vector_38_4b, .-_nds32_vector_38_4b
  56269. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid38.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid38.S
  56270. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid38.S 2014-01-02 23:25:22.000000000 +0100
  56271. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid38.S 2016-08-08 20:37:53.734588650 +0200
  56272. @@ -1,5 +1,5 @@
  56273. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56274. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56275. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56276. Contributed by Andes Technology Corporation.
  56277. This file is part of GCC.
  56278. @@ -24,8 +24,15 @@
  56279. <http://www.gnu.org/licenses/>. */
  56280. .section .nds32_vector.38, "ax"
  56281. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56282. + /* The vector size is default 4-byte for v3 architecture. */
  56283. + .vec_size 4
  56284. + .align 2
  56285. +#else
  56286. + /* The vector size is default 16-byte for other architectures. */
  56287. .vec_size 16
  56288. .align 4
  56289. +#endif
  56290. .weak _nds32_vector_38
  56291. .type _nds32_vector_38, @function
  56292. _nds32_vector_38:
  56293. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid39_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid39_4b.S
  56294. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid39_4b.S 2014-01-02 23:25:22.000000000 +0100
  56295. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid39_4b.S 1970-01-01 01:00:00.000000000 +0100
  56296. @@ -1,34 +0,0 @@
  56297. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56298. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56299. - Contributed by Andes Technology Corporation.
  56300. -
  56301. - This file is part of GCC.
  56302. -
  56303. - GCC is free software; you can redistribute it and/or modify it
  56304. - under the terms of the GNU General Public License as published
  56305. - by the Free Software Foundation; either version 3, or (at your
  56306. - option) any later version.
  56307. -
  56308. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56309. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56310. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56311. - License for more details.
  56312. -
  56313. - Under Section 7 of GPL version 3, you are granted additional
  56314. - permissions described in the GCC Runtime Library Exception, version
  56315. - 3.1, as published by the Free Software Foundation.
  56316. -
  56317. - You should have received a copy of the GNU General Public License and
  56318. - a copy of the GCC Runtime Library Exception along with this program;
  56319. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56320. - <http://www.gnu.org/licenses/>. */
  56321. -
  56322. - .section .nds32_vector.39, "ax"
  56323. - .vec_size 4
  56324. - .align 2
  56325. - .weak _nds32_vector_39_4b
  56326. - .type _nds32_vector_39_4b, @function
  56327. -_nds32_vector_39_4b:
  56328. -1:
  56329. - j 1b
  56330. - .size _nds32_vector_39_4b, .-_nds32_vector_39_4b
  56331. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid39.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid39.S
  56332. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid39.S 2014-01-02 23:25:22.000000000 +0100
  56333. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid39.S 2016-08-08 20:37:53.734588650 +0200
  56334. @@ -1,5 +1,5 @@
  56335. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56336. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56337. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56338. Contributed by Andes Technology Corporation.
  56339. This file is part of GCC.
  56340. @@ -24,8 +24,15 @@
  56341. <http://www.gnu.org/licenses/>. */
  56342. .section .nds32_vector.39, "ax"
  56343. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56344. + /* The vector size is default 4-byte for v3 architecture. */
  56345. + .vec_size 4
  56346. + .align 2
  56347. +#else
  56348. + /* The vector size is default 16-byte for other architectures. */
  56349. .vec_size 16
  56350. .align 4
  56351. +#endif
  56352. .weak _nds32_vector_39
  56353. .type _nds32_vector_39, @function
  56354. _nds32_vector_39:
  56355. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid40_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid40_4b.S
  56356. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid40_4b.S 2014-01-02 23:25:22.000000000 +0100
  56357. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid40_4b.S 1970-01-01 01:00:00.000000000 +0100
  56358. @@ -1,34 +0,0 @@
  56359. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56360. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56361. - Contributed by Andes Technology Corporation.
  56362. -
  56363. - This file is part of GCC.
  56364. -
  56365. - GCC is free software; you can redistribute it and/or modify it
  56366. - under the terms of the GNU General Public License as published
  56367. - by the Free Software Foundation; either version 3, or (at your
  56368. - option) any later version.
  56369. -
  56370. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56371. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56372. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56373. - License for more details.
  56374. -
  56375. - Under Section 7 of GPL version 3, you are granted additional
  56376. - permissions described in the GCC Runtime Library Exception, version
  56377. - 3.1, as published by the Free Software Foundation.
  56378. -
  56379. - You should have received a copy of the GNU General Public License and
  56380. - a copy of the GCC Runtime Library Exception along with this program;
  56381. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56382. - <http://www.gnu.org/licenses/>. */
  56383. -
  56384. - .section .nds32_vector.40, "ax"
  56385. - .vec_size 4
  56386. - .align 2
  56387. - .weak _nds32_vector_40_4b
  56388. - .type _nds32_vector_40_4b, @function
  56389. -_nds32_vector_40_4b:
  56390. -1:
  56391. - j 1b
  56392. - .size _nds32_vector_40_4b, .-_nds32_vector_40_4b
  56393. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid40.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid40.S
  56394. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid40.S 2014-01-02 23:25:22.000000000 +0100
  56395. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid40.S 2016-08-08 20:37:53.734588650 +0200
  56396. @@ -1,5 +1,5 @@
  56397. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56398. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56399. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56400. Contributed by Andes Technology Corporation.
  56401. This file is part of GCC.
  56402. @@ -24,8 +24,15 @@
  56403. <http://www.gnu.org/licenses/>. */
  56404. .section .nds32_vector.40, "ax"
  56405. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56406. + /* The vector size is default 4-byte for v3 architecture. */
  56407. + .vec_size 4
  56408. + .align 2
  56409. +#else
  56410. + /* The vector size is default 16-byte for other architectures. */
  56411. .vec_size 16
  56412. .align 4
  56413. +#endif
  56414. .weak _nds32_vector_40
  56415. .type _nds32_vector_40, @function
  56416. _nds32_vector_40:
  56417. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid41_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid41_4b.S
  56418. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid41_4b.S 2014-01-02 23:25:22.000000000 +0100
  56419. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid41_4b.S 1970-01-01 01:00:00.000000000 +0100
  56420. @@ -1,34 +0,0 @@
  56421. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56422. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56423. - Contributed by Andes Technology Corporation.
  56424. -
  56425. - This file is part of GCC.
  56426. -
  56427. - GCC is free software; you can redistribute it and/or modify it
  56428. - under the terms of the GNU General Public License as published
  56429. - by the Free Software Foundation; either version 3, or (at your
  56430. - option) any later version.
  56431. -
  56432. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56433. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56434. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56435. - License for more details.
  56436. -
  56437. - Under Section 7 of GPL version 3, you are granted additional
  56438. - permissions described in the GCC Runtime Library Exception, version
  56439. - 3.1, as published by the Free Software Foundation.
  56440. -
  56441. - You should have received a copy of the GNU General Public License and
  56442. - a copy of the GCC Runtime Library Exception along with this program;
  56443. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56444. - <http://www.gnu.org/licenses/>. */
  56445. -
  56446. - .section .nds32_vector.41, "ax"
  56447. - .vec_size 4
  56448. - .align 2
  56449. - .weak _nds32_vector_41_4b
  56450. - .type _nds32_vector_41_4b, @function
  56451. -_nds32_vector_41_4b:
  56452. -1:
  56453. - j 1b
  56454. - .size _nds32_vector_41_4b, .-_nds32_vector_41_4b
  56455. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid41.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid41.S
  56456. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid41.S 2014-01-02 23:25:22.000000000 +0100
  56457. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid41.S 2016-08-08 20:37:53.734588650 +0200
  56458. @@ -1,5 +1,5 @@
  56459. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56460. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56461. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56462. Contributed by Andes Technology Corporation.
  56463. This file is part of GCC.
  56464. @@ -24,8 +24,15 @@
  56465. <http://www.gnu.org/licenses/>. */
  56466. .section .nds32_vector.41, "ax"
  56467. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56468. + /* The vector size is default 4-byte for v3 architecture. */
  56469. + .vec_size 4
  56470. + .align 2
  56471. +#else
  56472. + /* The vector size is default 16-byte for other architectures. */
  56473. .vec_size 16
  56474. .align 4
  56475. +#endif
  56476. .weak _nds32_vector_41
  56477. .type _nds32_vector_41, @function
  56478. _nds32_vector_41:
  56479. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid42_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid42_4b.S
  56480. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid42_4b.S 2014-01-02 23:25:22.000000000 +0100
  56481. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid42_4b.S 1970-01-01 01:00:00.000000000 +0100
  56482. @@ -1,34 +0,0 @@
  56483. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56484. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56485. - Contributed by Andes Technology Corporation.
  56486. -
  56487. - This file is part of GCC.
  56488. -
  56489. - GCC is free software; you can redistribute it and/or modify it
  56490. - under the terms of the GNU General Public License as published
  56491. - by the Free Software Foundation; either version 3, or (at your
  56492. - option) any later version.
  56493. -
  56494. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56495. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56496. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56497. - License for more details.
  56498. -
  56499. - Under Section 7 of GPL version 3, you are granted additional
  56500. - permissions described in the GCC Runtime Library Exception, version
  56501. - 3.1, as published by the Free Software Foundation.
  56502. -
  56503. - You should have received a copy of the GNU General Public License and
  56504. - a copy of the GCC Runtime Library Exception along with this program;
  56505. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56506. - <http://www.gnu.org/licenses/>. */
  56507. -
  56508. - .section .nds32_vector.42, "ax"
  56509. - .vec_size 4
  56510. - .align 2
  56511. - .weak _nds32_vector_42_4b
  56512. - .type _nds32_vector_42_4b, @function
  56513. -_nds32_vector_42_4b:
  56514. -1:
  56515. - j 1b
  56516. - .size _nds32_vector_42_4b, .-_nds32_vector_42_4b
  56517. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid42.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid42.S
  56518. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid42.S 2014-01-02 23:25:22.000000000 +0100
  56519. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid42.S 2016-08-08 20:37:53.734588650 +0200
  56520. @@ -1,5 +1,5 @@
  56521. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56522. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56523. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56524. Contributed by Andes Technology Corporation.
  56525. This file is part of GCC.
  56526. @@ -24,8 +24,15 @@
  56527. <http://www.gnu.org/licenses/>. */
  56528. .section .nds32_vector.42, "ax"
  56529. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56530. + /* The vector size is default 4-byte for v3 architecture. */
  56531. + .vec_size 4
  56532. + .align 2
  56533. +#else
  56534. + /* The vector size is default 16-byte for other architectures. */
  56535. .vec_size 16
  56536. .align 4
  56537. +#endif
  56538. .weak _nds32_vector_42
  56539. .type _nds32_vector_42, @function
  56540. _nds32_vector_42:
  56541. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid43_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid43_4b.S
  56542. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid43_4b.S 2014-01-02 23:25:22.000000000 +0100
  56543. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid43_4b.S 1970-01-01 01:00:00.000000000 +0100
  56544. @@ -1,34 +0,0 @@
  56545. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56546. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56547. - Contributed by Andes Technology Corporation.
  56548. -
  56549. - This file is part of GCC.
  56550. -
  56551. - GCC is free software; you can redistribute it and/or modify it
  56552. - under the terms of the GNU General Public License as published
  56553. - by the Free Software Foundation; either version 3, or (at your
  56554. - option) any later version.
  56555. -
  56556. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56557. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56558. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56559. - License for more details.
  56560. -
  56561. - Under Section 7 of GPL version 3, you are granted additional
  56562. - permissions described in the GCC Runtime Library Exception, version
  56563. - 3.1, as published by the Free Software Foundation.
  56564. -
  56565. - You should have received a copy of the GNU General Public License and
  56566. - a copy of the GCC Runtime Library Exception along with this program;
  56567. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56568. - <http://www.gnu.org/licenses/>. */
  56569. -
  56570. - .section .nds32_vector.43, "ax"
  56571. - .vec_size 4
  56572. - .align 2
  56573. - .weak _nds32_vector_43_4b
  56574. - .type _nds32_vector_43_4b, @function
  56575. -_nds32_vector_43_4b:
  56576. -1:
  56577. - j 1b
  56578. - .size _nds32_vector_43_4b, .-_nds32_vector_43_4b
  56579. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid43.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid43.S
  56580. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid43.S 2014-01-02 23:25:22.000000000 +0100
  56581. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid43.S 2016-08-08 20:37:53.734588650 +0200
  56582. @@ -1,5 +1,5 @@
  56583. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56584. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56585. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56586. Contributed by Andes Technology Corporation.
  56587. This file is part of GCC.
  56588. @@ -24,8 +24,15 @@
  56589. <http://www.gnu.org/licenses/>. */
  56590. .section .nds32_vector.43, "ax"
  56591. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56592. + /* The vector size is default 4-byte for v3 architecture. */
  56593. + .vec_size 4
  56594. + .align 2
  56595. +#else
  56596. + /* The vector size is default 16-byte for other architectures. */
  56597. .vec_size 16
  56598. .align 4
  56599. +#endif
  56600. .weak _nds32_vector_43
  56601. .type _nds32_vector_43, @function
  56602. _nds32_vector_43:
  56603. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid44_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid44_4b.S
  56604. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid44_4b.S 2014-01-02 23:25:22.000000000 +0100
  56605. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid44_4b.S 1970-01-01 01:00:00.000000000 +0100
  56606. @@ -1,34 +0,0 @@
  56607. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56608. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56609. - Contributed by Andes Technology Corporation.
  56610. -
  56611. - This file is part of GCC.
  56612. -
  56613. - GCC is free software; you can redistribute it and/or modify it
  56614. - under the terms of the GNU General Public License as published
  56615. - by the Free Software Foundation; either version 3, or (at your
  56616. - option) any later version.
  56617. -
  56618. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56619. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56620. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56621. - License for more details.
  56622. -
  56623. - Under Section 7 of GPL version 3, you are granted additional
  56624. - permissions described in the GCC Runtime Library Exception, version
  56625. - 3.1, as published by the Free Software Foundation.
  56626. -
  56627. - You should have received a copy of the GNU General Public License and
  56628. - a copy of the GCC Runtime Library Exception along with this program;
  56629. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56630. - <http://www.gnu.org/licenses/>. */
  56631. -
  56632. - .section .nds32_vector.44, "ax"
  56633. - .vec_size 4
  56634. - .align 2
  56635. - .weak _nds32_vector_44_4b
  56636. - .type _nds32_vector_44_4b, @function
  56637. -_nds32_vector_44_4b:
  56638. -1:
  56639. - j 1b
  56640. - .size _nds32_vector_44_4b, .-_nds32_vector_44_4b
  56641. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid44.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid44.S
  56642. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid44.S 2014-01-02 23:25:22.000000000 +0100
  56643. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid44.S 2016-08-08 20:37:53.734588650 +0200
  56644. @@ -1,5 +1,5 @@
  56645. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56646. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56647. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56648. Contributed by Andes Technology Corporation.
  56649. This file is part of GCC.
  56650. @@ -24,8 +24,15 @@
  56651. <http://www.gnu.org/licenses/>. */
  56652. .section .nds32_vector.44, "ax"
  56653. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56654. + /* The vector size is default 4-byte for v3 architecture. */
  56655. + .vec_size 4
  56656. + .align 2
  56657. +#else
  56658. + /* The vector size is default 16-byte for other architectures. */
  56659. .vec_size 16
  56660. .align 4
  56661. +#endif
  56662. .weak _nds32_vector_44
  56663. .type _nds32_vector_44, @function
  56664. _nds32_vector_44:
  56665. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid45_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid45_4b.S
  56666. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid45_4b.S 2014-01-02 23:25:22.000000000 +0100
  56667. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid45_4b.S 1970-01-01 01:00:00.000000000 +0100
  56668. @@ -1,34 +0,0 @@
  56669. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56670. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56671. - Contributed by Andes Technology Corporation.
  56672. -
  56673. - This file is part of GCC.
  56674. -
  56675. - GCC is free software; you can redistribute it and/or modify it
  56676. - under the terms of the GNU General Public License as published
  56677. - by the Free Software Foundation; either version 3, or (at your
  56678. - option) any later version.
  56679. -
  56680. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56681. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56682. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56683. - License for more details.
  56684. -
  56685. - Under Section 7 of GPL version 3, you are granted additional
  56686. - permissions described in the GCC Runtime Library Exception, version
  56687. - 3.1, as published by the Free Software Foundation.
  56688. -
  56689. - You should have received a copy of the GNU General Public License and
  56690. - a copy of the GCC Runtime Library Exception along with this program;
  56691. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56692. - <http://www.gnu.org/licenses/>. */
  56693. -
  56694. - .section .nds32_vector.45, "ax"
  56695. - .vec_size 4
  56696. - .align 2
  56697. - .weak _nds32_vector_45_4b
  56698. - .type _nds32_vector_45_4b, @function
  56699. -_nds32_vector_45_4b:
  56700. -1:
  56701. - j 1b
  56702. - .size _nds32_vector_45_4b, .-_nds32_vector_45_4b
  56703. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid45.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid45.S
  56704. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid45.S 2014-01-02 23:25:22.000000000 +0100
  56705. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid45.S 2016-08-08 20:37:53.734588650 +0200
  56706. @@ -1,5 +1,5 @@
  56707. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56708. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56709. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56710. Contributed by Andes Technology Corporation.
  56711. This file is part of GCC.
  56712. @@ -24,8 +24,15 @@
  56713. <http://www.gnu.org/licenses/>. */
  56714. .section .nds32_vector.45, "ax"
  56715. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56716. + /* The vector size is default 4-byte for v3 architecture. */
  56717. + .vec_size 4
  56718. + .align 2
  56719. +#else
  56720. + /* The vector size is default 16-byte for other architectures. */
  56721. .vec_size 16
  56722. .align 4
  56723. +#endif
  56724. .weak _nds32_vector_45
  56725. .type _nds32_vector_45, @function
  56726. _nds32_vector_45:
  56727. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid46_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid46_4b.S
  56728. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid46_4b.S 2014-01-02 23:25:22.000000000 +0100
  56729. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid46_4b.S 1970-01-01 01:00:00.000000000 +0100
  56730. @@ -1,34 +0,0 @@
  56731. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56732. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56733. - Contributed by Andes Technology Corporation.
  56734. -
  56735. - This file is part of GCC.
  56736. -
  56737. - GCC is free software; you can redistribute it and/or modify it
  56738. - under the terms of the GNU General Public License as published
  56739. - by the Free Software Foundation; either version 3, or (at your
  56740. - option) any later version.
  56741. -
  56742. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56743. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56744. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56745. - License for more details.
  56746. -
  56747. - Under Section 7 of GPL version 3, you are granted additional
  56748. - permissions described in the GCC Runtime Library Exception, version
  56749. - 3.1, as published by the Free Software Foundation.
  56750. -
  56751. - You should have received a copy of the GNU General Public License and
  56752. - a copy of the GCC Runtime Library Exception along with this program;
  56753. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56754. - <http://www.gnu.org/licenses/>. */
  56755. -
  56756. - .section .nds32_vector.46, "ax"
  56757. - .vec_size 4
  56758. - .align 2
  56759. - .weak _nds32_vector_46_4b
  56760. - .type _nds32_vector_46_4b, @function
  56761. -_nds32_vector_46_4b:
  56762. -1:
  56763. - j 1b
  56764. - .size _nds32_vector_46_4b, .-_nds32_vector_46_4b
  56765. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid46.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid46.S
  56766. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid46.S 2014-01-02 23:25:22.000000000 +0100
  56767. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid46.S 2016-08-08 20:37:53.734588650 +0200
  56768. @@ -1,5 +1,5 @@
  56769. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56770. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56771. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56772. Contributed by Andes Technology Corporation.
  56773. This file is part of GCC.
  56774. @@ -24,8 +24,15 @@
  56775. <http://www.gnu.org/licenses/>. */
  56776. .section .nds32_vector.46, "ax"
  56777. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56778. + /* The vector size is default 4-byte for v3 architecture. */
  56779. + .vec_size 4
  56780. + .align 2
  56781. +#else
  56782. + /* The vector size is default 16-byte for other architectures. */
  56783. .vec_size 16
  56784. .align 4
  56785. +#endif
  56786. .weak _nds32_vector_46
  56787. .type _nds32_vector_46, @function
  56788. _nds32_vector_46:
  56789. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid47_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid47_4b.S
  56790. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid47_4b.S 2014-01-02 23:25:22.000000000 +0100
  56791. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid47_4b.S 1970-01-01 01:00:00.000000000 +0100
  56792. @@ -1,34 +0,0 @@
  56793. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56794. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56795. - Contributed by Andes Technology Corporation.
  56796. -
  56797. - This file is part of GCC.
  56798. -
  56799. - GCC is free software; you can redistribute it and/or modify it
  56800. - under the terms of the GNU General Public License as published
  56801. - by the Free Software Foundation; either version 3, or (at your
  56802. - option) any later version.
  56803. -
  56804. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56805. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56806. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56807. - License for more details.
  56808. -
  56809. - Under Section 7 of GPL version 3, you are granted additional
  56810. - permissions described in the GCC Runtime Library Exception, version
  56811. - 3.1, as published by the Free Software Foundation.
  56812. -
  56813. - You should have received a copy of the GNU General Public License and
  56814. - a copy of the GCC Runtime Library Exception along with this program;
  56815. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56816. - <http://www.gnu.org/licenses/>. */
  56817. -
  56818. - .section .nds32_vector.47, "ax"
  56819. - .vec_size 4
  56820. - .align 2
  56821. - .weak _nds32_vector_47_4b
  56822. - .type _nds32_vector_47_4b, @function
  56823. -_nds32_vector_47_4b:
  56824. -1:
  56825. - j 1b
  56826. - .size _nds32_vector_47_4b, .-_nds32_vector_47_4b
  56827. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid47.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid47.S
  56828. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid47.S 2014-01-02 23:25:22.000000000 +0100
  56829. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid47.S 2016-08-08 20:37:53.738588805 +0200
  56830. @@ -1,5 +1,5 @@
  56831. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56832. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56833. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56834. Contributed by Andes Technology Corporation.
  56835. This file is part of GCC.
  56836. @@ -24,8 +24,15 @@
  56837. <http://www.gnu.org/licenses/>. */
  56838. .section .nds32_vector.47, "ax"
  56839. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56840. + /* The vector size is default 4-byte for v3 architecture. */
  56841. + .vec_size 4
  56842. + .align 2
  56843. +#else
  56844. + /* The vector size is default 16-byte for other architectures. */
  56845. .vec_size 16
  56846. .align 4
  56847. +#endif
  56848. .weak _nds32_vector_47
  56849. .type _nds32_vector_47, @function
  56850. _nds32_vector_47:
  56851. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid48_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid48_4b.S
  56852. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid48_4b.S 2014-01-02 23:25:22.000000000 +0100
  56853. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid48_4b.S 1970-01-01 01:00:00.000000000 +0100
  56854. @@ -1,34 +0,0 @@
  56855. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56856. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56857. - Contributed by Andes Technology Corporation.
  56858. -
  56859. - This file is part of GCC.
  56860. -
  56861. - GCC is free software; you can redistribute it and/or modify it
  56862. - under the terms of the GNU General Public License as published
  56863. - by the Free Software Foundation; either version 3, or (at your
  56864. - option) any later version.
  56865. -
  56866. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56867. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56868. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56869. - License for more details.
  56870. -
  56871. - Under Section 7 of GPL version 3, you are granted additional
  56872. - permissions described in the GCC Runtime Library Exception, version
  56873. - 3.1, as published by the Free Software Foundation.
  56874. -
  56875. - You should have received a copy of the GNU General Public License and
  56876. - a copy of the GCC Runtime Library Exception along with this program;
  56877. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56878. - <http://www.gnu.org/licenses/>. */
  56879. -
  56880. - .section .nds32_vector.48, "ax"
  56881. - .vec_size 4
  56882. - .align 2
  56883. - .weak _nds32_vector_48_4b
  56884. - .type _nds32_vector_48_4b, @function
  56885. -_nds32_vector_48_4b:
  56886. -1:
  56887. - j 1b
  56888. - .size _nds32_vector_48_4b, .-_nds32_vector_48_4b
  56889. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid48.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid48.S
  56890. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid48.S 2014-01-02 23:25:22.000000000 +0100
  56891. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid48.S 2016-08-08 20:37:53.738588805 +0200
  56892. @@ -1,5 +1,5 @@
  56893. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56894. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56895. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56896. Contributed by Andes Technology Corporation.
  56897. This file is part of GCC.
  56898. @@ -24,8 +24,15 @@
  56899. <http://www.gnu.org/licenses/>. */
  56900. .section .nds32_vector.48, "ax"
  56901. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56902. + /* The vector size is default 4-byte for v3 architecture. */
  56903. + .vec_size 4
  56904. + .align 2
  56905. +#else
  56906. + /* The vector size is default 16-byte for other architectures. */
  56907. .vec_size 16
  56908. .align 4
  56909. +#endif
  56910. .weak _nds32_vector_48
  56911. .type _nds32_vector_48, @function
  56912. _nds32_vector_48:
  56913. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid49_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid49_4b.S
  56914. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid49_4b.S 2014-01-02 23:25:22.000000000 +0100
  56915. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid49_4b.S 1970-01-01 01:00:00.000000000 +0100
  56916. @@ -1,34 +0,0 @@
  56917. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56918. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56919. - Contributed by Andes Technology Corporation.
  56920. -
  56921. - This file is part of GCC.
  56922. -
  56923. - GCC is free software; you can redistribute it and/or modify it
  56924. - under the terms of the GNU General Public License as published
  56925. - by the Free Software Foundation; either version 3, or (at your
  56926. - option) any later version.
  56927. -
  56928. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56929. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56930. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56931. - License for more details.
  56932. -
  56933. - Under Section 7 of GPL version 3, you are granted additional
  56934. - permissions described in the GCC Runtime Library Exception, version
  56935. - 3.1, as published by the Free Software Foundation.
  56936. -
  56937. - You should have received a copy of the GNU General Public License and
  56938. - a copy of the GCC Runtime Library Exception along with this program;
  56939. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  56940. - <http://www.gnu.org/licenses/>. */
  56941. -
  56942. - .section .nds32_vector.49, "ax"
  56943. - .vec_size 4
  56944. - .align 2
  56945. - .weak _nds32_vector_49_4b
  56946. - .type _nds32_vector_49_4b, @function
  56947. -_nds32_vector_49_4b:
  56948. -1:
  56949. - j 1b
  56950. - .size _nds32_vector_49_4b, .-_nds32_vector_49_4b
  56951. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid49.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid49.S
  56952. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid49.S 2014-01-02 23:25:22.000000000 +0100
  56953. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid49.S 2016-08-08 20:37:53.738588805 +0200
  56954. @@ -1,5 +1,5 @@
  56955. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56956. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56957. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  56958. Contributed by Andes Technology Corporation.
  56959. This file is part of GCC.
  56960. @@ -24,8 +24,15 @@
  56961. <http://www.gnu.org/licenses/>. */
  56962. .section .nds32_vector.49, "ax"
  56963. +#if __NDS32_ISR_VECTOR_SIZE_4__
  56964. + /* The vector size is default 4-byte for v3 architecture. */
  56965. + .vec_size 4
  56966. + .align 2
  56967. +#else
  56968. + /* The vector size is default 16-byte for other architectures. */
  56969. .vec_size 16
  56970. .align 4
  56971. +#endif
  56972. .weak _nds32_vector_49
  56973. .type _nds32_vector_49, @function
  56974. _nds32_vector_49:
  56975. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid50_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid50_4b.S
  56976. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid50_4b.S 2014-01-02 23:25:22.000000000 +0100
  56977. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid50_4b.S 1970-01-01 01:00:00.000000000 +0100
  56978. @@ -1,34 +0,0 @@
  56979. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  56980. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  56981. - Contributed by Andes Technology Corporation.
  56982. -
  56983. - This file is part of GCC.
  56984. -
  56985. - GCC is free software; you can redistribute it and/or modify it
  56986. - under the terms of the GNU General Public License as published
  56987. - by the Free Software Foundation; either version 3, or (at your
  56988. - option) any later version.
  56989. -
  56990. - GCC is distributed in the hope that it will be useful, but WITHOUT
  56991. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  56992. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  56993. - License for more details.
  56994. -
  56995. - Under Section 7 of GPL version 3, you are granted additional
  56996. - permissions described in the GCC Runtime Library Exception, version
  56997. - 3.1, as published by the Free Software Foundation.
  56998. -
  56999. - You should have received a copy of the GNU General Public License and
  57000. - a copy of the GCC Runtime Library Exception along with this program;
  57001. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57002. - <http://www.gnu.org/licenses/>. */
  57003. -
  57004. - .section .nds32_vector.50, "ax"
  57005. - .vec_size 4
  57006. - .align 2
  57007. - .weak _nds32_vector_50_4b
  57008. - .type _nds32_vector_50_4b, @function
  57009. -_nds32_vector_50_4b:
  57010. -1:
  57011. - j 1b
  57012. - .size _nds32_vector_50_4b, .-_nds32_vector_50_4b
  57013. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid50.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid50.S
  57014. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid50.S 2014-01-02 23:25:22.000000000 +0100
  57015. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid50.S 2016-08-08 20:37:53.738588805 +0200
  57016. @@ -1,5 +1,5 @@
  57017. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57018. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57019. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57020. Contributed by Andes Technology Corporation.
  57021. This file is part of GCC.
  57022. @@ -24,8 +24,15 @@
  57023. <http://www.gnu.org/licenses/>. */
  57024. .section .nds32_vector.50, "ax"
  57025. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57026. + /* The vector size is default 4-byte for v3 architecture. */
  57027. + .vec_size 4
  57028. + .align 2
  57029. +#else
  57030. + /* The vector size is default 16-byte for other architectures. */
  57031. .vec_size 16
  57032. .align 4
  57033. +#endif
  57034. .weak _nds32_vector_50
  57035. .type _nds32_vector_50, @function
  57036. _nds32_vector_50:
  57037. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid51_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid51_4b.S
  57038. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid51_4b.S 2014-01-02 23:25:22.000000000 +0100
  57039. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid51_4b.S 1970-01-01 01:00:00.000000000 +0100
  57040. @@ -1,34 +0,0 @@
  57041. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57042. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57043. - Contributed by Andes Technology Corporation.
  57044. -
  57045. - This file is part of GCC.
  57046. -
  57047. - GCC is free software; you can redistribute it and/or modify it
  57048. - under the terms of the GNU General Public License as published
  57049. - by the Free Software Foundation; either version 3, or (at your
  57050. - option) any later version.
  57051. -
  57052. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57053. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57054. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57055. - License for more details.
  57056. -
  57057. - Under Section 7 of GPL version 3, you are granted additional
  57058. - permissions described in the GCC Runtime Library Exception, version
  57059. - 3.1, as published by the Free Software Foundation.
  57060. -
  57061. - You should have received a copy of the GNU General Public License and
  57062. - a copy of the GCC Runtime Library Exception along with this program;
  57063. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57064. - <http://www.gnu.org/licenses/>. */
  57065. -
  57066. - .section .nds32_vector.51, "ax"
  57067. - .vec_size 4
  57068. - .align 2
  57069. - .weak _nds32_vector_51_4b
  57070. - .type _nds32_vector_51_4b, @function
  57071. -_nds32_vector_51_4b:
  57072. -1:
  57073. - j 1b
  57074. - .size _nds32_vector_51_4b, .-_nds32_vector_51_4b
  57075. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid51.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid51.S
  57076. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid51.S 2014-01-02 23:25:22.000000000 +0100
  57077. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid51.S 2016-08-08 20:37:53.738588805 +0200
  57078. @@ -1,5 +1,5 @@
  57079. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57080. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57081. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57082. Contributed by Andes Technology Corporation.
  57083. This file is part of GCC.
  57084. @@ -24,8 +24,15 @@
  57085. <http://www.gnu.org/licenses/>. */
  57086. .section .nds32_vector.51, "ax"
  57087. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57088. + /* The vector size is default 4-byte for v3 architecture. */
  57089. + .vec_size 4
  57090. + .align 2
  57091. +#else
  57092. + /* The vector size is default 16-byte for other architectures. */
  57093. .vec_size 16
  57094. .align 4
  57095. +#endif
  57096. .weak _nds32_vector_51
  57097. .type _nds32_vector_51, @function
  57098. _nds32_vector_51:
  57099. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid52_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid52_4b.S
  57100. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid52_4b.S 2014-01-02 23:25:22.000000000 +0100
  57101. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid52_4b.S 1970-01-01 01:00:00.000000000 +0100
  57102. @@ -1,34 +0,0 @@
  57103. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57104. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57105. - Contributed by Andes Technology Corporation.
  57106. -
  57107. - This file is part of GCC.
  57108. -
  57109. - GCC is free software; you can redistribute it and/or modify it
  57110. - under the terms of the GNU General Public License as published
  57111. - by the Free Software Foundation; either version 3, or (at your
  57112. - option) any later version.
  57113. -
  57114. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57115. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57116. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57117. - License for more details.
  57118. -
  57119. - Under Section 7 of GPL version 3, you are granted additional
  57120. - permissions described in the GCC Runtime Library Exception, version
  57121. - 3.1, as published by the Free Software Foundation.
  57122. -
  57123. - You should have received a copy of the GNU General Public License and
  57124. - a copy of the GCC Runtime Library Exception along with this program;
  57125. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57126. - <http://www.gnu.org/licenses/>. */
  57127. -
  57128. - .section .nds32_vector.52, "ax"
  57129. - .vec_size 4
  57130. - .align 2
  57131. - .weak _nds32_vector_52_4b
  57132. - .type _nds32_vector_52_4b, @function
  57133. -_nds32_vector_52_4b:
  57134. -1:
  57135. - j 1b
  57136. - .size _nds32_vector_52_4b, .-_nds32_vector_52_4b
  57137. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid52.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid52.S
  57138. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid52.S 2014-01-02 23:25:22.000000000 +0100
  57139. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid52.S 2016-08-08 20:37:53.738588805 +0200
  57140. @@ -1,5 +1,5 @@
  57141. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57142. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57143. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57144. Contributed by Andes Technology Corporation.
  57145. This file is part of GCC.
  57146. @@ -24,8 +24,15 @@
  57147. <http://www.gnu.org/licenses/>. */
  57148. .section .nds32_vector.52, "ax"
  57149. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57150. + /* The vector size is default 4-byte for v3 architecture. */
  57151. + .vec_size 4
  57152. + .align 2
  57153. +#else
  57154. + /* The vector size is default 16-byte for other architectures. */
  57155. .vec_size 16
  57156. .align 4
  57157. +#endif
  57158. .weak _nds32_vector_52
  57159. .type _nds32_vector_52, @function
  57160. _nds32_vector_52:
  57161. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid53_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid53_4b.S
  57162. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid53_4b.S 2014-01-02 23:25:22.000000000 +0100
  57163. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid53_4b.S 1970-01-01 01:00:00.000000000 +0100
  57164. @@ -1,34 +0,0 @@
  57165. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57166. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57167. - Contributed by Andes Technology Corporation.
  57168. -
  57169. - This file is part of GCC.
  57170. -
  57171. - GCC is free software; you can redistribute it and/or modify it
  57172. - under the terms of the GNU General Public License as published
  57173. - by the Free Software Foundation; either version 3, or (at your
  57174. - option) any later version.
  57175. -
  57176. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57177. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57178. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57179. - License for more details.
  57180. -
  57181. - Under Section 7 of GPL version 3, you are granted additional
  57182. - permissions described in the GCC Runtime Library Exception, version
  57183. - 3.1, as published by the Free Software Foundation.
  57184. -
  57185. - You should have received a copy of the GNU General Public License and
  57186. - a copy of the GCC Runtime Library Exception along with this program;
  57187. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57188. - <http://www.gnu.org/licenses/>. */
  57189. -
  57190. - .section .nds32_vector.53, "ax"
  57191. - .vec_size 4
  57192. - .align 2
  57193. - .weak _nds32_vector_53_4b
  57194. - .type _nds32_vector_53_4b, @function
  57195. -_nds32_vector_53_4b:
  57196. -1:
  57197. - j 1b
  57198. - .size _nds32_vector_53_4b, .-_nds32_vector_53_4b
  57199. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid53.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid53.S
  57200. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid53.S 2014-01-02 23:25:22.000000000 +0100
  57201. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid53.S 2016-08-08 20:37:53.738588805 +0200
  57202. @@ -1,5 +1,5 @@
  57203. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57204. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57205. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57206. Contributed by Andes Technology Corporation.
  57207. This file is part of GCC.
  57208. @@ -24,8 +24,15 @@
  57209. <http://www.gnu.org/licenses/>. */
  57210. .section .nds32_vector.53, "ax"
  57211. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57212. + /* The vector size is default 4-byte for v3 architecture. */
  57213. + .vec_size 4
  57214. + .align 2
  57215. +#else
  57216. + /* The vector size is default 16-byte for other architectures. */
  57217. .vec_size 16
  57218. .align 4
  57219. +#endif
  57220. .weak _nds32_vector_53
  57221. .type _nds32_vector_53, @function
  57222. _nds32_vector_53:
  57223. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid54_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid54_4b.S
  57224. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid54_4b.S 2014-01-02 23:25:22.000000000 +0100
  57225. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid54_4b.S 1970-01-01 01:00:00.000000000 +0100
  57226. @@ -1,34 +0,0 @@
  57227. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57228. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57229. - Contributed by Andes Technology Corporation.
  57230. -
  57231. - This file is part of GCC.
  57232. -
  57233. - GCC is free software; you can redistribute it and/or modify it
  57234. - under the terms of the GNU General Public License as published
  57235. - by the Free Software Foundation; either version 3, or (at your
  57236. - option) any later version.
  57237. -
  57238. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57239. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57240. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57241. - License for more details.
  57242. -
  57243. - Under Section 7 of GPL version 3, you are granted additional
  57244. - permissions described in the GCC Runtime Library Exception, version
  57245. - 3.1, as published by the Free Software Foundation.
  57246. -
  57247. - You should have received a copy of the GNU General Public License and
  57248. - a copy of the GCC Runtime Library Exception along with this program;
  57249. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57250. - <http://www.gnu.org/licenses/>. */
  57251. -
  57252. - .section .nds32_vector.54, "ax"
  57253. - .vec_size 4
  57254. - .align 2
  57255. - .weak _nds32_vector_54_4b
  57256. - .type _nds32_vector_54_4b, @function
  57257. -_nds32_vector_54_4b:
  57258. -1:
  57259. - j 1b
  57260. - .size _nds32_vector_54_4b, .-_nds32_vector_54_4b
  57261. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid54.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid54.S
  57262. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid54.S 2014-01-02 23:25:22.000000000 +0100
  57263. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid54.S 2016-08-08 20:37:53.738588805 +0200
  57264. @@ -1,5 +1,5 @@
  57265. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57266. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57267. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57268. Contributed by Andes Technology Corporation.
  57269. This file is part of GCC.
  57270. @@ -24,8 +24,15 @@
  57271. <http://www.gnu.org/licenses/>. */
  57272. .section .nds32_vector.54, "ax"
  57273. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57274. + /* The vector size is default 4-byte for v3 architecture. */
  57275. + .vec_size 4
  57276. + .align 2
  57277. +#else
  57278. + /* The vector size is default 16-byte for other architectures. */
  57279. .vec_size 16
  57280. .align 4
  57281. +#endif
  57282. .weak _nds32_vector_54
  57283. .type _nds32_vector_54, @function
  57284. _nds32_vector_54:
  57285. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid55_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid55_4b.S
  57286. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid55_4b.S 2014-01-02 23:25:22.000000000 +0100
  57287. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid55_4b.S 1970-01-01 01:00:00.000000000 +0100
  57288. @@ -1,34 +0,0 @@
  57289. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57290. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57291. - Contributed by Andes Technology Corporation.
  57292. -
  57293. - This file is part of GCC.
  57294. -
  57295. - GCC is free software; you can redistribute it and/or modify it
  57296. - under the terms of the GNU General Public License as published
  57297. - by the Free Software Foundation; either version 3, or (at your
  57298. - option) any later version.
  57299. -
  57300. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57301. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57302. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57303. - License for more details.
  57304. -
  57305. - Under Section 7 of GPL version 3, you are granted additional
  57306. - permissions described in the GCC Runtime Library Exception, version
  57307. - 3.1, as published by the Free Software Foundation.
  57308. -
  57309. - You should have received a copy of the GNU General Public License and
  57310. - a copy of the GCC Runtime Library Exception along with this program;
  57311. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57312. - <http://www.gnu.org/licenses/>. */
  57313. -
  57314. - .section .nds32_vector.55, "ax"
  57315. - .vec_size 4
  57316. - .align 2
  57317. - .weak _nds32_vector_55_4b
  57318. - .type _nds32_vector_55_4b, @function
  57319. -_nds32_vector_55_4b:
  57320. -1:
  57321. - j 1b
  57322. - .size _nds32_vector_55_4b, .-_nds32_vector_55_4b
  57323. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid55.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid55.S
  57324. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid55.S 2014-01-02 23:25:22.000000000 +0100
  57325. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid55.S 2016-08-08 20:37:53.738588805 +0200
  57326. @@ -1,5 +1,5 @@
  57327. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57328. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57329. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57330. Contributed by Andes Technology Corporation.
  57331. This file is part of GCC.
  57332. @@ -24,8 +24,15 @@
  57333. <http://www.gnu.org/licenses/>. */
  57334. .section .nds32_vector.55, "ax"
  57335. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57336. + /* The vector size is default 4-byte for v3 architecture. */
  57337. + .vec_size 4
  57338. + .align 2
  57339. +#else
  57340. + /* The vector size is default 16-byte for other architectures. */
  57341. .vec_size 16
  57342. .align 4
  57343. +#endif
  57344. .weak _nds32_vector_55
  57345. .type _nds32_vector_55, @function
  57346. _nds32_vector_55:
  57347. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid56_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid56_4b.S
  57348. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid56_4b.S 2014-01-02 23:25:22.000000000 +0100
  57349. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid56_4b.S 1970-01-01 01:00:00.000000000 +0100
  57350. @@ -1,34 +0,0 @@
  57351. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57352. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57353. - Contributed by Andes Technology Corporation.
  57354. -
  57355. - This file is part of GCC.
  57356. -
  57357. - GCC is free software; you can redistribute it and/or modify it
  57358. - under the terms of the GNU General Public License as published
  57359. - by the Free Software Foundation; either version 3, or (at your
  57360. - option) any later version.
  57361. -
  57362. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57363. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57364. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57365. - License for more details.
  57366. -
  57367. - Under Section 7 of GPL version 3, you are granted additional
  57368. - permissions described in the GCC Runtime Library Exception, version
  57369. - 3.1, as published by the Free Software Foundation.
  57370. -
  57371. - You should have received a copy of the GNU General Public License and
  57372. - a copy of the GCC Runtime Library Exception along with this program;
  57373. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57374. - <http://www.gnu.org/licenses/>. */
  57375. -
  57376. - .section .nds32_vector.56, "ax"
  57377. - .vec_size 4
  57378. - .align 2
  57379. - .weak _nds32_vector_56_4b
  57380. - .type _nds32_vector_56_4b, @function
  57381. -_nds32_vector_56_4b:
  57382. -1:
  57383. - j 1b
  57384. - .size _nds32_vector_56_4b, .-_nds32_vector_56_4b
  57385. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid56.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid56.S
  57386. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid56.S 2014-01-02 23:25:22.000000000 +0100
  57387. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid56.S 2016-08-08 20:37:53.738588805 +0200
  57388. @@ -1,5 +1,5 @@
  57389. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57390. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57391. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57392. Contributed by Andes Technology Corporation.
  57393. This file is part of GCC.
  57394. @@ -24,8 +24,15 @@
  57395. <http://www.gnu.org/licenses/>. */
  57396. .section .nds32_vector.56, "ax"
  57397. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57398. + /* The vector size is default 4-byte for v3 architecture. */
  57399. + .vec_size 4
  57400. + .align 2
  57401. +#else
  57402. + /* The vector size is default 16-byte for other architectures. */
  57403. .vec_size 16
  57404. .align 4
  57405. +#endif
  57406. .weak _nds32_vector_56
  57407. .type _nds32_vector_56, @function
  57408. _nds32_vector_56:
  57409. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid57_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid57_4b.S
  57410. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid57_4b.S 2014-01-02 23:25:22.000000000 +0100
  57411. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid57_4b.S 1970-01-01 01:00:00.000000000 +0100
  57412. @@ -1,34 +0,0 @@
  57413. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57414. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57415. - Contributed by Andes Technology Corporation.
  57416. -
  57417. - This file is part of GCC.
  57418. -
  57419. - GCC is free software; you can redistribute it and/or modify it
  57420. - under the terms of the GNU General Public License as published
  57421. - by the Free Software Foundation; either version 3, or (at your
  57422. - option) any later version.
  57423. -
  57424. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57425. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57426. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57427. - License for more details.
  57428. -
  57429. - Under Section 7 of GPL version 3, you are granted additional
  57430. - permissions described in the GCC Runtime Library Exception, version
  57431. - 3.1, as published by the Free Software Foundation.
  57432. -
  57433. - You should have received a copy of the GNU General Public License and
  57434. - a copy of the GCC Runtime Library Exception along with this program;
  57435. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57436. - <http://www.gnu.org/licenses/>. */
  57437. -
  57438. - .section .nds32_vector.57, "ax"
  57439. - .vec_size 4
  57440. - .align 2
  57441. - .weak _nds32_vector_57_4b
  57442. - .type _nds32_vector_57_4b, @function
  57443. -_nds32_vector_57_4b:
  57444. -1:
  57445. - j 1b
  57446. - .size _nds32_vector_57_4b, .-_nds32_vector_57_4b
  57447. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid57.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid57.S
  57448. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid57.S 2014-01-02 23:25:22.000000000 +0100
  57449. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid57.S 2016-08-08 20:37:53.738588805 +0200
  57450. @@ -1,5 +1,5 @@
  57451. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57452. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57453. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57454. Contributed by Andes Technology Corporation.
  57455. This file is part of GCC.
  57456. @@ -24,8 +24,15 @@
  57457. <http://www.gnu.org/licenses/>. */
  57458. .section .nds32_vector.57, "ax"
  57459. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57460. + /* The vector size is default 4-byte for v3 architecture. */
  57461. + .vec_size 4
  57462. + .align 2
  57463. +#else
  57464. + /* The vector size is default 16-byte for other architectures. */
  57465. .vec_size 16
  57466. .align 4
  57467. +#endif
  57468. .weak _nds32_vector_57
  57469. .type _nds32_vector_57, @function
  57470. _nds32_vector_57:
  57471. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid58_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid58_4b.S
  57472. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid58_4b.S 2014-01-02 23:25:22.000000000 +0100
  57473. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid58_4b.S 1970-01-01 01:00:00.000000000 +0100
  57474. @@ -1,34 +0,0 @@
  57475. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57476. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57477. - Contributed by Andes Technology Corporation.
  57478. -
  57479. - This file is part of GCC.
  57480. -
  57481. - GCC is free software; you can redistribute it and/or modify it
  57482. - under the terms of the GNU General Public License as published
  57483. - by the Free Software Foundation; either version 3, or (at your
  57484. - option) any later version.
  57485. -
  57486. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57487. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57488. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57489. - License for more details.
  57490. -
  57491. - Under Section 7 of GPL version 3, you are granted additional
  57492. - permissions described in the GCC Runtime Library Exception, version
  57493. - 3.1, as published by the Free Software Foundation.
  57494. -
  57495. - You should have received a copy of the GNU General Public License and
  57496. - a copy of the GCC Runtime Library Exception along with this program;
  57497. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57498. - <http://www.gnu.org/licenses/>. */
  57499. -
  57500. - .section .nds32_vector.58, "ax"
  57501. - .vec_size 4
  57502. - .align 2
  57503. - .weak _nds32_vector_58_4b
  57504. - .type _nds32_vector_58_4b, @function
  57505. -_nds32_vector_58_4b:
  57506. -1:
  57507. - j 1b
  57508. - .size _nds32_vector_58_4b, .-_nds32_vector_58_4b
  57509. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid58.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid58.S
  57510. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid58.S 2014-01-02 23:25:22.000000000 +0100
  57511. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid58.S 2016-08-08 20:37:53.742588960 +0200
  57512. @@ -1,5 +1,5 @@
  57513. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57514. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57515. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57516. Contributed by Andes Technology Corporation.
  57517. This file is part of GCC.
  57518. @@ -24,8 +24,15 @@
  57519. <http://www.gnu.org/licenses/>. */
  57520. .section .nds32_vector.58, "ax"
  57521. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57522. + /* The vector size is default 4-byte for v3 architecture. */
  57523. + .vec_size 4
  57524. + .align 2
  57525. +#else
  57526. + /* The vector size is default 16-byte for other architectures. */
  57527. .vec_size 16
  57528. .align 4
  57529. +#endif
  57530. .weak _nds32_vector_58
  57531. .type _nds32_vector_58, @function
  57532. _nds32_vector_58:
  57533. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid59_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid59_4b.S
  57534. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid59_4b.S 2014-01-02 23:25:22.000000000 +0100
  57535. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid59_4b.S 1970-01-01 01:00:00.000000000 +0100
  57536. @@ -1,34 +0,0 @@
  57537. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57538. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57539. - Contributed by Andes Technology Corporation.
  57540. -
  57541. - This file is part of GCC.
  57542. -
  57543. - GCC is free software; you can redistribute it and/or modify it
  57544. - under the terms of the GNU General Public License as published
  57545. - by the Free Software Foundation; either version 3, or (at your
  57546. - option) any later version.
  57547. -
  57548. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57549. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57550. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57551. - License for more details.
  57552. -
  57553. - Under Section 7 of GPL version 3, you are granted additional
  57554. - permissions described in the GCC Runtime Library Exception, version
  57555. - 3.1, as published by the Free Software Foundation.
  57556. -
  57557. - You should have received a copy of the GNU General Public License and
  57558. - a copy of the GCC Runtime Library Exception along with this program;
  57559. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57560. - <http://www.gnu.org/licenses/>. */
  57561. -
  57562. - .section .nds32_vector.59, "ax"
  57563. - .vec_size 4
  57564. - .align 2
  57565. - .weak _nds32_vector_59_4b
  57566. - .type _nds32_vector_59_4b, @function
  57567. -_nds32_vector_59_4b:
  57568. -1:
  57569. - j 1b
  57570. - .size _nds32_vector_59_4b, .-_nds32_vector_59_4b
  57571. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid59.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid59.S
  57572. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid59.S 2014-01-02 23:25:22.000000000 +0100
  57573. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid59.S 2016-08-08 20:37:53.742588960 +0200
  57574. @@ -1,5 +1,5 @@
  57575. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57576. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57577. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57578. Contributed by Andes Technology Corporation.
  57579. This file is part of GCC.
  57580. @@ -24,8 +24,15 @@
  57581. <http://www.gnu.org/licenses/>. */
  57582. .section .nds32_vector.59, "ax"
  57583. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57584. + /* The vector size is default 4-byte for v3 architecture. */
  57585. + .vec_size 4
  57586. + .align 2
  57587. +#else
  57588. + /* The vector size is default 16-byte for other architectures. */
  57589. .vec_size 16
  57590. .align 4
  57591. +#endif
  57592. .weak _nds32_vector_59
  57593. .type _nds32_vector_59, @function
  57594. _nds32_vector_59:
  57595. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid60_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid60_4b.S
  57596. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid60_4b.S 2014-01-02 23:25:22.000000000 +0100
  57597. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid60_4b.S 1970-01-01 01:00:00.000000000 +0100
  57598. @@ -1,34 +0,0 @@
  57599. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57600. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57601. - Contributed by Andes Technology Corporation.
  57602. -
  57603. - This file is part of GCC.
  57604. -
  57605. - GCC is free software; you can redistribute it and/or modify it
  57606. - under the terms of the GNU General Public License as published
  57607. - by the Free Software Foundation; either version 3, or (at your
  57608. - option) any later version.
  57609. -
  57610. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57611. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57612. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57613. - License for more details.
  57614. -
  57615. - Under Section 7 of GPL version 3, you are granted additional
  57616. - permissions described in the GCC Runtime Library Exception, version
  57617. - 3.1, as published by the Free Software Foundation.
  57618. -
  57619. - You should have received a copy of the GNU General Public License and
  57620. - a copy of the GCC Runtime Library Exception along with this program;
  57621. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57622. - <http://www.gnu.org/licenses/>. */
  57623. -
  57624. - .section .nds32_vector.60, "ax"
  57625. - .vec_size 4
  57626. - .align 2
  57627. - .weak _nds32_vector_60_4b
  57628. - .type _nds32_vector_60_4b, @function
  57629. -_nds32_vector_60_4b:
  57630. -1:
  57631. - j 1b
  57632. - .size _nds32_vector_60_4b, .-_nds32_vector_60_4b
  57633. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid60.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid60.S
  57634. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid60.S 2014-01-02 23:25:22.000000000 +0100
  57635. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid60.S 2016-08-08 20:37:53.742588960 +0200
  57636. @@ -1,5 +1,5 @@
  57637. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57638. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57639. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57640. Contributed by Andes Technology Corporation.
  57641. This file is part of GCC.
  57642. @@ -24,8 +24,15 @@
  57643. <http://www.gnu.org/licenses/>. */
  57644. .section .nds32_vector.60, "ax"
  57645. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57646. + /* The vector size is default 4-byte for v3 architecture. */
  57647. + .vec_size 4
  57648. + .align 2
  57649. +#else
  57650. + /* The vector size is default 16-byte for other architectures. */
  57651. .vec_size 16
  57652. .align 4
  57653. +#endif
  57654. .weak _nds32_vector_60
  57655. .type _nds32_vector_60, @function
  57656. _nds32_vector_60:
  57657. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid61_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid61_4b.S
  57658. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid61_4b.S 2014-01-02 23:25:22.000000000 +0100
  57659. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid61_4b.S 1970-01-01 01:00:00.000000000 +0100
  57660. @@ -1,34 +0,0 @@
  57661. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57662. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57663. - Contributed by Andes Technology Corporation.
  57664. -
  57665. - This file is part of GCC.
  57666. -
  57667. - GCC is free software; you can redistribute it and/or modify it
  57668. - under the terms of the GNU General Public License as published
  57669. - by the Free Software Foundation; either version 3, or (at your
  57670. - option) any later version.
  57671. -
  57672. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57673. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57674. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57675. - License for more details.
  57676. -
  57677. - Under Section 7 of GPL version 3, you are granted additional
  57678. - permissions described in the GCC Runtime Library Exception, version
  57679. - 3.1, as published by the Free Software Foundation.
  57680. -
  57681. - You should have received a copy of the GNU General Public License and
  57682. - a copy of the GCC Runtime Library Exception along with this program;
  57683. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57684. - <http://www.gnu.org/licenses/>. */
  57685. -
  57686. - .section .nds32_vector.61, "ax"
  57687. - .vec_size 4
  57688. - .align 2
  57689. - .weak _nds32_vector_61_4b
  57690. - .type _nds32_vector_61_4b, @function
  57691. -_nds32_vector_61_4b:
  57692. -1:
  57693. - j 1b
  57694. - .size _nds32_vector_61_4b, .-_nds32_vector_61_4b
  57695. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid61.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid61.S
  57696. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid61.S 2014-01-02 23:25:22.000000000 +0100
  57697. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid61.S 2016-08-08 20:37:53.742588960 +0200
  57698. @@ -1,5 +1,5 @@
  57699. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57700. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57701. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57702. Contributed by Andes Technology Corporation.
  57703. This file is part of GCC.
  57704. @@ -24,8 +24,15 @@
  57705. <http://www.gnu.org/licenses/>. */
  57706. .section .nds32_vector.61, "ax"
  57707. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57708. + /* The vector size is default 4-byte for v3 architecture. */
  57709. + .vec_size 4
  57710. + .align 2
  57711. +#else
  57712. + /* The vector size is default 16-byte for other architectures. */
  57713. .vec_size 16
  57714. .align 4
  57715. +#endif
  57716. .weak _nds32_vector_61
  57717. .type _nds32_vector_61, @function
  57718. _nds32_vector_61:
  57719. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid62_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid62_4b.S
  57720. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid62_4b.S 2014-01-02 23:25:22.000000000 +0100
  57721. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid62_4b.S 1970-01-01 01:00:00.000000000 +0100
  57722. @@ -1,34 +0,0 @@
  57723. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57724. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57725. - Contributed by Andes Technology Corporation.
  57726. -
  57727. - This file is part of GCC.
  57728. -
  57729. - GCC is free software; you can redistribute it and/or modify it
  57730. - under the terms of the GNU General Public License as published
  57731. - by the Free Software Foundation; either version 3, or (at your
  57732. - option) any later version.
  57733. -
  57734. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57735. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57736. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57737. - License for more details.
  57738. -
  57739. - Under Section 7 of GPL version 3, you are granted additional
  57740. - permissions described in the GCC Runtime Library Exception, version
  57741. - 3.1, as published by the Free Software Foundation.
  57742. -
  57743. - You should have received a copy of the GNU General Public License and
  57744. - a copy of the GCC Runtime Library Exception along with this program;
  57745. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57746. - <http://www.gnu.org/licenses/>. */
  57747. -
  57748. - .section .nds32_vector.62, "ax"
  57749. - .vec_size 4
  57750. - .align 2
  57751. - .weak _nds32_vector_62_4b
  57752. - .type _nds32_vector_62_4b, @function
  57753. -_nds32_vector_62_4b:
  57754. -1:
  57755. - j 1b
  57756. - .size _nds32_vector_62_4b, .-_nds32_vector_62_4b
  57757. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid62.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid62.S
  57758. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid62.S 2014-01-02 23:25:22.000000000 +0100
  57759. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid62.S 2016-08-08 20:37:53.742588960 +0200
  57760. @@ -1,5 +1,5 @@
  57761. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57762. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57763. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57764. Contributed by Andes Technology Corporation.
  57765. This file is part of GCC.
  57766. @@ -24,8 +24,15 @@
  57767. <http://www.gnu.org/licenses/>. */
  57768. .section .nds32_vector.62, "ax"
  57769. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57770. + /* The vector size is default 4-byte for v3 architecture. */
  57771. + .vec_size 4
  57772. + .align 2
  57773. +#else
  57774. + /* The vector size is default 16-byte for other architectures. */
  57775. .vec_size 16
  57776. .align 4
  57777. +#endif
  57778. .weak _nds32_vector_62
  57779. .type _nds32_vector_62, @function
  57780. _nds32_vector_62:
  57781. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid63_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid63_4b.S
  57782. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid63_4b.S 2014-01-02 23:25:22.000000000 +0100
  57783. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid63_4b.S 1970-01-01 01:00:00.000000000 +0100
  57784. @@ -1,34 +0,0 @@
  57785. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57786. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57787. - Contributed by Andes Technology Corporation.
  57788. -
  57789. - This file is part of GCC.
  57790. -
  57791. - GCC is free software; you can redistribute it and/or modify it
  57792. - under the terms of the GNU General Public License as published
  57793. - by the Free Software Foundation; either version 3, or (at your
  57794. - option) any later version.
  57795. -
  57796. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57797. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57798. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57799. - License for more details.
  57800. -
  57801. - Under Section 7 of GPL version 3, you are granted additional
  57802. - permissions described in the GCC Runtime Library Exception, version
  57803. - 3.1, as published by the Free Software Foundation.
  57804. -
  57805. - You should have received a copy of the GNU General Public License and
  57806. - a copy of the GCC Runtime Library Exception along with this program;
  57807. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57808. - <http://www.gnu.org/licenses/>. */
  57809. -
  57810. - .section .nds32_vector.63, "ax"
  57811. - .vec_size 4
  57812. - .align 2
  57813. - .weak _nds32_vector_63_4b
  57814. - .type _nds32_vector_63_4b, @function
  57815. -_nds32_vector_63_4b:
  57816. -1:
  57817. - j 1b
  57818. - .size _nds32_vector_63_4b, .-_nds32_vector_63_4b
  57819. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid63.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid63.S
  57820. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid63.S 2014-01-02 23:25:22.000000000 +0100
  57821. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid63.S 2016-08-08 20:37:53.742588960 +0200
  57822. @@ -1,5 +1,5 @@
  57823. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57824. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57825. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57826. Contributed by Andes Technology Corporation.
  57827. This file is part of GCC.
  57828. @@ -24,8 +24,15 @@
  57829. <http://www.gnu.org/licenses/>. */
  57830. .section .nds32_vector.63, "ax"
  57831. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57832. + /* The vector size is default 4-byte for v3 architecture. */
  57833. + .vec_size 4
  57834. + .align 2
  57835. +#else
  57836. + /* The vector size is default 16-byte for other architectures. */
  57837. .vec_size 16
  57838. .align 4
  57839. +#endif
  57840. .weak _nds32_vector_63
  57841. .type _nds32_vector_63, @function
  57842. _nds32_vector_63:
  57843. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid64_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid64_4b.S
  57844. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid64_4b.S 2014-01-02 23:25:22.000000000 +0100
  57845. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid64_4b.S 1970-01-01 01:00:00.000000000 +0100
  57846. @@ -1,34 +0,0 @@
  57847. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57848. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57849. - Contributed by Andes Technology Corporation.
  57850. -
  57851. - This file is part of GCC.
  57852. -
  57853. - GCC is free software; you can redistribute it and/or modify it
  57854. - under the terms of the GNU General Public License as published
  57855. - by the Free Software Foundation; either version 3, or (at your
  57856. - option) any later version.
  57857. -
  57858. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57859. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57860. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57861. - License for more details.
  57862. -
  57863. - Under Section 7 of GPL version 3, you are granted additional
  57864. - permissions described in the GCC Runtime Library Exception, version
  57865. - 3.1, as published by the Free Software Foundation.
  57866. -
  57867. - You should have received a copy of the GNU General Public License and
  57868. - a copy of the GCC Runtime Library Exception along with this program;
  57869. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57870. - <http://www.gnu.org/licenses/>. */
  57871. -
  57872. - .section .nds32_vector.64, "ax"
  57873. - .vec_size 4
  57874. - .align 2
  57875. - .weak _nds32_vector_64_4b
  57876. - .type _nds32_vector_64_4b, @function
  57877. -_nds32_vector_64_4b:
  57878. -1:
  57879. - j 1b
  57880. - .size _nds32_vector_64_4b, .-_nds32_vector_64_4b
  57881. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid64.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid64.S
  57882. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid64.S 2014-01-02 23:25:22.000000000 +0100
  57883. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid64.S 2016-08-08 20:37:53.742588960 +0200
  57884. @@ -1,5 +1,5 @@
  57885. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57886. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57887. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57888. Contributed by Andes Technology Corporation.
  57889. This file is part of GCC.
  57890. @@ -24,8 +24,15 @@
  57891. <http://www.gnu.org/licenses/>. */
  57892. .section .nds32_vector.64, "ax"
  57893. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57894. + /* The vector size is default 4-byte for v3 architecture. */
  57895. + .vec_size 4
  57896. + .align 2
  57897. +#else
  57898. + /* The vector size is default 16-byte for other architectures. */
  57899. .vec_size 16
  57900. .align 4
  57901. +#endif
  57902. .weak _nds32_vector_64
  57903. .type _nds32_vector_64, @function
  57904. _nds32_vector_64:
  57905. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid65_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid65_4b.S
  57906. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid65_4b.S 2014-01-02 23:25:22.000000000 +0100
  57907. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid65_4b.S 1970-01-01 01:00:00.000000000 +0100
  57908. @@ -1,34 +0,0 @@
  57909. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57910. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57911. - Contributed by Andes Technology Corporation.
  57912. -
  57913. - This file is part of GCC.
  57914. -
  57915. - GCC is free software; you can redistribute it and/or modify it
  57916. - under the terms of the GNU General Public License as published
  57917. - by the Free Software Foundation; either version 3, or (at your
  57918. - option) any later version.
  57919. -
  57920. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57921. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57922. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57923. - License for more details.
  57924. -
  57925. - Under Section 7 of GPL version 3, you are granted additional
  57926. - permissions described in the GCC Runtime Library Exception, version
  57927. - 3.1, as published by the Free Software Foundation.
  57928. -
  57929. - You should have received a copy of the GNU General Public License and
  57930. - a copy of the GCC Runtime Library Exception along with this program;
  57931. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57932. - <http://www.gnu.org/licenses/>. */
  57933. -
  57934. - .section .nds32_vector.65, "ax"
  57935. - .vec_size 4
  57936. - .align 2
  57937. - .weak _nds32_vector_65_4b
  57938. - .type _nds32_vector_65_4b, @function
  57939. -_nds32_vector_65_4b:
  57940. -1:
  57941. - j 1b
  57942. - .size _nds32_vector_65_4b, .-_nds32_vector_65_4b
  57943. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid65.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid65.S
  57944. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid65.S 2014-01-02 23:25:22.000000000 +0100
  57945. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid65.S 2016-08-08 20:37:53.742588960 +0200
  57946. @@ -1,5 +1,5 @@
  57947. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57948. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57949. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  57950. Contributed by Andes Technology Corporation.
  57951. This file is part of GCC.
  57952. @@ -24,8 +24,15 @@
  57953. <http://www.gnu.org/licenses/>. */
  57954. .section .nds32_vector.65, "ax"
  57955. +#if __NDS32_ISR_VECTOR_SIZE_4__
  57956. + /* The vector size is default 4-byte for v3 architecture. */
  57957. + .vec_size 4
  57958. + .align 2
  57959. +#else
  57960. + /* The vector size is default 16-byte for other architectures. */
  57961. .vec_size 16
  57962. .align 4
  57963. +#endif
  57964. .weak _nds32_vector_65
  57965. .type _nds32_vector_65, @function
  57966. _nds32_vector_65:
  57967. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid66_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid66_4b.S
  57968. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid66_4b.S 2014-01-02 23:25:22.000000000 +0100
  57969. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid66_4b.S 1970-01-01 01:00:00.000000000 +0100
  57970. @@ -1,34 +0,0 @@
  57971. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  57972. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  57973. - Contributed by Andes Technology Corporation.
  57974. -
  57975. - This file is part of GCC.
  57976. -
  57977. - GCC is free software; you can redistribute it and/or modify it
  57978. - under the terms of the GNU General Public License as published
  57979. - by the Free Software Foundation; either version 3, or (at your
  57980. - option) any later version.
  57981. -
  57982. - GCC is distributed in the hope that it will be useful, but WITHOUT
  57983. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  57984. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  57985. - License for more details.
  57986. -
  57987. - Under Section 7 of GPL version 3, you are granted additional
  57988. - permissions described in the GCC Runtime Library Exception, version
  57989. - 3.1, as published by the Free Software Foundation.
  57990. -
  57991. - You should have received a copy of the GNU General Public License and
  57992. - a copy of the GCC Runtime Library Exception along with this program;
  57993. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  57994. - <http://www.gnu.org/licenses/>. */
  57995. -
  57996. - .section .nds32_vector.66, "ax"
  57997. - .vec_size 4
  57998. - .align 2
  57999. - .weak _nds32_vector_66_4b
  58000. - .type _nds32_vector_66_4b, @function
  58001. -_nds32_vector_66_4b:
  58002. -1:
  58003. - j 1b
  58004. - .size _nds32_vector_66_4b, .-_nds32_vector_66_4b
  58005. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid66.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid66.S
  58006. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid66.S 2014-01-02 23:25:22.000000000 +0100
  58007. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid66.S 2016-08-08 20:37:53.742588960 +0200
  58008. @@ -1,5 +1,5 @@
  58009. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58010. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58011. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58012. Contributed by Andes Technology Corporation.
  58013. This file is part of GCC.
  58014. @@ -24,8 +24,15 @@
  58015. <http://www.gnu.org/licenses/>. */
  58016. .section .nds32_vector.66, "ax"
  58017. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58018. + /* The vector size is default 4-byte for v3 architecture. */
  58019. + .vec_size 4
  58020. + .align 2
  58021. +#else
  58022. + /* The vector size is default 16-byte for other architectures. */
  58023. .vec_size 16
  58024. .align 4
  58025. +#endif
  58026. .weak _nds32_vector_66
  58027. .type _nds32_vector_66, @function
  58028. _nds32_vector_66:
  58029. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid67_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid67_4b.S
  58030. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid67_4b.S 2014-01-02 23:25:22.000000000 +0100
  58031. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid67_4b.S 1970-01-01 01:00:00.000000000 +0100
  58032. @@ -1,34 +0,0 @@
  58033. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58034. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58035. - Contributed by Andes Technology Corporation.
  58036. -
  58037. - This file is part of GCC.
  58038. -
  58039. - GCC is free software; you can redistribute it and/or modify it
  58040. - under the terms of the GNU General Public License as published
  58041. - by the Free Software Foundation; either version 3, or (at your
  58042. - option) any later version.
  58043. -
  58044. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58045. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58046. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58047. - License for more details.
  58048. -
  58049. - Under Section 7 of GPL version 3, you are granted additional
  58050. - permissions described in the GCC Runtime Library Exception, version
  58051. - 3.1, as published by the Free Software Foundation.
  58052. -
  58053. - You should have received a copy of the GNU General Public License and
  58054. - a copy of the GCC Runtime Library Exception along with this program;
  58055. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58056. - <http://www.gnu.org/licenses/>. */
  58057. -
  58058. - .section .nds32_vector.67, "ax"
  58059. - .vec_size 4
  58060. - .align 2
  58061. - .weak _nds32_vector_67_4b
  58062. - .type _nds32_vector_67_4b, @function
  58063. -_nds32_vector_67_4b:
  58064. -1:
  58065. - j 1b
  58066. - .size _nds32_vector_67_4b, .-_nds32_vector_67_4b
  58067. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid67.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid67.S
  58068. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid67.S 2014-01-02 23:25:22.000000000 +0100
  58069. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid67.S 2016-08-08 20:37:53.742588960 +0200
  58070. @@ -1,5 +1,5 @@
  58071. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58072. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58073. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58074. Contributed by Andes Technology Corporation.
  58075. This file is part of GCC.
  58076. @@ -24,8 +24,15 @@
  58077. <http://www.gnu.org/licenses/>. */
  58078. .section .nds32_vector.67, "ax"
  58079. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58080. + /* The vector size is default 4-byte for v3 architecture. */
  58081. + .vec_size 4
  58082. + .align 2
  58083. +#else
  58084. + /* The vector size is default 16-byte for other architectures. */
  58085. .vec_size 16
  58086. .align 4
  58087. +#endif
  58088. .weak _nds32_vector_67
  58089. .type _nds32_vector_67, @function
  58090. _nds32_vector_67:
  58091. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid68_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid68_4b.S
  58092. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid68_4b.S 2014-01-02 23:25:22.000000000 +0100
  58093. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid68_4b.S 1970-01-01 01:00:00.000000000 +0100
  58094. @@ -1,34 +0,0 @@
  58095. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58096. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58097. - Contributed by Andes Technology Corporation.
  58098. -
  58099. - This file is part of GCC.
  58100. -
  58101. - GCC is free software; you can redistribute it and/or modify it
  58102. - under the terms of the GNU General Public License as published
  58103. - by the Free Software Foundation; either version 3, or (at your
  58104. - option) any later version.
  58105. -
  58106. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58107. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58108. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58109. - License for more details.
  58110. -
  58111. - Under Section 7 of GPL version 3, you are granted additional
  58112. - permissions described in the GCC Runtime Library Exception, version
  58113. - 3.1, as published by the Free Software Foundation.
  58114. -
  58115. - You should have received a copy of the GNU General Public License and
  58116. - a copy of the GCC Runtime Library Exception along with this program;
  58117. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58118. - <http://www.gnu.org/licenses/>. */
  58119. -
  58120. - .section .nds32_vector.68, "ax"
  58121. - .vec_size 4
  58122. - .align 2
  58123. - .weak _nds32_vector_68_4b
  58124. - .type _nds32_vector_68_4b, @function
  58125. -_nds32_vector_68_4b:
  58126. -1:
  58127. - j 1b
  58128. - .size _nds32_vector_68_4b, .-_nds32_vector_68_4b
  58129. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid68.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid68.S
  58130. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid68.S 2014-01-02 23:25:22.000000000 +0100
  58131. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid68.S 2016-08-08 20:37:53.742588960 +0200
  58132. @@ -1,5 +1,5 @@
  58133. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58134. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58135. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58136. Contributed by Andes Technology Corporation.
  58137. This file is part of GCC.
  58138. @@ -24,8 +24,15 @@
  58139. <http://www.gnu.org/licenses/>. */
  58140. .section .nds32_vector.68, "ax"
  58141. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58142. + /* The vector size is default 4-byte for v3 architecture. */
  58143. + .vec_size 4
  58144. + .align 2
  58145. +#else
  58146. + /* The vector size is default 16-byte for other architectures. */
  58147. .vec_size 16
  58148. .align 4
  58149. +#endif
  58150. .weak _nds32_vector_68
  58151. .type _nds32_vector_68, @function
  58152. _nds32_vector_68:
  58153. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid69_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid69_4b.S
  58154. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid69_4b.S 2014-01-02 23:25:22.000000000 +0100
  58155. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid69_4b.S 1970-01-01 01:00:00.000000000 +0100
  58156. @@ -1,34 +0,0 @@
  58157. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58158. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58159. - Contributed by Andes Technology Corporation.
  58160. -
  58161. - This file is part of GCC.
  58162. -
  58163. - GCC is free software; you can redistribute it and/or modify it
  58164. - under the terms of the GNU General Public License as published
  58165. - by the Free Software Foundation; either version 3, or (at your
  58166. - option) any later version.
  58167. -
  58168. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58169. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58170. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58171. - License for more details.
  58172. -
  58173. - Under Section 7 of GPL version 3, you are granted additional
  58174. - permissions described in the GCC Runtime Library Exception, version
  58175. - 3.1, as published by the Free Software Foundation.
  58176. -
  58177. - You should have received a copy of the GNU General Public License and
  58178. - a copy of the GCC Runtime Library Exception along with this program;
  58179. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58180. - <http://www.gnu.org/licenses/>. */
  58181. -
  58182. - .section .nds32_vector.69, "ax"
  58183. - .vec_size 4
  58184. - .align 2
  58185. - .weak _nds32_vector_69_4b
  58186. - .type _nds32_vector_69_4b, @function
  58187. -_nds32_vector_69_4b:
  58188. -1:
  58189. - j 1b
  58190. - .size _nds32_vector_69_4b, .-_nds32_vector_69_4b
  58191. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid69.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid69.S
  58192. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid69.S 2014-01-02 23:25:22.000000000 +0100
  58193. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid69.S 2016-08-08 20:37:53.742588960 +0200
  58194. @@ -1,5 +1,5 @@
  58195. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58196. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58197. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58198. Contributed by Andes Technology Corporation.
  58199. This file is part of GCC.
  58200. @@ -24,8 +24,15 @@
  58201. <http://www.gnu.org/licenses/>. */
  58202. .section .nds32_vector.69, "ax"
  58203. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58204. + /* The vector size is default 4-byte for v3 architecture. */
  58205. + .vec_size 4
  58206. + .align 2
  58207. +#else
  58208. + /* The vector size is default 16-byte for other architectures. */
  58209. .vec_size 16
  58210. .align 4
  58211. +#endif
  58212. .weak _nds32_vector_69
  58213. .type _nds32_vector_69, @function
  58214. _nds32_vector_69:
  58215. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid70_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid70_4b.S
  58216. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid70_4b.S 2014-01-02 23:25:22.000000000 +0100
  58217. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid70_4b.S 1970-01-01 01:00:00.000000000 +0100
  58218. @@ -1,34 +0,0 @@
  58219. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58220. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58221. - Contributed by Andes Technology Corporation.
  58222. -
  58223. - This file is part of GCC.
  58224. -
  58225. - GCC is free software; you can redistribute it and/or modify it
  58226. - under the terms of the GNU General Public License as published
  58227. - by the Free Software Foundation; either version 3, or (at your
  58228. - option) any later version.
  58229. -
  58230. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58231. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58232. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58233. - License for more details.
  58234. -
  58235. - Under Section 7 of GPL version 3, you are granted additional
  58236. - permissions described in the GCC Runtime Library Exception, version
  58237. - 3.1, as published by the Free Software Foundation.
  58238. -
  58239. - You should have received a copy of the GNU General Public License and
  58240. - a copy of the GCC Runtime Library Exception along with this program;
  58241. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58242. - <http://www.gnu.org/licenses/>. */
  58243. -
  58244. - .section .nds32_vector.70, "ax"
  58245. - .vec_size 4
  58246. - .align 2
  58247. - .weak _nds32_vector_70_4b
  58248. - .type _nds32_vector_70_4b, @function
  58249. -_nds32_vector_70_4b:
  58250. -1:
  58251. - j 1b
  58252. - .size _nds32_vector_70_4b, .-_nds32_vector_70_4b
  58253. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid70.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid70.S
  58254. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid70.S 2014-01-02 23:25:22.000000000 +0100
  58255. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid70.S 2016-08-08 20:37:53.746589115 +0200
  58256. @@ -1,5 +1,5 @@
  58257. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58258. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58259. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58260. Contributed by Andes Technology Corporation.
  58261. This file is part of GCC.
  58262. @@ -24,8 +24,15 @@
  58263. <http://www.gnu.org/licenses/>. */
  58264. .section .nds32_vector.70, "ax"
  58265. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58266. + /* The vector size is default 4-byte for v3 architecture. */
  58267. + .vec_size 4
  58268. + .align 2
  58269. +#else
  58270. + /* The vector size is default 16-byte for other architectures. */
  58271. .vec_size 16
  58272. .align 4
  58273. +#endif
  58274. .weak _nds32_vector_70
  58275. .type _nds32_vector_70, @function
  58276. _nds32_vector_70:
  58277. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid71_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid71_4b.S
  58278. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid71_4b.S 2014-01-02 23:25:22.000000000 +0100
  58279. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid71_4b.S 1970-01-01 01:00:00.000000000 +0100
  58280. @@ -1,34 +0,0 @@
  58281. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58282. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58283. - Contributed by Andes Technology Corporation.
  58284. -
  58285. - This file is part of GCC.
  58286. -
  58287. - GCC is free software; you can redistribute it and/or modify it
  58288. - under the terms of the GNU General Public License as published
  58289. - by the Free Software Foundation; either version 3, or (at your
  58290. - option) any later version.
  58291. -
  58292. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58293. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58294. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58295. - License for more details.
  58296. -
  58297. - Under Section 7 of GPL version 3, you are granted additional
  58298. - permissions described in the GCC Runtime Library Exception, version
  58299. - 3.1, as published by the Free Software Foundation.
  58300. -
  58301. - You should have received a copy of the GNU General Public License and
  58302. - a copy of the GCC Runtime Library Exception along with this program;
  58303. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58304. - <http://www.gnu.org/licenses/>. */
  58305. -
  58306. - .section .nds32_vector.71, "ax"
  58307. - .vec_size 4
  58308. - .align 2
  58309. - .weak _nds32_vector_71_4b
  58310. - .type _nds32_vector_71_4b, @function
  58311. -_nds32_vector_71_4b:
  58312. -1:
  58313. - j 1b
  58314. - .size _nds32_vector_71_4b, .-_nds32_vector_71_4b
  58315. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid71.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid71.S
  58316. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid71.S 2014-01-02 23:25:22.000000000 +0100
  58317. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid71.S 2016-08-08 20:37:53.746589115 +0200
  58318. @@ -1,5 +1,5 @@
  58319. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58320. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58321. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58322. Contributed by Andes Technology Corporation.
  58323. This file is part of GCC.
  58324. @@ -24,8 +24,15 @@
  58325. <http://www.gnu.org/licenses/>. */
  58326. .section .nds32_vector.71, "ax"
  58327. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58328. + /* The vector size is default 4-byte for v3 architecture. */
  58329. + .vec_size 4
  58330. + .align 2
  58331. +#else
  58332. + /* The vector size is default 16-byte for other architectures. */
  58333. .vec_size 16
  58334. .align 4
  58335. +#endif
  58336. .weak _nds32_vector_71
  58337. .type _nds32_vector_71, @function
  58338. _nds32_vector_71:
  58339. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid72_4b.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid72_4b.S
  58340. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid72_4b.S 2014-01-02 23:25:22.000000000 +0100
  58341. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid72_4b.S 1970-01-01 01:00:00.000000000 +0100
  58342. @@ -1,34 +0,0 @@
  58343. -/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58344. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58345. - Contributed by Andes Technology Corporation.
  58346. -
  58347. - This file is part of GCC.
  58348. -
  58349. - GCC is free software; you can redistribute it and/or modify it
  58350. - under the terms of the GNU General Public License as published
  58351. - by the Free Software Foundation; either version 3, or (at your
  58352. - option) any later version.
  58353. -
  58354. - GCC is distributed in the hope that it will be useful, but WITHOUT
  58355. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  58356. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  58357. - License for more details.
  58358. -
  58359. - Under Section 7 of GPL version 3, you are granted additional
  58360. - permissions described in the GCC Runtime Library Exception, version
  58361. - 3.1, as published by the Free Software Foundation.
  58362. -
  58363. - You should have received a copy of the GNU General Public License and
  58364. - a copy of the GCC Runtime Library Exception along with this program;
  58365. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  58366. - <http://www.gnu.org/licenses/>. */
  58367. -
  58368. - .section .nds32_vector.72, "ax"
  58369. - .vec_size 4
  58370. - .align 2
  58371. - .weak _nds32_vector_72_4b
  58372. - .type _nds32_vector_72_4b, @function
  58373. -_nds32_vector_72_4b:
  58374. -1:
  58375. - j 1b
  58376. - .size _nds32_vector_72_4b, .-_nds32_vector_72_4b
  58377. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid72.S gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid72.S
  58378. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/vec_vid72.S 2014-01-02 23:25:22.000000000 +0100
  58379. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/vec_vid72.S 2016-08-08 20:37:53.746589115 +0200
  58380. @@ -1,5 +1,5 @@
  58381. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58382. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58383. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58384. Contributed by Andes Technology Corporation.
  58385. This file is part of GCC.
  58386. @@ -24,8 +24,15 @@
  58387. <http://www.gnu.org/licenses/>. */
  58388. .section .nds32_vector.72, "ax"
  58389. +#if __NDS32_ISR_VECTOR_SIZE_4__
  58390. + /* The vector size is default 4-byte for v3 architecture. */
  58391. + .vec_size 4
  58392. + .align 2
  58393. +#else
  58394. + /* The vector size is default 16-byte for other architectures. */
  58395. .vec_size 16
  58396. .align 4
  58397. +#endif
  58398. .weak _nds32_vector_72
  58399. .type _nds32_vector_72, @function
  58400. _nds32_vector_72:
  58401. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/isr-library/wrh.S gcc-4.9.4/libgcc/config/nds32/isr-library/wrh.S
  58402. --- gcc-4.9.4.orig/libgcc/config/nds32/isr-library/wrh.S 2014-01-02 23:25:22.000000000 +0100
  58403. +++ gcc-4.9.4/libgcc/config/nds32/isr-library/wrh.S 2016-08-08 20:37:53.746589115 +0200
  58404. @@ -1,5 +1,5 @@
  58405. /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
  58406. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58407. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58408. Contributed by Andes Technology Corporation.
  58409. This file is part of GCC.
  58410. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib1asmsrc-mculib.S gcc-4.9.4/libgcc/config/nds32/lib1asmsrc-mculib.S
  58411. --- gcc-4.9.4.orig/libgcc/config/nds32/lib1asmsrc-mculib.S 2014-01-02 23:25:22.000000000 +0100
  58412. +++ gcc-4.9.4/libgcc/config/nds32/lib1asmsrc-mculib.S 2016-08-08 20:37:53.750589269 +0200
  58413. @@ -1,5 +1,5 @@
  58414. /* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
  58415. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  58416. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  58417. Contributed by Andes Technology Corporation.
  58418. This file is part of GCC.
  58419. @@ -33,278 +33,281 @@
  58420. #ifdef L_addsub_sf
  58421. +#define VALUA $r2 // A<<1
  58422. +#define VALUB $r3 // B<<1
  58423. +#define EXPOA $r4 // exponent(A)
  58424. +#ifdef __NDS32_REDUCE_REGS__
  58425. +#define EXPOB $r8 // exponent(B)
  58426. +#define MANTA $r6 // mantissa(A) related
  58427. +#define MANTB $r9 // mantissa(B) related
  58428. +#define SIGN $r7 // 0x80000000
  58429. +#else
  58430. +#define EXPOB $r18 // exponent(B)
  58431. +#define MANTA $r16 // mantissa(A) related
  58432. +#define MANTB $r19 // mantissa(B) related
  58433. +#define SIGN $r17 // 0x80000000
  58434. +#endif
  58435. +#define W1 $r5
  58436. +
  58437. .text
  58438. .align 2
  58439. .global __subsf3
  58440. .type __subsf3, @function
  58441. __subsf3:
  58442. - push $lp
  58443. - pushm $r6, $r9
  58444. -
  58445. - move $r2, #0x80000000
  58446. - xor $r1, $r1, $r2
  58447. -
  58448. - j .Lsfpadd
  58449. +#ifdef __NDS32_EXT_PERF__
  58450. + btgl $r1, $r1, 31
  58451. +#else
  58452. + move $r2, #0x80000000
  58453. + xor $r1, $r1, $r2 ! A-B is now A+(-B)
  58454. +#endif
  58455. .global __addsf3
  58456. .type __addsf3, @function
  58457. __addsf3:
  58458. - push $lp
  58459. - pushm $r6, $r9
  58460. -.Lsfpadd:
  58461. - srli $r5, $r0, #23
  58462. - andi $r5, $r5, #0xff
  58463. - srli $r7, $r1, #23
  58464. - andi $r7, $r7, #0xff
  58465. - move $r3, #0x80000000
  58466. - slli $r4, $r0, #8
  58467. - or $r4, $r4, $r3
  58468. - slli $r6, $r1, #8
  58469. - or $r6, $r6, $r3
  58470. -
  58471. - addi $r9, $r5, #-1
  58472. - slti $r15, $r9, #0xfe
  58473. - beqzs8 .LEspecA
  58474. + slli VALUA, $r0, 1 ! A<<1
  58475. +#ifdef __NDS32_REDUCE_REGS__
  58476. + smw.adm $r6, [$sp], $r9, 0
  58477. +#endif
  58478. +
  58479. + slli VALUB, $r1, 1 ! B<<1
  58480. + move SIGN, #0x80000000
  58481. + slt $r15, VALUA, VALUB ! absolute value(A)<absolute value(B)?
  58482. + beqz $r15, .LEcont
  58483. + move W1, $r0 ! yes, swap A and B
  58484. + move $r0, $r1
  58485. + move $r1, W1
  58486. + slli VALUA, $r0, 1 ! A<<1
  58487. + slli VALUB, $r1, 1 ! B<<1
  58488. +
  58489. + ! ---------------------------------------------------------------------
  58490. + ! absolute value(A) >= absolute value(B)
  58491. + ! ---------------------------------------------------------------------
  58492. +.LEcont:
  58493. + xor $r1, $r1, $r0
  58494. + and $r1, $r1, SIGN ! sign(A xor B)
  58495. + srli EXPOA, VALUA, 24 ! exponent(A)
  58496. + srli EXPOB, VALUB, 24 ! exponent(B)
  58497. + slli MANTA, VALUA, 7 ! mantissa(A)<<8
  58498. + slli MANTB, VALUB, 7 ! mantissa(B)<<8
  58499. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  58500. + beqc EXPOA, 0xff, .LEinfnan ! A is inf or NaN, goto .LEinfnan
  58501. +#else
  58502. + move W1, #0xff
  58503. + beq W1, EXPOA, .LEinfnan ! A is inf or NaN, goto .LEinfnan
  58504. +#endif
  58505. + ! A is finite and thus B can only be finite
  58506. + beqz VALUA, .LEzeroP ! A is zero, simply return zero
  58507. + beqz VALUB, .LEretA ! B is zero, simply return A
  58508. + sub W1, EXPOA, EXPOB ! exponent(A)-exponent(B)
  58509. + slti $r15, EXPOA, #0x2
  58510. + bnez $r15, .LElab2 ! exponent(A) is 0 or 1, goto .LElab2
  58511. + sltsi $r15, W1, #0x20
  58512. + beqz $r15, .LEretA ! B is insignificant, simply return A
  58513. + or MANTA, MANTA, SIGN ! decimal-part(A)
  58514. + beqz EXPOB, .LElab1
  58515. + or MANTB, MANTB, SIGN ! decimal-part(B)
  58516. .LElab1:
  58517. - addi $r9, $r7, #-1
  58518. - slti $r15, $r9, #0xfe
  58519. - beqzs8 .LEspecB
  58520. + addi $r15, W1, -1
  58521. + cmovz W1, $r15, EXPOB
  58522. + move $r15, MANTB
  58523. + srl MANTB, MANTB, W1
  58524. + sll W1, MANTB, W1
  58525. + beq W1, $r15, .LElab2
  58526. + ori MANTB, MANTB, #2 ! B is quite small comapre to A
  58527. .LElab2:
  58528. - sub $r8, $r5, $r7
  58529. - sltsi $r15, $r8, #0
  58530. - bnezs8 .Li1
  58531. - sltsi $r15, $r8, #0x20
  58532. - bnezs8 .Li2
  58533. - move $r6, #2
  58534. - j .Le1
  58535. -.Li2:
  58536. - move $r2, $r6
  58537. - srl $r6, $r6, $r8
  58538. - sll $r9, $r6, $r8
  58539. - beq $r9, $r2, .Le1
  58540. - ori $r6, $r6, #2
  58541. - j .Le1
  58542. -.Li1:
  58543. - move $r5, $r7
  58544. - subri $r8, $r8, #0
  58545. - sltsi $r15, $r8, #0x20
  58546. - bnezs8 .Li4
  58547. - move $r4, #2
  58548. - j .Le1
  58549. -.Li4:
  58550. - move $r2, $r4
  58551. - srl $r4, $r4, $r8
  58552. - sll $r9, $r4, $r8
  58553. - beq $r9, $r2, .Le1
  58554. - ori $r4, $r4, #2
  58555. -
  58556. -.Le1:
  58557. - and $r8, $r0, $r3
  58558. - xor $r9, $r8, $r1
  58559. - sltsi $r15, $r9, #0
  58560. - bnezs8 .LEsub1
  58561. -
  58562. - #ADD($r4, $r6)
  58563. - add $r4, $r4, $r6
  58564. - slt $r15, $r4, $r6
  58565. - beqzs8 .LEres
  58566. - andi $r9, $r4, #1
  58567. - beqz $r9, .Li7
  58568. - ori $r4, $r4, #2
  58569. -.Li7:
  58570. - srli $r4, $r4, #1
  58571. - addi $r5, $r5, #1
  58572. - subri $r15, $r5, #0xff
  58573. - bnezs8 .LEres
  58574. - move $r4, #0
  58575. - j .LEres
  58576. + bnez $r1, .LEsub ! different sign, do subtraction
  58577. -.LEsub1:
  58578. - #SUB($r4, $r6)
  58579. - move $r15, $r4
  58580. - sub $r4, $r4, $r6
  58581. - slt $r15, $r15, $r4
  58582. - beqzs8 .Li9
  58583. - subri $r4, $r4, #0
  58584. - xor $r8, $r8, $r3
  58585. - j .Le9
  58586. -.Li9:
  58587. - beqz $r4, .LEzer
  58588. -.Le9:
  58589. -#ifdef __NDS32_PERF_EXT__
  58590. - clz $r2, $r4
  58591. -#else
  58592. - pushm $r0, $r1
  58593. - pushm $r3, $r5
  58594. - move $r0, $r4
  58595. - bal __clzsi2
  58596. - move $r2, $r0
  58597. - popm $r3, $r5
  58598. - popm $r0, $r1
  58599. -#endif
  58600. - sub $r5, $r5, $r2
  58601. - sll $r4, $r4, $r2
  58602. + ! ---------------------------------------------------------------------
  58603. + ! same sign, do addition
  58604. + ! ---------------------------------------------------------------------
  58605. + add MANTA, MANTA, MANTB
  58606. + slt $r15, MANTA, MANTB
  58607. + beqz $r15, .LEaddnoover ! no overflow, goto .LEaddnoover
  58608. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  58609. + beqc EXPOA, #0xfe, .LEinf
  58610. +#else
  58611. + subri $r15, EXPOA, #0xfe
  58612. + beqz $r15, .LEinf
  58613. +#endif
  58614. + andi $r15, MANTA, #1
  58615. + ori W1, MANTA, #2
  58616. + cmovn MANTA, W1, $r15
  58617. + srli MANTA, MANTA, #1
  58618. + addi EXPOA, EXPOA, #1
  58619. + b .LEround
  58620. +
  58621. +.LEaddnoover:
  58622. + bnez EXPOA, .LEround ! special handling when exponent(A) is zero
  58623. +
  58624. +.LEdenorm:
  58625. + srli MANTA, MANTA, #8 ! 0x008nnnnn-0x00fnnnnn
  58626. + b .LEpack
  58627. +
  58628. + ! ---------------------------------------------------------------------
  58629. + ! different sign, do subtraction
  58630. + ! ---------------------------------------------------------------------
  58631. +.LEsub:
  58632. + beq VALUA, VALUB, .LEzero
  58633. + slt $r15, MANTA, MANTB
  58634. + beqz $r15, .LEsub2
  58635. + srli MANTB, MANTB, 1
  58636. + addi EXPOA, EXPOA, -1
  58637. +
  58638. +.LEsub2:
  58639. + sub MANTA, MANTA, MANTB
  58640. + slti $r15, EXPOA, 2
  58641. + bnez $r15, .LEdenorm ! only when exponent(A,B) is (0,0) or (1,0/1)
  58642. +#ifdef __NDS32_EXT_PERF__
  58643. + clz W1, MANTA
  58644. + slt $r15, W1, EXPOA
  58645. + subri $r15, $r15, #1
  58646. + min W1, W1, EXPOA
  58647. + sub EXPOA, EXPOA, W1
  58648. + sub W1, W1, $r15
  58649. + sll MANTA, MANTA, W1
  58650. +#else
  58651. + b .LEloopC2
  58652. +
  58653. +.LEloopC:
  58654. + addi EXPOA, EXPOA, #-1
  58655. + beqz EXPOA, .LEround
  58656. + add MANTA, MANTA, MANTA
  58657. +
  58658. +.LEloopC2:
  58659. + slt $r15, MANTA, SIGN
  58660. + bnez $r15, .LEloopC
  58661. +#endif
  58662. +
  58663. + ! ---------------------------------------------------------------------
  58664. + ! do rounding
  58665. + ! ---------------------------------------------------------------------
  58666. +.LEround:
  58667. + addi MANTA, MANTA, #128
  58668. + slti $r15, MANTA, #128
  58669. + add EXPOA, EXPOA, $r15
  58670. + srli W1, MANTA, 8
  58671. + andi W1, W1, 1
  58672. + sub MANTA, MANTA, W1
  58673. +
  58674. + ! ---------------------------------------------------------------------
  58675. + ! pack result
  58676. + ! ---------------------------------------------------------------------
  58677. + slli MANTA, MANTA, #1 ! shift out implied 1
  58678. + srli MANTA, MANTA, #9
  58679. + slli $r1, EXPOA, #23
  58680. + or MANTA, MANTA, $r1
  58681. +.LEpack:
  58682. + and $r0, $r0, SIGN
  58683. + or $r0, $r0, MANTA
  58684. -.LEres:
  58685. - blez $r5, .LEund
  58686. +.LEretA:
  58687. +.LEret:
  58688. +#ifdef __NDS32_REDUCE_REGS__
  58689. + lmw.bim $r6, [$sp], $r9, 0
  58690. +#endif
  58691. + ret5 $lp
  58692. -.LElab12:
  58693. - #ADD($r4, $0x80)
  58694. - move $r15, #0x80
  58695. - add $r4, $r4, $r15
  58696. - slt $r15, $r4, $r15
  58697. + ! 0.0f and -0.0f handling: both A and B are zeroes
  58698. +.LEzeroP:
  58699. + beqz $r1, .LEretA ! A and B same sign: return A
  58700. - #ADDC($r5, $0x0)
  58701. - add $r5, $r5, $r15
  58702. - srli $r9, $r4, #8
  58703. - andi $r9, $r9, #1
  58704. - sub $r4, $r4, $r9
  58705. - slli $r4, $r4, #1
  58706. - srli $r4, $r4, #9
  58707. - slli $r9, $r5, #23
  58708. - or $r4, $r4, $r9
  58709. - or $r0, $r4, $r8
  58710. -
  58711. -.LE999:
  58712. - popm $r6, $r9
  58713. - pop $lp
  58714. - ret5 $lp
  58715. +.LEzero:
  58716. + move $r0, #0 ! return +0.0f
  58717. + b .LEret
  58718. -.LEund:
  58719. - subri $r2, $r5, #1
  58720. - slti $r15, $r2, #0x20
  58721. - beqzs8 .LEzer
  58722. - move $r9, #0x80000000
  58723. - or $r4, $r4, $r9
  58724. - subri $r9, $r2, #0x20
  58725. - sll $r5, $r4, $r9
  58726. - srl $r4, $r4, $r2
  58727. - beqz $r5, .Li10
  58728. - ori $r4, $r4, #1
  58729. -.Li10:
  58730. - move $r5, #0
  58731. - addi $r9, $r4, #0x80
  58732. - sltsi $r15, $r9, #0
  58733. - beqzs8 .LElab12
  58734. - move $r5, #1
  58735. - j .LElab12
  58736. -
  58737. -.LEspecA:
  58738. - bnez $r5, .Li12
  58739. - add $r4, $r4, $r4
  58740. - beqz $r4, .Li13
  58741. -#ifdef __NDS32_PERF_EXT__
  58742. - clz $r8, $r4
  58743. -#else
  58744. - pushm $r0, $r5
  58745. - move $r0, $r4
  58746. - bal __clzsi2
  58747. - move $r8, $r0
  58748. - popm $r0, $r5
  58749. -#endif
  58750. - sub $r5, $r5, $r8
  58751. - sll $r4, $r4, $r8
  58752. - j .LElab1
  58753. -.Li13:
  58754. - subri $r15, $r7, #0xff
  58755. - beqzs8 .LEspecB
  58756. - move $r9, #0x80000000
  58757. - bne $r1, $r9, .LEretB
  58758. -.Li12:
  58759. - add $r9, $r4, $r4
  58760. - bnez $r9, .LEnan
  58761. - subri $r15, $r7, #0xff
  58762. - bnezs8 .LEretA
  58763. - xor $r9, $r0, $r1
  58764. - sltsi $r15, $r9, #0
  58765. - bnezs8 .LEnan
  58766. - j .LEretB
  58767. -
  58768. -.LEspecB:
  58769. - bnez $r7, .Li15
  58770. - add $r6, $r6, $r6
  58771. - beqz $r6, .LEretA
  58772. -#ifdef __NDS32_PERF_EXT__
  58773. - clz $r8, $r6
  58774. + ! ---------------------------------------------------------------------
  58775. + ! exponent(A) is 0xff: A is inf or NaN
  58776. + ! ---------------------------------------------------------------------
  58777. +.LEinfnan:
  58778. + bne MANTA, SIGN, .LEnan ! A is NaN, goto .LEnan
  58779. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  58780. + bnec EXPOB, #0xff, .LEretA ! B is finite, return A
  58781. #else
  58782. - pushm $r0, $r5
  58783. - move $r0, $r6
  58784. - bal __clzsi2
  58785. - move $r8, $r0
  58786. - popm $r0, $r5
  58787. + bne W1, EXPOB, .LEretA ! B is finite, return A
  58788. #endif
  58789. - sub $r7, $r7, $r8
  58790. - sll $r6, $r6, $r8
  58791. - j .LElab2
  58792. -.Li15:
  58793. - add $r9, $r6, $r6
  58794. - bnez $r9, .LEnan
  58795. -
  58796. -.LEretB:
  58797. - move $r0, $r1
  58798. - j .LE999
  58799. -
  58800. -.LEretA:
  58801. - j .LE999
  58802. -.LEzer:
  58803. - move $r0, #0
  58804. - j .LE999
  58805. + ! both A and B are inf
  58806. + beqz $r1, .LEretA ! same sign, return inf
  58807. .LEnan:
  58808. - move $r0, #0xffc00000
  58809. - j .LE999
  58810. + move $r0, #0xffc00000 ! return NaN
  58811. + b .LEret
  58812. +
  58813. +.LEinf:
  58814. + move MANTA, 0x7f800000 ! return inf
  58815. + b .LEpack
  58816. .size __subsf3, .-__subsf3
  58817. .size __addsf3, .-__addsf3
  58818. #endif /* L_addsub_sf */
  58819. -#ifdef L_sf_to_si
  58820. +#ifdef L_fixsfsi
  58821. +
  58822. +#define VALUA $r1 // A<<1
  58823. +#define EXPOA VALUA // exponent(A)
  58824. +#define MANTA $r2 // mantissa(A) related
  58825. +#define W0 $r4
  58826. +#define W1 $r5
  58827. .text
  58828. .align 2
  58829. .global __fixsfsi
  58830. .type __fixsfsi, @function
  58831. __fixsfsi:
  58832. - push $lp
  58833. -
  58834. - slli $r1, $r0, #8
  58835. - move $r3, #0x80000000
  58836. - or $r1, $r1, $r3
  58837. - srli $r3, $r0, #23
  58838. - andi $r3, $r3, #0xff
  58839. - subri $r2, $r3, #0x9e
  58840. - blez $r2, .LJspec
  58841. - sltsi $r15, $r2, #0x20
  58842. - bnezs8 .Li42
  58843. - move $r0, #0
  58844. - j .LJ999
  58845. -.Li42:
  58846. - srl $r1, $r1, $r2
  58847. - sltsi $r15, $r0, #0
  58848. - beqzs8 .Li43
  58849. - subri $r1, $r1, #0
  58850. -.Li43:
  58851. - move $r0, $r1
  58852. -
  58853. -.LJ999:
  58854. - pop $lp
  58855. - ret5 $lp
  58856. -
  58857. -.LJspec:
  58858. - move $r3, #0x7f800000
  58859. - slt $r15, $r3, $r0
  58860. - beqzs8 .Li44
  58861. - move $r0, #0x80000000
  58862. - j .LJ999
  58863. -.Li44:
  58864. - move $r0, #0x7fffffff
  58865. - j .LJ999
  58866. +#if defined(__NDS32_EXT_FPU_SP)
  58867. + fs2si.z $fs0, $fs0
  58868. + fmfsr $r0, $fs0
  58869. + ret5 $lp
  58870. +#else
  58871. + slli VALUA, $r0, #1
  58872. + slli MANTA, VALUA, #7
  58873. + srli EXPOA, VALUA, #24
  58874. + subri EXPOA, EXPOA, #0x9e
  58875. +#if defined(__OPTIMIZE_SIZE__)||!defined(__NDS32_EXT_PERF__)
  58876. + move W1, #0x80000000
  58877. +#endif
  58878. + blez EXPOA, .LJover ! number is too big
  58879. + sltsi $r15, EXPOA, #0x20
  58880. + beqz $r15, .LJzero ! number is too small
  58881. +
  58882. +#if defined(__NDS32_EXT_PERF__)&&!defined(__OPTIMIZE_SIZE__)
  58883. + bset MANTA, MANTA, 31
  58884. +#else
  58885. + or MANTA, MANTA, W1
  58886. +#endif
  58887. + srl MANTA, MANTA, EXPOA
  58888. + sltsi $r15, $r0, #0
  58889. + subri $r0, MANTA, #0
  58890. + cmovz $r0, MANTA, $r15
  58891. + ret5 $lp
  58892. +
  58893. +.LJzero:
  58894. + move $r0, #0
  58895. + ret5 $lp
  58896. +
  58897. +.LJover:
  58898. + move W0, #0x7f800000
  58899. + slt $r15, W0, $r0
  58900. + beqzs8 .LJnan
  58901. +#if defined(__NDS32_EXT_PERF__)&&!defined(__OPTIMIZE_SIZE__)
  58902. + move $r0, #0x80000000
  58903. +#else
  58904. + move $r0, W1
  58905. +#endif
  58906. + ret5 $lp
  58907. +.LJnan:
  58908. +#if defined(__NDS32_EXT_PERF__)&&!defined(__OPTIMIZE_SIZE__)
  58909. + move $r0, #0x7fffffff
  58910. +#else
  58911. + addi $r0, W1, -1
  58912. +#endif
  58913. + ret5 $lp
  58914. +#endif
  58915. .size __fixsfsi, .-__fixsfsi
  58916. -#endif /* L_sf_to_si */
  58917. +#endif /* L_fixsfsi */
  58918. @@ -416,66 +419,72 @@
  58919. #ifdef L_divdi3
  58920. - !--------------------------------------
  58921. - #ifdef __big_endian__
  58922. - #define V1H $r0
  58923. - #define V1L $r1
  58924. - #define V2H $r2
  58925. - #define V2L $r3
  58926. - #else
  58927. - #define V1H $r1
  58928. - #define V1L $r0
  58929. - #define V2H $r3
  58930. - #define V2L $r2
  58931. - #endif
  58932. - !--------------------------------------
  58933. +#ifdef __big_endian__
  58934. +#define P1H $r0
  58935. +#define P1L $r1
  58936. +#define P2H $r2
  58937. +#define P2L $r3
  58938. +#else
  58939. +#define P1H $r1
  58940. +#define P1L $r0
  58941. +#define P2H $r3
  58942. +#define P2L $r2
  58943. +#endif
  58944. +
  58945. .text
  58946. .align 2
  58947. .globl __divdi3
  58948. .type __divdi3, @function
  58949. __divdi3:
  58950. - ! prologue
  58951. -#ifdef __NDS32_ISA_V3M__
  58952. - push25 $r10, 0
  58953. -#else
  58954. - smw.adm $r6, [$sp], $r10, 2
  58955. -#endif
  58956. - ! end of prologue
  58957. - move $r8, V1L
  58958. - move $r9, V1H
  58959. - move $r6, V2L
  58960. - move $r7, V2H
  58961. - movi $r10, 0
  58962. - bgez V1H, .L80
  58963. - bal __negdi2
  58964. - move $r8, V1L
  58965. - move $r9, V1H
  58966. - movi $r10, -1
  58967. + ! =====================================================================
  58968. + ! uint64_t __divdi3(uint64_t n, uint64-t d)
  58969. + !
  58970. + ! This function divides n by d and returns the quotient.
  58971. + !
  58972. + ! stack allocation:
  58973. + ! sp+8 +-----------------------+
  58974. + ! | $lp |
  58975. + ! sp+4 +-----------------------+
  58976. + ! | $r6 |
  58977. + ! sp +-----------------------+
  58978. + ! =====================================================================
  58979. + smw.adm $r6, [$sp], $r6, 2
  58980. +
  58981. + xor $r6, P1H, P2H
  58982. + srai45 $r6, 31 ! signof(numerator xor denominator)
  58983. + ! abs(denominator)
  58984. + bgez P2H, .L80
  58985. + neg P2H, P2H
  58986. + beqz P2L, .L80
  58987. + neg P2L, P2L
  58988. + addi P2H, P2H, -1
  58989. +
  58990. .L80:
  58991. - bgez $r7, .L81
  58992. - move V1L, $r6
  58993. - move V1H, $r7
  58994. - bal __negdi2
  58995. - move $r6, V1L
  58996. - move $r7, V1H
  58997. - nor $r10, $r10, $r10
  58998. + ! abs(numerator)
  58999. + bgez P1H, .L81
  59000. + neg P1H, P1H
  59001. + beqz P1L, .L81
  59002. + neg P1L, P1L
  59003. + addi P1H, P1H, -1
  59004. +
  59005. .L81:
  59006. - move V2L, $r6
  59007. - move V2H, $r7
  59008. - move V1L, $r8
  59009. - move V1H, $r9
  59010. - movi $r4, 0
  59011. + ! abs(numerator) / abs(denominator)
  59012. + movi $r4, 0 ! ignore remainder
  59013. bal __udivmoddi4
  59014. - beqz $r10, .L82
  59015. - bal __negdi2
  59016. + ! numerator / denominator
  59017. + beqz $r6, .L82
  59018. + or $r4, P1H, P1L
  59019. + beqz $r4, .L82
  59020. + neg P1H, P1H
  59021. + beqz P1L, .L82
  59022. + neg P1L, P1L
  59023. + addi P1H, P1H, -1
  59024. +
  59025. + ! to eliminate unaligned branch target
  59026. + .align 2
  59027. .L82:
  59028. - ! epilogue
  59029. -#ifdef __NDS32_ISA_V3M__
  59030. - pop25 $r10, 0
  59031. -#else
  59032. - lmw.bim $r6, [$sp], $r10, 2
  59033. + lmw.bim $r6, [$sp], $r6, 2
  59034. ret
  59035. -#endif
  59036. .size __divdi3, .-__divdi3
  59037. #endif /* L_divdi3 */
  59038. @@ -500,7 +509,7 @@
  59039. cmovn $r0, $r4, $r5 ! $r0 <- |a|
  59040. ! ---------------------------------------------------------------------
  59041. ! if (b < 0)
  59042. -#ifndef __NDS32_PERF_EXT__
  59043. +#ifndef __NDS32_EXT_PERF__
  59044. ! ---------------------------------------------------------------------
  59045. bgez $r1, .L3 ! if b >= 0, skip
  59046. ! ---------------------------------------------------------------------
  59047. @@ -512,20 +521,20 @@
  59048. !!res = udivmodsi4 (a, b, 1);
  59049. ! if (den != 0)
  59050. ! ---------------------------------------------------------------------
  59051. -#else /* __NDS32_PERF_EXT__ */
  59052. +#else /* __NDS32_EXT_PERF__ */
  59053. ! b = -b;
  59054. !!res = udivmodsi4 (a, b, 1);
  59055. ! if (den != 0)
  59056. ! ---------------------------------------------------------------------
  59057. abs $r1, $r1 ! $r1 <- |b|
  59058. -#endif /* __NDS32_PERF_EXT__ */
  59059. +#endif /* __NDS32_EXT_PERF__ */
  59060. beqz $r1, .L1 ! if den == 0, skip
  59061. ! ---------------------------------------------------------------------
  59062. ! { bit = 1;
  59063. ! res = 0;
  59064. ! ---------------------------------------------------------------------
  59065. movi $r4, 1 ! $r4 <- bit = 1
  59066. -#ifndef __OPTIMIZE_SIZE__
  59067. +#if !(defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__))
  59068. .L6:
  59069. #endif
  59070. ! ---------------------------------------------------------------------
  59071. @@ -587,102 +596,81 @@
  59072. #ifdef L_moddi3
  59073. - !--------------------------------------
  59074. - #ifdef __big_endian__
  59075. - #define V1H $r0
  59076. - #define V1L $r1
  59077. - #define V2H $r2
  59078. - #define V2L $r3
  59079. - #else
  59080. - #define V1H $r1
  59081. - #define V1L $r0
  59082. - #define V2H $r3
  59083. - #define V2L $r2
  59084. - #endif
  59085. - !--------------------------------------
  59086. +#ifdef __big_endian__
  59087. +#define P1H $r0
  59088. +#define P1L $r1
  59089. +#define P2H $r2
  59090. +#define P2L $r3
  59091. +#define OFFSET_H 0
  59092. +#define OFFSET_L 4
  59093. +#else
  59094. +#define P1H $r1
  59095. +#define P1L $r0
  59096. +#define P2H $r3
  59097. +#define P2L $r2
  59098. +#define OFFSET_H 4
  59099. +#define OFFSET_L 0
  59100. +#endif
  59101. +
  59102. .text
  59103. .align 2
  59104. .globl __moddi3
  59105. .type __moddi3, @function
  59106. __moddi3:
  59107. ! =====================================================================
  59108. + ! uint64_t __moddi3(uint64_t n, uint64-t d)
  59109. + !
  59110. + ! This function divides n by d and returns the remainder.
  59111. + !
  59112. ! stack allocation:
  59113. - ! sp+32 +-----------------------+
  59114. - ! | $lp |
  59115. - ! sp+28 +-----------------------+
  59116. - ! | $r6 - $r10 |
  59117. + ! sp+16 +-----------------------+
  59118. + ! | remainder |
  59119. ! sp+8 +-----------------------+
  59120. - ! | |
  59121. + ! | $lp |
  59122. ! sp+4 +-----------------------+
  59123. - ! | |
  59124. + ! | $r6 |
  59125. ! sp +-----------------------+
  59126. ! =====================================================================
  59127. - ! prologue
  59128. -#ifdef __NDS32_ISA_V3M__
  59129. - push25 $r10, 8
  59130. -#else
  59131. - smw.adm $r6, [$sp], $r10, 2
  59132. - addi $sp, $sp, -8
  59133. -#endif
  59134. - ! end of prologue
  59135. - !------------------------------------------
  59136. - ! __moddi3 (DWtype u, DWtype v)
  59137. - ! {
  59138. - ! word_type c = 0;
  59139. - ! DWunion uu = {.ll = u};
  59140. - ! DWunion vv = {.ll = v};
  59141. - ! DWtype w;
  59142. - ! if (uu.s.high < 0)
  59143. - ! c = ~c,
  59144. - ! uu.ll = -uu.ll;
  59145. - !---------------------------------------------
  59146. - move $r8, V1L
  59147. - move $r9, V1H
  59148. - move $r6, V2L
  59149. - move $r7, V2H
  59150. - movi $r10, 0 ! r10 = c = 0
  59151. - bgez V1H, .L80 ! if u > 0 , go L80
  59152. - bal __negdi2
  59153. - move $r8, V1L
  59154. - move $r9, V1H
  59155. - movi $r10, -1 ! r10 = c = ~c
  59156. - !------------------------------------------------
  59157. - ! if (vv.s.high < 0)
  59158. - ! vv.ll = -vv.ll;
  59159. - !----------------------------------------------
  59160. + addi $sp, $sp, -16
  59161. + smw.bi $r6, [$sp], $r6, 2
  59162. +
  59163. + srai $r6, P1H, 31 ! signof(numerator)
  59164. + ! abs(denominator)
  59165. + bgez P2H, .L80
  59166. + neg P2H, P2H
  59167. + beqz P2L, .L80
  59168. + neg P2L, P2L
  59169. + addi P2H, P2H, -1
  59170. +
  59171. .L80:
  59172. - bgez $r7, .L81 ! if v > 0 , go L81
  59173. - move V1L, $r6
  59174. - move V1H, $r7
  59175. - bal __negdi2
  59176. - move $r6, V1L
  59177. - move $r7, V1H
  59178. - !------------------------------------------
  59179. - ! (void) __udivmoddi4 (uu.ll, vv.ll, &w);
  59180. - ! if (c)
  59181. - ! w = -w;
  59182. - ! return w;
  59183. - !-----------------------------------------
  59184. + ! abs(numerator)
  59185. + beqz $r6, .L81
  59186. + neg P1H, P1H
  59187. + beqz P1L, .L81
  59188. + neg P1L, P1L
  59189. + addi P1H, P1H, -1
  59190. +
  59191. .L81:
  59192. - move V2L, $r6
  59193. - move V2H, $r7
  59194. - move V1L, $r8
  59195. - move V1H, $r9
  59196. - addi $r4, $sp, 0
  59197. + ! abs(numerator) % abs(denominator)
  59198. + addi $r4, $sp, 8
  59199. bal __udivmoddi4
  59200. - lwi $r0, [$sp+(0)] ! le: sp + 0 is low, be: sp + 0 is high
  59201. - lwi $r1, [$sp+(4)] ! le: sp + 4 is low, be: sp + 4 is high
  59202. - beqz $r10, .L82
  59203. - bal __negdi2
  59204. + ! numerator % denominator
  59205. + lwi P1L, [$sp+(8+OFFSET_L)]
  59206. + lwi P1H, [$sp+(8+OFFSET_H)]
  59207. + beqz $r6, .L82
  59208. + or $r4, P1H, P1L
  59209. + beqz $r4, .L82
  59210. + neg P1H, P1H
  59211. + beqz P1L, .L82
  59212. + neg P1L, P1L
  59213. + addi P1H, P1H, -1
  59214. +
  59215. + ! to eliminate unaligned branch target
  59216. + .align 2
  59217. .L82:
  59218. - ! epilogue
  59219. -#ifdef __NDS32_ISA_V3M__
  59220. - pop25 $r10, 8
  59221. -#else
  59222. - addi $sp, $sp, 8
  59223. - lmw.bim $r6, [$sp], $r10, 2
  59224. + lmw.bi $r6, [$sp], $r6, 2
  59225. + addi $sp, $sp, 16
  59226. ret
  59227. -#endif
  59228. .size __moddi3, .-__moddi3
  59229. #endif /* L_moddi3 */
  59230. @@ -822,197 +810,302 @@
  59231. #ifdef L_udivdi3
  59232. - !--------------------------------------
  59233. - #ifdef __big_endian__
  59234. - #define V1H $r0
  59235. - #define V1L $r1
  59236. - #define V2H $r2
  59237. - #define V2L $r3
  59238. - #else
  59239. - #define V1H $r1
  59240. - #define V1L $r0
  59241. - #define V2H $r3
  59242. - #define V2L $r2
  59243. - #endif
  59244. - !--------------------------------------
  59245. -
  59246. .text
  59247. .align 2
  59248. .globl __udivdi3
  59249. .type __udivdi3, @function
  59250. __udivdi3:
  59251. - ! prologue
  59252. -#ifdef __NDS32_ISA_V3M__
  59253. - push25 $r8, 0
  59254. -#else
  59255. - smw.adm $r6, [$sp], $r8, 2
  59256. -#endif
  59257. - ! end of prologue
  59258. - movi $r4, 0
  59259. - bal __udivmoddi4
  59260. - ! epilogue
  59261. -#ifdef __NDS32_ISA_V3M__
  59262. - pop25 $r8, 0
  59263. -#else
  59264. - lmw.bim $r6, [$sp], $r8, 2
  59265. - ret
  59266. -#endif
  59267. + movi $r4, 0 ! ignore remainder
  59268. + b __udivmoddi4
  59269. .size __udivdi3, .-__udivdi3
  59270. #endif /* L_udivdi3 */
  59271. +#ifdef L_umul_ppmm
  59272. +
  59273. +#ifdef __big_endian__
  59274. + #define P1H $r0
  59275. + #define P1L $r1
  59276. + #define P2H $r2
  59277. + #define P2L $r3
  59278. +#else
  59279. + #define P1H $r1
  59280. + #define P1L $r0
  59281. + #define P2H $r3
  59282. + #define P2L $r2
  59283. +#endif
  59284. +#define W1 $r5
  59285. +
  59286. + .text
  59287. + .align 2
  59288. + .globl umul_ppmm
  59289. + .type umul_ppmm, @function
  59290. + ! =====================================================================
  59291. + ! uint64_t umul_ppmm(uint32_t a, uint32_t b)
  59292. + !
  59293. + ! This function multiplies `a' by `b' to obtain a 64-bit product. The
  59294. + ! product is broken into two 32-bit pieces which are stored in the zl
  59295. + ! (low-part at P1L) and zh (high-part at P1H).
  59296. + ! =====================================================================
  59297. +umul_ppmm:
  59298. + ! ---------------------------------------------------------------------
  59299. + ! uint16_t ah, al, bh, bl;
  59300. + ! uint32_t zh, zA, zB, zl;
  59301. + ! al = a&0xffff;
  59302. + ! ah = a>>16;
  59303. + ! bl = b&0xffff;
  59304. + ! bh = b>>16;
  59305. + ! ---------------------------------------------------------------------
  59306. + zeh P2L, $r0 ! al=a&0xffff
  59307. + srli P2H, $r0, 16 ! ah=a>>16
  59308. +#ifdef __NDS32_EB__
  59309. + srli P1H, $r1, 16 ! bh=b>>16
  59310. + zeh P1L, $r1 ! bl=b&0xffff
  59311. +#else
  59312. + zeh P1L, $r1 ! bl=b&0xffff
  59313. + srli P1H, $r1, 16 ! bh=b>>16
  59314. +#endif
  59315. + ! ---------------------------------------------------------------------
  59316. + ! zA = ( (uint32_t) al ) * bh;
  59317. + ! zl = ( (uint32_t) al ) * bl;
  59318. + ! zB = ( (uint32_t) ah ) * bl;
  59319. + ! ---------------------------------------------------------------------
  59320. + mul W1, P2L, P1H ! zA=al*bh
  59321. + mul P2L, P2L, P1L ! zl=al*bl
  59322. + mul P1L, P2H, P1L ! zB=ah*bl
  59323. + ! ---------------------------------------------------------------------
  59324. + ! zh = ( (uint32_t) ah ) * bh;
  59325. + ! zA += zB;
  59326. + ! zh += ( ( (uint32_t) ( zA < zB ) )<<16 ) + ( zA>>16 );
  59327. + ! ---------------------------------------------------------------------
  59328. + add W1, W1, P1L ! zA+=zB
  59329. + slt $ta, W1, P1L ! zA<zB
  59330. + slli $ta, $ta, 16 ! (zA<zB)<<16
  59331. + maddr32 $ta, P2H, P1H ! zh=ah*bh+((zA<zB)<<16)
  59332. + srli P1H, W1, 16 ! zA>>16
  59333. + add P1H, P1H, $ta ! zh+=(zA>>16)
  59334. + ! ---------------------------------------------------------------------
  59335. + ! zA <<= 16;
  59336. + ! zl += zA;
  59337. + ! zh += ( zl < zA );
  59338. + ! *zlPtr = zl;
  59339. + ! *zhPtr = zh;
  59340. + ! ---------------------------------------------------------------------
  59341. + slli P1L, W1, 16 ! zA<<=16
  59342. + add P1L, P1L, P2L ! zl+=zA
  59343. + slt $ta, P1L, P2L ! zl<zA
  59344. + add P1H, P1H, $ta ! zh+=(zl<zA)
  59345. + ret
  59346. + .size umul_ppmm, .-umul_ppmm
  59347. +#endif /* L_umul_ppmm */
  59348. +
  59349. +
  59350. +
  59351. #ifdef L_udivmoddi4
  59352. +#ifdef __big_endian__
  59353. + #define P1H $r0
  59354. + #define P1L $r1
  59355. +#else
  59356. + #define P1H $r1
  59357. + #define P1L $r0
  59358. +#endif
  59359. +#define W0 $r4
  59360. +#define W1 $r5
  59361. +#define W2 P1L
  59362. +#define NHI P1H // n1
  59363. +#define NLO P1L // n0
  59364. +#define D $r2 // d
  59365. +#define DLO $r3 // d0
  59366. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59367. +#define DHI $r10 // d1
  59368. +#else
  59369. +#define DHI $r20 // d1
  59370. +#endif
  59371. +#define Q NHI // q/q0
  59372. +#define QHI W0 // q1
  59373. +#define R NLO // r/r0
  59374. +#define RHI NHI // r1
  59375. +#define M W2 // m
  59376. +
  59377. .text
  59378. .align 2
  59379. - .globl fudiv_qrnnd
  59380. .type fudiv_qrnnd, @function
  59381. - #ifdef __big_endian__
  59382. - #define P1H $r0
  59383. - #define P1L $r1
  59384. - #define P2H $r2
  59385. - #define P2L $r3
  59386. - #define W6H $r4
  59387. - #define W6L $r5
  59388. - #define OFFSET_L 4
  59389. - #define OFFSET_H 0
  59390. - #else
  59391. - #define P1H $r1
  59392. - #define P1L $r0
  59393. - #define P2H $r3
  59394. - #define P2L $r2
  59395. - #define W6H $r5
  59396. - #define W6L $r4
  59397. - #define OFFSET_L 0
  59398. - #define OFFSET_H 4
  59399. - #endif
  59400. + ! =====================================================================
  59401. + ! uint64_t fudiv_qrnnd(uint64_t n, uint32_t d)
  59402. + !
  59403. + ! This function divides 64-bit numerator n by 32-bit denominator d. The
  59404. + ! 64-bit return value contains remainder (low-part at P1L) and quotient
  59405. + ! (high-part at P1H).
  59406. + ! Caller has to make sure that DHI is saved if necessary.
  59407. + ! =====================================================================
  59408. + !------------------------------------------------------
  59409. + ! in regs: ($r0,$r1) - NUMERATOR, $r2 - DENOMINATOR
  59410. + ! out regs: ($r0,$r1) - (Q,R)
  59411. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59412. + ! scratch: $r3-$r5, $r10, $ta
  59413. +#else
  59414. + ! scratch: $r3-$r5, $ta, $r20
  59415. +#endif
  59416. + !------------------------------------------------------
  59417. fudiv_qrnnd:
  59418. !------------------------------------------------------
  59419. - ! function: fudiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator)
  59420. - ! divides a UDWtype, composed by the UWtype integers,HIGH_NUMERATOR (from $r4)
  59421. - ! and LOW_NUMERATOR(from $r5) by DENOMINATOR(from $r6), and places the quotient
  59422. - ! in $r7 and the remainder in $r8.
  59423. - !------------------------------------------------------
  59424. - ! in reg:$r4(n1), $r5(n0), $r6(d0)
  59425. - ! __d1 = ((USItype) (d) >> ((4 * 8) / 2));
  59426. - ! __d0 = ((USItype) (d) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
  59427. - ! __r1 = (n1) % __d1;
  59428. - ! __q1 = (n1) / __d1;
  59429. + ! __d1 = ((USItype) (d) >> (W_TYPE_SIZE / 2));
  59430. + ! __d0 = ((USItype) (d) & (((USItype) 1 << (W_TYPE_SIZE / 2)) - 1));
  59431. + ! __r1 = (n1) % __d1; __q1 = (n1) / __d1;
  59432. ! __m = (USItype) __q1 * __d0;
  59433. - ! __r1 = __r1 * ((USItype) 1 << ((4 * 8) / 2)) | ((USItype) (n0) >> ((4 * 8) / 2));
  59434. - ! if (__r1 < __m)
  59435. - ! {
  59436. - !------------------------------------------------------
  59437. - smw.adm $r0, [$sp], $r4, 2 ! store $lp, when use BASELINE_V1,and must store $r0-$r3
  59438. - srli $r7, $r6, 16 ! $r7 = d1 =__ll_highpart (d)
  59439. - movi $ta, 65535
  59440. - and $r8, $r6, $ta ! $r8 = d0 = __ll_lowpart (d)
  59441. -
  59442. - divr $r9, $r10, $r4, $r7 ! $r9 = q1, $r10 = r1
  59443. - and $r4, $r5, $ta ! $r4 = __ll_lowpart (n0)
  59444. - slli $r10, $r10, 16 ! $r10 = r1 << 16
  59445. - srli $ta, $r5, 16 ! $ta = __ll_highpart (n0)
  59446. -
  59447. - or $r10, $r10, $ta ! $r10 <- $r0|$r3=__r1
  59448. - mul $r5, $r9, $r8 ! $r5 = m = __q1*__d0
  59449. - slt $ta, $r10, $r5 ! $ta <- __r1<__m
  59450. - beqz $ta, .L2 !if yes,skip
  59451. - !------------------------------------------------------
  59452. - ! __q1--, __r1 += (d);
  59453. - ! if (__r1 >= (d))
  59454. - ! {
  59455. + ! __r1 = __r1 * ((USItype) 1 << (W_TYPE_SIZE / 2)) | ((USItype) (n0) >> (W_TYPE_SIZE / 2));
  59456. + ! if (__r1 < __m) {
  59457. !------------------------------------------------------
  59458. + srli DHI, D, 16 ! d1 = ll_highpart (d)
  59459. + zeh W1, NLO ! ll_lowpart (n0)
  59460. + srli W2, NLO, 16 ! ll_highpart (n0)
  59461. + divr QHI, RHI, NHI, DHI ! q1 = n1 / __d1, r1 = n1 % __d1
  59462. + zeh DLO, D ! d0 = ll_lowpart (d)
  59463. + slli RHI, RHI, 16 ! r1 << 16
  59464. + or RHI, RHI, W2 ! __r1 = (__r1 << 16) | ll_highpart(n0)
  59465. + mul M, QHI, DLO ! m = __q1*__d0
  59466. + slt $ta, RHI, M ! __r1 < __m
  59467. + beqz $ta, .L2 ! if no, skip
  59468. - add $r10, $r10, $r6 !$r10 <- __r1+d=__r1
  59469. - addi $r9, $r9, -1 !$r9 <- __q1--=__q1
  59470. - slt $ta, $r10, $r6 !$ta <- __r1<d
  59471. - bnez $ta, .L2 !if yes,skip
  59472. !------------------------------------------------------
  59473. - ! if (__r1 < __m)
  59474. - ! {
  59475. + ! __q1--, __r1 += (d);
  59476. + ! if (__r1 >= (d) && __r1 < __m) {
  59477. !------------------------------------------------------
  59478. + addi QHI, QHI, -1 ! __q1--
  59479. + add RHI, RHI, D ! __r1 += d
  59480. + slt $ta, RHI, D ! __r1 < d
  59481. + bnez $ta, .L2 ! if yes, skip
  59482. + slt $ta, RHI, M ! __r1 < __m
  59483. + beqz $ta, .L2 ! if no, skip
  59484. - slt $ta, $r10, $r5 !$ta <- __r1<__m
  59485. - beqz $ta, .L2 !if yes,skip
  59486. !------------------------------------------------------
  59487. - ! __q1--, __r1 += (d);
  59488. - ! }
  59489. - ! }
  59490. + ! __q1--, __r1 += (d);
  59491. + ! }
  59492. ! }
  59493. !------------------------------------------------------
  59494. + addi QHI, QHI, -1 ! __q1--
  59495. + add RHI, RHI, D ! __r1 += d
  59496. - addi $r9, $r9, -1 !$r9 <- __q1--=__q1
  59497. - add $r10, $r10, $r6 !$r2 <- __r1+d=__r1
  59498. .L2:
  59499. !------------------------------------------------------
  59500. ! __r1 -= __m;
  59501. - ! __r0 = __r1 % __d1;
  59502. - ! __q0 = __r1 / __d1;
  59503. + ! __r0 = __r1 % __d1; __q0 = __r1 / __d1;
  59504. ! __m = (USItype) __q0 * __d0;
  59505. - ! __r0 = __r0 * ((USItype) 1 << ((4 * 8) / 2)) \
  59506. - ! | ((USItype) (n0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
  59507. - ! if (__r0 < __m)
  59508. - ! {
  59509. - !------------------------------------------------------
  59510. - sub $r10, $r10, $r5 !$r10 <- __r1-__m=__r1
  59511. - divr $r7, $r10, $r10, $r7 !$r7 <- r1/__d1=__q0,$r10 <- r1%__d1=__r0
  59512. - slli $r10, $r10, 16 !$r10 <- __r0<<16
  59513. - mul $r5, $r8, $r7 !$r5 <- __q0*__d0=__m
  59514. - or $r10, $r4, $r10 !$r3 <- $r0|__ll_lowpart (n0) =__r0
  59515. - slt $ta, $r10, $r5 !$ta <- __r0<__m
  59516. - beqz $ta, .L5 !if yes,skip
  59517. - !------------------------------------------------------
  59518. - ! __q0--, __r0 += (d);
  59519. - ! if (__r0 >= (d))
  59520. - ! {
  59521. - !------------------------------------------------------
  59522. -
  59523. - add $r10, $r10, $r6 !$r10 <- __r0+d=__r0
  59524. - addi $r7, $r7, -1 !$r7 <- __q0--=__q0
  59525. - slt $ta, $r10, $r6 !$ta <- __r0<d
  59526. - bnez $ta, .L5 !if yes,skip
  59527. - !------------------------------------------------------
  59528. - ! if (__r0 < __m)
  59529. - ! {
  59530. - !------------------------------------------------------
  59531. + ! __r0 = __r0 * ((USItype) 1 << (W_TYPE_SIZE / 2)) \
  59532. + ! | ((USItype) (n0) & (((USItype) 1 << (W_TYPE_SIZE / 2)) - 1));
  59533. + ! if (__r0 < __m) {
  59534. + !------------------------------------------------------
  59535. + sub RHI, RHI, M ! __r1 -= __m
  59536. + divr Q, W2, RHI, DHI ! __q0 = r1 / __d1, __r0 = r1 % __d1
  59537. + slli W2, W2, 16 ! __r0 << 16
  59538. + or R, W2, W1 ! __r0 = (__r0 << 16) | ll_lowpart(n0)
  59539. +#undef M
  59540. +#define M DLO
  59541. + mul M, DLO, Q ! __m = __q0 * __d0
  59542. + slt $ta, R, M ! __r0 < __m
  59543. + beqz $ta, .L5 ! if no, skip
  59544. +
  59545. + !------------------------------------------------------
  59546. + ! __q0--, __r0 += (d);
  59547. + ! if (__r0 >= (d) && __r0 < __m) {
  59548. + !------------------------------------------------------
  59549. + add R, R, D ! __r0 += d
  59550. + addi Q, Q, -1 ! __q0--
  59551. + slt $ta, R, D ! __r0 < d
  59552. + bnez $ta, .L5 ! if yes, skip
  59553. + slt $ta, R, M ! __r0 < __m
  59554. + beqz $ta, .L5 ! if no, skip
  59555. - slt $ta, $r10, $r5 !$ta <- __r0<__m
  59556. - beqz $ta, .L5 !if yes,skip
  59557. !------------------------------------------------------
  59558. - ! __q0--, __r0 += (d);
  59559. - ! }
  59560. - ! }
  59561. - ! }
  59562. + ! __q0--, __r0 += (d);
  59563. + ! }
  59564. + ! }
  59565. !------------------------------------------------------
  59566. + add R, R, D ! __r0 += d
  59567. + addi Q, Q, -1 ! __q0--
  59568. - add $r10, $r10, $r6 !$r3 <- __r0+d=__r0
  59569. - addi $r7, $r7, -1 !$r2 <- __q0--=__q0
  59570. .L5:
  59571. !------------------------------------------------------
  59572. - ! __r0 -= __m;
  59573. - ! *q = (USItype) __q1 * ((USItype) 1 << ((4 * 8) / 2)) | __q0;
  59574. - ! *r = __r0;
  59575. + ! __r0 -= __m;
  59576. + ! *q = (USItype) __q1 * ((USItype) 1 << (W_TYPE_SIZE / 2)) | __q0;
  59577. + ! *r = __r0;
  59578. !}
  59579. !------------------------------------------------------
  59580. -
  59581. - sub $r8, $r10, $r5 !$r8 = r = r0 = __r0-__m
  59582. - slli $r9, $r9, 16 !$r9 <- __q1<<16
  59583. - or $r7, $r9, $r7 !$r7 = q = $r9|__q0
  59584. - lmw.bim $r0, [$sp], $r4, 2
  59585. + sub R, R, M ! r = r0 = __r0 - __m
  59586. + slli QHI, QHI, 16 ! __q1 << 16
  59587. + or Q, Q, QHI ! q = (__q1 << 16) | __q0
  59588. ret
  59589. .size fudiv_qrnnd, .-fudiv_qrnnd
  59590. +
  59591. +
  59592. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59593. +#define NREGS $r6
  59594. +#define DREGS $r8
  59595. +#else
  59596. +#define NREGS $r16
  59597. +#define DREGS $r18
  59598. +#endif
  59599. +#ifdef __big_endian__
  59600. + #define P2H $r2
  59601. + #define P2L $r3
  59602. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59603. + #define NUMHI $r6
  59604. + #define NUMLO $r7
  59605. + #define DENHI $r8
  59606. + #define DENLO $r9
  59607. +#else
  59608. + #define NUMHI $r16
  59609. + #define NUMLO $r17
  59610. + #define DENHI $r18
  59611. + #define DENLO $r19
  59612. + #define W3H $r22
  59613. + #define W3L $r23
  59614. +#endif
  59615. + #define OFFSET_L 4
  59616. + #define OFFSET_H 0
  59617. +#else
  59618. + #define P2H $r3
  59619. + #define P2L $r2
  59620. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59621. + #define NUMHI $r7
  59622. + #define NUMLO $r6
  59623. + #define DENHI $r9
  59624. + #define DENLO $r8
  59625. +#else
  59626. + #define NUMHI $r17
  59627. + #define NUMLO $r16
  59628. + #define DENHI $r19
  59629. + #define DENLO $r18
  59630. + #define W3H $r23
  59631. + #define W3L $r22
  59632. +#endif
  59633. + #define OFFSET_L 0
  59634. + #define OFFSET_H 4
  59635. +#endif
  59636. +#define MHI P1H // m1
  59637. +#define MLO P1L // m0
  59638. +#if defined(__NDS32_EXT_PERF__)||!defined(__NDS32_REDUCE_REGS__)
  59639. +#define BM $r21 // bm
  59640. +#endif
  59641. +#undef W2
  59642. +#define W2 $r3
  59643. +
  59644. .align 2
  59645. .globl __udivmoddi4
  59646. .type __udivmoddi4, @function
  59647. -__udivmoddi4:
  59648. ! =====================================================================
  59649. + ! uint64_t __udivmoddi4(uint64_t n, uint64_t d, uint64_t *r)
  59650. + !
  59651. + ! This function divides 64-bit numerator n by 64-bit denominator d. The
  59652. + ! quotient is returned as 64-bit return value and the 64-bit remainder
  59653. + ! is stored at the input address r.
  59654. ! stack allocation:
  59655. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59656. ! sp+40 +------------------+
  59657. - ! | q1 |
  59658. - ! sp+36 +------------------+
  59659. - ! | q0 |
  59660. + ! | q |
  59661. ! sp+32 +------------------+
  59662. ! | bm |
  59663. ! sp+28 +------------------+
  59664. @@ -1020,422 +1113,520 @@
  59665. ! sp+24 +------------------+
  59666. ! | $fp |
  59667. ! sp+20 +------------------+
  59668. - ! | $r6 - $r10 |
  59669. + ! | $r10 |
  59670. + ! sp+16 +------------------+
  59671. + ! | $r6 - $r9 |
  59672. + ! sp +------------------+
  59673. +#else
  59674. + ! sp+8 +------------------+
  59675. + ! | $lp |
  59676. + ! sp+4 +------------------+
  59677. + ! | $fp |
  59678. ! sp +------------------+
  59679. +#endif
  59680. ! =====================================================================
  59681. -
  59682. + !------------------------------------------------------
  59683. + !UDWtype __udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
  59684. + !{
  59685. + ! const DWunion nn = {.ll = n};
  59686. + ! const DWunion dd = {.ll = d};
  59687. + ! DWunion rr;
  59688. + ! UWtype d0, d1, n0, n1, n2;
  59689. + ! UWtype q0, q1;
  59690. + ! UWtype b, bm;
  59691. + !------------------------------------------------------
  59692. + ! in regs: ($r0,$r1) - NUMERATOR, ($r2,$r3) - DENOMINATOR,
  59693. + ! $r4 - pointer to REMAINDER
  59694. + ! out regs: ($r0,$r1) - QUOTIENT
  59695. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59696. + ! scratch: $r2-$r9 , $ta, $fp, $lp
  59697. +#else
  59698. + ! scratch: $r2-$r5, $ta, $r16-$r21 $fp, $lp
  59699. +#endif
  59700. + !------------------------------------------------------
  59701. +__udivmoddi4:
  59702. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59703. addi $sp, $sp, -40
  59704. - smw.bi $r6, [$sp], $r10, 10
  59705. + smw.bi $r6, [$sp], $r10 , 10
  59706. +#else
  59707. + smw.adm $sp, [$sp], $sp, 10
  59708. +#endif
  59709. +
  59710. !------------------------------------------------------
  59711. ! d0 = dd.s.low;
  59712. ! d1 = dd.s.high;
  59713. ! n0 = nn.s.low;
  59714. ! n1 = nn.s.high;
  59715. - ! if (d1 == 0)
  59716. - ! {
  59717. + ! if (d1 == 0) {
  59718. !------------------------------------------------------
  59719. + movd44 NREGS, $r0 ! (n1,n0)
  59720. + movd44 DREGS, $r2 ! (d1,d0)
  59721. + move $fp, $r4 ! rp
  59722. + bnez P2H, .L9 ! if d1 != 0, skip
  59723. - move $fp, $r4 !$fp <- rp
  59724. - bnez P2H, .L9 !if yes,skip
  59725. !------------------------------------------------------
  59726. - ! if (d0 > n1)
  59727. - ! {
  59728. + ! if (d0 > n1) {
  59729. + ! /* 0q = nn / 0D */
  59730. !------------------------------------------------------
  59731. + slt $ta, NUMHI, DENLO ! n1 < d0
  59732. + beqz $ta, .L10 ! if no, skip
  59733. - slt $ta, P1H, P2L !$ta <- n1<d0
  59734. - beqz $ta, .L10 !if yes,skip
  59735. -#ifndef __NDS32_PERF_EXT__
  59736. - smw.adm $r0, [$sp], $r5, 0
  59737. - move $r0, P2L
  59738. - bal __clzsi2
  59739. - move $r7, $r0
  59740. - lmw.bim $r0, [$sp], $r5, 0
  59741. + !------------------------------------------------------
  59742. + ! count_leading_zeros (bm, d0);
  59743. + ! if (bm != 0) {
  59744. + ! /* Normalize, i.e. make the most significant bit of the
  59745. + ! denominator set. */
  59746. + !------------------------------------------------------
  59747. +#ifdef __NDS32_EXT_PERF__
  59748. + clz $r0, DENLO
  59749. +#else
  59750. + move $r0, DENLO
  59751. + bal __clzsi2
  59752. +#endif
  59753. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59754. + swi $r0, [$sp+(28)] ! bm
  59755. #else
  59756. - clz $r7, P2L
  59757. + move BM, $r0 ! bm
  59758. #endif
  59759. - swi $r7, [$sp+(28)]
  59760. - beqz $r7, .L18 !if yes,skip
  59761. + beqz $r0, .LZskipnorm1 ! if bm == 0, skip
  59762. +
  59763. + !------------------------------------------------------
  59764. + ! d0 = d0 << bm;
  59765. + ! n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm));
  59766. + ! n0 = n0 << bm;
  59767. + ! }
  59768. !------------------------------------------------------
  59769. - ! d0 = d0 << bm;
  59770. - ! n1 = (n1 << bm) | (n0 >> ((4 * 8) - bm));
  59771. - ! n0 = n0 << bm;
  59772. + sll DENLO, DENLO, $r0 ! d0 <<= bm
  59773. + subri W1, $r0, 32 ! 32 - bm
  59774. + srl W1, NUMLO, W1 ! n0 >> (32 - bm)
  59775. + sll NUMHI, NUMHI, $r0 ! n1 << bm
  59776. + or NUMHI, NUMHI, W1 ! n1 = (n1 << bm) | (n0 >> (32 - bm))
  59777. + sll NUMLO, NUMLO, $r0 ! n0 <<= bm
  59778. +
  59779. +.LZskipnorm1:
  59780. + !------------------------------------------------------
  59781. + ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
  59782. + ! q1 = 0;
  59783. + ! /* Remainder in n0 >> bm. */
  59784. ! }
  59785. !------------------------------------------------------
  59786. -
  59787. - subri $r5, $r7, 32 !$r5 <- 32-bm
  59788. - srl $r5, P1L, $r5 !$r5 <- n0>>$r5
  59789. - sll $r6, P1H, $r7 !$r6 <- n1<<bm
  59790. - or P1H, $r6, $r5 !P2h <- $r5|$r6=n1
  59791. - sll P1L, P1L, $r7 !P1H <- n0<<bm=n0
  59792. - sll P2L, P2L, $r7 !P2L <- d0<<bm=d0
  59793. -.L18:
  59794. - !------------------------------------------------------
  59795. - ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
  59796. - ! q1 = 0;
  59797. - ! } #if (d0 > n1)
  59798. - !------------------------------------------------------
  59799. -
  59800. - move $r4,P1H ! give fudiv_qrnnd args
  59801. - move $r5,P1L !
  59802. - move $r6,P2L !
  59803. - bal fudiv_qrnnd !calcaulte q0 n0
  59804. - movi $r6, 0 !P1L <- 0
  59805. - swi $r7,[$sp+32] !q0
  59806. - swi $r6,[$sp+36] !q1
  59807. - move P1L,$r8 !n0
  59808. + movd44 $r0, NREGS ! (n1,n0)
  59809. + move $r2, DENLO ! d0
  59810. + bal fudiv_qrnnd ! calcaulte q0 n0
  59811. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59812. + swi P1H, [$sp+(32+OFFSET_L)]! q0
  59813. +#else
  59814. + move W3L, P1H ! q0
  59815. +#endif
  59816. + move NUMLO, P1L ! n0
  59817. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59818. + move W1, 0
  59819. + swi W1, [$sp+(32+OFFSET_H)] ! q1 = 0
  59820. +#else
  59821. + move W3H, 0 ! q1 = 0
  59822. +#endif
  59823. b .L19
  59824. +
  59825. .L10:
  59826. !------------------------------------------------------
  59827. - ! else #if (d0 > n1)
  59828. - ! {
  59829. - ! if(d0 == 0)
  59830. + ! else {
  59831. + ! if (d0 == 0)
  59832. + ! d0 = 1 / d0; /* Divide intentionally by zero. */
  59833. !------------------------------------------------------
  59834. + beqz P2L, .LZdivzero ! if d0 != 0, skip
  59835. - bnez P2L, .L20 !if yes,skip
  59836. !------------------------------------------------------
  59837. - ! d0 = 1 / d0;
  59838. + ! count_leading_zeros (bm, d0);
  59839. + ! if (bm == 0) {
  59840. + ! /* From (n1 >= d0), (the most significant bit of d0 is set),
  59841. + ! conclude (the most significant bit of n1 is set) and (the
  59842. + ! leading quotient digit q1 = 1).
  59843. + ! This special case is necessary, not an optimization.
  59844. + ! (Shifts counts of W_TYPE_SIZE are undefined.) */
  59845. !------------------------------------------------------
  59846. -
  59847. - movi $r4, 1 !P1L <- 1
  59848. - divr P2L, $r4, $r4, P2L !$r9=1/d0,P1L=1%d0
  59849. -.L20:
  59850. -
  59851. -#ifndef __NDS32_PERF_EXT__
  59852. - smw.adm $r0, [$sp], $r5, 0
  59853. - move $r0, P2L
  59854. - bal __clzsi2
  59855. - move $r7, $r0
  59856. - lmw.bim $r0, [$sp], $r5, 0
  59857. +#ifdef __NDS32_EXT_PERF__
  59858. + clz $r0, DENLO
  59859. +#else
  59860. + move $r0, DENLO
  59861. + bal __clzsi2
  59862. +#endif
  59863. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59864. + swi $r0, [$sp+(28)] ! bm
  59865. #else
  59866. - clz $r7, P2L
  59867. + move BM, $r0 ! bm
  59868. #endif
  59869. - swi $r7,[$sp+(28)] ! store bm
  59870. - beqz $r7, .L28 ! if yes,skip
  59871. + bnez $r0, .LZnorm1 ! if bm != 0, skip
  59872. +
  59873. !------------------------------------------------------
  59874. - ! b = (4 * 8) - bm;
  59875. - ! d0 = d0 << bm;
  59876. - ! n2 = n1 >> b;
  59877. - ! n1 = (n1 << bm) | (n0 >> b);
  59878. - ! n0 = n0 << bm;
  59879. - ! fudiv_qrnnd (&q1, &n1, n2, n1, d0);
  59880. - ! }
  59881. + ! n1 -= d0;
  59882. + ! q1 = 1;
  59883. + ! }
  59884. !------------------------------------------------------
  59885. -
  59886. - subri $r10, $r7, 32 !$r10 <- 32-bm=b
  59887. - srl $r4, P1L, $r10 !$r4 <- n0>>b
  59888. - sll $r5, P1H, $r7 !$r5 <- n1<<bm
  59889. - or $r5, $r5, $r4 !$r5 <- $r5|$r4=n1 !for fun
  59890. - sll P2L, P2L, $r7 !P2L <- d0<<bm=d0 !for fun
  59891. - sll P1L, P1L, $r7 !P1L <- n0<<bm=n0
  59892. - srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !for fun
  59893. -
  59894. - move $r6,P2L !for fun
  59895. - bal fudiv_qrnnd !caculate q1, n1
  59896. -
  59897. - swi $r7,[$sp+(36)] ! q1 store
  59898. - move P1H,$r8 ! n1 store
  59899. -
  59900. - move $r4,$r8 ! prepare for next fudiv_qrnnd()
  59901. - move $r5,P1L
  59902. - move $r6,P2L
  59903. + sub NUMHI, NUMHI, DENLO ! n1 -= d0
  59904. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59905. + movi W1, 1
  59906. + swi W1, [$sp+(32+OFFSET_H)] ! q1 = 1
  59907. +#else
  59908. + movi W3H, 1 ! q1 = 1
  59909. +#endif
  59910. b .L29
  59911. -.L28:
  59912. +
  59913. + ! to eliminate unaligned branch target
  59914. + .align 2
  59915. +.LZnorm1:
  59916. !------------------------------------------------------
  59917. - ! else // bm != 0
  59918. - ! {
  59919. - ! n1 -= d0;
  59920. - ! q1 = 1;
  59921. - !
  59922. + ! else {
  59923. + ! /* Normalize. */
  59924. + ! b = W_TYPE_SIZE - bm;
  59925. + ! d0 = d0 << bm;
  59926. + ! n2 = n1 >> b;
  59927. + ! n1 = (n1 << bm) | (n0 >> b);
  59928. + ! n0 = n0 << bm;
  59929. + ! fudiv_qrnnd (&q1, &n1, n2, n1, d0);
  59930. + ! }
  59931. !------------------------------------------------------
  59932. + subri $ta, $r0, 32 ! b = 32 - bm
  59933. + sll DENLO, DENLO, $r0 ! d0 <<= bm
  59934. + move $r2, DENLO
  59935. + srl W0, NUMLO, $ta ! n0 >> b
  59936. + sll W1, NUMHI, $r0 ! n1 << bm
  59937. + sll NUMLO, NUMLO, $r0 ! n0 <<= bm
  59938. + or P1L, W1, W0 ! n1 = (n1 << bm) | (n0 >> b)
  59939. + srl P1H, NUMHI, $ta ! n2 = n1 >> b
  59940. + bal fudiv_qrnnd ! caculate q1, n1
  59941. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59942. + swi P1H, [$sp+(32+OFFSET_H)]! q1
  59943. +#else
  59944. + move W3H, P1H ! q1
  59945. +#endif
  59946. + move NUMHI, P1L ! n1
  59947. - sub P1H, P1H, P2L !P1L <- n1-d0=n1
  59948. - movi $ta, 1 !
  59949. - swi $ta, [$sp+(36)] !1 -> [$sp+(36)]
  59950. -
  59951. - move $r4,P1H ! give fudiv_qrnnd args
  59952. - move $r5,P1L
  59953. - move $r6,P2L
  59954. .L29:
  59955. !------------------------------------------------------
  59956. - ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
  59957. + ! /* n1 != d0... */
  59958. + ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
  59959. + ! /* Remainder in n0 >> bm. */
  59960. + ! }
  59961. !------------------------------------------------------
  59962. + movd44 $r0, NREGS ! (n1,n0)
  59963. + move $r2, DENLO ! d0
  59964. + bal fudiv_qrnnd ! calcuate q0, n0
  59965. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59966. + swi P1H, [$sp+(32+OFFSET_L)]
  59967. +#else
  59968. + move W3L, P1H
  59969. +#endif
  59970. + move NUMLO, P1L
  59971. - bal fudiv_qrnnd !calcuate q0, n0
  59972. - swi $r7,[$sp+(32)] !q0 store
  59973. - move P1L,$r8 !n0
  59974. + ! to eliminate unaligned branch target
  59975. + .align 2
  59976. .L19:
  59977. !------------------------------------------------------
  59978. - ! if (rp != 0)
  59979. - ! {
  59980. + ! if (rp != 0) {
  59981. !------------------------------------------------------
  59982. + beqz $fp, .LZsetq ! if rp == 0, skip
  59983. - beqz $fp, .L31 !if yes,skip
  59984. !------------------------------------------------------
  59985. - ! rr.s.low = n0 >> bm;
  59986. - ! rr.s.high = 0;
  59987. - ! *rp = rr.ll;
  59988. - ! }
  59989. + ! rr.s.low = n0 >> bm; rr.s.high = 0;
  59990. + ! *rp = rr.ll;
  59991. + ! }
  59992. + ! }
  59993. !------------------------------------------------------
  59994. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59995. + lwi W2, [$sp+(28)] ! bm
  59996. +#endif
  59997. + movi NUMHI, 0
  59998. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  59999. + srl NUMLO, NUMLO, W2 ! n0 >> bm
  60000. +#else
  60001. + srl NUMLO, NUMLO, BM ! n0 >> bm
  60002. +#endif
  60003. + b .LZsetr
  60004. +
  60005. + ! to eliminate unaligned branch target
  60006. + .align 2
  60007. +.LZdivzero:
  60008. + ! divide-by-zero exception or quotient = 0 and remainder = 0 returned
  60009. + divr NUMHI, NUMLO, DENLO, DENLO
  60010. +
  60011. +.LZqzero:
  60012. + movi P1H, 0
  60013. + movi P1L, 0
  60014. + beqz $fp, .LZret ! if rp == NULL, skip
  60015. +
  60016. + swi NUMLO, [$fp+OFFSET_L] ! *rp
  60017. + swi NUMHI, [$fp+OFFSET_H]
  60018. + b .LZret
  60019. - movi $r5, 0 !$r5 <- 0
  60020. - lwi $r7,[$sp+(28)] !load bm
  60021. - srl $r4, P1L, $r7 !$r4 <- n0>>bm
  60022. - swi $r4, [$fp+OFFSET_L] !r0 !$r4 -> [$sp+(48)]
  60023. - swi $r5, [$fp+OFFSET_H] !r1 !0 -> [$sp+(52)]
  60024. - b .L31
  60025. .L9:
  60026. !------------------------------------------------------
  60027. - ! else # d1 == 0
  60028. - ! {
  60029. - ! if(d1 > n1)
  60030. - ! {
  60031. + ! else {
  60032. + ! if (d1 > n1) {
  60033. + ! /* 00 = nn / DD */
  60034. + ! q0 = 0; q1 = 0;
  60035. + ! /* Remainder in n1n0. */
  60036. + ! if (rp != 0) {
  60037. + ! rr.s.low = n0; rr.s.high = n1;
  60038. + ! *rp = rr.ll;
  60039. + ! }
  60040. + ! }
  60041. !------------------------------------------------------
  60042. + slt $ta, NUMHI, DENHI ! n1 < d1
  60043. + bnez $ta, .LZqzero ! if yes, skip
  60044. - slt $ta, P1H, P2H !$ta <- n1<d1
  60045. - beqz $ta, .L32 !if yes,skip
  60046. !------------------------------------------------------
  60047. - ! q0 = 0;
  60048. - ! q1 = 0;
  60049. - ! if (rp != 0)
  60050. - ! {
  60051. + ! else {
  60052. + ! /* 0q = NN / dd */
  60053. + ! count_leading_zeros (bm, d1);
  60054. + ! if (bm != 0) {
  60055. + ! /* Normalize. */
  60056. + ! UWtype m1, m0;
  60057. !------------------------------------------------------
  60058. +#ifdef __NDS32_EXT_PERF__
  60059. + clz $r0, DENHI
  60060. +#else
  60061. + move $r0, DENHI
  60062. + bal __clzsi2
  60063. +#endif
  60064. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60065. + swi $r0, [$sp+(28)] ! bm
  60066. +#else
  60067. + move BM, $r0 ! bm
  60068. +#endif
  60069. + beqz $r0, .LZskipnorm2 ! if bm == 0, skip
  60070. - movi $r5, 0 !$r5 <- 0
  60071. - swi $r5, [$sp+(32)] !q0 !0 -> [$sp+(40)]=q1
  60072. - swi $r5, [$sp+(36)] !q1 !0 -> [$sp+(32)]=q0
  60073. - beqz $fp, .L31 !if yes,skip
  60074. !------------------------------------------------------
  60075. - ! rr.s.low = n0;
  60076. - ! rr.s.high = n1;
  60077. - ! *rp = rr.ll;
  60078. - ! }
  60079. - !------------------------------------------------------
  60080. -
  60081. - swi P1L, [$fp+OFFSET_L] !P1L -> [rp]
  60082. - swi P1H, [$fp+OFFSET_H] !P1H -> [rp+4]
  60083. - b .L31
  60084. -.L32:
  60085. -#ifndef __NDS32_PERF_EXT__
  60086. - smw.adm $r0, [$sp], $r5, 0
  60087. - move $r0, P2H
  60088. - bal __clzsi2
  60089. - move $r7, $r0
  60090. - lmw.bim $r0, [$sp], $r5, 0
  60091. -#else
  60092. - clz $r7,P2H
  60093. -#endif
  60094. - swi $r7,[$sp+(28)] !$r7=bm store
  60095. - beqz $r7, .L42 !if yes,skip
  60096. - !------------------------------------------------------
  60097. - ! USItype m1, m0;
  60098. - ! b = (4 * 8) - bm;
  60099. - ! d1 = (d0 >> b) | (d1 << bm);
  60100. - ! d0 = d0 << bm;
  60101. - ! n2 = n1 >> b;
  60102. - ! n1 = (n0 >> b) | (n1 << bm);
  60103. - ! n0 = n0 << bm;
  60104. - ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
  60105. - !------------------------------------------------------
  60106. -
  60107. - subri $r10, $r7, 32 !$r10 <- 32-bm=b
  60108. - srl $r5, P2L, $r10 !$r5 <- d0>>b
  60109. - sll $r6, P2H, $r7 !$r6 <- d1<<bm
  60110. - or $r6, $r5, $r6 !$r6 <- $r5|$r6=d1 !! func
  60111. - move P2H, $r6 !P2H <- d1
  60112. - srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !!! func
  60113. - srl $r8, P1L, $r10 !$r8 <- n0>>b !!$r8
  60114. - sll $r9, P1H, $r7 !$r9 <- n1<<bm
  60115. - or $r5, $r8, $r9 !$r5 <- $r8|$r9=n1 !func
  60116. - sll P2L, P2L, $r7 !P2L <- d0<<bm=d0
  60117. - sll P1L, P1L, $r7 !P1L <- n0<<bm=n0
  60118. -
  60119. - bal fudiv_qrnnd ! cal q0,n1
  60120. - swi $r7,[$sp+(32)]
  60121. - move P1H,$r8 ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
  60122. - move $r6, $r7 ! from func
  60123. + ! b = W_TYPE_SIZE - bm;
  60124. + ! d1 = (d0 >> b) | (d1 << bm);
  60125. + ! d0 = d0 << bm;
  60126. + ! n2 = n1 >> b;
  60127. + ! n1 = (n0 >> b) | (n1 << bm);
  60128. + ! n0 = n0 << bm;
  60129. + ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
  60130. + !------------------------------------------------------
  60131. + subri W0, $r0, 32 ! b = 32 - bm
  60132. + srl W1, DENLO, W0 ! d0 >> b
  60133. + sll $r2, DENHI, $r0 ! d1 << bm
  60134. + or $r2, $r2, W1 ! d1 = (d0 >> b) | (d1 << bm)
  60135. + move DENHI, $r2
  60136. + sll DENLO, DENLO, $r0 ! d0 <<= bm
  60137. + srl W2, NUMLO, W0 ! n0 >> b
  60138. + sll NUMLO, NUMLO, $r0 ! n0 <<= bm
  60139. + sll P1L, NUMHI, $r0 ! n1 << bm
  60140. + srl P1H, NUMHI, W0 ! n2 = n1 >> b
  60141. + or P1L, P1L, W2 ! n1 = (n0 >> b) | (n1 << bm)
  60142. + bal fudiv_qrnnd ! calculate q0, n1
  60143. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60144. + swi P1H, [$sp+(32+OFFSET_L)]
  60145. +#else
  60146. + move W3L, P1H
  60147. +#endif
  60148. + move NUMHI, P1L
  60149. !----------------------------------------------------
  60150. - ! #umul_ppmm (m1, m0, q0, d0);
  60151. - ! do
  60152. - ! { USItype __x0, __x1, __x2, __x3;
  60153. - ! USItype __ul, __vl, __uh, __vh;
  60154. - ! __ul = ((USItype) (q0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
  60155. - ! __uh = ((USItype) (q0) >> ((4 * 8) / 2));
  60156. - ! __vl = ((USItype) (d0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
  60157. - ! __vh = ((USItype) (d0) >> ((4 * 8) / 2));
  60158. - ! __x0 = (USItype) __ul * __vl;
  60159. - ! __x1 = (USItype) __ul * __vh;
  60160. - ! __x2 = (USItype) __uh * __vl;
  60161. - ! __x3 = (USItype) __uh * __vh;
  60162. - ! __x1 += ((USItype) (__x0) >> ((4 * 8) / 2));
  60163. - ! __x1 += __x2;
  60164. - ! if (__x1 < __x2)
  60165. - ! __x3 += ((USItype) 1 << ((4 * 8) / 2));
  60166. - ! (m1) = __x3 + ((USItype) (__x1) >> ((4 * 8) / 2));
  60167. - ! (m0) = (USItype)(q0*d0);
  60168. - ! }
  60169. - ! if (m1 > n1)
  60170. + ! umul_ppmm (m1, m0, q0, d0);
  60171. + !!!!!! do {
  60172. + !!!!!! USItype __x0, __x1, __x2, __x3;
  60173. + !!!!!! USItype __ul, __vl, __uh, __vh;
  60174. + !!!!!! __ul = ((USItype) (q0) & (((USItype) 1 << (W_TYPE_SIZE / 2)) - 1));
  60175. + !!!!!! __uh = ((USItype) (q0) >> (W_TYPE_SIZE / 2));
  60176. + !!!!!! __vl = ((USItype) (d0) & (((USItype) 1 << (W_TYPE_SIZE / 2)) - 1));
  60177. + !!!!!! __vh = ((USItype) (d0) >> (W_TYPE_SIZE / 2));
  60178. + !!!!!! __x0 = (USItype) __ul * __vl;
  60179. + !!!!!! __x1 = (USItype) __ul * __vh;
  60180. + !!!!!! __x2 = (USItype) __uh * __vl;
  60181. + !!!!!! __x3 = (USItype) __uh * __vh;
  60182. + !!!!!! __x1 += ((USItype) (__x0) >> (W_TYPE_SIZE / 2));
  60183. + !!!!!! __x1 += __x2;
  60184. + !!!!!! if (__x1 < __x2)
  60185. + !!!!!! __x3 += ((USItype) 1 << (W_TYPE_SIZE / 2));
  60186. + !!!!!! (m1) = __x3 + ((USItype) (__x1) >> (W_TYPE_SIZE / 2));
  60187. + !!!!!! (m0) = (USItype)(q0*d0);
  60188. + !!!!!! }
  60189. + ! if (m1 > n1 || (m1 == n1 && m0 > n0)) {
  60190. !---------------------------------------------------
  60191. #ifdef __NDS32_ISA_V3M__
  60192. - !mulr64 $r4, P2L, $r6
  60193. - smw.adm $r0, [$sp], $r3, 0
  60194. - move P1L, P2L
  60195. - move P2L, $r6
  60196. - movi P1H, 0
  60197. - movi P2H, 0
  60198. - bal __muldi3
  60199. - movd44 $r4, $r0
  60200. - lmw.bim $r0, [$sp], $r3, 0
  60201. - move $r8, W6H
  60202. - move $r5, W6L
  60203. + move P1L, DENLO ! d0
  60204. + bal umul_ppmm
  60205. #else
  60206. - mulr64 $r4, P2L, $r6
  60207. - move $r8, W6H
  60208. - move $r5, W6L
  60209. + mulr64 $r0, P1H, DENLO
  60210. #endif
  60211. - slt $ta, P1H, $r8 !$ta <- n1<m1
  60212. - bnez $ta, .L46 !if yes,skip
  60213. - !------------------------------------------------------
  60214. - ! if(m1 == n1)
  60215. - !------------------------------------------------------
  60216. -
  60217. - bne $r8, P1H, .L45 !if yes,skip
  60218. - !------------------------------------------------------
  60219. - ! if(m0 > n0)
  60220. - !------------------------------------------------------
  60221. + slt $ta, NUMHI, MHI ! n1 < m1
  60222. + bnez $ta, .L46 ! if yes, skip
  60223. + bne MHI, NUMHI, .L45 ! if m1 != n1, skip
  60224. + slt $ta, NUMLO, MLO ! n0 < m0
  60225. + beqz $ta, .L45 ! if no, skip
  60226. - slt $ta, P1L, $r5 !$ta <- n0<m0
  60227. - beqz $ta, .L45 !if yes,skip
  60228. .L46:
  60229. !------------------------------------------------------
  60230. - ! {
  60231. - ! q0--;
  60232. - ! # sub_ddmmss (m1, m0, m1, m0, d1, d0);
  60233. - ! do
  60234. - ! { USItype __x;
  60235. - ! __x = (m0) - (d0);
  60236. - ! (m1) = (m1) - (d1) - (__x > (m0));
  60237. - ! (m0) = __x;
  60238. - ! }
  60239. - ! }
  60240. - !------------------------------------------------------
  60241. + ! q0--;
  60242. + ! sub_ddmmss (m1, m0, m1, m0, d1, d0);
  60243. + !!!!!! do {
  60244. + !!!!!! USItype __x;
  60245. + !!!!!! __x = (m0) - (d0);
  60246. + !!!!!! (m1) = (m1) - (d1) - (__x > (m0));
  60247. + !!!!!! (m0) = __x;
  60248. + !!!!!! }
  60249. + ! }
  60250. + !------------------------------------------------------
  60251. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60252. + lwi W2, [$sp+(32+OFFSET_L)]
  60253. + sub MHI, MHI, DENHI ! m1 - d1
  60254. + addi W2, W2, -1 ! q0--
  60255. + swi W2, [$sp+(32+OFFSET_L)]
  60256. +#else
  60257. + addi W3L, W3L, -1 ! q0--
  60258. + sub MHI, MHI, DENHI ! m1 - d1
  60259. +#endif
  60260. + sub W2, MLO, DENLO ! __x = m0 - d0
  60261. + slt $ta, MLO, W2 ! m0 < __x
  60262. + sub MHI, MHI, $ta ! m1 = m1 - d1 - (__x > m0)
  60263. + move MLO, W2 ! m0 = __x
  60264. - sub $r4, $r5, P2L !$r4 <- m0-d0=__x
  60265. - addi $r6, $r6, -1 !$r6 <- q0--=q0
  60266. - sub $r8, $r8, P2H !$r8 <- m1-d1
  60267. - swi $r6, [$sp+(32)] ! q0 !$r6->[$sp+(32)]
  60268. - slt $ta, $r5, $r4 !$ta <- m0<__x
  60269. - sub $r8, $r8, $ta !$r8 <- P1H-P1L=m1
  60270. - move $r5, $r4 !$r5 <- __x=m0
  60271. .L45:
  60272. !------------------------------------------------------
  60273. - ! q1 = 0;
  60274. - ! if (rp != 0)
  60275. - ! {
  60276. - !------------------------------------------------------
  60277. -
  60278. - movi $r4, 0 !$r4 <- 0
  60279. - swi $r4, [$sp+(36)] !0 -> [$sp+(40)]=q1
  60280. - beqz $fp, .L31 !if yes,skip
  60281. - !------------------------------------------------------
  60282. - ! # sub_ddmmss (n1, n0, n1, n0, m1, m0);
  60283. - ! do
  60284. - ! { USItype __x;
  60285. - ! __x = (n0) - (m0);
  60286. - ! (n1) = (n1) - (m1) - (__x > (n0));
  60287. - ! (n0) = __x;
  60288. - ! }
  60289. - ! rr.s.low = (n1 << b) | (n0 >> bm);
  60290. - ! rr.s.high = n1 >> bm;
  60291. - ! *rp = rr.ll;
  60292. - !------------------------------------------------------
  60293. -
  60294. - sub $r4, P1H, $r8 !$r4 <- n1-m1
  60295. - sub $r6, P1L, $r5 !$r6 <- n0-m0=__x=n0
  60296. - slt $ta, P1L, $r6 !$ta <- n0<__x
  60297. - sub P1H, $r4, $ta !P1H <- $r4-$ta=n1
  60298. - move P1L, $r6
  60299. -
  60300. - lwi $r7,[$sp+(28)] ! load bm
  60301. - subri $r10,$r7,32
  60302. - sll $r4, P1H, $r10 !$r4 <- n1<<b
  60303. - srl $r5, P1L, $r7 !$r5 <- __x>>bm
  60304. - or $r6, $r5, $r4 !$r6 <- $r5|$r4=rr.s.low
  60305. - srl $r8, P1H, $r7 !$r8 <- n1>>bm =rr.s.high
  60306. - swi $r6, [$fp+OFFSET_L] !
  60307. - swi $r8, [$fp+OFFSET_H] !
  60308. - b .L31
  60309. -.L42:
  60310. - !------------------------------------------------------
  60311. - ! else
  60312. - ! {
  60313. - ! if(n1 > d1)
  60314. - !------------------------------------------------------
  60315. -
  60316. - slt $ta, P2H, P1H !$ta <- P2H<P1H
  60317. - bnez $ta, .L52 !if yes,skip
  60318. - !------------------------------------------------------
  60319. - ! if (n0 >= d0)
  60320. - !------------------------------------------------------
  60321. -
  60322. - slt $ta, P1L, P2L !$ta <- P1L<P2L
  60323. - bnez $ta, .L51 !if yes,skip
  60324. - !------------------------------------------------------
  60325. - ! q0 = 1;
  60326. - ! do
  60327. - ! { USItype __x;
  60328. - ! __x = (n0) - (d0);
  60329. - ! (n1) = (n1) - (d1) - (__x > (n0));
  60330. - ! (n0) = __x;
  60331. - ! }
  60332. + ! q1 = 0;
  60333. + ! if (rp != 0) {
  60334. + !------------------------------------------------------
  60335. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60336. + movi W2, 0
  60337. + swi W2, [$sp+(32+OFFSET_H)] ! q1 = 0
  60338. +#else
  60339. + movi W3H, 0 ! q1 = 0
  60340. +#endif
  60341. + beqz $fp, .LZsetq ! if yes, skip
  60342. +
  60343. + !------------------------------------------------------
  60344. + ! sub_ddmmss (n1, n0, n1, n0, m1, m0);
  60345. + !!!!!! do {
  60346. + !!!!!! USItype __x;
  60347. + !!!!!! __x = (n0) - (m0);
  60348. + !!!!!! (n1) = (n1) - (m1) - (__x > (n0));
  60349. + !!!!!! (n0) = __x;
  60350. + !!!!!! }
  60351. + ! rr.s.low = (n1 << b) | (n0 >> bm);
  60352. + ! rr.s.high = n1 >> bm;
  60353. + ! *rp = rr.ll;
  60354. + ! }
  60355. + ! }
  60356. + !------------------------------------------------------
  60357. + sub P1L, NUMLO, MLO ! __x = n0 - m0
  60358. + sub P1H, NUMHI, MHI ! n1 - m1
  60359. + slt $ta, NUMLO, P1L ! n0 < __x
  60360. + sub P1H, P1H, $ta ! n1 = n1 - m1 - (__x > n0)
  60361. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60362. + lwi W2, [$sp+(28)] ! bm
  60363. + subri W0, W2, 32 ! b
  60364. + sll NUMHI, P1H, W0 ! n1 << b
  60365. + srl NUMLO, P1L, W2 ! n0 >> bm
  60366. + or NUMLO, NUMLO, NUMHI ! (n1 << b) | (n0 >> bm)
  60367. + srl NUMHI, P1H, W2 ! n1 >> bm
  60368. +#else
  60369. + subri W0, BM, 32 ! b
  60370. + sll NUMHI, P1H, W0 ! n1 << b
  60371. + srl NUMLO, P1L, BM ! n0 >> bm
  60372. + or NUMLO, NUMLO, NUMHI ! (n1 << b) | (n0 >> bm)
  60373. + srl NUMHI, P1H, BM ! n1 >> bm
  60374. +#endif
  60375. +
  60376. +.LZsetr:
  60377. + swi NUMLO, [$fp+OFFSET_L] ! remainder
  60378. + swi NUMHI, [$fp+OFFSET_H]
  60379. +
  60380. +.LZsetq:
  60381. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60382. + lwi P1L, [$sp+(32+OFFSET_L)]! quotient
  60383. + lwi P1H, [$sp+(32+OFFSET_H)]
  60384. +#else
  60385. + move P1L, W3L ! quotient
  60386. + move P1H, W3H
  60387. +#endif
  60388. +
  60389. + ! to eliminate unaligned branch target
  60390. + .align 2
  60391. +.LZret:
  60392. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60393. + lmw.bi $r6, [$sp], $r10 , 10
  60394. + addi $sp, $sp, 40
  60395. +#else
  60396. + lmw.bim $sp, [$sp], $sp, 10
  60397. +#endif
  60398. + ret
  60399. +
  60400. +.LZskipnorm2:
  60401. !------------------------------------------------------
  60402. + ! else {
  60403. + ! /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
  60404. + ! conclude (the most significant bit of n1 is set) /\ (the
  60405. + ! quotient digit q0 = 0 or 1).
  60406. + ! This special case is necessary, not an optimization. */
  60407. + ! if (n1 > d1 || n0 >= d0) {
  60408. + !------------------------------------------------------
  60409. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60410. + move W2, 0
  60411. +#endif
  60412. + slt $ta, DENHI, NUMHI ! n1 > d1
  60413. + bnez $ta, .L52 ! if yes, skip
  60414. + slt $ta, NUMLO, DENLO ! n0 < d0
  60415. + bnez $ta, .L51 ! if yes, skip
  60416. +
  60417. .L52:
  60418. - sub $r4, P1H, P2H !$r4 <- P1H-P2H
  60419. - sub $r6, P1L, P2L !$r6 <- no-d0=__x=n0
  60420. - slt $ta, P1L, $r6 !$ta <- no<__x
  60421. - sub P1H, $r4, $ta !P1H <- $r4-$ta=n1
  60422. - move P1L, $r6 !n0
  60423. - movi $r5, 1 !
  60424. - swi $r5, [$sp+(32)] !1 -> [$sp+(32)]=q0
  60425. + !------------------------------------------------------
  60426. + ! q0 = 1;
  60427. + ! sub_ddmmss (n1, n0, n1, n0, d1, d0);
  60428. + !!!!!! do {
  60429. + !!!!!! USItype __x;
  60430. + !!!!!! __x = (n0) - (d0);
  60431. + !!!!!! (n1) = (n1) - (d1) - (__x > (n0));
  60432. + !!!!!! (n0) = __x;
  60433. + !!!!!! }
  60434. + ! }
  60435. + !------------------------------------------------------
  60436. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60437. + move W1, 1
  60438. + swi W1, [$sp+(32+OFFSET_L)] ! q0 = 1
  60439. +#else
  60440. + movi W3L, 1 ! q0 = 1
  60441. +#endif
  60442. + sub W0, NUMLO, DENLO ! __x = n0 - d0
  60443. + sub NUMHI, NUMHI, DENHI ! n1 - d1
  60444. + slt $ta, NUMLO, W0 ! n0 < __x
  60445. + sub NUMHI, NUMHI, $ta ! n1 = n1 -d1 - (_-x > n0)
  60446. + move NUMLO, W0 ! n0 = __x
  60447. b .L54
  60448. +
  60449. .L51:
  60450. !------------------------------------------------------
  60451. - ! q0 = 0;
  60452. + ! else
  60453. + ! q0 = 0;
  60454. !------------------------------------------------------
  60455. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60456. + swi W2, [$sp+(32+OFFSET_L)] ! q0 = 0
  60457. +#else
  60458. + movi W3L, 0 ! q0 = 0
  60459. +#endif
  60460. - movi $r5,0
  60461. - swi $r5, [$sp+(32)] !$r5=0 -> [$sp+(32)]
  60462. .L54:
  60463. !------------------------------------------------------
  60464. - ! q1 = 0;
  60465. - ! if (rp != 0)
  60466. - ! {
  60467. - !------------------------------------------------------
  60468. -
  60469. - movi $r5, 0 !
  60470. - swi $r5, [$sp+(36)] !0 -> [$sp+(36)]
  60471. - beqz $fp, .L31
  60472. - !------------------------------------------------------
  60473. - ! rr.s.low = n0;
  60474. - ! rr.s.high = n1;
  60475. - ! *rp = rr.ll;
  60476. + ! q1 = 0;
  60477. + ! if (rp != 0) {
  60478. + ! rr.s.low = n0; rr.s.high = n1;
  60479. + ! *rp = rr.ll;
  60480. + ! }
  60481. + ! }
  60482. ! }
  60483. - !------------------------------------------------------
  60484. -
  60485. - swi P1L, [$fp+OFFSET_L] !remainder
  60486. - swi P1H, [$fp+OFFSET_H] !
  60487. -.L31:
  60488. - !------------------------------------------------------
  60489. - ! const DWunion ww = {{.low = q0, .high = q1}};
  60490. - ! return ww.ll;
  60491. + ! }
  60492. + ! const DWunion ww = {{.low = q0, .high = q1}};
  60493. + ! return ww.ll;
  60494. !}
  60495. !------------------------------------------------------
  60496. -
  60497. - lwi P1L, [$sp+(32)] !quotient
  60498. - lwi P1H, [$sp+(36)]
  60499. - lmw.bim $r6, [$sp], $r10, 10
  60500. - addi $sp, $sp, 12
  60501. - ret
  60502. +#if defined(__NDS32_REDUCE_REGS__)||!defined(__NDS32_EXT_PERF__)
  60503. + swi W2, [$sp+(32+OFFSET_H)] ! q1 = 0
  60504. +#else
  60505. + movi W3H, 0
  60506. +#endif
  60507. + bnez $fp, .LZsetr
  60508. + b .LZsetq
  60509. .size __udivmoddi4, .-__udivmoddi4
  60510. #endif /* L_udivmoddi4 */
  60511. @@ -1520,36 +1711,41 @@
  60512. #ifdef L_umoddi3
  60513. - !--------------------------------------
  60514. - #ifdef __big_endian__
  60515. - #define V1H $r0
  60516. - #define V1L $r1
  60517. - #define V2H $r2
  60518. - #define V2L $r3
  60519. - #else
  60520. - #define V1H $r1
  60521. - #define V1L $r0
  60522. - #define V2H $r3
  60523. - #define V2L $r2
  60524. - #endif
  60525. - !--------------------------------------
  60526. +#ifdef __big_endian__
  60527. +#define P1H $r0
  60528. +#define P1L $r1
  60529. +#define OFFSET_H 0
  60530. +#define OFFSET_L 4
  60531. +#else
  60532. +#define P1H $r1
  60533. +#define P1L $r0
  60534. +#define OFFSET_H 4
  60535. +#define OFFSET_L 0
  60536. +#endif
  60537. +
  60538. .text
  60539. .align 2
  60540. .globl __umoddi3
  60541. .type __umoddi3, @function
  60542. __umoddi3:
  60543. - ! prologue
  60544. + ! =====================================================================
  60545. + ! stack allocation:
  60546. + ! sp+12 +-----------------------+
  60547. + ! | remainder |
  60548. + ! sp+4 +-----------------------+
  60549. + ! | $lp |
  60550. + ! sp +-----------------------+
  60551. + ! =====================================================================
  60552. addi $sp, $sp, -12
  60553. swi $lp, [$sp+(0)]
  60554. - ! end of prologue
  60555. +
  60556. addi $r4, $sp, 4
  60557. bal __udivmoddi4
  60558. - lwi $r0, [$sp+(4)] ! __udivmoddi4 return low when LE mode or return high when BE mode
  60559. - lwi $r1, [$sp+(8)] !
  60560. -.L82:
  60561. + lwi P1L, [$sp+(4+OFFSET_L)]
  60562. + lwi P1H, [$sp+(4+OFFSET_H)]
  60563. +
  60564. ! epilogue
  60565. - lwi $lp, [$sp+(0)]
  60566. - addi $sp, $sp, 12
  60567. + lwi.bi $lp, [$sp], 12
  60568. ret
  60569. .size __umoddi3, .-__umoddi3
  60570. #endif /* L_umoddi3 */
  60571. @@ -1559,64 +1755,51 @@
  60572. #ifdef L_muldi3
  60573. #ifdef __big_endian__
  60574. - #define P1H $r0
  60575. - #define P1L $r1
  60576. - #define P2H $r2
  60577. - #define P2L $r3
  60578. -
  60579. - #define V2H $r4
  60580. - #define V2L $r5
  60581. -#else
  60582. - #define P1H $r1
  60583. - #define P1L $r0
  60584. - #define P2H $r3
  60585. - #define P2L $r2
  60586. -
  60587. - #define V2H $r5
  60588. - #define V2L $r4
  60589. +#define P1H $r0
  60590. +#define P1L $r1
  60591. +#define P2H $r2
  60592. +#define P2L $r3
  60593. +#else
  60594. +#define P1H $r1
  60595. +#define P1L $r0
  60596. +#define P2H $r3
  60597. +#define P2L $r2
  60598. #endif
  60599. -
  60600. - ! ====================================================================
  60601. .text
  60602. .align 2
  60603. .globl __muldi3
  60604. .type __muldi3, @function
  60605. __muldi3:
  60606. - ! parameter passing for libgcc functions normally involves 2 doubles
  60607. - !---------------------------------------
  60608. #ifdef __NDS32_ISA_V3M__
  60609. ! There is no mulr64 instruction in Andes ISA V3M.
  60610. ! So we must provide a sequence of calculations to complete the job.
  60611. - smw.adm $r6, [$sp], $r9, 0x0
  60612. - zeh33 $r4, P1L
  60613. - srli $r7, P1L, 16
  60614. - zeh33 $r5, P2L
  60615. - mul $r6, $r5, $r4
  60616. - mul33 $r5, $r7
  60617. - srli $r8, P2L, 16
  60618. - mov55 $r9, $r5
  60619. - maddr32 $r9, $r8, $r4
  60620. - srli $r4, $r6, 16
  60621. - add $r4, $r9, $r4
  60622. - slt45 $r4, $r5
  60623. - slli $r5, $r15, 16
  60624. - maddr32 $r5, $r8, $r7
  60625. - mul P2L, P1H, P2L
  60626. - srli $r7, $r4, 16
  60627. - maddr32 P2L, P2H, P1L
  60628. - add333 P1H, $r5, $r7
  60629. - slli $r4, $r4, 16
  60630. - zeh33 $r6, $r6
  60631. - add333 P1L, $r4, $r6
  60632. - add333 P1H, P2L, P1H
  60633. - lmw.bim $r6, [$sp], $r9, 0x0
  60634. + mul $r5, P1H, P2L ! (ah=a>>31)*(bl=b&0xffffffff)
  60635. + srli P1H, P1L, 16 ! alh=al>>16
  60636. + maddr32 $r5, P1L, P2H ! ah*bl+(bh=b>>31)*(al=a&0xffffffff)
  60637. + zeh P1L, P1L ! all=al&0xffff
  60638. + srli P2H, P2L, 16 ! blh=bl>>16
  60639. + zeh P2L, P2L ! bll=bl&0xffff
  60640. +
  60641. + mul $ta, P1L, P2H ! zA=all*blh
  60642. + mul $r4, P1L, P2L ! zl=all*bll
  60643. + mul P2L, P1H, P2L ! zB=alh*bll
  60644. + add P1L, $ta, P2L ! zA+=zB
  60645. + slt $ta, P1L, P2L ! zA<zB
  60646. + slli $ta, $ta, 16 ! (zA<zB)<<16
  60647. + slli P2L, P1L, 16 ! zA<<16
  60648. + maddr32 $ta, P1H, P2H ! zh=alh*blh+((zA<zB)<<16)
  60649. + srli P1H, P1L, 16 ! zA>>16
  60650. + add P1H, P1H, $ta ! zh+=(zA>>16)
  60651. + add P1L, $r4, P2L ! zl+=(zA<<16)
  60652. + slt $ta, P1L, $r4 ! zl<zA
  60653. + add P1H, P1H, $ta ! zh+=(zl<zA)
  60654. + add P1H, P1H, $r5 ! zh+=ah*bl+bh*al
  60655. ret
  60656. #else /* not __NDS32_ISA_V3M__ */
  60657. - mul $ta, P1L, P2H
  60658. - mulr64 $r4, P1L, P2L
  60659. - maddr32 $ta, P1H, P2L
  60660. - move P1L, V2L
  60661. - add P1H, $ta, V2H
  60662. + mul P2H, P2H, P1L
  60663. + maddr32 P2H, P1H, P2L
  60664. + mulr64 $r0, P1L, P2L
  60665. + add P1H, P1H, P2H
  60666. ret
  60667. #endif /* not __NDS32_ISA_V3M__ */
  60668. .size __muldi3, .-__muldi3
  60669. @@ -1626,1923 +1809,1626 @@
  60670. #ifdef L_addsub_df
  60671. -#ifndef __big_endian__
  60672. - #define P1L $r0
  60673. - #define P1H $r1
  60674. - #define P2L $r2
  60675. - #define P2H $r3
  60676. - #define P3L $r4
  60677. - #define P3H $r5
  60678. - #define O1L $r7
  60679. - #define O1H $r8
  60680. +#ifdef __big_endian__
  60681. + #define P1H $r0
  60682. + #define P1L $r1
  60683. + #define P2H $r2
  60684. + #define P2L $r3
  60685. #else
  60686. - #define P1H $r0
  60687. - #define P1L $r1
  60688. - #define P2H $r2
  60689. - #define P2L $r3
  60690. - #define P3H $r4
  60691. - #define P3L $r5
  60692. - #define O1H $r7
  60693. - #define O1L $r8
  60694. + #define P1L $r0
  60695. + #define P1H $r1
  60696. + #define P2L $r2
  60697. + #define P2H $r3
  60698. #endif
  60699. +#define VALAH $r4
  60700. +#define EXPOA $r7
  60701. +#define MANAH $r9
  60702. +#define MANAL P1L
  60703. +#define VALBH $r6
  60704. +#define EXPOB $r10
  60705. +#define MANBH $r8
  60706. +#define MANBL P2L
  60707. +#define SIGN $lp
  60708. +#define W1 $r5
  60709. +#define W0 $r4
  60710. +#define W2 $r6
  60711. +#define AXORB P2H // sign of a xor b
  60712. +
  60713. .text
  60714. .align 2
  60715. - .global __subdf3
  60716. - .type __subdf3, @function
  60717. + .global __subdf3
  60718. + .type __subdf3, @function
  60719. __subdf3:
  60720. - push $lp
  60721. - pushm $r6, $r10
  60722. -
  60723. - move $r4, #0x80000000
  60724. - xor P2H, P2H, $r4
  60725. -
  60726. - j .Lsdpadd
  60727. -
  60728. - .global __adddf3
  60729. - .type __adddf3, @function
  60730. -__adddf3:
  60731. - push $lp
  60732. - pushm $r6, $r10
  60733. -.Lsdpadd:
  60734. - slli $r6, P1H, #1
  60735. - srli $r6, $r6, #21
  60736. - slli P3H, P1H, #11
  60737. - srli $r10, P1L, #21
  60738. - or P3H, P3H, $r10
  60739. - slli P3L, P1L, #11
  60740. - move O1L, #0x80000000
  60741. - or P3H, P3H, O1L
  60742. - slli $r9, P2H, #1
  60743. - srli $r9, $r9, #21
  60744. - slli O1H, P2H, #11
  60745. - srli $r10, P2L, #21
  60746. - or O1H, O1H, $r10
  60747. - or O1H, O1H, O1L
  60748. - slli O1L, P2L, #11
  60749. -
  60750. - addi $r10, $r6, #-1
  60751. - slti $r15, $r10, #0x7fe
  60752. - beqzs8 .LEspecA
  60753. -
  60754. -.LElab1:
  60755. - addi $r10, $r9, #-1
  60756. - slti $r15, $r10, #0x7fe
  60757. - beqzs8 .LEspecB
  60758. -
  60759. -.LElab2:
  60760. - #NORMd($r4, P2L, P1L)
  60761. - bnez P3H, .LL1
  60762. - bnez P3L, .LL2
  60763. - move $r6, #0
  60764. - j .LL3
  60765. -.LL2:
  60766. - move P3H, P3L
  60767. - move P3L, #0
  60768. - move P2L, #32
  60769. - sub $r6, $r6, P2L
  60770. -.LL1:
  60771. -#ifndef __big_endian__
  60772. -#ifdef __NDS32_PERF_EXT__
  60773. - clz $r2, $r5
  60774. +#ifdef __NDS32_EXT_PERF__
  60775. + btgl P2H, P2H, 31
  60776. #else
  60777. - pushm $r0, $r1
  60778. - pushm $r3, $r5
  60779. - move $r0, $r5
  60780. - bal __clzsi2
  60781. - move $r2, $r0
  60782. - popm $r3, $r5
  60783. - popm $r0, $r1
  60784. + move $r4, #0x80000000
  60785. + xor P2H, P2H, $r4 ! A-B is now A+(-B)
  60786. #endif
  60787. -#else /* __big_endian__ */
  60788. -#ifdef __NDS32_PERF_EXT__
  60789. - clz $r3, $r4
  60790. -#else
  60791. - pushm $r0, $r2
  60792. - pushm $r4, $r5
  60793. - move $r0, $r4
  60794. - bal __clzsi2
  60795. - move $r3, $r0
  60796. - popm $r4, $r5
  60797. - popm $r0, $r2
  60798. -#endif
  60799. -#endif /* __big_endian__ */
  60800. - beqz P2L, .LL3
  60801. - sub $r6, $r6, P2L
  60802. - subri P1L, P2L, #32
  60803. - srl P1L, P3L, P1L
  60804. - sll P3L, P3L, P2L
  60805. - sll P3H, P3H, P2L
  60806. - or P3H, P3H, P1L
  60807. -.LL3:
  60808. - #NORMd End
  60809. - #NORMd($r7, P2L, P1L)
  60810. - bnez O1H, .LL4
  60811. - bnez O1L, .LL5
  60812. - move $r9, #0
  60813. - j .LL6
  60814. -.LL5:
  60815. - move O1H, O1L
  60816. - move O1L, #0
  60817. - move P2L, #32
  60818. - sub $r9, $r9, P2L
  60819. -.LL4:
  60820. -#ifndef __big_endian__
  60821. -#ifdef __NDS32_PERF_EXT__
  60822. - clz $r2, O1H
  60823. -#else
  60824. - pushm $r0, $r1
  60825. - pushm $r3, $r5
  60826. - move $r0, O1H
  60827. - bal __clzsi2
  60828. - move $r2, $r0
  60829. - popm $r3, $r5
  60830. - popm $r0, $r1
  60831. -#endif
  60832. -#else /* __big_endian__ */
  60833. -#ifdef __NDS32_PERF_EXT__
  60834. - clz $r3, O1H
  60835. -#else
  60836. - pushm $r0, $r2
  60837. - pushm $r4, $r5
  60838. - move $r0, O1H
  60839. - bal __clzsi2
  60840. - move $r3, $r0
  60841. - popm $r4, $r5
  60842. - popm $r0, $r2
  60843. -#endif
  60844. -#endif /* __big_endian__ */
  60845. - beqz P2L, .LL6
  60846. - sub $r9, $r9, P2L
  60847. - subri P1L, P2L, #32
  60848. - srl P1L, O1L, P1L
  60849. - sll O1L, O1L, P2L
  60850. - sll O1H, O1H, P2L
  60851. - or O1H, O1H, P1L
  60852. -.LL6:
  60853. - #NORMd End
  60854. -
  60855. - move $r10, #0x80000000
  60856. - and P1H, P1H, $r10
  60857. -
  60858. - beq $r6, $r9, .LEadd3
  60859. - slts $r15, $r9, $r6
  60860. - beqzs8 .Li1
  60861. - sub $r9, $r6, $r9
  60862. - move P2L, #0
  60863. -.LL7:
  60864. - move $r10, #0x20
  60865. - slt $r15, $r9, $r10
  60866. - bnezs8 .LL8
  60867. - or P2L, P2L, O1L
  60868. - move O1L, O1H
  60869. - move O1H, #0
  60870. - addi $r9, $r9, #0xffffffe0
  60871. - bnez O1L, .LL7
  60872. -.LL8:
  60873. - beqz $r9, .LEadd3
  60874. - move P1L, O1H
  60875. - move $r10, O1L
  60876. - srl O1L, O1L, $r9
  60877. - srl O1H, O1H, $r9
  60878. - subri $r9, $r9, #0x20
  60879. - sll P1L, P1L, $r9
  60880. - or O1L, O1L, P1L
  60881. - sll $r10, $r10, $r9
  60882. - or P2L, P2L, $r10
  60883. - beqz P2L, .LEadd3
  60884. - ori O1L, O1L, #1
  60885. - j .LEadd3
  60886. -.Li1:
  60887. - move $r15, $r6
  60888. - move $r6, $r9
  60889. - sub $r9, $r9, $r15
  60890. - move P2L, #0
  60891. -.LL10:
  60892. - move $r10, #0x20
  60893. - slt $r15, $r9, $r10
  60894. - bnezs8 .LL11
  60895. - or P2L, P2L, P3L
  60896. - move P3L, P3H
  60897. - move P3H, #0
  60898. - addi $r9, $r9, #0xffffffe0
  60899. - bnez P3L, .LL10
  60900. -.LL11:
  60901. - beqz $r9, .LEadd3
  60902. - move P1L, P3H
  60903. - move $r10, P3L
  60904. - srl P3L, P3L, $r9
  60905. - srl P3H, P3H, $r9
  60906. - subri $r9, $r9, #0x20
  60907. - sll P1L, P1L, $r9
  60908. - or P3L, P3L, P1L
  60909. - sll $r10, $r10, $r9
  60910. - or P2L, P2L, $r10
  60911. - beqz P2L, .LEadd3
  60912. - ori P3L, P3L, #1
  60913. -
  60914. -.LEadd3:
  60915. - xor $r10, P1H, P2H
  60916. - sltsi $r15, $r10, #0
  60917. - bnezs8 .LEsub1
  60918. -
  60919. - #ADD(P3L, O1L)
  60920. - add P3L, P3L, O1L
  60921. - slt $r15, P3L, O1L
  60922. + .global __adddf3
  60923. + .type __adddf3, @function
  60924. +__adddf3:
  60925. + slli VALAH, P1H, 1 ! hi-part(A)<<1
  60926. + smw.adm $r6, [$sp], $r10, 2
  60927. - #ADDCC(P3H, O1H)
  60928. - beqzs8 .LL13
  60929. - add P3H, P3H, O1H
  60930. - slt $r15, P3H, O1H
  60931. - beqzs8 .LL14
  60932. - addi P3H, P3H, #0x1
  60933. - j .LL15
  60934. -.LL14:
  60935. - move $r15, #1
  60936. - add P3H, P3H, $r15
  60937. - slt $r15, P3H, $r15
  60938. - j .LL15
  60939. -.LL13:
  60940. - add P3H, P3H, O1H
  60941. - slt $r15, P3H, O1H
  60942. -.LL15:
  60943. + slli VALBH, P2H, 1 ! hi-part(B)<<1
  60944. + move SIGN, #0x80000000
  60945. + slt $r15, VALAH, VALBH
  60946. + bnez $r15, .LEswap
  60947. + bne VALAH, VALBH, .LEmain
  60948. + slt $r15, P1L, P2L
  60949. + beqz $r15, .LEmain
  60950. - beqzs8 .LEres
  60951. - andi $r10, P3L, #1
  60952. - beqz $r10, .Li3
  60953. - ori P3L, P3L, #2
  60954. -.Li3:
  60955. - srli P3L, P3L, #1
  60956. - slli $r10, P3H, #31
  60957. - or P3L, P3L, $r10
  60958. - srli P3H, P3H, #1
  60959. - move $r10, #0x80000000
  60960. - or P3H, P3H, $r10
  60961. - addi $r6, $r6, #1
  60962. - subri $r15, $r6, #0x7ff
  60963. - bnezs8 .LEres
  60964. - move $r10, #0x7ff00000
  60965. - or P1H, P1H, $r10
  60966. - move P1L, #0
  60967. - j .LEretA
  60968. + ! |A|<|B|, do swap
  60969. +.LEswap:
  60970. + movd44 $r8, $r0
  60971. + movd44 $r0, $r2
  60972. + movd44 $r2, $r8
  60973. + slli VALAH, P1H, 1 ! hi-part(A)<<1
  60974. + slli VALBH, P2H, 1 ! hi-part(B)<<1
  60975. +
  60976. + ! ---------------------------------------------------------------------
  60977. + ! |A|>=|B|
  60978. + ! ---------------------------------------------------------------------
  60979. +.LEmain:
  60980. + xor P2H, P2H, P1H
  60981. + and AXORB, P2H, SIGN ! sign of (A xor B)
  60982. + srli EXPOA, VALAH, #21 ! exponent(A)
  60983. + srli EXPOB, VALBH, #21 ! exponent(B)
  60984. + slli MANAH, VALAH, #10 ! (dirty) hi-part of mantissa(A)
  60985. + slli MANBH, VALBH, #10 ! (dirty) hi-part of mantissa(B)
  60986. + move W1, #0x7ff
  60987. + beq W1, EXPOA, .LEinfnan ! if A is NaN or inf, goto .LEinfnan
  60988. + ! A is finite, thus B must be finite
  60989. + or $r15, VALAH, P1L
  60990. + beqz $r15, .LEzeroP ! if A is zero, return zero
  60991. + or $r15, VALBH, P2L
  60992. + beqz $r15, .LEretA ! if B is zero, return A
  60993. + sub W2, EXPOA, EXPOB ! exponent(A)-exponent(B)
  60994. + slti $r15, W2, #0x40
  60995. + beqz $r15, .LEretA ! B is insignificant, return A
  60996. + srli W1, P1L, #21 ! (dirty) mantissa(A)<<11
  60997. + or MANAH, MANAH, W1
  60998. + slli MANAL, P1L, #11
  60999. + srli W1, P2L, #21 ! (dirty) mantissa(B)<<11
  61000. + or MANBH, MANBH, W1
  61001. + slli MANBL, P2L, #11
  61002. + slti $r15, EXPOA, #0x2
  61003. + bnez $r15, .LEmain4 ! if exponent(A) is 0 or 1, got .LEmain4
  61004. + or MANAH, MANAH, SIGN ! mantissa(A)<<11
  61005. +! or W1, MANBH, SIGN
  61006. +! cmovn MANBH, W1, EXPOB
  61007. + beqz EXPOB, .LEmain1
  61008. + or MANBH, MANBH, SIGN ! mantissa(A)<<11
  61009. +
  61010. +.LEmain1:
  61011. + addi W1, W2, #-1 ! adjusted shift amount
  61012. + cmovz W2, W1, EXPOB
  61013. + beqz W2, .LEmain4 ! shift amount is zero, simply skip
  61014. + ! mantissa(b)>>shift amount
  61015. + subri W1, W2, #0x20 ! 32-exponent(sum)
  61016. + blez W1, .LEmain2 ! if exponent(sum)>=32, goto .LEmain2
  61017. +
  61018. + ! exponent(sum)<32
  61019. + sll W0, MANBL, W1 ! shift-out portion
  61020. + sll W1, MANBH, W1
  61021. + srl MANBH, MANBH, W2
  61022. + srl MANBL, MANBL, W2
  61023. + or MANBL, MANBL, W1
  61024. + b .LEmain3
  61025. +
  61026. +.LEmain2:
  61027. + ! exponent(sum)>=32
  61028. + subri W2, W1, #0
  61029. + addi W1, W1, #0x20
  61030. + sll W0, MANBH, W1
  61031. + or W0, W0, MANBL ! shift-out portion
  61032. + cmovz W0, W2, W2
  61033. + srl MANBL, MANBH, W2
  61034. + move MANBH, #0
  61035. +
  61036. +.LEmain3:
  61037. +! ori $r15, MANBL, #2
  61038. +! cmovn MANBL, W0, $r15
  61039. + beqz W0, .LEmain4
  61040. + ori MANBL, MANBL, #2 ! B is quite small compare to A
  61041. +
  61042. +.LEmain4:
  61043. + beqz AXORB, .LEadd ! same sign, do addition
  61044. +
  61045. + ! ---------------------------------------------------------------------
  61046. + ! differnet sign, do subtraction
  61047. + ! ---------------------------------------------------------------------
  61048. + bne EXPOA, EXPOB, .LEsub1
  61049. + bne MANAH, MANBH, .LEsub1
  61050. + beq MANAL, MANBL, .LEzero ! |A|==|B|, return zero
  61051. + ! |A|>|B|
  61052. .LEsub1:
  61053. - #SUB(P3L, O1L)
  61054. - move $r15, P3L
  61055. - sub P3L, P3L, O1L
  61056. - slt $r15, $r15, P3L
  61057. -
  61058. - #SUBCC(P3H, O1H)
  61059. - beqzs8 .LL16
  61060. - move $r15, P3H
  61061. - sub P3H, P3H, O1H
  61062. - slt $r15, $r15, P3H
  61063. - beqzs8 .LL17
  61064. - subi333 P3H, P3H, #1
  61065. - j .LL18
  61066. -.LL17:
  61067. - move $r15, P3H
  61068. - subi333 P3H, P3H, #1
  61069. - slt $r15, $r15, P3H
  61070. - j .LL18
  61071. -.LL16:
  61072. - move $r15, P3H
  61073. - sub P3H, P3H, O1H
  61074. - slt $r15, $r15, P3H
  61075. -.LL18:
  61076. -
  61077. - beqzs8 .Li5
  61078. - move $r10, #0x80000000
  61079. - xor P1H, P1H, $r10
  61080. -
  61081. - subri P3H, P3H, #0
  61082. - beqz P3L, .LL19
  61083. - subri P3L, P3L, #0
  61084. - subi45 P3H, #1
  61085. -.LL19:
  61086. -
  61087. -.Li5:
  61088. - #NORMd($r4, $r9, P1L)
  61089. - bnez P3H, .LL20
  61090. - bnez P3L, .LL21
  61091. - move $r6, #0
  61092. - j .LL22
  61093. -.LL21:
  61094. - move P3H, P3L
  61095. - move P3L, #0
  61096. - move $r9, #32
  61097. - sub $r6, $r6, $r9
  61098. -.LL20:
  61099. -#ifdef __NDS32_PERF_EXT__
  61100. - clz $r9, P3H
  61101. -#else
  61102. - pushm $r0, $r5
  61103. - move $r0, P3H
  61104. - bal __clzsi2
  61105. - move $r9, $r0
  61106. - popm $r0, $r5
  61107. -#endif
  61108. - beqz $r9, .LL22
  61109. - sub $r6, $r6, $r9
  61110. - subri P1L, $r9, #32
  61111. - srl P1L, P3L, P1L
  61112. - sll P3L, P3L, $r9
  61113. - sll P3H, P3H, $r9
  61114. - or P3H, P3H, P1L
  61115. -.LL22:
  61116. - #NORMd End
  61117. -
  61118. - or $r10, P3H, P3L
  61119. - bnez $r10, .LEres
  61120. - move P1H, #0
  61121. -
  61122. -.LEres:
  61123. - blez $r6, .LEund
  61124. -
  61125. -.LElab8:
  61126. - #ADD(P3L, $0x400)
  61127. - move $r15, #0x400
  61128. - add P3L, P3L, $r15
  61129. - slt $r15, P3L, $r15
  61130. -
  61131. - #ADDCC(P3H, $0x0)
  61132. - beqzs8 .LL25
  61133. - add P3H, P3H, $r15
  61134. - slt $r15, P3H, $r15
  61135. -.LL25:
  61136. -
  61137. - #ADDC($r6, $0x0)
  61138. - add $r6, $r6, $r15
  61139. - srli $r10, P3L, #11
  61140. - andi $r10, $r10, #1
  61141. - sub P3L, P3L, $r10
  61142. - srli P1L, P3L, #11
  61143. - slli $r10, P3H, #21
  61144. - or P1L, P1L, $r10
  61145. - slli $r10, P3H, #1
  61146. - srli $r10, $r10, #12
  61147. - or P1H, P1H, $r10
  61148. - slli $r10, $r6, #20
  61149. - or P1H, P1H, $r10
  61150. + ! is mantissa(|A|)<mantissa(|B|)?
  61151. + slt $r15, MANAH, MANBH
  61152. + bnez $r15, .LEsub2 ! mantissa(|A|)<mantissa(|B|), continue
  61153. + bne MANAH, MANBH, .LEsub3 ! mantissa(|A|)!=mantissa(|B|), skip
  61154. + slt $r15, MANAL, MANBL
  61155. + beqz $r15, .LEsub3 ! mantissa(|A|)>=mantissa(|B|), skip
  61156. +
  61157. +.LEsub2:
  61158. + ! mantissa(|A|)<mantissa(|B|), adjust
  61159. + addi EXPOA, EXPOA, #-1
  61160. + ! mantissa(|B|)>>1
  61161. + slli W0, MANBH, #31
  61162. + srli MANBH, MANBH, #1
  61163. + srli MANBL, MANBL, #1
  61164. + or MANBL, MANBL, W0
  61165. +
  61166. +.LEsub3:
  61167. + ! calculate mantissa(|A|)-mantissa(|B|)
  61168. + move W0, MANAL
  61169. + sub MANAL, MANAL, MANBL
  61170. + slt $r15, W0, MANAL
  61171. + sub MANAH, MANAH, $r15 ! no undeflow issue
  61172. + sub MANAH, MANAH, MANBH
  61173. + slti $r15, EXPOA, #2
  61174. + bnez $r15, .LEdenorm ! when exponent(A,B) is (0,0) or (1,0/1)
  61175. + ! count leading zero of mantissa(|A|)
  61176. + bnez MANAH, .LEsub4
  61177. +#ifdef __NDS32_EXT_PERF__
  61178. + move W0, #0x20
  61179. + slt W0, EXPOA, W0
  61180. + move W1, EXPOA
  61181. + bnez W0, .LEsub5
  61182. + move MANAH, MANAL
  61183. + move MANAL, #0
  61184. + addi EXPOA, EXPOA, #-32
  61185. +
  61186. +.LEsub4:
  61187. + clz W1, MANAH ! leading zero count
  61188. + slt $r15, W1, EXPOA ! leading zero count>=exponent(A)?
  61189. + subri W0, $r15, #1
  61190. + min W1, W1, EXPOA ! calculated shift amount
  61191. + beqz W1, .LEround ! shift amount is 0, skip
  61192. +.LEsub5:
  61193. + sub EXPOA, EXPOA, W1
  61194. + ! mantissa(diff)<<adjusted shift amount
  61195. + sub W1, W1, W0 ! adjusted shift amount
  61196. + subri W2, W1, #0x20
  61197. + srl W0, MANAL, W2
  61198. + sll MANAH, MANAH, W1
  61199. + sll MANAL, MANAL, W1
  61200. + or MANAH, MANAH, W0
  61201. +#else
  61202. + slti $r15, EXPOA, #0x20
  61203. + bnez $r15, .LEsub4
  61204. + move MANAH, MANAL
  61205. + move MANAL, #0
  61206. + addi EXPOA, EXPOA, #-32
  61207. + bnez EXPOA, .LEsub4
  61208. + b .LEround
  61209. +
  61210. +.LEloop:
  61211. + addi EXPOA, EXPOA, #-1
  61212. + beqz EXPOA, .LEround
  61213. + srli W0, MANAL, #31
  61214. + slli MANAH, MANAH, #1
  61215. + slli MANAL, MANAL, #1
  61216. + or MANAH, MANAH, W0
  61217. +
  61218. +.LEsub4:
  61219. + slt $r15, MANAH, SIGN
  61220. + bnez $r15, .LEloop
  61221. +#endif
  61222. +
  61223. + ! ---------------------------------------------------------------------
  61224. + ! do rounding
  61225. + ! ---------------------------------------------------------------------
  61226. +.LEround:
  61227. + addi MANAL, MANAL, #0x400
  61228. + slti $r15, MANAL, #0x400
  61229. + add MANAH, MANAH, $r15
  61230. + slt $r15, MANAH, $r15
  61231. + add EXPOA, EXPOA, $r15
  61232. + srli W1, MANAL, #11
  61233. + andi W1, W1, #1
  61234. + move W2, MANAL
  61235. + sub MANAL, MANAL, W1
  61236. + slt $r15, W2, MANAL
  61237. + sub MANAH, MANAH, $r15
  61238. +
  61239. + ! ---------------------------------------------------------------------
  61240. + ! pack result
  61241. + ! ---------------------------------------------------------------------
  61242. + slli MANAH, MANAH, #1 ! shift our implied 1
  61243. + slli W1, MANAH, #20
  61244. + srli MANAH, MANAH, #12
  61245. + srli MANAL, MANAL, #11
  61246. + or MANAL, MANAL, W1
  61247. + slli W1, EXPOA, #20
  61248. + or MANAH, MANAH, W1
  61249. +
  61250. +.LEpack:
  61251. + and P1H, P1H, SIGN
  61252. + or P1H, P1H, MANAH
  61253. .LEretA:
  61254. -.LE999:
  61255. - popm $r6, $r10
  61256. - pop $lp
  61257. - ret5 $lp
  61258. +.LEret:
  61259. + lmw.bim $r6, [$sp], $r10, 2
  61260. + ret5 $lp
  61261. -.LEspecA:
  61262. - #ADD(P3L, P3L)
  61263. - move $r15, P3L
  61264. - add P3L, P3L, P3L
  61265. - slt $r15, P3L, $r15
  61266. -
  61267. - #ADDC(P3H, P3H)
  61268. - add P3H, P3H, P3H
  61269. - add P3H, P3H, $r15
  61270. - bnez $r6, .Li7
  61271. - or $r10, P3H, P3L
  61272. - beqz $r10, .Li8
  61273. - j .LElab1
  61274. -.Li8:
  61275. - subri $r15, $r9, #0x7ff
  61276. - beqzs8 .LEspecB
  61277. - add P3L, P2H, P2H
  61278. - or $r10, P3L, P2L
  61279. - bnez $r10, .LEretB
  61280. - sltsi $r15, P2H, #0
  61281. - bnezs8 .LEretA
  61282. -
  61283. -.LEretB:
  61284. - move P1L, P2L
  61285. - move P1H, P2H
  61286. - j .LE999
  61287. -.Li7:
  61288. - or $r10, P3H, P3L
  61289. - bnez $r10, .LEnan
  61290. - subri $r15, $r9, #0x7ff
  61291. - bnezs8 .LEretA
  61292. - xor $r10, P1H, P2H
  61293. - sltsi $r15, $r10, #0
  61294. - bnezs8 .LEnan
  61295. - j .LEretB
  61296. -
  61297. -.LEspecB:
  61298. - #ADD(O1L, O1L)
  61299. - move $r15, O1L
  61300. - add O1L, O1L, O1L
  61301. - slt $r15, O1L, $r15
  61302. -
  61303. - #ADDC(O1H, O1H)
  61304. - add O1H, O1H, O1H
  61305. - add O1H, O1H, $r15
  61306. - bnez $r9, .Li11
  61307. - or $r10, O1H, O1L
  61308. - beqz $r10, .LEretA
  61309. - j .LElab2
  61310. -.Li11:
  61311. - or $r10, O1H, O1L
  61312. - beqz $r10, .LEretB
  61313. +.LEadd:
  61314. + ! ---------------------------------------------------------------------
  61315. + ! same sign, do addition
  61316. + ! ---------------------------------------------------------------------
  61317. + add MANAL, MANAL, MANBL
  61318. + slt $r15, MANAL, MANBL
  61319. + add MANAH, MANAH, $r15
  61320. + slt r15, MANAH, $r15
  61321. + add MANAH, MANAH, MANBH
  61322. + bnez $r15, .LEaddover ! overflow, goto .LEaddover
  61323. + slt $r15, MANAH, MANBH
  61324. + bnez $r15, .LEaddover ! overflow, goto .LEaddover
  61325. + ! all works fine without overflow
  61326. + bnez EXPOA, .LEround
  61327. +
  61328. +.LEdenorm:
  61329. + ! mantissa(sum)>>11
  61330. + srli MANAL, MANAL, #11
  61331. + slli W0, MANAH, #21
  61332. + srli MANAH, MANAH, #11
  61333. + or MANAL, MANAL, W0
  61334. + b .LEpack
  61335. +
  61336. + ! handle overflow
  61337. +.LEaddover:
  61338. + subri W1, EXPOA, #0x7fe
  61339. + beqz W1, .LEinf
  61340. + andi $r15, MANAL, #1
  61341. + ori W1, MANAL, #2
  61342. + cmovn MANAL, W1, $r15
  61343. + ! mantissa(sum)>>1
  61344. + slli W0, MANAH, #31
  61345. + srli MANAH, MANAH, #1
  61346. + srli MANAL, MANAL, #1
  61347. + or MANAL, MANAL, W0
  61348. + addi EXPOA, EXPOA, #1
  61349. + b .LEround
  61350. +
  61351. +.LEinf:
  61352. + move P1L, #0
  61353. + move MANAH, 0x7ff00000 ! return inf
  61354. + b .LEpack
  61355. +
  61356. + ! handle 0.0f or -0.0f
  61357. +.LEzeroP:
  61358. + beqz AXORB, .LEretA ! A and B same sign, return A
  61359. +
  61360. +.LEzero:
  61361. + move P1L, #0
  61362. + move P1H, #0 ! otherwise, return 0.0f
  61363. + b .LEret
  61364. +
  61365. + ! ---------------------------------------------------------------------
  61366. + ! exponent(A) is 0x7ff
  61367. + ! ---------------------------------------------------------------------
  61368. +.LEinfnan:
  61369. + or MANAH, MANAH, MANAL
  61370. + bne MANAH, SIGN, .LEnan ! if A is NaN, goto .LEnan
  61371. + ! A is inf
  61372. + bne W1, EXPOB, .LEretA ! B is finite, return A
  61373. + ! B is also inf
  61374. + beqz AXORB, .LEretA ! same sign, return A
  61375. .LEnan:
  61376. - move P1H, #0xfff80000
  61377. - move P1L, #0
  61378. - j .LEretA
  61379. -
  61380. -.LEund:
  61381. - subri $r9, $r6, #1
  61382. - move P2L, #0
  61383. -.LL26:
  61384. - move $r10, #0x20
  61385. - slt $r15, $r9, $r10
  61386. - bnezs8 .LL27
  61387. - or P2L, P2L, P3L
  61388. - move P3L, P3H
  61389. - move P3H, #0
  61390. - addi $r9, $r9, #0xffffffe0
  61391. - bnez P3L, .LL26
  61392. -.LL27:
  61393. - beqz $r9, .LL28
  61394. - move P1L, P3H
  61395. - move $r10, P3L
  61396. - srl P3L, P3L, $r9
  61397. - srl P3H, P3H, $r9
  61398. - subri $r9, $r9, #0x20
  61399. - sll P1L, P1L, $r9
  61400. - or P3L, P3L, P1L
  61401. - sll $r10, $r10, $r9
  61402. - or P2L, P2L, $r10
  61403. - beqz P2L, .LL28
  61404. - ori P3L, P3L, #1
  61405. -.LL28:
  61406. - move $r6, #0
  61407. - j .LElab8
  61408. + move P1L, #0
  61409. + move P1H, #0xfff80000 ! return NaN
  61410. + b .LEret
  61411. .size __subdf3, .-__subdf3
  61412. .size __adddf3, .-__adddf3
  61413. #endif /* L_addsub_df */
  61414. +#ifdef L_mul_df
  61415. -#ifdef L_mul_sf
  61416. -
  61417. -#if !defined (__big_endian__)
  61418. - #define P1L $r0
  61419. - #define P1H $r1
  61420. - #define P2L $r2
  61421. - #define P2H $r3
  61422. +#ifdef __big_endian__
  61423. + #define P1H $r0
  61424. + #define P1L $r1
  61425. + #define P2H $r2
  61426. + #define P2L $r3
  61427. + #define MANAH $r6
  61428. + #define MANAL $r7
  61429. + #define MANBH $r8
  61430. + #define MANBL $r9
  61431. #else
  61432. - #define P1H $r0
  61433. - #define P1L $r1
  61434. - #define P2H $r2
  61435. - #define P2L $r3
  61436. -#endif
  61437. + #define P1L $r0
  61438. + #define P1H $r1
  61439. + #define P2L $r2
  61440. + #define P2H $r3
  61441. + #define MANAL $r6
  61442. + #define MANAH $r7
  61443. + #define MANBL $r8
  61444. + #define MANBH $r9
  61445. +#endif
  61446. +#define EXPOA $r4
  61447. +#define EXPOB $r5
  61448. +#define SIGN $fp
  61449. +#define W1 $r5
  61450. +#define W2 P2L
  61451. +#define W3 P2H
  61452. +#define W4 P1L
  61453. +#define W5 P1H
  61454. +#define W6 $r10
  61455. +#define AXORB $r10
  61456. +
  61457. .text
  61458. .align 2
  61459. - .global __mulsf3
  61460. - .type __mulsf3, @function
  61461. -__mulsf3:
  61462. - push $lp
  61463. - pushm $r6, $r10
  61464. -
  61465. - srli $r3, $r0, #23
  61466. - andi $r3, $r3, #0xff
  61467. - srli $r5, $r1, #23
  61468. - andi $r5, $r5, #0xff
  61469. - move $r6, #0x80000000
  61470. - slli $r2, $r0, #8
  61471. - or $r2, $r2, $r6
  61472. - slli $r4, $r1, #8
  61473. - or $r4, $r4, $r6
  61474. - xor $r8, $r0, $r1
  61475. - and $r6, $r6, $r8
  61476. -
  61477. - addi $r8, $r3, #-1
  61478. - slti $r15, $r8, #0xfe
  61479. - beqzs8 .LFspecA
  61480. -
  61481. -.LFlab1:
  61482. - addi $r8, $r5, #-1
  61483. - slti $r15, $r8, #0xfe
  61484. - beqzs8 .LFspecB
  61485. + .global __muldf3
  61486. + .type __muldf3, @function
  61487. +__muldf3:
  61488. + push25 $r10, #16
  61489. -.LFlab2:
  61490. - move $r10, $r3
  61491. -/* This is a 64-bit multiple. ($r2, $r7) is (high, low). */
  61492. + slli EXPOA, P1H, #1
  61493. + srli EXPOA, EXPOA, #21 ! exponent(a)
  61494. + slli MANAH, P1H, #11 ! (dirty) mantissa(a)
  61495. + srli MANAL, P1L, #21
  61496. + or MANAH, MANAH, MANAL
  61497. + slli MANAL, P1L, #11
  61498. + move SIGN, #0x80000000
  61499. + slli EXPOB, P2H, #1
  61500. + srli EXPOB, EXPOB, #21 ! exponent(b)
  61501. + slli MANBH, P2H, #11 ! (dirty) mantissa(b)
  61502. + srli MANBL, P2L, #21
  61503. + or MANBH, MANBH, MANBL
  61504. + slli MANBL, P2L, #11
  61505. + xor W3, P2H, P1H
  61506. + and AXORB, W3, SIGN ! sign of (A xor B)
  61507. +
  61508. + move W3, 0x7ff
  61509. + beqz EXPOA, .LFAexpzero ! exponent(A) is 0x000
  61510. + beq W3, EXPOA, .LFAinfnan ! exponent(A) is 0x7ff
  61511. + or MANAH, MANAH, SIGN
  61512. +
  61513. +.LFmain1:
  61514. + beqz EXPOB, .LFBexpzero ! exponent(B) is 0x000
  61515. + beq W3, EXPOB, .LFBinfnan ! exponent(B) is 0x7ff
  61516. + or MANBH, MANBH, SIGN
  61517. +
  61518. + ! ---------------------------------------------------------------------
  61519. + ! multiply two 64-bit unsigned integers for 128-bit product.
  61520. + ! ---------------------------------------------------------------------
  61521. +.LFmain2:
  61522. + ! exponent(product) = exponent(A) + exponent(B) - 0x3fe
  61523. + swi AXORB, [$sp+(12)]
  61524. + addi W4, EXPOB, #0xfffffc02
  61525. + add EXPOA, EXPOA, W4
  61526. + ! PHH: hi-part of mantissa(A) * hi-part of mantissa(B)
  61527. + ! This is a 64-bit multiplication: (P2H, P2L) is (high, low).
  61528. #ifndef __NDS32_ISA_V3M__
  61529. - mulr64 $r2, $r2, $r4
  61530. + mulr64 $r2, MANAH, MANBH
  61531. #else
  61532. - pushm $r0, $r1
  61533. - pushm $r4, $r5
  61534. - move P1L, $r2
  61535. - movi P1H, #0
  61536. - move P2L, $r4
  61537. - movi P2H, #0
  61538. - bal __muldi3
  61539. + swi EXPOA, [$sp+(8)]
  61540. + move $r0, MANAH
  61541. + move $r1, MANBH
  61542. + bal umul_ppmm
  61543. movd44 $r2, $r0
  61544. - popm $r4, $r5
  61545. - popm $r0, $r1
  61546. #endif
  61547. -#ifndef __big_endian__
  61548. - move $r7, $r2
  61549. - move $r2, $r3
  61550. + ! PLH: lo-part of mantissa(A) * hi-part of mantissa(B)
  61551. + ! This is a 64-bit multiplication: (P1H, P1L) is (high, low).
  61552. +#ifndef __NDS32_ISA_V3M__
  61553. + mulr64 $r0, MANAL, MANBH
  61554. #else
  61555. - move $r7, $r3
  61556. -#endif
  61557. - move $r3, $r10
  61558. -
  61559. - beqz $r7, .Li17
  61560. - ori $r2, $r2, #1
  61561. -
  61562. -.Li17:
  61563. - sltsi $r15, $r2, #0
  61564. - bnezs8 .Li18
  61565. - slli $r2, $r2, #1
  61566. - addi $r3, $r3, #-1
  61567. -.Li18:
  61568. - addi $r8, $r5, #0xffffff82
  61569. - add $r3, $r3, $r8
  61570. - addi $r8, $r3, #-1
  61571. - slti $r15, $r8, #0xfe
  61572. - beqzs8 .LFoveund
  61573. -
  61574. -.LFlab8:
  61575. - #ADD($r2, $0x80)
  61576. - move $r15, #0x80
  61577. - add $r2, $r2, $r15
  61578. - slt $r15, $r2, $r15
  61579. -
  61580. - #ADDC($r3, $0x0)
  61581. - add $r3, $r3, $r15
  61582. - srli $r8, $r2, #8
  61583. - andi $r8, $r8, #1
  61584. - sub $r2, $r2, $r8
  61585. - slli $r2, $r2, #1
  61586. - srli $r2, $r2, #9
  61587. - slli $r8, $r3, #23
  61588. - or $r2, $r2, $r8
  61589. - or $r0, $r2, $r6
  61590. -
  61591. -.LF999:
  61592. - popm $r6, $r10
  61593. - pop $lp
  61594. - ret5 $lp
  61595. -
  61596. -.LFspecA:
  61597. - bnez $r3, .Li19
  61598. - add $r2, $r2, $r2
  61599. - beqz $r2, .Li20
  61600. -#ifdef __NDS32_PERF_EXT__
  61601. - clz $r7, $r2
  61602. + smw.bi $r2, [$sp], $r3, #0
  61603. + move $r0, MANAL
  61604. + move $r1, MANBH
  61605. + bal umul_ppmm
  61606. + lmw.bi $r2, [$sp], $r3, #0
  61607. +#endif
  61608. + ! add PLH and PHH for 96-bit result in (W6, MANBH, P1L).
  61609. + add MANBH, P2L, P1H
  61610. + slt $r15, MANBH, P1H
  61611. + add W6, P2H, $r15
  61612. + ! PHL: hi-part of mantissa(A) * lo-part of mantissa(B)
  61613. + ! This is a 64-bit multiplication: (P2H, P2L) is (high, low).
  61614. +#ifndef __NDS32_ISA_V3M__
  61615. + mulr64 $r2, MANAH, MANBL
  61616. #else
  61617. - pushm $r0, $r5
  61618. - move $r0, $r2
  61619. - bal __clzsi2
  61620. - move $r7, $r0
  61621. - popm $r0, $r5
  61622. + swi P1L, [$sp+(4)]
  61623. + move $r0, MANAH
  61624. + move $r1, MANBL
  61625. + bal umul_ppmm
  61626. + movd44 $r2, $r0
  61627. + lwi P1L, [$sp+(4)]
  61628. #endif
  61629. - sub $r3, $r3, $r7
  61630. - sll $r2, $r2, $r7
  61631. - j .LFlab1
  61632. -.Li20:
  61633. - subri $r15, $r5, #0xff
  61634. - beqzs8 .LFnan
  61635. - j .LFzer
  61636. -.Li19:
  61637. - add $r8, $r2, $r2
  61638. - bnez $r8, .LFnan
  61639. - bnez $r5, .Li21
  61640. - add $r8, $r4, $r4
  61641. - beqz $r8, .LFnan
  61642. -.Li21:
  61643. - subri $r15, $r5, #0xff
  61644. - bnezs8 .LFinf
  61645. -
  61646. -.LFspecB:
  61647. - bnez $r5, .Li22
  61648. - add $r4, $r4, $r4
  61649. - beqz $r4, .LFzer
  61650. -#ifdef __NDS32_PERF_EXT__
  61651. - clz $r7, $r4
  61652. + ! add PHL, PLH, and PHH for 96-bit result in (W6, MANBH, MANAH).
  61653. + add MANAH, P2L, P1L
  61654. + slt $r15, MANAH, P1L
  61655. + add MANBH, MANBH, $r15
  61656. + slt $r15, MANBH, $r15
  61657. + add W6, W6, $r15
  61658. + add MANBH, MANBH, P2H
  61659. + slt $r15, MANBH, P2H
  61660. + add W6, W6, $r15
  61661. + ! PLL: lo-part of mantissa(A) * lo-part of mantissa(B)
  61662. + ! This is a 64-bit multiplication: (P1H, P1L) is (high, low).
  61663. +#ifndef __NDS32_ISA_V3M__
  61664. + mulr64 $r0, MANAL, MANBL
  61665. #else
  61666. - pushm $r0, $r5
  61667. - move $r0, $r4
  61668. - bal __clzsi2
  61669. - move $r7, $r0
  61670. - popm $r0, $r5
  61671. -#endif
  61672. - sub $r5, $r5, $r7
  61673. - sll $r4, $r4, $r7
  61674. - j .LFlab2
  61675. -
  61676. -.LFzer:
  61677. - move $r0, $r6
  61678. - j .LF999
  61679. -.Li22:
  61680. - add $r8, $r4, $r4
  61681. - bnez $r8, .LFnan
  61682. + move $r0, MANAL
  61683. + move $r1, MANBL
  61684. + bal umul_ppmm
  61685. + lwi EXPOA, [$sp+(8)]
  61686. +#endif
  61687. + ! add PLL, PHL, PLH, and PHH for 128-bit result in (P1H, MANBH, MANAH, P1L).
  61688. + add MANAH, MANAH, P1H
  61689. + slt $r15, MANAH, P1H
  61690. + add MANBH, MANBH, $r15
  61691. + slt $r15, MANBH, $r15
  61692. + add P1H, W6, $r15
  61693. +
  61694. + ! take high 64-bit part of the product into (P1H, P1L).
  61695. + or MANAH, MANAH, P1L
  61696. + ori P1L, MANBH, #1 ! adjust if low 64-bit is non-zero.
  61697. + cmovz P1L, MANBH, MANAH
  61698. + sltsi $r15, P1H, #0
  61699. + bnez $r15, .LFmain3
  61700. + ! MSB is zero, adjust
  61701. + move $r15, P1L
  61702. + add P1L, P1L, P1L
  61703. + slt $r15, P1L, $r15
  61704. + add P1H, P1H, P1H
  61705. + add P1H, P1H, $r15
  61706. + addi EXPOA, EXPOA, #-1
  61707. +
  61708. +.LFmain3:
  61709. + lwi AXORB, [$sp+(12)]
  61710. + blez EXPOA, .LFunderflow ! exponent(product) is too small
  61711. + subri W1, EXPOA, #0x7ff
  61712. + blez W1, .LFinf ! exponent(product) is too big, return inf
  61713. + addi P1L, P1L, #0x400
  61714. + slti $r15, P1L, #0x400
  61715. + beqz $r15, .LFround
  61716. + add P1H, P1H, $r15
  61717. + slt $r15, P1H, $r15
  61718. + add EXPOA, EXPOA, $r15
  61719. +
  61720. + ! do rounding
  61721. +.LFround:
  61722. + srli W2, P1L, #11
  61723. + andi W2, W2, #1
  61724. + sub P1L, P1L, W2
  61725. + srli P1L, P1L, #11
  61726. + slli W2, P1H, #21
  61727. + or P1L, P1L, W2
  61728. +
  61729. + ! do packing
  61730. + slli P1H, P1H, #1
  61731. + srli P1H, P1H, #12
  61732. + slli W1, EXPOA, #20
  61733. + or P1H, P1H, W1
  61734. -.LFinf:
  61735. - move $r8, #0x7f800000
  61736. - or $r0, $r6, $r8
  61737. - j .LF999
  61738. +.LFret:
  61739. + or P1H, P1H, AXORB
  61740. + pop25 $r10, #16
  61741. -.LFnan:
  61742. - move $r0, #0xffc00000
  61743. - j .LF999
  61744. + ! ---------------------------------------------------------------------
  61745. + ! exponent(A) is 0x000
  61746. + ! ---------------------------------------------------------------------
  61747. +.LFAexpzero:
  61748. + or $r15, MANAH, MANAL
  61749. + beqz $r15, .LFAzero ! A is zero
  61750. + ! A is subnormal
  61751. + srli $r15, MANAL, #31
  61752. + add MANAH, MANAH, MANAH
  61753. + add MANAH, MANAH, $r15
  61754. + add MANAL, MANAL, MANAL
  61755. + ! count leading zeros of A
  61756. + bnez MANAH, .LFAcont
  61757. + move MANAH, MANAL
  61758. + move MANAL, #0
  61759. + addi EXPOA, EXPOA, #-32
  61760. +
  61761. + ! MANAH is non-zero
  61762. +.LFAcont:
  61763. +#ifdef __NDS32_EXT_PERF__
  61764. + clz W4, MANAH
  61765. +#else
  61766. + move W4, #0
  61767. + move W5, MANAH
  61768. + b .LFAloop2
  61769. +
  61770. +.LFAloop:
  61771. + add W5, W5, W5
  61772. + addi W4, W4, #1
  61773. +
  61774. +.LFAloop2:
  61775. + slt $r15, W5, SIGN
  61776. + bnez $r15, .LFAloop
  61777. +#endif
  61778. + beqz W4, .LFmain1
  61779. + sub EXPOA, EXPOA, W4
  61780. + subri W2, W4, #32
  61781. + srl W2, MANAL, W2
  61782. + sll MANAL, MANAL, W4
  61783. + sll MANAH, MANAH, W4
  61784. + or MANAH, MANAH, W2
  61785. + b .LFmain1
  61786. +
  61787. +.LFAzero:
  61788. + beq W3, EXPOB, .LFnan ! B is NaN or inf, return NaN
  61789. +
  61790. +.LFsetsign:
  61791. + move P1H, AXORB
  61792. + pop25 $r10, #16
  61793. +
  61794. + ! ---------------------------------------------------------------------
  61795. + ! exponent(A) is 0x7ff
  61796. + ! ---------------------------------------------------------------------
  61797. +.LFAinfnan:
  61798. + or MANAH, MANAH, MANAL
  61799. + bne MANAH, SIGN, .LFnan ! A is NaN, return NaN
  61800. + ! A is inf: check whether B is zero.
  61801. + bnez EXPOB, .LFAcont2
  61802. + slli W2, MANBH, #1
  61803. + or W2, W2, MANBL
  61804. + beqz W2, .LFnan ! inf*zero is NaN
  61805. +
  61806. +.LFAcont2:
  61807. + bne W3, EXPOB, .LFinf ! B is finite, return inf
  61808. +
  61809. + ! ---------------------------------------------------------------------
  61810. + ! exponent(B) is 0x7ff
  61811. + ! ---------------------------------------------------------------------
  61812. +.LFBinfnan:
  61813. + or MANBH, MANBH, MANBL
  61814. + bne MANBH, SIGN, .LFnan ! B is NaN, return NaN
  61815. + ! B is inf
  61816. -.LFoveund:
  61817. - bgtz $r3, .LFinf
  61818. - subri $r7, $r3, #1
  61819. - slti $r15, $r7, #0x20
  61820. - beqzs8 .LFzer
  61821. - subri $r8, $r7, #0x20
  61822. - sll $r3, $r2, $r8
  61823. - srl $r2, $r2, $r7
  61824. - beqz $r3, .Li25
  61825. - ori $r2, $r2, #2
  61826. -.Li25:
  61827. - move $r3, #0
  61828. - addi $r8, $r2, #0x80
  61829. - sltsi $r15, $r8, #0
  61830. - beqzs8 .LFlab8
  61831. - move $r3, #1
  61832. - j .LFlab8
  61833. - .size __mulsf3, .-__mulsf3
  61834. -#endif /* L_mul_sf */
  61835. +.LFinf:
  61836. + move P1L, #0
  61837. + move P1H, #0x7ff00000
  61838. + b .LFret
  61839. +.LFnan:
  61840. + move P1L, #0
  61841. + move P1H, #0xfff80000
  61842. + pop25 $r10, #16
  61843. +
  61844. + ! ---------------------------------------------------------------------
  61845. + ! exponent(B) is 0x000
  61846. + ! ---------------------------------------------------------------------
  61847. +.LFBexpzero:
  61848. + or P1L, MANBH, MANBL
  61849. + beqz P1L, .LFsetsign ! B is zero, return zero
  61850. + ! B is subnormal
  61851. + srli $r15, MANBL, #31
  61852. + add MANBH, MANBH, MANBH
  61853. + add MANBH, MANBH, $r15
  61854. + add MANBL, MANBL, MANBL
  61855. + ! count leading zeros of B
  61856. + bnez MANBH, .LFBcont
  61857. + move MANBH, MANBL
  61858. + move MANBL, #0
  61859. + addi EXPOB, EXPOB, #-32
  61860. +
  61861. + ! MANBH is non-zero
  61862. +.LFBcont:
  61863. +#ifdef __NDS32_EXT_PERF__
  61864. + clz W4, MANBH
  61865. +#else
  61866. + move W4, #0
  61867. + move W5, MANBH
  61868. + b .LFBloop2
  61869. +
  61870. +.LFBloop:
  61871. + add W5, W5, W5
  61872. + addi W4, W4, #1
  61873. +
  61874. +.LFBloop2:
  61875. + slt $r15, W5, SIGN
  61876. + bnez $r15, .LFBloop
  61877. +#endif
  61878. + beqz W4, .LFmain2
  61879. + sub EXPOB, EXPOB, W4
  61880. + subri W2, W4, #32
  61881. + srl W2, MANBL, W2
  61882. + sll MANBL, MANBL, W4
  61883. + sll MANBH, MANBH, W4
  61884. + or MANBH, MANBH, W2
  61885. + b .LFmain2
  61886. +
  61887. + ! ---------------------------------------------------------------------
  61888. + ! handle underflow
  61889. + ! ---------------------------------------------------------------------
  61890. +.LFunderflow:
  61891. + move MANAL, #0
  61892. + subri W3, EXPOA, #1
  61893. + slti $r15, W3, #0x20
  61894. + bnez $r15, .LFunderflow2
  61895. + move MANAL, P1L
  61896. + move P1L, P1H
  61897. + move P1H, #0
  61898. + addi W3, W3, #0xffffffe0
  61899. + beqz P1L, .LFunderflow2
  61900. + slti $r15, W3, #0x20
  61901. + beqz $r15, .LFignore ! result too small, return zero
  61902. +
  61903. + ! 1-exponent(A), in W3, is 0-31
  61904. +.LFunderflow2:
  61905. + beqz W3, .LFunderflow3 ! it is zero, skip
  61906. + subri W2, W3, #0x20
  61907. + sll MANAH, P1H, W2
  61908. + sll W1, P1L, W2
  61909. + srl P1L, P1L, W3
  61910. + srl P1H, P1H, W3
  61911. + or P1L, P1L, MANAH
  61912. + or MANAL, MANAL, W1
  61913. +! ori W3, P1L, #1
  61914. +! cmovn P1L, W3, MANAL
  61915. + beqz MANAL, .LFunderflow3
  61916. + ori P1L, P1L, #1
  61917. +
  61918. +.LFunderflow3:
  61919. + addi P1L, P1L, #0x400
  61920. + slti $r15, P1L, #0x400
  61921. + add P1H, P1H, $r15
  61922. + srli EXPOA, P1H, #31
  61923. + b .LFround
  61924. +
  61925. +.LFignore:
  61926. + move P1L, #0
  61927. + b .LFsetsign
  61928. + .size __muldf3, .-__muldf3
  61929. +#endif /* L_mul_df */
  61930. -#ifdef L_mul_df
  61931. +#ifdef L_div_df
  61932. -#ifndef __big_endian__
  61933. - #define P1L $r0
  61934. - #define P1H $r1
  61935. - #define P2L $r2
  61936. - #define P2H $r3
  61937. - #define P3L $r4
  61938. - #define P3H $r5
  61939. - #define O1L $r7
  61940. - #define O1H $r8
  61941. +#ifdef __big_endian__
  61942. + #define P1H $r0
  61943. + #define P1L $r1
  61944. + #define P2H $r2
  61945. + #define P2L $r3
  61946. + #define MANAH $r6
  61947. + #define MANAL $r7
  61948. + #define MANBH $r8
  61949. + #define MANBL $r9
  61950. #else
  61951. - #define P1H $r0
  61952. - #define P1L $r1
  61953. - #define P2H $r2
  61954. - #define P2L $r3
  61955. - #define P3H $r4
  61956. - #define P3L $r5
  61957. - #define O1H $r7
  61958. - #define O1L $r8
  61959. -#endif
  61960. + #define P1L $r0
  61961. + #define P1H $r1
  61962. + #define P2L $r2
  61963. + #define P2H $r3
  61964. + #define MANAL $r6
  61965. + #define MANAH $r7
  61966. + #define MANBL $r8
  61967. + #define MANBH $r9
  61968. +#endif
  61969. +#define EXPOA $r4
  61970. +#define EXPOB $r5
  61971. +#define SIGN $fp
  61972. +#define W1 $r5
  61973. +#define W2 P2L
  61974. +#define W3 P2H
  61975. +#define W4 P1L
  61976. +#define W5 P1H
  61977. +#define AXORB $r10
  61978. +
  61979. .text
  61980. .align 2
  61981. - .global __muldf3
  61982. - .type __muldf3, @function
  61983. -__muldf3:
  61984. - push $lp
  61985. - pushm $r6, $r10
  61986. -
  61987. - slli $r6, P1H, #1
  61988. - srli $r6, $r6, #21
  61989. - slli P3H, P1H, #11
  61990. - srli $r10, P1L, #21
  61991. - or P3H, P3H, $r10
  61992. - slli P3L, P1L, #11
  61993. - move O1L, #0x80000000
  61994. - or P3H, P3H, O1L
  61995. - slli $r9, P2H, #1
  61996. - srli $r9, $r9, #21
  61997. - slli O1H, P2H, #11
  61998. - srli $r10, P2L, #21
  61999. - or O1H, O1H, $r10
  62000. - or O1H, O1H, O1L
  62001. - xor P1H, P1H, P2H
  62002. - and P1H, P1H, O1L
  62003. - slli O1L, P2L, #11
  62004. -
  62005. - addi $r10, $r6, #-1
  62006. - slti $r15, $r10, #0x7fe
  62007. - beqzs8 .LFspecA
  62008. -
  62009. -.LFlab1:
  62010. - addi $r10, $r9, #-1
  62011. - slti $r15, $r10, #0x7fe
  62012. - beqzs8 .LFspecB
  62013. -
  62014. -.LFlab2:
  62015. - addi $r10, $r9, #0xfffffc02
  62016. - add $r6, $r6, $r10
  62017. -
  62018. - move $r10, $r8
  62019. -/* This is a 64-bit multiple. */
  62020. -#ifndef __big_endian__
  62021. -/* For little endian: ($r9, $r3) is (high, low). */
  62022. -#ifndef __NDS32_ISA_V3M__
  62023. - mulr64 $r8, $r5, $r8
  62024. -#else
  62025. - pushm $r0, $r5
  62026. - move $r0, $r5
  62027. - movi $r1, #0
  62028. - move $r2, $r8
  62029. - movi $r3, #0
  62030. - bal __muldi3
  62031. - movd44 $r8, $r0
  62032. - popm $r0, $r5
  62033. -#endif
  62034. - move $r3, $r8
  62035. -#else /* __big_endian__ */
  62036. -/* For big endain: ($r9, $r2) is (high, low). */
  62037. -#ifndef __NDS32_ISA_V3M__
  62038. - mulr64 $r8, $r4, $r7
  62039. -#else
  62040. - pushm $r0, $r5
  62041. - move $r1, $r4
  62042. - movi $r0, #0
  62043. - move $r3, $r7
  62044. - movi $r2, #0
  62045. - bal __muldi3
  62046. - movd44 $r8, $r0
  62047. - popm $r0, $r5
  62048. -#endif
  62049. - move $r2, $r9
  62050. - move $r9, $r8
  62051. -#endif /* __big_endian__ */
  62052. - move $r8, $r10
  62053. + .global __divdf3
  62054. + .type __divdf3, @function
  62055. +__divdf3:
  62056. + push25 $r10, #16
  62057. - move $r10, P1H
  62058. -/* This is a 64-bit multiple. */
  62059. -#ifndef __big_endian__
  62060. -/* For little endian: ($r0, $r2) is (high, low). */
  62061. -#ifndef __NDS32_ISA_V3M__
  62062. - mulr64 $r0, $r4, $r8
  62063. -#else
  62064. - pushm $r2, $r5
  62065. - move $r0, $r4
  62066. - movi $r1, #0
  62067. - move $r2, $r8
  62068. - movi $r3, #0
  62069. - bal __muldi3
  62070. - popm $r2, $r5
  62071. -#endif
  62072. - move $r2, $r0
  62073. - move $r0, $r1
  62074. -#else /* __big_endian__ */
  62075. -/* For big endain: ($r1, $r3) is (high, low). */
  62076. + slli EXPOA, P1H, #1
  62077. + srli EXPOA, EXPOA, #21 ! exponent(a)
  62078. + slli MANAH, P1H, #11 ! (dirty) mantissa(a)
  62079. + srli MANAL, P1L, #21
  62080. + or MANAH, MANAH, MANAL
  62081. + slli MANAL, P1L, #11
  62082. + move SIGN, #0x80000000
  62083. + slli EXPOB, P2H, #1
  62084. + srli EXPOB, EXPOB, #21 ! exponent(b)
  62085. + slli MANBH, P2H, #11 ! (dirty) mantissa(b)
  62086. + srli MANBL, P2L, #21
  62087. + or MANBH, MANBH, MANBL
  62088. + slli MANBL, P2L, #11
  62089. + xor W3, P2H, P1H
  62090. + and AXORB, W3, SIGN ! sign of (A xor B)
  62091. +
  62092. + move W3, 0x7ff
  62093. + beqz EXPOA, .LGAexpzero ! exponent(A) is 0x000
  62094. + beq W3, EXPOA, .LGAinfnan ! exponent(A) is 0x7ff
  62095. + or MANAH, MANAH, SIGN
  62096. +
  62097. +.LGmain1:
  62098. + beqz EXPOB, .LGBexpzero ! exponent(B) is 0x000
  62099. + beq W3, EXPOB, .LGBinfnan ! exponent(B) is 0x7ff
  62100. + or MANBH, MANBH, SIGN
  62101. +
  62102. + ! ---------------------------------------------------------------------
  62103. + ! divide two 64-bit unsigned integers for 64-bit quotient.
  62104. + ! ---------------------------------------------------------------------
  62105. +.LGmain2:
  62106. + ! exponent(quotient) = exponent(A) - exponent(B) + 0x3ff
  62107. + sub EXPOA, EXPOA, EXPOB
  62108. + addi EXPOA, EXPOA, #0x3ff
  62109. + ! Use mantissa(A)>>1: hi-part 31 bits and lo-part 22 bits
  62110. + srli MANAL, MANAL, #1
  62111. + slli W5, MANAH, #31
  62112. + or MANAL, MANAL, W5
  62113. + srli MANAH, MANAH, #1
  62114. + ! Split divisor into four 16-bit parts to do division:
  62115. + ! HH in W2, HL in W5
  62116. + srli W2, MANBH, #16
  62117. + divr W3, MANAH, MANAH, W2
  62118. + zeh W5, MANBH
  62119. + mul W1, W5, W3
  62120. + slli MANAH, MANAH, #16
  62121. + srli W4, MANAL, #16
  62122. + or MANAH, MANAH, W4
  62123. + move W4, MANAH
  62124. + sub MANAH, MANAH, W1
  62125. + slt $r15, W4, MANAH
  62126. + beqz $r15, .LGmain3
  62127. +
  62128. +.LGloop1:
  62129. + addi W3, W3, #-1
  62130. + add MANAH, MANAH, MANBH
  62131. + slt $r15, MANAH, MANBH
  62132. + beqz $r15, .LGloop1
  62133. +
  62134. +.LGmain3:
  62135. + divr W2, MANAH, MANAH, W2
  62136. + mul W1, W5, W2
  62137. + slli MANAH, MANAH, #16
  62138. + zeh W4, MANAL
  62139. + or MANAH, MANAH, W4
  62140. + move W4, MANAH
  62141. + sub MANAH, MANAH, W1
  62142. + slt $r15, W4, MANAH
  62143. + beqz $r15, .LGmain4
  62144. +
  62145. +.LGloop2:
  62146. + addi W2, W2, #-1
  62147. + add MANAH, MANAH, MANBH
  62148. + slt $r15, MANAH, MANBH
  62149. + beqz $r15, .LGloop2
  62150. +
  62151. +.LGmain4:
  62152. + slli W3, W3, #16
  62153. + add W3, W3, W2
  62154. + ! This is a 64-bit multiplication: (P1H, P1L) is (high, low).
  62155. #ifndef __NDS32_ISA_V3M__
  62156. - mulr64 $r0, $r5, $r7
  62157. + mulr64 $r0, W3, MANBL
  62158. #else
  62159. - pushm $r2, $r5
  62160. - move $r1, $r5
  62161. - movi $r0, #0
  62162. - move $r3, $r7
  62163. - movi $r2, #0
  62164. - bal __muldi3
  62165. - popm $r2, $r5
  62166. -#endif
  62167. - move $r3, $r1
  62168. - move $r1, $r0
  62169. -#endif /* __big_endian__ */
  62170. - move P1H, $r10
  62171. + swi EXPOA, [$sp+(8)]
  62172. + swi W3, [$sp+(4)]
  62173. + move $r0, W3
  62174. + move $r1, MANBL
  62175. + bal umul_ppmm
  62176. + lwi W3, [$sp+(4)]
  62177. +#endif
  62178. + subri MANAL, P1L, #0
  62179. + move W4, MANAH
  62180. + sub MANAH, MANAH, P1H
  62181. + slt $r15, W4, MANAH
  62182. + beqz MANAL, .LGmain5
  62183. + move W4, MANAH
  62184. + addi MANAH, MANAH, #-1
  62185. + bnez $r15, .LGloopA
  62186. + slt $r15, W4, MANAH
  62187. +
  62188. +.LGmain5:
  62189. + beqz $r15, .LGmain6
  62190. +
  62191. +.LGloopA:
  62192. + addi W3, W3, #-1
  62193. + add MANAL, MANAL, MANBL
  62194. + slt W4, MANAL, MANBL
  62195. + add MANAH, MANAH, MANBH
  62196. + slt $r15, MANAH, MANBH
  62197. + beqz W4, .LGloopA2
  62198. + addi MANAH, MANAH, #1
  62199. + bnez $r15, .LGmain6
  62200. + slti $r15, MANAH, #1
  62201. +
  62202. +.LGloopA2:
  62203. + beqz $r15, .LGloopA
  62204. +
  62205. +.LGmain6:
  62206. + bne MANAH, MANBH, .Li25
  62207. + move P1H, MANBL
  62208. + move MANAH, MANAL
  62209. + move W2, #0
  62210. + move P1L, #0
  62211. + b .LGmain7
  62212. - #ADD(P2H, P1L)
  62213. - add P2H, P2H, P1L
  62214. - slt $r15, P2H, P1L
  62215. +.Li25:
  62216. + srli W5, MANBH, #16
  62217. + divr W2, MANAH, MANAH, W5
  62218. + zeh W4, MANBH
  62219. + mul $r15, W4, W2
  62220. + slli MANAH, MANAH, #16
  62221. + srli W1, MANAL, #16
  62222. + or MANAH, MANAH, W1
  62223. + move W1, MANAH
  62224. + sub MANAH, MANAH, $r15
  62225. + slt $r15, W1, MANAH
  62226. + beqz $r15, .Li26
  62227. +
  62228. +.LGloop3:
  62229. + addi W2, W2, #-1
  62230. + add MANAH, MANAH, MANBH
  62231. + slt $r15, MANAH, MANBH
  62232. + beqz $r15, .LGloop3
  62233. - #ADDC($r9, $0x0)
  62234. - add $r9, $r9, $r15
  62235. +.Li26:
  62236. + divr W5, MANAH, MANAH, W5
  62237. + mul W1, W4, W5
  62238. + slli MANAH, MANAH, #16
  62239. + zeh W4, MANAL
  62240. + or MANAH, MANAH, W4
  62241. + move W4, MANAH
  62242. + sub MANAH, MANAH, W1
  62243. + slt $r15, W4, MANAH
  62244. + beqz $r15, .Li28
  62245. +
  62246. +.LGloop4:
  62247. + addi W5, W5, #-1
  62248. + add MANAH, MANAH, MANBH
  62249. + slt $r15, MANAH, MANBH
  62250. + beqz $r15, .LGloop4
  62251. - move $r10, P1H
  62252. -/* This is a 64-bit multiple. */
  62253. -#ifndef __big_endian__
  62254. -/* For little endian: ($r0, $r8) is (high, low). */
  62255. -#ifndef __NDS32_ISA_V3M__
  62256. - mulr64 $r0, $r5, $r7
  62257. -#else
  62258. - pushm $r2, $r5
  62259. - move $r0, $r5
  62260. - movi $r1, #0
  62261. - move $r2, $r7
  62262. - movi $r3, #0
  62263. - bal __muldi3
  62264. - popm $r2, $r5
  62265. -#endif
  62266. - move $r8, $r0
  62267. - move $r0, $r1
  62268. -#else /* __big_endian__ */
  62269. -/* For big endian: ($r1, $r7) is (high, low). */
  62270. +.Li28:
  62271. + slli W2, W2, #16
  62272. + add W2, W2, W5
  62273. + ! This is a 64-bit multiplication: (P1H, P1L) is (high, low).
  62274. #ifndef __NDS32_ISA_V3M__
  62275. - mulr64 $r0, $r4, $r8
  62276. + mulr64 $r0, W2, MANBL
  62277. #else
  62278. - pushm $r2, $r5
  62279. - move $r1, $r4
  62280. - movi $r0, #0
  62281. - move $r3, $r8
  62282. - movi $r2, #0
  62283. - bal __muldi3
  62284. - popm $r2, $r5
  62285. -#endif
  62286. - move $r7, $r1
  62287. - move $r1, $r0
  62288. -#endif /* __big_endian__ */
  62289. - move P1H, $r10
  62290. + smw.bi $r2, [$sp], $r3, #0
  62291. + move $r0, W2
  62292. + move $r1, MANBL
  62293. + bal umul_ppmm
  62294. + lmw.bi $r2, [$sp], $r3, #0
  62295. +#endif
  62296. +
  62297. +.LGmain7:
  62298. + subri MANAL, P1L, #0
  62299. + move W4, MANAH
  62300. + sub MANAH, MANAH, P1H
  62301. + slt $r15, W4, MANAH
  62302. + beqz MANAL, .LGmain8
  62303. + move W4, MANAH
  62304. + addi MANAH, MANAH, #-1
  62305. + bnez $r15, .LGloopB
  62306. + slt $r15, W4, MANAH
  62307. +
  62308. +.LGmain8:
  62309. + beqz $r15, .LGmain9
  62310. +
  62311. +.LGloopB:
  62312. + addi W2, W2, #-1
  62313. + add MANAL, MANAL, MANBL
  62314. + slt W4, MANAL, MANBL
  62315. + add MANAH, MANAH, MANBH
  62316. + slt $r15, MANAH, MANBH
  62317. + beqz W4, .LGloopB2
  62318. + addi MANAH, MANAH, #1
  62319. + bnez $r15, .LGmain9
  62320. + slti $r15, MANAH, #1
  62321. - #ADD(P2L, O1H)
  62322. - add P2L, P2L, O1H
  62323. - slt $r15, P2L, O1H
  62324. -
  62325. -
  62326. - #ADDCC(P2H, P1L)
  62327. - beqzs8 .LL29
  62328. - add P2H, P2H, P1L
  62329. - slt $r15, P2H, P1L
  62330. - beqzs8 .LL30
  62331. - addi P2H, P2H, #0x1
  62332. - j .LL31
  62333. -.LL30:
  62334. - move $r15, #1
  62335. - add P2H, P2H, $r15
  62336. - slt $r15, P2H, $r15
  62337. - j .LL31
  62338. -.LL29:
  62339. - add P2H, P2H, P1L
  62340. - slt $r15, P2H, P1L
  62341. -.LL31:
  62342. +.LGloopB2:
  62343. + beqz $r15, .LGloopB
  62344. - #ADDC($r9, $0x0)
  62345. - add $r9, $r9, $r15
  62346. -
  62347. -/* This is a 64-bit multiple. */
  62348. -#ifndef __big_endian__
  62349. -/* For little endian: ($r8, $r0) is (high, low). */
  62350. - move $r10, $r9
  62351. -#ifndef __NDS32_ISA_V3M__
  62352. - mulr64 $r8, $r4, $r7
  62353. -#else
  62354. - pushm $r0, $r5
  62355. - move $r0, $r4
  62356. - movi $r1, #0
  62357. - move $r2, $r7
  62358. - movi $r3, #0
  62359. - bal __muldi3
  62360. - movd44 $r8, $r0
  62361. - popm $r0, $r5
  62362. -#endif
  62363. - move $r0, $r8
  62364. - move $r8, $r9
  62365. - move $r9, $r10
  62366. -#else /* __big_endian__ */
  62367. -/* For big endian: ($r7, $r1) is (high, low). */
  62368. - move $r10, $r6
  62369. -#ifndef __NDS32_ISA_V3M__
  62370. - mulr64 $r6, $r5, $r8
  62371. -#else
  62372. - pushm $r0, $r5
  62373. - move $r1, $r5
  62374. - movi $r0, #0
  62375. - move $r3, $r8
  62376. - movi $r2, #0
  62377. - bal __muldi3
  62378. - movd44 $r6, $r0
  62379. - popm $r0, $r5
  62380. +.LGmain9:
  62381. + sltsi $r15, W3, #0
  62382. +#ifdef __NDS32_ISA_V3M__
  62383. + lwi EXPOA, [$sp+(8)]
  62384. #endif
  62385. - move $r1, $r7
  62386. - move $r7, $r6
  62387. - move $r6, $r10
  62388. -#endif /* __big_endian__ */
  62389. -
  62390. - #ADD(P2L, O1H)
  62391. - add P2L, P2L, O1H
  62392. - slt $r15, P2L, O1H
  62393. + bnez $r15, .LGmain10
  62394. + move $r15, W2
  62395. + add W2, W2, W2
  62396. + slt $r15, W2, $r15
  62397. + add W3, W3, W3
  62398. + add W3, W3, $r15
  62399. + addi EXPOA, EXPOA, #-1
  62400. +
  62401. +.LGmain10:
  62402. + or MANAH, MANAH, MANAL
  62403. + ori P1L, W2, #1
  62404. + cmovz P1L, W2, MANAH
  62405. + move P1H, W3
  62406. + blez EXPOA, .LGunderflow ! exponent(quotient) is too small
  62407. + subri W1, EXPOA, #0x7ff
  62408. + blez W1, .LGinf ! exponent(quotient) is too big, return inf
  62409. + addi P1L, P1L, #0x400
  62410. + slti $r15, P1L, #0x400
  62411. + beqz $r15, .LGround
  62412. + add P1H, P1H, $r15
  62413. + slt $r15, P1H, $r15
  62414. + add EXPOA, EXPOA, $r15
  62415. +
  62416. + ! do rounding
  62417. +.LGround:
  62418. + srli W2, P1L, #11
  62419. + andi W2, W2, #1
  62420. + sub P1L, P1L, W2
  62421. + srli P1L, P1L, #11
  62422. + slli W2, P1H, #21
  62423. + or P1L, P1L, W2
  62424. +
  62425. + ! do packing
  62426. + slli P1H, P1H, #1
  62427. + srli P1H, P1H, #12
  62428. + slli W1, EXPOA, #20
  62429. + or P1H, P1H, W1
  62430. +.LGret:
  62431. + or P1H, P1H, AXORB
  62432. + pop25 $r10, #16
  62433. - #ADDCC(P2H, $0x0)
  62434. - beqzs8 .LL34
  62435. - add P2H, P2H, $r15
  62436. - slt $r15, P2H, $r15
  62437. -.LL34:
  62438. + ! ---------------------------------------------------------------------
  62439. + ! exponent(A) is 0x000
  62440. + ! ---------------------------------------------------------------------
  62441. +.LGAexpzero:
  62442. + or $r15, MANAH, MANAL
  62443. + beqz $r15, .LGAzero ! A is zero
  62444. + ! A is subnormal
  62445. + srli $r15, MANAL, #31
  62446. + add MANAH, MANAH, MANAH
  62447. + add MANAH, MANAH, $r15
  62448. + add MANAL, MANAL, MANAL
  62449. + ! count leading zeros of A
  62450. + bnez MANAH, .LGAcont
  62451. + move MANAH, MANAL
  62452. + move MANAL, #0
  62453. + addi EXPOA, EXPOA, #-32
  62454. +
  62455. + ! MANAH is non-zero
  62456. +.LGAcont:
  62457. +#ifdef __NDS32_EXT_PERF__
  62458. + clz W4, MANAH
  62459. +#else
  62460. + move W4, #0
  62461. + move W5, MANAH
  62462. + b .LGAloop2
  62463. +
  62464. +.LGAloop:
  62465. + add W5, W5, W5
  62466. + addi W4, W4, #1
  62467. +
  62468. +.LGAloop2:
  62469. + slt $r15, W5, SIGN
  62470. + bnez $r15, .LGAloop
  62471. +#endif
  62472. + beqz W4, .LGmain1
  62473. + sub EXPOA, EXPOA, W4
  62474. + subri W2, W4, #32
  62475. + srl W2, MANAL, W2
  62476. + sll MANAL, MANAL, W4
  62477. + sll MANAH, MANAH, W4
  62478. + or MANAH, MANAH, W2
  62479. + b .LGmain1
  62480. +
  62481. +.LGAzero:
  62482. + beq W3, EXPOB, .LGAzero2 ! B is NaN or inf, goto .LGAzero2
  62483. + ! B is finite: check whether B is zero.
  62484. + bnez EXPOB, .LGsetsign
  62485. + or $r15, MANBH, MANBL
  62486. + beqz $r15, .LGnan ! zero/zero is NaN
  62487. +
  62488. +.LGsetsign:
  62489. + move P1H, AXORB
  62490. + pop25 $r10, #16
  62491. +
  62492. +.LGAzero2:
  62493. + or MANBH, MANBH, MANBL
  62494. + beq MANBH, SIGN, .LGsetsign ! zero/inf is zero
  62495. + ! zero/NaN is NaN
  62496. - #ADDC($r9, $0x0)
  62497. - add $r9, $r9, $r15
  62498. - or $r10, P1L, P2L
  62499. - beqz $r10, .Li13
  62500. - ori P2H, P2H, #1
  62501. -.Li13:
  62502. - move P3H, $r9
  62503. - move P3L, P2H
  62504. - sltsi $r15, P3H, #0
  62505. - bnezs8 .Li14
  62506. -
  62507. - move $r15, P3L
  62508. - add P3L, P3L, P3L
  62509. - slt $r15, P3L, $r15
  62510. - add P3H, P3H, P3H
  62511. - add P3H, P3H, $r15
  62512. - addi $r6, $r6, #-1
  62513. -.Li14:
  62514. - addi $r10, $r6, #-1
  62515. - slti $r15, $r10, #0x7fe
  62516. - beqzs8 .LFoveund
  62517. +.LGnan:
  62518. + move P1L, #0
  62519. + move P1H, #0xfff80000
  62520. + pop25 $r10, #16
  62521. - #ADD(P3L, $0x400)
  62522. - move $r15, #0x400
  62523. - add P3L, P3L, $r15
  62524. - slt $r15, P3L, $r15
  62525. + ! ---------------------------------------------------------------------
  62526. + ! exponent(A) is 0x7ff
  62527. + ! ---------------------------------------------------------------------
  62528. +.LGAinfnan:
  62529. + or MANAH, MANAH, MANAL
  62530. + bne MANAH, SIGN, .LGnan ! A is NaN, return NaN
  62531. + ! A is inf: check whether B is finite.
  62532. + beq W3, EXPOB, .LGnan ! both inf/inf and inf/NaN are NaN
  62533. + ! inf/finite is inf
  62534. +.LGinf:
  62535. + move P1L, #0
  62536. + move P1H, #0x7ff00000
  62537. + or P1H, P1H, AXORB
  62538. + pop25 $r10, #16
  62539. +
  62540. + ! ---------------------------------------------------------------------
  62541. + ! exponent(B) is 0x7ff
  62542. + ! ---------------------------------------------------------------------
  62543. +.LGBinfnan:
  62544. + or MANBH, MANBH, MANBL
  62545. + bne MANBH, SIGN, .LGnan ! B is NaN, return NaN
  62546. + ! B is inf: finite/inf is zero
  62547. + move P1L, #0
  62548. + b .LGsetsign
  62549. +
  62550. + ! ---------------------------------------------------------------------
  62551. + ! exponent(B) is 0x000
  62552. + ! ---------------------------------------------------------------------
  62553. +.LGBexpzero:
  62554. + or $r15, MANBH, MANBL
  62555. + beqz $r15, .LGinf ! finite/zero is inf
  62556. + ! B is subnormal
  62557. + srli $r15, MANBL, #31
  62558. + add MANBH, MANBH, MANBH
  62559. + add MANBH, MANBH, $r15
  62560. + add MANBL, MANBL, MANBL
  62561. + ! count leading zeros of B
  62562. + bnez MANBH, .LGBcont
  62563. + move MANBH, MANBL
  62564. + move MANBL, #0
  62565. + addi EXPOB, EXPOB, #-32
  62566. +
  62567. + ! MANBH is non-zero
  62568. +.LGBcont:
  62569. +#ifdef __NDS32_EXT_PERF__
  62570. + clz W4, MANBH
  62571. +#else
  62572. + move W4, #0
  62573. + move W5, MANBH
  62574. + b .LGBloop2
  62575. +
  62576. +.LGBloop:
  62577. + add W5, W5, W5
  62578. + addi W4, W4, #1
  62579. +
  62580. +.LGBloop2:
  62581. + slt $r15, W5, SIGN
  62582. + bnez $r15, .LGBloop
  62583. +#endif
  62584. + beqz W4, .LGmain2
  62585. + sub EXPOB, EXPOB, W4
  62586. + subri W2, W4, #32
  62587. + srl W2, MANBL, W2
  62588. + sll MANBL, MANBL, W4
  62589. + sll MANBH, MANBH, W4
  62590. + or MANBH, MANBH, W2
  62591. + b .LGmain2
  62592. +
  62593. + ! ---------------------------------------------------------------------
  62594. + ! handle underflow
  62595. + ! ---------------------------------------------------------------------
  62596. +.LGunderflow:
  62597. + move MANAL, #0
  62598. + subri W3, EXPOA, #1
  62599. + slti $r15, W3, #0x20
  62600. + bnez $r15, .LGunderflow2
  62601. + move MANAL, P1L
  62602. + move P1L, P1H
  62603. + move P1H, #0
  62604. + addi W3, W3, #0xffffffe0
  62605. + beqz P1L, .LGunderflow2
  62606. + slti $r15, W3, #0x20
  62607. + beqz $r15, .LGignore ! result too small, return zero
  62608. +
  62609. + ! 1-exponent(A), in W3, is 0-31
  62610. +.LGunderflow2:
  62611. + beqz W3, .LGunderflow3 ! it is zero, skip
  62612. + subri W2, W3, #0x20
  62613. + sll MANAH, P1H, W2
  62614. + sll W1, P1L, W2
  62615. + srl P1L, P1L, W3
  62616. + srl P1H, P1H, W3
  62617. + or P1L, P1L, MANAH
  62618. + or MANAL, MANAL, W1
  62619. +! ori W3, P1L, #1
  62620. +! cmovn P1L, W3, MANAL
  62621. + beqz MANAL, .LGunderflow3
  62622. + ori P1L, P1L, #1
  62623. +
  62624. +.LGunderflow3:
  62625. + addi P1L, P1L, #0x400
  62626. + slti $r15, P1L, #0x400
  62627. + add P1H, P1H, $r15
  62628. + srli EXPOA, P1H, #31
  62629. + b .LGround
  62630. +
  62631. +.LGignore:
  62632. + move P1L, #0
  62633. + b .LGsetsign
  62634. + .size __divdf3, .-__divdf3
  62635. +#endif /* L_div_df */
  62636. - #ADDCC(P3H, $0x0)
  62637. - beqzs8 .LL37
  62638. - add P3H, P3H, $r15
  62639. - slt $r15, P3H, $r15
  62640. -.LL37:
  62641. -
  62642. - #ADDC($r6, $0x0)
  62643. - add $r6, $r6, $r15
  62644. -
  62645. -.LFlab8:
  62646. - srli $r10, P3L, #11
  62647. - andi $r10, $r10, #1
  62648. - sub P3L, P3L, $r10
  62649. - srli P1L, P3L, #11
  62650. - slli $r10, P3H, #21
  62651. - or P1L, P1L, $r10
  62652. - slli $r10, P3H, #1
  62653. - srli $r10, $r10, #12
  62654. - or P1H, P1H, $r10
  62655. - slli $r10, $r6, #20
  62656. - or P1H, P1H, $r10
  62657. -.LFret:
  62658. -.LF999:
  62659. - popm $r6, $r10
  62660. - pop $lp
  62661. - ret5 $lp
  62662. -.LFspecA:
  62663. - #ADD(P3L, P3L)
  62664. - move $r15, P3L
  62665. - add P3L, P3L, P3L
  62666. - slt $r15, P3L, $r15
  62667. -
  62668. - #ADDC(P3H, P3H)
  62669. - add P3H, P3H, P3H
  62670. - add P3H, P3H, $r15
  62671. - bnez $r6, .Li15
  62672. - or $r10, P3H, P3L
  62673. - beqz $r10, .Li16
  62674. -
  62675. -
  62676. - #NORMd($r4, P1L, P2H)
  62677. - bnez P3H, .LL38
  62678. - bnez P3L, .LL39
  62679. - move $r6, #0
  62680. - j .LL40
  62681. -.LL39:
  62682. - move P3H, P3L
  62683. - move P3L, #0
  62684. - move P1L, #32
  62685. - sub $r6, $r6, P1L
  62686. -.LL38:
  62687. -#ifndef __big_endian__
  62688. -#ifdef __NDS32_PERF_EXT__
  62689. - clz $r0, P3H
  62690. -#else
  62691. - pushm $r1, P3H
  62692. - move $r0, P3H
  62693. - bal __clzsi2
  62694. - popm $r1, $r5
  62695. -#endif
  62696. -#else /* __big_endian__ */
  62697. -#ifdef __NDS32_PERF_EXT__
  62698. - clz $r1, $r4
  62699. -#else
  62700. - push $r0
  62701. - pushm $r2, $r5
  62702. - move $r0, $r4
  62703. - bal __clzsi2
  62704. - move $r1, $r0
  62705. - popm $r2, $r5
  62706. - pop $r0
  62707. -#endif
  62708. -#endif /* __big_endian__ */
  62709. - beqz P1L, .LL40
  62710. - sub $r6, $r6, P1L
  62711. - subri P2H, P1L, #32
  62712. - srl P2H, P3L, P2H
  62713. - sll P3L, P3L, P1L
  62714. - sll P3H, P3H, P1L
  62715. - or P3H, P3H, P2H
  62716. -.LL40:
  62717. - #NORMd End
  62718. +#ifdef L_mul_sf
  62719. - j .LFlab1
  62720. -.Li16:
  62721. - subri $r15, $r9, #0x7ff
  62722. - beqzs8 .LFnan
  62723. - j .LFret
  62724. -.Li15:
  62725. - or $r10, P3H, P3L
  62726. - bnez $r10, .LFnan
  62727. - bnez $r9, .Li17
  62728. - slli $r10, O1H, #1
  62729. - or $r10, $r10, O1L
  62730. - beqz $r10, .LFnan
  62731. -.Li17:
  62732. - subri $r15, $r9, #0x7ff
  62733. - bnezs8 .LFinf
  62734. -
  62735. -.LFspecB:
  62736. - #ADD(O1L, O1L)
  62737. - move $r15, O1L
  62738. - add O1L, O1L, O1L
  62739. - slt $r15, O1L, $r15
  62740. -
  62741. - #ADDC(O1H, O1H)
  62742. - add O1H, O1H, O1H
  62743. - add O1H, O1H, $r15
  62744. - bnez $r9, .Li18
  62745. - or $r10, O1H, O1L
  62746. - beqz $r10, .Li19
  62747. -
  62748. -
  62749. - #NORMd($r7, P2L, P1L)
  62750. - bnez O1H, .LL41
  62751. - bnez O1L, .LL42
  62752. - move $r9, #0
  62753. - j .LL43
  62754. -.LL42:
  62755. - move O1H, O1L
  62756. - move O1L, #0
  62757. - move P2L, #32
  62758. - sub $r9, $r9, P2L
  62759. -.LL41:
  62760. -#ifndef __big_endian__
  62761. -#ifdef __NDS32_PERF_EXT__
  62762. - clz $r2, $r8
  62763. +#if !defined (__big_endian__)
  62764. + #define P1L $r0
  62765. + #define P1H $r1
  62766. + #define P2L $r2
  62767. + #define P2H $r3
  62768. #else
  62769. - pushm $r0, $r1
  62770. - pushm $r3, $r5
  62771. - move $r0, $r8
  62772. - bal __clzsi2
  62773. - move $r2, $r0
  62774. - popm $r3, $r5
  62775. - popm $r0, $r1
  62776. + #define P1H $r0
  62777. + #define P1L $r1
  62778. + #define P2H $r2
  62779. + #define P2L $r3
  62780. #endif
  62781. -#else /* __big_endian__ */
  62782. -#ifdef __NDS32_PERF_EXT__
  62783. - clz $r3, $r7
  62784. -#else
  62785. - pushm $r0, $r2
  62786. - pushm $r4, $r5
  62787. - move $r0, $r7
  62788. - bal __clzsi2
  62789. - move $r3, $r0
  62790. - popm $r4, $r5
  62791. - popm $r0, $r2
  62792. +#define SIGN $r4
  62793. +#ifdef __NDS32_REDUCE_REGS__
  62794. +#define EXPOA $r6
  62795. +#define MANTA P2L
  62796. +#define VALUA P2H
  62797. +#define EXPOB $r7
  62798. +#define MANTB P1L
  62799. +#define VALUB P1H
  62800. +#define SPROD $r8
  62801. +#else
  62802. +#define EXPOA $r16
  62803. +#define MANTA P2L
  62804. +#define VALUA P2H
  62805. +#define EXPOB $r17
  62806. +#define MANTB P1L
  62807. +#define VALUB P1H
  62808. +#define SPROD $r18
  62809. #endif
  62810. -#endif /* __big_endian__ */
  62811. - beqz P2L, .LL43
  62812. - sub $r9, $r9, P2L
  62813. - subri P1L, P2L, #32
  62814. - srl P1L, O1L, P1L
  62815. - sll O1L, O1L, P2L
  62816. - sll O1H, O1H, P2L
  62817. - or O1H, O1H, P1L
  62818. -.LL43:
  62819. - #NORMd End
  62820. -
  62821. - j .LFlab2
  62822. -.Li19:
  62823. - move P1L, #0
  62824. - j .LFret
  62825. -.Li18:
  62826. - or $r10, O1H, O1L
  62827. - bnez $r10, .LFnan
  62828. -
  62829. -.LFinf:
  62830. - move $r10, #0x7ff00000
  62831. - or P1H, P1H, $r10
  62832. - move P1L, #0
  62833. - j .LFret
  62834. -
  62835. -.LFnan:
  62836. - move P1H, #0xfff80000
  62837. - move P1L, #0
  62838. - j .LFret
  62839. -
  62840. -.LFoveund:
  62841. - bgtz $r6, .LFinf
  62842. - subri P1L, $r6, #1
  62843. - move P2L, #0
  62844. -.LL44:
  62845. - move $r10, #0x20
  62846. - slt $r15, P1L, $r10
  62847. - bnezs8 .LL45
  62848. - or P2L, P2L, P3L
  62849. - move P3L, P3H
  62850. - move P3H, #0
  62851. - addi P1L, P1L, #0xffffffe0
  62852. - bnez P3L, .LL44
  62853. -.LL45:
  62854. - beqz P1L, .LL46
  62855. - move P2H, P3H
  62856. - move $r10, P3L
  62857. - srl P3L, P3L, P1L
  62858. - srl P3H, P3H, P1L
  62859. - subri P1L, P1L, #0x20
  62860. - sll P2H, P2H, P1L
  62861. - or P3L, P3L, P2H
  62862. - sll $r10, $r10, P1L
  62863. - or P2L, P2L, $r10
  62864. - beqz P2L, .LL46
  62865. - ori P3L, P3L, #1
  62866. -.LL46:
  62867. - #ADD(P3L, $0x400)
  62868. - move $r15, #0x400
  62869. - add P3L, P3L, $r15
  62870. - slt $r15, P3L, $r15
  62871. -
  62872. - #ADDC(P3H, $0x0)
  62873. - add P3H, P3H, $r15
  62874. - srli $r6, P3H, #31
  62875. - j .LFlab8
  62876. - .size __muldf3, .-__muldf3
  62877. -#endif /* L_mul_df */
  62878. -
  62879. -
  62880. -
  62881. -#ifdef L_div_sf
  62882. +#define W0 VALUB
  62883. +#define W1 $r5
  62884. .text
  62885. .align 2
  62886. - .global __divsf3
  62887. - .type __divsf3, @function
  62888. -__divsf3:
  62889. - push $lp
  62890. - pushm $r6, $r10
  62891. -
  62892. - move $r7, #0x80000000
  62893. - srli $r4, $r0, #23
  62894. - andi $r4, $r4, #0xff
  62895. - srli $r6, $r1, #23
  62896. - andi $r6, $r6, #0xff
  62897. - slli $r3, $r0, #8
  62898. - or $r3, $r3, $r7
  62899. - slli $r5, $r1, #8
  62900. - or $r5, $r5, $r7
  62901. - xor $r10, $r0, $r1
  62902. - and $r7, $r7, $r10
  62903. -
  62904. - addi $r10, $r4, #-1
  62905. - slti $r15, $r10, #0xfe
  62906. - beqzs8 .LGspecA
  62907. -
  62908. -.LGlab1:
  62909. - addi $r10, $r6, #-1
  62910. - slti $r15, $r10, #0xfe
  62911. - beqzs8 .LGspecB
  62912. -
  62913. -.LGlab2:
  62914. - slt $r15, $r3, $r5
  62915. - bnezs8 .Li27
  62916. - srli $r3, $r3, #1
  62917. - addi $r4, $r4, #1
  62918. -.Li27:
  62919. - srli $r8, $r5, #14
  62920. - divr $r0, $r2, $r3, $r8
  62921. - andi $r9, $r5, #0x3fff
  62922. - mul $r1, $r9, $r0
  62923. - slli $r2, $r2, #14
  62924. -
  62925. - #SUB($r2, $r1)
  62926. - move $r15, $r2
  62927. - sub $r2, $r2, $r1
  62928. - slt $r15, $r15, $r2
  62929. - beqzs8 .Li28
  62930. - addi $r0, $r0, #-1
  62931. -
  62932. - #ADD($r2, $r5)
  62933. - add $r2, $r2, $r5
  62934. - slt $r15, $r2, $r5
  62935. -.Li28:
  62936. - divr $r3, $r2, $r2, $r8
  62937. - mul $r1, $r9, $r3
  62938. - slli $r2, $r2, #14
  62939. -
  62940. - #SUB($r2, $r1)
  62941. - move $r15, $r2
  62942. - sub $r2, $r2, $r1
  62943. - slt $r15, $r15, $r2
  62944. - beqzs8 .Li29
  62945. - addi $r3, $r3, #-1
  62946. -
  62947. - #ADD($r2, $r5)
  62948. - add $r2, $r2, $r5
  62949. - slt $r15, $r2, $r5
  62950. -.Li29:
  62951. - slli $r10, $r0, #14
  62952. - add $r3, $r3, $r10
  62953. - slli $r3, $r3, #4
  62954. - beqz $r2, .Li30
  62955. - ori $r3, $r3, #1
  62956. -.Li30:
  62957. - subri $r10, $r6, #0x7e
  62958. - add $r4, $r4, $r10
  62959. - addi $r10, $r4, #-1
  62960. - slti $r15, $r10, #0xfe
  62961. - beqzs8 .LGoveund
  62962. -
  62963. -.LGlab8:
  62964. - #ADD($r3, $0x80)
  62965. - move $r15, #0x80
  62966. - add $r3, $r3, $r15
  62967. - slt $r15, $r3, $r15
  62968. -
  62969. - #ADDC($r4, $0x0)
  62970. - add $r4, $r4, $r15
  62971. - srli $r10, $r3, #8
  62972. - andi $r10, $r10, #1
  62973. - sub $r3, $r3, $r10
  62974. - slli $r3, $r3, #1
  62975. - srli $r3, $r3, #9
  62976. - slli $r10, $r4, #23
  62977. - or $r3, $r3, $r10
  62978. - or $r0, $r3, $r7
  62979. -
  62980. -.LG999:
  62981. - popm $r6, $r10
  62982. - pop $lp
  62983. - ret5 $lp
  62984. + .global __mulsf3
  62985. + .type __mulsf3, @function
  62986. +__mulsf3:
  62987. +#ifdef __NDS32_REDUCE_REGS__
  62988. + smw.adm $r6, [$sp], $r8, 2
  62989. +#endif
  62990. -.LGspecA:
  62991. - bnez $r4, .Li31
  62992. - add $r3, $r3, $r3
  62993. - beqz $r3, .Li31
  62994. -#ifdef __NDS32_PERF_EXT__
  62995. - clz $r8, $r3
  62996. -#else
  62997. - pushm $r0, $r5
  62998. - move $r0, $r3
  62999. - bal __clzsi2
  63000. - move $r8, $r0
  63001. - popm $r0, $r5
  63002. + xor SPROD, $r1, $r0
  63003. + move SIGN, #0x80000000
  63004. + and SPROD, SPROD, SIGN ! sign(A xor B)
  63005. + slli VALUA, $r0, 1 ! A<<1
  63006. + slli VALUB, $r1, 1 ! B<<1
  63007. + srli EXPOA, VALUA, 24 ! exponent(A)
  63008. + srli EXPOB, VALUB, 24 ! exponent(B)
  63009. + slli MANTA, VALUA, 7 ! mantissa(A)<<8
  63010. + slli MANTB, VALUB, 7 ! mantissa(B)<<8
  63011. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63012. + beqz EXPOA, .LFzeroAexp ! exponent(A) is zero, goto .LFzeroAexp
  63013. + beqc EXPOA, 0xff, .LFinfnanA ! A is inf or NaN, goto .LFinfnanA
  63014. +#else
  63015. + move W1, #0xff
  63016. + beqz EXPOA, .LFzeroAexp ! exponent(A) is zero, goto .LFzeroAexp
  63017. + beq W1, EXPOA, .LFinfnanA ! A is inf or NaN, goto .LFinfnanA
  63018. #endif
  63019. - sub $r4, $r4, $r8
  63020. - sll $r3, $r3, $r8
  63021. - j .LGlab1
  63022. -.Li31:
  63023. - bne $r6, $r4, .Li33
  63024. - add $r10, $r5, $r5
  63025. - beqz $r10, .LGnan
  63026. -.Li33:
  63027. - subri $r15, $r6, #0xff
  63028. - beqzs8 .LGspecB
  63029. - beqz $r4, .LGzer
  63030. - add $r10, $r3, $r3
  63031. - bnez $r10, .LGnan
  63032. - j .LGinf
  63033. -
  63034. -.LGspecB:
  63035. - bnez $r6, .Li34
  63036. - add $r5, $r5, $r5
  63037. - beqz $r5, .LGinf
  63038. -#ifdef __NDS32_PERF_EXT__
  63039. - clz $r8, $r5
  63040. + or MANTA, MANTA, SIGN
  63041. +
  63042. +.LFlab1:
  63043. + beqz EXPOB, .LFzeroB ! exponent(B) is zero, goto .LFzeroB
  63044. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63045. + beqc EXPOB, 0xff, .LFinfnanB ! B is inf or NaN, goto .LFinfnanB
  63046. #else
  63047. - pushm $r0, $r5
  63048. - move $r0, $r5
  63049. - bal __clzsi2
  63050. - move $r8, $r0
  63051. - popm $r0, $r5
  63052. + beq W1, EXPOB, .LFinfnanB ! B is inf or NaN, goto .LFinfnanB
  63053. #endif
  63054. - sub $r6, $r6, $r8
  63055. - sll $r5, $r5, $r8
  63056. - j .LGlab2
  63057. -.Li34:
  63058. - add $r10, $r5, $r5
  63059. - bnez $r10, .LGnan
  63060. -
  63061. -.LGzer:
  63062. - move $r0, $r7
  63063. - j .LG999
  63064. -
  63065. -.LGoveund:
  63066. - bgtz $r4, .LGinf
  63067. - subri $r8, $r4, #1
  63068. - slti $r15, $r8, #0x20
  63069. - beqzs8 .LGzer
  63070. - subri $r10, $r8, #0x20
  63071. - sll $r4, $r3, $r10
  63072. - srl $r3, $r3, $r8
  63073. - beqz $r4, .Li37
  63074. - ori $r3, $r3, #2
  63075. -.Li37:
  63076. - move $r4, #0
  63077. - addi $r10, $r3, #0x80
  63078. - sltsi $r15, $r10, #0
  63079. - beqzs8 .LGlab8
  63080. - move $r4, #1
  63081. - j .LGlab8
  63082. -
  63083. -.LGinf:
  63084. - move $r10, #0x7f800000
  63085. - or $r0, $r7, $r10
  63086. - j .LG999
  63087. -
  63088. -.LGnan:
  63089. - move $r0, #0xffc00000
  63090. - j .LG999
  63091. - .size __divsf3, .-__divsf3
  63092. -#endif /* L_div_sf */
  63093. + or MANTB, MANTB, SIGN
  63094. -
  63095. -
  63096. -#ifdef L_div_df
  63097. -
  63098. -#ifndef __big_endian__
  63099. - #define P1L $r0
  63100. - #define P1H $r1
  63101. - #define P2L $r2
  63102. - #define P2H $r3
  63103. - #define P3L $r4
  63104. - #define P3H $r5
  63105. - #define O1L $r7
  63106. - #define O1H $r8
  63107. + ! ---------------------------------------------------------------------
  63108. + ! This is a 64-bit multiplication.
  63109. + ! ---------------------------------------------------------------------
  63110. +.LFlab2:
  63111. +#ifdef __NDS32_ISA_V3M__
  63112. + move P1H, MANTA
  63113. + bal umul_ppmm
  63114. #else
  63115. - #define P1H $r0
  63116. - #define P1L $r1
  63117. - #define P2H $r2
  63118. - #define P2L $r3
  63119. - #define P3H $r4
  63120. - #define P3L $r5
  63121. - #define O1H $r7
  63122. - #define O1L $r8
  63123. + mulr64 $r0, MANTA, MANTB
  63124. #endif
  63125. - .text
  63126. - .align 2
  63127. - .global __divdf3
  63128. - .type __divdf3, @function
  63129. -__divdf3:
  63130. - push $lp
  63131. - pushm $r6, $r10
  63132. + ori MANTA, P1H, #1
  63133. + cmovz MANTA, P1H, P1L
  63134. + sltsi $r15, MANTA, #0
  63135. + bnezs8 .Li18
  63136. + slli MANTA, MANTA, #1
  63137. + addi EXPOA, EXPOA, #-1
  63138. - slli $r6, P1H, #1
  63139. - srli $r6, $r6, #21
  63140. - slli P3H, P1H, #11
  63141. - srli $r10, P1L, #21
  63142. - or P3H, P3H, $r10
  63143. - slli P3L, P1L, #11
  63144. - move O1L, #0x80000000
  63145. - or P3H, P3H, O1L
  63146. - slli $r9, P2H, #1
  63147. - srli $r9, $r9, #21
  63148. - slli O1H, P2H, #11
  63149. - srli $r10, P2L, #21
  63150. - or O1H, O1H, $r10
  63151. - or O1H, O1H, O1L
  63152. - xor P1H, P1H, P2H
  63153. - and P1H, P1H, O1L
  63154. - slli O1L, P2L, #11
  63155. -
  63156. - addi $r10, $r6, #-1
  63157. - slti $r15, $r10, #0x7fe
  63158. - beqzs8 .LGspecA
  63159. +.Li18:
  63160. + addi W1, EXPOB, #0xffffff82
  63161. + add EXPOA, EXPOA, W1
  63162. + blez EXPOA, .LFunder ! A*B underflow, goto .LFunder
  63163. + slti $r15, EXPOA, #0xff
  63164. + beqz $r15, .LFinf ! A*B overflow, goto .LFinf
  63165. +
  63166. + ! ---------------------------------------------------------------------
  63167. + ! do rounding
  63168. + ! ---------------------------------------------------------------------
  63169. +.LFround:
  63170. + addi MANTA, MANTA, #128
  63171. + slti $r15, MANTA, #128
  63172. + add EXPOA, EXPOA, $r15
  63173. + srli W1, MANTA, #8
  63174. + andi W1, W1, #1
  63175. + sub MANTA, MANTA, W1
  63176. +
  63177. + ! ---------------------------------------------------------------------
  63178. + ! pack result
  63179. + ! ---------------------------------------------------------------------
  63180. + slli MANTA, MANTA, #1
  63181. + srli MANTA, MANTA, #9
  63182. + slli $r0, EXPOA, #23
  63183. + or $r0, $r0, MANTA
  63184. +.LFpack:
  63185. + or $r0, $r0, SPROD
  63186. -.LGlab1:
  63187. - addi $r10, $r9, #-1
  63188. - slti $r15, $r10, #0x7fe
  63189. - beqzs8 .LGspecB
  63190. +.LFret:
  63191. +#ifdef __NDS32_REDUCE_REGS__
  63192. + lmw.bim $r6, [$sp], $r8, 2
  63193. +#endif
  63194. + ret5 $lp
  63195. -.LGlab2:
  63196. - sub $r6, $r6, $r9
  63197. - addi $r6, $r6, #0x3ff
  63198. - srli P3L, P3L, #1
  63199. - slli $r10, P3H, #31
  63200. - or P3L, P3L, $r10
  63201. - srli P3H, P3H, #1
  63202. - srli $r9, O1H, #16
  63203. - divr P2H, P3H, P3H, $r9
  63204. - move $r10, #0xffff
  63205. - and P2L, O1H, $r10
  63206. - mul P1L, P2L, P2H
  63207. - slli P3H, P3H, #16
  63208. - srli $r10, P3L, #16
  63209. - or P3H, P3H, $r10
  63210. -
  63211. - #SUB(P3H, P1L)
  63212. - move $r15, P3H
  63213. - sub P3H, P3H, P1L
  63214. - slt $r15, $r15, P3H
  63215. - beqzs8 .Li20
  63216. -
  63217. -.Lb21:
  63218. - addi P2H, P2H, #-1
  63219. - add P3H, P3H, O1H
  63220. - slt $r15, P3H, O1H
  63221. - beqzs8 .Lb21
  63222. -.Li20:
  63223. - divr $r9, P3H, P3H, $r9
  63224. - mul P1L, P2L, $r9
  63225. - slli P3H, P3H, #16
  63226. - move $r15, #0xffff
  63227. - and $r10, P3L, $r15
  63228. - or P3H, P3H, $r10
  63229. -
  63230. - #SUB(P3H, P1L)
  63231. - move $r15, P3H
  63232. - sub P3H, P3H, P1L
  63233. - slt $r15, $r15, P3H
  63234. - beqzs8 .Li22
  63235. -
  63236. -.Lb23:
  63237. - addi $r9, $r9, #-1
  63238. - add P3H, P3H, O1H
  63239. - slt $r15, P3H, O1H
  63240. - beqzs8 .Lb23
  63241. -.Li22:
  63242. - slli P2H, P2H, #16
  63243. - add P2H, P2H, $r9
  63244. + ! ---------------------------------------------------------------------
  63245. + ! exponent(A) is 0x00
  63246. + ! ---------------------------------------------------------------------
  63247. +.LFzeroAexp:
  63248. +#ifdef __NDS32_EXT_PERF__
  63249. + beqz MANTA, .LFzeroA ! A is zero
  63250. -/* This is a 64-bit multiple. */
  63251. -#ifndef __big_endian__
  63252. -/* For little endian: ($r0, $r9) is (high, low). */
  63253. - move $r10, $r1
  63254. -#ifndef __NDS32_ISA_V3M__
  63255. - mulr64 $r0, $r3, $r7
  63256. + ! A is denorm
  63257. + add MANTA, MANTA, MANTA
  63258. + clz $r15, MANTA
  63259. + sub EXPOA, EXPOA, $r15
  63260. + sll MANTA, MANTA, $r15
  63261. + b .LFlab1
  63262. +
  63263. +.LFzeroA:
  63264. + ! A is zero
  63265. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63266. + beqc EXPOB, 0xff, .LFnan ! zero * inf = zero * NaN = NaN
  63267. #else
  63268. - pushm $r2, $r5
  63269. - move $r0, $r3
  63270. - movi $r1, #0
  63271. - move $r2, $r7
  63272. - movi $r3, #0
  63273. - bal __muldi3
  63274. - popm $r2, $r5
  63275. + beq W1, EXPOB,.LFnan ! zero * inf = zero * NaN = NaN
  63276. #endif
  63277. - move $r9, $r0
  63278. - move $r0, $r1
  63279. - move $r1, $r10
  63280. -#else /* __big_endian__ */
  63281. -/* For big endian: ($r1, $r9) is (high, low). */
  63282. - move $r10, $r0
  63283. -#ifndef __NDS32_ISA_V3M__
  63284. - mulr64 $r0, $r2, $r8
  63285. -#else
  63286. - pushm $r2, $r5
  63287. - move $r1, $r2
  63288. - movi $r0, #0
  63289. - move $r3, $r8
  63290. - movi $r2, #0
  63291. - bal __muldi3
  63292. - popm $r2, $r5
  63293. -#endif
  63294. - move $r9, $r1
  63295. - move $r1, $r0
  63296. - move $r0, $r10
  63297. -#endif /* __big_endian__ */
  63298. - move P3L, #0
  63299. +.LFzero:
  63300. + move $r0, SPROD
  63301. + b .LFret
  63302. +#else
  63303. + bnez MANTA, .LFloopA2 ! A is denorm
  63304. - #SUB(P3L, $r9)
  63305. - move $r15, P3L
  63306. - sub P3L, P3L, $r9
  63307. - slt $r15, $r15, P3L
  63308. -
  63309. -
  63310. - #SUBCC(P3H, P1L)
  63311. - beqzs8 .LL47
  63312. - move $r15, P3H
  63313. - sub P3H, P3H, P1L
  63314. - slt $r15, $r15, P3H
  63315. - beqzs8 .LL48
  63316. - subi333 P3H, P3H, #1
  63317. - j .LL49
  63318. -.LL48:
  63319. - move $r15, P3H
  63320. - subi333 P3H, P3H, #1
  63321. - slt $r15, $r15, P3H
  63322. - j .LL49
  63323. -.LL47:
  63324. - move $r15, P3H
  63325. - sub P3H, P3H, P1L
  63326. - slt $r15, $r15, P3H
  63327. -.LL49:
  63328. + ! A is zero
  63329. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63330. + beqc EXPOB, 0xff, .LFnan ! zero * inf = zero * NaN = NaN
  63331. +#else
  63332. + beq W1, EXPOB,.LFnan ! zero * inf = zero * NaN = NaN
  63333. +#endif
  63334. - beqzs8 .Li24
  63335. +.LFzero:
  63336. + move $r0, SPROD
  63337. + b .LFret
  63338. -.LGlab3:
  63339. - addi P2H, P2H, #-1
  63340. +.LFloopA:
  63341. + addi EXPOA, EXPOA, #-1
  63342. +.LFloopA2:
  63343. + add MANTA, MANTA, MANTA
  63344. + slt $r15, MANTA, SIGN
  63345. + bnez $r15, .LFloopA
  63346. + b .LFlab1
  63347. +#endif
  63348. - #ADD(P3L, O1L)
  63349. - add P3L, P3L, O1L
  63350. - slt $r15, P3L, O1L
  63351. -
  63352. -
  63353. - #ADDCC(P3H, O1H)
  63354. - beqzs8 .LL50
  63355. - add P3H, P3H, O1H
  63356. - slt $r15, P3H, O1H
  63357. - beqzs8 .LL51
  63358. - addi P3H, P3H, #0x1
  63359. - j .LL52
  63360. -.LL51:
  63361. - move $r15, #1
  63362. - add P3H, P3H, $r15
  63363. - slt $r15, P3H, $r15
  63364. - j .LL52
  63365. -.LL50:
  63366. - add P3H, P3H, O1H
  63367. - slt $r15, P3H, O1H
  63368. -.LL52:
  63369. -
  63370. - beqzs8 .LGlab3
  63371. -.Li24:
  63372. - bne P3H, O1H, .Li25
  63373. - move P1L, O1L
  63374. - move P3H, P3L
  63375. - move $r9, #0
  63376. - move P2L, $r9
  63377. - j .Le25
  63378. -.Li25:
  63379. - srli P2L, O1H, #16
  63380. - divr $r9, P3H, P3H, P2L
  63381. - move $r10, #0xffff
  63382. - and $r10, O1H, $r10
  63383. - mul P1L, $r10, $r9
  63384. - slli P3H, P3H, #16
  63385. - srli $r15, P3L, #16
  63386. - or P3H, P3H, $r15
  63387. -
  63388. - #SUB(P3H, P1L)
  63389. - move $r15, P3H
  63390. - sub P3H, P3H, P1L
  63391. - slt $r15, $r15, P3H
  63392. - beqzs8 .Li26
  63393. -
  63394. -.Lb27:
  63395. - addi $r9, $r9, #-1
  63396. - add P3H, P3H, O1H
  63397. - slt $r15, P3H, O1H
  63398. - beqzs8 .Lb27
  63399. -.Li26:
  63400. - divr P2L, P3H, P3H, P2L
  63401. - mul P1L, $r10, P2L
  63402. - slli P3H, P3H, #16
  63403. - move $r10, #0xffff
  63404. - and $r10, P3L, $r10
  63405. - or P3H, P3H, $r10
  63406. -
  63407. - #SUB(P3H, P1L)
  63408. - move $r15, P3H
  63409. - sub P3H, P3H, P1L
  63410. - slt $r15, $r15, P3H
  63411. - beqzs8 .Li28
  63412. -
  63413. -.Lb29:
  63414. - addi P2L, P2L, #-1
  63415. - add P3H, P3H, O1H
  63416. - slt $r15, P3H, O1H
  63417. - beqzs8 .Lb29
  63418. -.Li28:
  63419. - slli $r9, $r9, #16
  63420. - add $r9, $r9, P2L
  63421. + ! ---------------------------------------------------------------------
  63422. + ! exponent(A) is 0xff
  63423. + ! ---------------------------------------------------------------------
  63424. +.LFinfnanA:
  63425. + bne MANTA, SIGN, .LFnan ! A is NaN: NaN * B = NaN
  63426. -/* This is a 64-bit multiple. */
  63427. -#ifndef __big_endian__
  63428. -/* For little endian: ($r0, $r2) is (high, low). */
  63429. - move $r10, $r1
  63430. -#ifndef __NDS32_ISA_V3M__
  63431. - mulr64 $r0, $r9, $r7
  63432. + ! A is inf
  63433. + beqz VALUB, .LFnan ! B is zero: inf * zero = NaN
  63434. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63435. + bnec EXPOB, 0xff, .LFinf ! B is finite: inf * B = inf
  63436. #else
  63437. - pushm $r2, $r5
  63438. - move $r0, $r9
  63439. - movi $r1, #0
  63440. - move $r2, $r7
  63441. - movi $r3, #0
  63442. - bal __muldi3
  63443. - popm $r2, $r5
  63444. + bne W1, EXPOB, .LFinf ! B is finite: inf * B = inf
  63445. #endif
  63446. - move $r2, $r0
  63447. - move $r0, $r1
  63448. - move $r1, $r10
  63449. -#else /* __big_endian__ */
  63450. -/* For big endian: ($r1, $r3) is (high, low). */
  63451. - move $r10, $r0
  63452. -#ifndef __NDS32_ISA_V3M__
  63453. - mulr64 $r0, $r9, $r8
  63454. -#else
  63455. - pushm $r2, $r5
  63456. - move $r0, $r9
  63457. - movi $r1, #0
  63458. - move $r2, $r7
  63459. - movi $r3, #0
  63460. - bal __muldi3
  63461. - popm $r2, $r5
  63462. -#endif
  63463. - move $r3, $r1
  63464. - move $r1, $r0
  63465. - move $r0, $r10
  63466. -#endif /* __big_endian__ */
  63467. -
  63468. -.Le25:
  63469. - move P3L, #0
  63470. - #SUB(P3L, P2L)
  63471. - move $r15, P3L
  63472. - sub P3L, P3L, P2L
  63473. - slt $r15, $r15, P3L
  63474. -
  63475. -
  63476. - #SUBCC(P3H, P1L)
  63477. - beqzs8 .LL53
  63478. - move $r15, P3H
  63479. - sub P3H, P3H, P1L
  63480. - slt $r15, $r15, P3H
  63481. - beqzs8 .LL54
  63482. - subi333 P3H, P3H, #1
  63483. - j .LL55
  63484. -.LL54:
  63485. - move $r15, P3H
  63486. - subi333 P3H, P3H, #1
  63487. - slt $r15, $r15, P3H
  63488. - j .LL55
  63489. -.LL53:
  63490. - move $r15, P3H
  63491. - sub P3H, P3H, P1L
  63492. - slt $r15, $r15, P3H
  63493. -.LL55:
  63494. + ! ---------------------------------------------------------------------
  63495. + ! exponent(B) is 0xff
  63496. + ! ---------------------------------------------------------------------
  63497. +.LFinfnanB:
  63498. + bne MANTB, SIGN, .LFnan ! B is NaN: A * NaN = NaN
  63499. - beqzs8 .Li30
  63500. +.LFinf:
  63501. + move $r0, #0x7f800000
  63502. + b .LFpack
  63503. -.LGlab4:
  63504. - addi $r9, $r9, #-1
  63505. + ! ---------------------------------------------------------------------
  63506. + ! exponent(B) is 0x00
  63507. + ! ---------------------------------------------------------------------
  63508. +.LFzeroB:
  63509. +#ifdef __NDS32_EXT_PERF__
  63510. + beqz MANTB, .LFzero ! B is zero
  63511. +
  63512. + ! B is denorm
  63513. + add MANTB, MANTB, MANTB
  63514. + clz $r15, MANTB
  63515. + sub EXPOB, EXPOB, $r15
  63516. + sll MANTB, MANTB, $r15
  63517. +#else
  63518. + bnez MANTB, .LFloopB2 ! B is denorm
  63519. + b .LFzero ! B is zero
  63520. +.LFloopB:
  63521. + addi EXPOB, EXPOB, #-1
  63522. +.LFloopB2:
  63523. + add MANTB, MANTB, MANTB
  63524. + slt $r15, MANTB, SIGN
  63525. + bnez $r15, .LFloopB
  63526. +#endif
  63527. + b .LFlab2
  63528. - #ADD(P3L, O1L)
  63529. - add P3L, P3L, O1L
  63530. - slt $r15, P3L, O1L
  63531. -
  63532. -
  63533. - #ADDCC(P3H, O1H)
  63534. - beqzs8 .LL56
  63535. - add P3H, P3H, O1H
  63536. - slt $r15, P3H, O1H
  63537. - beqzs8 .LL57
  63538. - addi P3H, P3H, #0x1
  63539. - j .LL58
  63540. -.LL57:
  63541. - move $r15, #1
  63542. - add P3H, P3H, $r15
  63543. - slt $r15, P3H, $r15
  63544. - j .LL58
  63545. -.LL56:
  63546. - add P3H, P3H, O1H
  63547. - slt $r15, P3H, O1H
  63548. -.LL58:
  63549. -
  63550. - beqzs8 .LGlab4
  63551. -.Li30:
  63552. - sltsi $r15, P2H, #0
  63553. - bnezs8 .Li31
  63554. -
  63555. - #ADD($r9, $r9)
  63556. - move $r15, $r9
  63557. - add $r9, $r9, $r9
  63558. - slt $r15, $r9, $r15
  63559. +.LFnan:
  63560. + move $r0, #0xffc00000
  63561. + b .LFret
  63562. - #ADDC(P2H, P2H)
  63563. - add P2H, P2H, P2H
  63564. - add P2H, P2H, $r15
  63565. - addi $r6, $r6, #-1
  63566. -.Li31:
  63567. - or $r10, P3H, P3L
  63568. - beqz $r10, .Li32
  63569. - ori $r9, $r9, #1
  63570. -.Li32:
  63571. - move P3H, P2H
  63572. - move P3L, $r9
  63573. - addi $r10, $r6, #-1
  63574. - slti $r15, $r10, #0x7fe
  63575. - beqzs8 .LGoveund
  63576. + ! ---------------------------------------------------------------------
  63577. + ! A*B underflow
  63578. + ! ---------------------------------------------------------------------
  63579. +.LFunder:
  63580. + subri W0, EXPOA, #1
  63581. + slti $r15, W0, #0x20
  63582. + beqzs8 .LFzero
  63583. + subri W1, W0, #0x20
  63584. + sll EXPOA, MANTA, W1
  63585. + srl MANTA, MANTA, W0
  63586. + beqz EXPOA, .LFunder2
  63587. + ori MANTA, MANTA, #2
  63588. +.LFunder2:
  63589. + addi W1, MANTA, #0x80
  63590. + sltsi EXPOA, W1, #0
  63591. + b .LFround
  63592. + .size __mulsf3, .-__mulsf3
  63593. +#endif /* L_mul_sf */
  63594. - #ADD(P3L, $0x400)
  63595. - move $r15, #0x400
  63596. - add P3L, P3L, $r15
  63597. - slt $r15, P3L, $r15
  63598. - #ADDCC(P3H, $0x0)
  63599. - beqzs8 .LL61
  63600. - add P3H, P3H, $r15
  63601. - slt $r15, P3H, $r15
  63602. -.LL61:
  63603. -
  63604. - #ADDC($r6, $0x0)
  63605. - add $r6, $r6, $r15
  63606. -
  63607. -.LGlab8:
  63608. - srli $r10, P3L, #11
  63609. - andi $r10, $r10, #1
  63610. - sub P3L, P3L, $r10
  63611. - srli P1L, P3L, #11
  63612. - slli $r10, P3H, #21
  63613. - or P1L, P1L, $r10
  63614. - slli $r10, P3H, #1
  63615. - srli $r10, $r10, #12
  63616. - or P1H, P1H, $r10
  63617. - slli $r10, $r6, #20
  63618. - or P1H, P1H, $r10
  63619. +#ifdef L_div_sf
  63620. -.LGret:
  63621. -.LG999:
  63622. - popm $r6, $r10
  63623. - pop $lp
  63624. - ret5 $lp
  63625. +#define SIGN $r4
  63626. +#ifdef __NDS32_REDUCE_REGS__
  63627. +#define EXPOA $r6
  63628. +#define MANTA $r2
  63629. +#define VALUA $r2
  63630. +#define EXPOB $r7
  63631. +#define MANTB $r3
  63632. +#define VALUB $r1
  63633. +#define SQUOT $r8
  63634. +#define W0 VALUB
  63635. +#define W1 $r5
  63636. +#define W2 $r0
  63637. +#define W3 $r9
  63638. +#else
  63639. +#define EXPOA $r16
  63640. +#define MANTA $r2
  63641. +#define VALUA $r2
  63642. +#define EXPOB $r17
  63643. +#define MANTB $r3
  63644. +#define VALUB $r1
  63645. +#define SQUOT $r18
  63646. +#define W0 VALUB
  63647. +#define W1 $r5
  63648. +#define W2 $r0
  63649. +#define W3 $r19
  63650. +#endif
  63651. +
  63652. +#define DHI W1 // high18(MANTB)
  63653. +#define DLO W3 // low14(MANTB)
  63654. +#define QHI W0 // MANTA / MANTB
  63655. +#define REM W2 // MANTA % MANTB
  63656. -.LGoveund:
  63657. - bgtz $r6, .LGinf
  63658. - subri P2H, $r6, #1
  63659. - move P1L, #0
  63660. -.LL62:
  63661. - move $r10, #0x20
  63662. - slt $r15, P2H, $r10
  63663. - bnezs8 .LL63
  63664. - or P1L, P1L, P3L
  63665. - move P3L, P3H
  63666. - move P3H, #0
  63667. - addi P2H, P2H, #0xffffffe0
  63668. - bnez P3L, .LL62
  63669. -.LL63:
  63670. - beqz P2H, .LL64
  63671. - move P2L, P3H
  63672. - move $r10, P3L
  63673. - srl P3L, P3L, P2H
  63674. - srl P3H, P3H, P2H
  63675. - subri P2H, P2H, #0x20
  63676. - sll P2L, P2L, P2H
  63677. - or P3L, P3L, P2L
  63678. - sll $r10, $r10, P2H
  63679. - or P1L, P1L, $r10
  63680. - beqz P1L, .LL64
  63681. - ori P3L, P3L, #1
  63682. -.LL64:
  63683. - #ADD(P3L, $0x400)
  63684. - move $r15, #0x400
  63685. - add P3L, P3L, $r15
  63686. - slt $r15, P3L, $r15
  63687. + .text
  63688. + .align 2
  63689. + .global __divsf3
  63690. + .type __divsf3, @function
  63691. +__divsf3:
  63692. +#ifdef __NDS32_REDUCE_REGS__
  63693. + smw.adm $r6, [$sp], $r9, 0
  63694. +#endif
  63695. - #ADDC(P3H, $0x0)
  63696. - add P3H, P3H, $r15
  63697. - srli $r6, P3H, #31
  63698. - j .LGlab8
  63699. -
  63700. -.LGspecA:
  63701. - #ADD(P3L, P3L)
  63702. - move $r15, P3L
  63703. - add P3L, P3L, P3L
  63704. - slt $r15, P3L, $r15
  63705. -
  63706. - #ADDC(P3H, P3H)
  63707. - add P3H, P3H, P3H
  63708. - add P3H, P3H, $r15
  63709. - bnez $r6, .Li33
  63710. - or $r10, P3H, P3L
  63711. - beqz $r10, .Li33
  63712. -
  63713. -
  63714. - #NORMd($r4, P2H, P2L)
  63715. - bnez P3H, .LL65
  63716. - bnez P3L, .LL66
  63717. - move $r6, #0
  63718. - j .LL67
  63719. -.LL66:
  63720. - move P3H, P3L
  63721. - move P3L, #0
  63722. - move P2H, #32
  63723. - sub $r6, $r6, P2H
  63724. -.LL65:
  63725. -#ifndef __big_endian__
  63726. -#ifdef __NDS32_PERF_EXT__
  63727. - clz $r3, $r5
  63728. + xor SQUOT, $r1, $r0
  63729. + move SIGN, #0x80000000
  63730. + and SQUOT, SQUOT, SIGN ! sign(A xor B)
  63731. + slli VALUA, $r0, 1 ! A<<1
  63732. + slli VALUB, $r1, 1 ! B<<1
  63733. + srli EXPOA, VALUA, 24 ! exponent(A)
  63734. + srli EXPOB, VALUB, 24 ! exponent(B)
  63735. + slli MANTA, VALUA, 7 ! mantissa(A)<<8
  63736. + slli MANTB, VALUB, 7 ! mantissa(B)<<8
  63737. + beqz EXPOA, .LGzeroAexp ! exponent(A) is zero, goto .LGzeroAexp
  63738. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63739. + beqc EXPOA, 0xff, .LGinfnanA ! A is inf or NaN, goto .LGinfnanA
  63740. #else
  63741. - pushm $r0, $r2
  63742. - pushm $r4, $r5
  63743. - move $r0, $r5
  63744. - bal __clzsi2
  63745. - move $r3, $r0
  63746. - popm $r4, $r5
  63747. - popm $r0, $r2
  63748. + move W1, #0xff
  63749. + beq W1, EXPOA, .LGinfnanA ! A is inf or NaN, goto .LGinfnanA
  63750. #endif
  63751. -#else /* __big_endian__ */
  63752. -#ifdef __NDS32_PERF_EXT__
  63753. - clz $r2, $r4
  63754. + or MANTA, MANTA, SIGN
  63755. +
  63756. +.LGlab1:
  63757. + beqz EXPOB, .LGzeroB ! exponent(B) is zero, goto .LGzeroB
  63758. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  63759. + beqc EXPOB, 0xff, .LGinfnanB ! B is inf or NaN, goto .LGinfnanB
  63760. #else
  63761. - pushm $r0, $r1
  63762. - pushm $r3, $r5
  63763. - move $r0, $r4
  63764. - bal __clzsi2
  63765. - move $r2, $r0
  63766. - popm $r3, $r5
  63767. - popm $r0, $r1
  63768. -#endif
  63769. -#endif /* __big_endian_ */
  63770. - beqz P2H, .LL67
  63771. - sub $r6, $r6, P2H
  63772. - subri P2L, P2H, #32
  63773. - srl P2L, P3L, P2L
  63774. - sll P3L, P3L, P2H
  63775. - sll P3H, P3H, P2H
  63776. - or P3H, P3H, P2L
  63777. -.LL67:
  63778. - #NORMd End
  63779. + beq W1, EXPOB, .LGinfnanB ! B is inf or NaN, goto .LGinfnanB
  63780. +#endif
  63781. + or MANTB, MANTB, SIGN
  63782. - j .LGlab1
  63783. -.Li33:
  63784. - bne $r6, $r9, .Li35
  63785. - slli $r10, O1H, #1
  63786. - or $r10, $r10, O1L
  63787. - beqz $r10, .LGnan
  63788. -.Li35:
  63789. - subri $r15, $r9, #0x7ff
  63790. - beqzs8 .LGspecB
  63791. - beqz $r6, .LGret
  63792. - or $r10, P3H, P3L
  63793. - bnez $r10, .LGnan
  63794. +.LGlab2:
  63795. + slt $r15, MANTA, MANTB
  63796. + bnez $r15, .LGlab3
  63797. + srli MANTA, MANTA, #1
  63798. + addi EXPOA, EXPOA, #1
  63799. -.LGinf:
  63800. - move $r10, #0x7ff00000
  63801. - or P1H, P1H, $r10
  63802. - move P1L, #0
  63803. - j .LGret
  63804. -
  63805. -.LGspecB:
  63806. - #ADD(O1L, O1L)
  63807. - move $r15, O1L
  63808. - add O1L, O1L, O1L
  63809. - slt $r15, O1L, $r15
  63810. -
  63811. - #ADDC(O1H, O1H)
  63812. - add O1H, O1H, O1H
  63813. - add O1H, O1H, $r15
  63814. - bnez $r9, .Li36
  63815. - or $r10, O1H, O1L
  63816. - beqz $r10, .LGinf
  63817. -
  63818. -
  63819. - #NORMd($r7, P2H, P2L)
  63820. - bnez O1H, .LL68
  63821. - bnez O1L, .LL69
  63822. - move $r9, #0
  63823. - j .LL70
  63824. -.LL69:
  63825. - move O1H, O1L
  63826. - move O1L, #0
  63827. - move P2H, #32
  63828. - sub $r9, $r9, P2H
  63829. -.LL68:
  63830. -#ifndef __big_endian__
  63831. -#ifdef __NDS32_PERF_EXT__
  63832. - clz $r3, $r8
  63833. -#else
  63834. - pushm $r0, $r2
  63835. - pushm $r4, $r5
  63836. - move $r0, $r8
  63837. - bal __clzsi2
  63838. - move $r3, $r0
  63839. - popm $r4, $r5
  63840. - popm $r0, $r2
  63841. + ! ---------------------------------------------------------------------
  63842. + ! This is a 64-bit division.
  63843. + ! high part of dividend, MANTA, is smaller than divisor MANTB.
  63844. + ! ---------------------------------------------------------------------
  63845. +.LGlab3:
  63846. + srli DHI, MANTB, #14
  63847. + andi DLO, MANTB, #0x3fff
  63848. + divr QHI, REM, MANTA, DHI
  63849. + mul MANTA, DLO, QHI
  63850. + slli REM, REM, #14
  63851. + slt $r15, REM, MANTA
  63852. + beqz $r15, .LGlab4
  63853. + addi QHI, QHI, #-1
  63854. + add REM, REM, MANTB
  63855. +
  63856. +.LGlab4:
  63857. + sub REM, REM, MANTA
  63858. + divr MANTA, REM, REM, DHI
  63859. + mul DLO, DLO, MANTA
  63860. + slli REM, REM, #14
  63861. + slt $r15, REM, DLO
  63862. + beqz $r15, .LGlab5
  63863. + addi MANTA, MANTA, #-1
  63864. + add REM, REM, MANTB
  63865. +
  63866. +.LGlab5:
  63867. + sub REM, REM, DLO
  63868. + slli W3, QHI, #14
  63869. + add MANTA, MANTA, W3
  63870. + slli MANTA, MANTA, #4
  63871. + beqz REM, .LGlab6
  63872. + ori MANTA, MANTA, #1
  63873. +
  63874. +.LGlab6:
  63875. + subri W1, EXPOB, #0x7e
  63876. + add EXPOA, EXPOA, W1
  63877. + blez EXPOA, .LGunder ! A/B underflow, goto .LGunder
  63878. + slti $r15, EXPOA, #0xff
  63879. + beqz $r15, .LGinf ! A/B overflow, goto .LGinf
  63880. +
  63881. + ! ---------------------------------------------------------------------
  63882. + ! do rounding
  63883. + ! ---------------------------------------------------------------------
  63884. +.LGround:
  63885. + addi MANTA, MANTA, #128
  63886. + slti $r15, MANTA, #128
  63887. + add EXPOA, EXPOA, $r15
  63888. + srli W1, MANTA, #8
  63889. + andi W1, W1, #1
  63890. + sub MANTA, MANTA, W1
  63891. +
  63892. + ! ---------------------------------------------------------------------
  63893. + ! pack result
  63894. + ! ---------------------------------------------------------------------
  63895. + slli MANTA, MANTA, #1
  63896. + srli MANTA, MANTA, #9
  63897. + slli $r0, EXPOA, #23
  63898. + or $r0, $r0, MANTA
  63899. +.LGpack:
  63900. + or $r0, $r0, SQUOT
  63901. +
  63902. +.LGret:
  63903. +#ifdef __NDS32_REDUCE_REGS__
  63904. + lmw.bim $r6, [$sp], $r9, 0
  63905. #endif
  63906. -#else /* __big_endian__ */
  63907. -#ifdef __NDS32_PERF_EXT__
  63908. - clz $r2, $r7
  63909. + ret5 $lp
  63910. +
  63911. + ! ---------------------------------------------------------------------
  63912. + ! exponent(A) is 0x00
  63913. + ! ---------------------------------------------------------------------
  63914. +.LGzeroAexp:
  63915. +#ifdef __NDS32_EXT_PERF__
  63916. + add MANTA, MANTA, MANTA
  63917. + beqz MANTA, .LGzeroA
  63918. + clz $r15, MANTA
  63919. + sub EXPOA, EXPOA, $r15
  63920. + sll MANTA, MANTA, $r15
  63921. #else
  63922. - pushm $r0, $r1
  63923. - pushm $r3, $r5
  63924. - move $r0, $r7
  63925. - bal __clzsi2
  63926. - move $r2, $r0
  63927. - popm $r3, $r5
  63928. - popm $r0, $r1
  63929. + bnez MANTA, .LGloopA2
  63930. + b .LGzeroA
  63931. +.LGloopA:
  63932. + addi EXPOA, EXPOA, #-1
  63933. +.LGloopA2:
  63934. + add MANTA, MANTA, MANTA
  63935. + slt $r15, MANTA, SIGN
  63936. + bnez $r15, .LGloopA
  63937. #endif
  63938. -#endif /* __big_endian__ */
  63939. - beqz P2H, .LL70
  63940. - sub $r9, $r9, P2H
  63941. - subri P2L, P2H, #32
  63942. - srl P2L, O1L, P2L
  63943. - sll O1L, O1L, P2H
  63944. - sll O1H, O1H, P2H
  63945. - or O1H, O1H, P2L
  63946. -.LL70:
  63947. - #NORMd End
  63948. + b .LGlab1
  63949. +
  63950. + ! A is 0.0f
  63951. +.LGzeroA:
  63952. + beqz VALUB, .LGnan ! 0.0f / 0.0f = NaN
  63953. + move W1, 0xff000000
  63954. + slt $r15, W1, VALUB
  63955. + bnez $r15, .LGnan ! 0.0f / NaN = NaN
  63956. +
  63957. +.LGzero:
  63958. + move $r0, SQUOT
  63959. + b .LGret
  63960. +
  63961. + ! ---------------------------------------------------------------------
  63962. + ! exponent(A) is 0xff
  63963. + ! ---------------------------------------------------------------------
  63964. +.LGinfnanA:
  63965. + bne MANTA, SIGN, .LGnan ! A is NaN: NaN / B = NaN
  63966. +
  63967. + ! A if inf
  63968. + beq EXPOB, EXPOA, .LGnan ! no matter B is inf or NaN
  63969. +
  63970. +.LGinf:
  63971. + move $r0, #0x7f800000
  63972. + or $r0, $r0, SQUOT
  63973. + b .LGret
  63974. - j .LGlab2
  63975. -.Li36:
  63976. - or $r10, O1H, O1L
  63977. - beqz $r10, .Li38
  63978. + ! ---------------------------------------------------------------------
  63979. + ! exponent(B) is 0xff
  63980. + ! ---------------------------------------------------------------------
  63981. +.LGinfnanB:
  63982. + beq MANTB, SIGN, .LGzero ! B is inf: A / inf = 0.0f
  63983. .LGnan:
  63984. - move P1H, #0xfff80000
  63985. -.Li38:
  63986. - move P1L, #0
  63987. - j .LGret
  63988. - .size __divdf3, .-__divdf3
  63989. -#endif /* L_div_df */
  63990. + move $r0, #0xffc00000
  63991. + b .LGret
  63992. +
  63993. + ! ---------------------------------------------------------------------
  63994. + ! exponent(B) is 0x00
  63995. + ! ---------------------------------------------------------------------
  63996. +.LGzeroB:
  63997. +#ifdef __NDS32_EXT_PERF__
  63998. + add MANTB, MANTB, MANTB
  63999. + beqz MANTB, .LGinf
  64000. + clz $r15, MANTB
  64001. + sub EXPOB, EXPOB, $r15
  64002. + sll MANTB, MANTB, $r15
  64003. +#else
  64004. + bnez MANTB, .LGloopB2
  64005. + b .LGinf
  64006. +.LGloopB:
  64007. + addi EXPOB, EXPOB, #-1
  64008. +.LGloopB2:
  64009. + add MANTB, MANTB, MANTB
  64010. + slt $r15, MANTB, SIGN
  64011. + bnez $r15, .LGloopB
  64012. +#endif
  64013. + b .LGlab2
  64014. +
  64015. + ! ---------------------------------------------------------------------
  64016. + ! A/B underflow
  64017. + ! ---------------------------------------------------------------------
  64018. +.LGunder:
  64019. + subri W0, EXPOA, #1
  64020. + slti $r15, W0, #0x20
  64021. + beqzs8 .LGzero
  64022. + subri W1, W0, #0x20
  64023. + sll EXPOA, MANTA, W1
  64024. + srl MANTA, MANTA, W0
  64025. + beqz EXPOA, .LGunder2
  64026. + ori MANTA, MANTA, #2
  64027. +.LGunder2:
  64028. + addi W1, MANTA, #0x80
  64029. + sltsi EXPOA, W1, #0
  64030. + b .LGround
  64031. + .size __divsf3, .-__divsf3
  64032. +#endif /* L_div_sf */
  64033. @@ -3553,13 +3439,8 @@
  64034. .global __negsf2
  64035. .type __negsf2, @function
  64036. __negsf2:
  64037. - push $lp
  64038. -
  64039. move $r1, #0x80000000
  64040. xor $r0, $r0, $r1
  64041. -
  64042. -.LN999:
  64043. - pop $lp
  64044. ret5 $lp
  64045. .size __negsf2, .-__negsf2
  64046. #endif /* L_negate_sf */
  64047. @@ -3578,13 +3459,8 @@
  64048. .global __negdf2
  64049. .type __negdf2, @function
  64050. __negdf2:
  64051. - push $lp
  64052. -
  64053. move $r2, #0x80000000
  64054. xor P1H, P1H, $r2
  64055. -
  64056. -.LP999:
  64057. - pop $lp
  64058. ret5 $lp
  64059. .size __negdf2, .-__negdf2
  64060. #endif /* L_negate_df */
  64061. @@ -3594,64 +3470,83 @@
  64062. #ifdef L_sf_to_df
  64063. #ifndef __big_endian__
  64064. - #define O1L $r1
  64065. - #define O1H $r2
  64066. + #define P1L $r0
  64067. + #define P1H $r1
  64068. #else
  64069. - #define O1H $r1
  64070. - #define O1L $r2
  64071. + #define P1H $r0
  64072. + #define P1L $r1
  64073. #endif
  64074. +#define SIGN $r2
  64075. +#define EXPO $r3
  64076. +#define MANT $r4
  64077. .text
  64078. .align 2
  64079. .global __extendsfdf2
  64080. .type __extendsfdf2, @function
  64081. __extendsfdf2:
  64082. - push $lp
  64083. + slli $r5, $r0, 1
  64084. + beqz $r5, .LJzero ! A-in is zero, goto .LJzero
  64085. - srli $r3, $r0, #23
  64086. - andi $r3, $r3, #0xff
  64087. - move $r5, #0x80000000
  64088. - and O1H, $r0, $r5
  64089. - addi $r5, $r3, #-1
  64090. - slti $r15, $r5, #0xfe
  64091. - beqzs8 .LJspec
  64092. + srli EXPO, $r5, #24 ! exponent(A-in)
  64093. + move $r1, #0x80000000
  64094. + and SIGN, $r1, $r0 ! sign(A-in)
  64095. + slli MANT, $r5, #8 ! mantissa(A-in)
  64096. + beqz EXPO, .LJdenorm ! exponent(A-in) is zerop, goto .LJdenorm
  64097. +#ifndef __FAST_MATH__
  64098. +#if defined(__NDS32_ISA_V3__)||defined(__NDS32_ISA_V3M__)
  64099. + beqc EXPO, #0xff, .LJinfnan ! exponent(A-in) is 0xff, goto .LJinfnan
  64100. +#else
  64101. + slti $r15, EXPO, #0xff
  64102. + beqzs8 .LJinfnan ! exponent(A-in) is 0xff, goto .LJinfnan
  64103. +#endif
  64104. +#endif // end of __FAST_MATH__
  64105. .LJlab1:
  64106. - addi $r3, $r3, #0x380
  64107. - slli $r5, $r0, #9
  64108. - srli $r5, $r5, #12
  64109. - or O1H, O1H, $r5
  64110. - slli O1L, $r0, #29
  64111. + addi EXPO, EXPO, #0x380 ! exponent(A-out)
  64112. + slli P1L, MANT, #20 ! low 32-bit(A-out)
  64113. + srli P1H, MANT, #12 ! high 20-bit mantissa(A-out)
  64114. + or P1H, P1H, SIGN
  64115. + slli EXPO, EXPO, #20
  64116. + or P1H, P1H, EXPO ! high 32-bit(-out)
  64117. + ret5 $lp
  64118. +
  64119. +#ifdef __NDS32_EXT_PERF__
  64120. +.LJdenorm:
  64121. + clz $r1, MANT
  64122. + sub EXPO, EXPO, $r1
  64123. + sll MANT, MANT, $r1
  64124. +#else
  64125. +.LJdenorm2:
  64126. + addi EXPO, EXPO, #-1
  64127. + add MANT, MANT, MANT
  64128. +.LJdenorm:
  64129. + slt $r15, MANT, $r1
  64130. + bnezs8 .LJdenorm2
  64131. +#endif
  64132. + slli MANT, MANT, 1 ! shift out implied 1
  64133. + b .LJlab1
  64134. +#ifndef __FAST_MATH__
  64135. +.LJinfnan:
  64136. + beqz MANT, .LJinf
  64137. + move P1H, 0xfff80000
  64138. + b .LJcont
  64139. -.LJret:
  64140. - slli $r5, $r3, #20
  64141. - or O1H, O1H, $r5
  64142. - move $r0, $r1
  64143. - move $r1, $r2
  64144. -
  64145. -.LJ999:
  64146. - pop $lp
  64147. - ret5 $lp
  64148. +.LJinf:
  64149. + move $r5, 0x700000
  64150. +#ifdef __big_endian__
  64151. + or P1H, $r0, $r5
  64152. +#else
  64153. + or $r0, $r0, $r5
  64154. +#endif
  64155. +#endif // end of __FAST_MATH__
  64156. +.LJzero:
  64157. +#ifndef __big_endian__
  64158. + move P1H, $r0
  64159. +#endif
  64160. -.LJspec:
  64161. - move O1L, #0
  64162. - add $r0, $r0, $r0
  64163. - beqz $r0, .LJret
  64164. - bnez $r3, .Li42
  64165. -
  64166. -.Lb43:
  64167. - addi $r3, $r3, #-1
  64168. - add $r0, $r0, $r0
  64169. - move $r5, #0x800000
  64170. - slt $r15, $r0, $r5
  64171. - bnezs8 .Lb43
  64172. - j .LJlab1
  64173. -.Li42:
  64174. - move $r3, #0x7ff
  64175. - move $r5, #0xff000000
  64176. - slt $r15, $r5, $r0
  64177. - beqzs8 .LJret
  64178. - move O1H, #0xfff80000
  64179. - j .LJret
  64180. +.LJcont:
  64181. + move P1L, 0
  64182. + ret5 $lp
  64183. .size __extendsfdf2, .-__extendsfdf2
  64184. #endif /* L_sf_to_df */
  64185. @@ -3675,7 +3570,6 @@
  64186. .global __truncdfsf2
  64187. .type __truncdfsf2, @function
  64188. __truncdfsf2:
  64189. - push $lp
  64190. pushm $r6, $r8
  64191. slli P2H, P1H, #11
  64192. @@ -3714,7 +3608,6 @@
  64193. .LK999:
  64194. popm $r6, $r8
  64195. - pop $lp
  64196. ret5 $lp
  64197. .LKspec:
  64198. @@ -3724,20 +3617,20 @@
  64199. or $r7, $r7, P2L
  64200. beqz $r7, .Li46
  64201. move $r0, #0xffc00000
  64202. - j .LK999
  64203. + b .LK999
  64204. .Li46:
  64205. sltsi $r15, $r4, #0xff
  64206. bnezs8 .Li48
  64207. move $r7, #0x7f800000
  64208. or $r0, $r5, $r7
  64209. - j .LK999
  64210. + b .LK999
  64211. .Li48:
  64212. subri $r6, $r4, #1
  64213. move $r7, #0x20
  64214. slt $r15, $r6, $r7
  64215. bnezs8 .Li49
  64216. move $r0, $r5
  64217. - j .LK999
  64218. + b .LK999
  64219. .Li49:
  64220. subri $r8, $r6, #0x20
  64221. sll $r7, P2H, $r8
  64222. @@ -3746,13 +3639,13 @@
  64223. move $r4, #0
  64224. move $r7, #0x80000000
  64225. or P2H, P2H, $r7
  64226. - j .LKlab1
  64227. + b .LKlab1
  64228. .size __truncdfsf2, .-__truncdfsf2
  64229. #endif /* L_df_to_sf */
  64230. -#ifdef L_df_to_si
  64231. +#ifdef L_fixdfsi
  64232. #ifndef __big_endian__
  64233. #define P1L $r0
  64234. @@ -3764,20 +3657,25 @@
  64235. .global __fixdfsi
  64236. .type __fixdfsi, @function
  64237. __fixdfsi:
  64238. - push $lp
  64239. - pushm $r6, $r6
  64240. -
  64241. +#if defined(__NDS32_EXT_FPU_DP)
  64242. + fd2si.z $fs0, $fd0
  64243. + fmfsr $r0, $fs0
  64244. + ret5 $lp
  64245. +#else
  64246. +#if defined(__NDS32_EXT_FPU_SP)
  64247. + fmfdr $r0, $fd0
  64248. +#endif
  64249. slli $r3, P1H, #11
  64250. - srli $r6, P1L, #21
  64251. - or $r3, $r3, $r6
  64252. - move $r6, #0x80000000
  64253. - or $r3, $r3, $r6
  64254. - slli $r6, P1H, #1
  64255. - srli $r6, $r6, #21
  64256. - subri $r2, $r6, #0x41e
  64257. + srli $r4, P1L, #21
  64258. + or $r3, $r3, $r4
  64259. + move $r4, #0x80000000
  64260. + or $r3, $r3, $r4
  64261. + slli $r4, P1H, #1
  64262. + srli $r4, $r4, #21
  64263. + subri $r2, $r4, #0x41e
  64264. blez $r2, .LLnaninf
  64265. - move $r6, #0x20
  64266. - slt $r15, $r2, $r6
  64267. + move $r4, #0x20
  64268. + slt $r15, $r2, $r4
  64269. bnezs8 .LL72
  64270. move $r3, #0
  64271. .LL72:
  64272. @@ -3787,26 +3685,23 @@
  64273. subri $r3, $r3, #0
  64274. .Li50:
  64275. move $r0, $r3
  64276. -
  64277. -.LL999:
  64278. - popm $r6, $r6
  64279. - pop $lp
  64280. ret5 $lp
  64281. .LLnaninf:
  64282. beqz P1L, .Li51
  64283. ori P1H, P1H, #1
  64284. .Li51:
  64285. - move $r6, #0x7ff00000
  64286. - slt $r15, $r6, P1H
  64287. + move $r4, #0x7ff00000
  64288. + slt $r15, $r4, P1H
  64289. beqzs8 .Li52
  64290. move $r0, #0x80000000
  64291. - j .LL999
  64292. + ret5 $lp
  64293. .Li52:
  64294. move $r0, #0x7fffffff
  64295. - j .LL999
  64296. + ret5 $lp
  64297. +#endif
  64298. .size __fixdfsi, .-__fixdfsi
  64299. -#endif /* L_df_to_si */
  64300. +#endif /* L_fixdfsi */
  64301. @@ -3824,8 +3719,9 @@
  64302. .global __fixsfdi
  64303. .type __fixsfdi, @function
  64304. __fixsfdi:
  64305. - push $lp
  64306. -
  64307. +#if defined(__NDS32_EXT_FPU_SP)
  64308. + fmfsr $r0, $fs0
  64309. +#endif
  64310. srli $r3, $r0, #23
  64311. andi $r3, $r3, #0xff
  64312. slli O1H, $r0, #8
  64313. @@ -3864,9 +3760,6 @@
  64314. .LCret:
  64315. move $r0, $r1
  64316. move $r1, $r2
  64317. -
  64318. -.LC999:
  64319. - pop $lp
  64320. ret5 $lp
  64321. .LCinfnan:
  64322. @@ -3879,11 +3772,11 @@
  64323. .LCret3:
  64324. move O1H, #0x80000000
  64325. - j .LCret
  64326. + b .LCret
  64327. .Li7:
  64328. move O1H, #0x7fffffff
  64329. move O1L, #-1
  64330. - j .LCret
  64331. + b .LCret
  64332. .size __fixsfdi, .-__fixsfdi
  64333. #endif /* L_fixsfdi */
  64334. @@ -3907,9 +3800,10 @@
  64335. .global __fixdfdi
  64336. .type __fixdfdi, @function
  64337. __fixdfdi:
  64338. - push $lp
  64339. pushm $r6, $r6
  64340. -
  64341. +#if defined(__NDS32_EXT_FPU_SP)
  64342. + fmfdr $r0, $fd0
  64343. +#endif
  64344. slli $r5, P1H, #1
  64345. srli $r5, $r5, #21
  64346. slli O1H, P1H, #11
  64347. @@ -3950,10 +3844,7 @@
  64348. .LCret:
  64349. move P1L, O1L
  64350. move P1H, O1H
  64351. -
  64352. -.LC999:
  64353. popm $r6, $r6
  64354. - pop $lp
  64355. ret5 $lp
  64356. .LCnaninf:
  64357. @@ -3968,56 +3859,48 @@
  64358. .LCret3:
  64359. move O1H, #0x80000000
  64360. move O1L, #0
  64361. - j .LCret
  64362. + b .LCret
  64363. .Li5:
  64364. move O1H, #0x7fffffff
  64365. move O1L, #-1
  64366. - j .LCret
  64367. + b .LCret
  64368. .size __fixdfdi, .-__fixdfdi
  64369. #endif /* L_fixdfdi */
  64370. #ifdef L_fixunssfsi
  64371. -
  64372. .global __fixunssfsi
  64373. .type __fixunssfsi, @function
  64374. __fixunssfsi:
  64375. - push $lp
  64376. -
  64377. - slli $r1, $r0, #8
  64378. - move $r3, #0x80000000
  64379. - or $r1, $r1, $r3
  64380. - srli $r3, $r0, #23
  64381. - andi $r3, $r3, #0xff
  64382. - subri $r2, $r3, #0x9e
  64383. - sltsi $r15, $r2, #0
  64384. - bnezs8 .LLspec
  64385. - sltsi $r15, $r2, #0x20
  64386. - bnezs8 .Li45
  64387. - move $r0, #0
  64388. - j .LL999
  64389. -.Li45:
  64390. - srl $r1, $r1, $r2
  64391. - sltsi $r15, $r0, #0
  64392. - beqzs8 .Li46
  64393. - subri $r1, $r1, #0
  64394. -.Li46:
  64395. - move $r0, $r1
  64396. -
  64397. -.LL999:
  64398. - pop $lp
  64399. - ret5 $lp
  64400. -
  64401. -.LLspec:
  64402. - move $r3, #0x7f800000
  64403. - slt $r15, $r3, $r0
  64404. - beqzs8 .Li47
  64405. - move $r0, #0x80000000
  64406. - j .LL999
  64407. -.Li47:
  64408. - move $r0, #-1
  64409. - j .LL999
  64410. +#if defined(__NDS32_EXT_FPU_SP)
  64411. + fs2ui.z $fs0, $fs0
  64412. + fmfsr $r0, $fs0
  64413. + ret5 $lp
  64414. +#else
  64415. + bltz $r0, .LZero /* negative, return 0 */
  64416. + srli $r3,$r0,#0x17
  64417. + addi $r3,$r3,#-127
  64418. + bltz $r3, .LZero /* too small, return 0 */
  64419. + sltsi $r15,$r3,#0x20
  64420. + beqzs8 .LMax /* too big, return MAX */
  64421. + slli $r0,$r0,#0x8
  64422. +#ifdef __NDS32_EXT_PERF__
  64423. + bset $r1,$r0,#0x1f
  64424. +#else
  64425. + sethi $r2,#0x80000
  64426. + or $r1,$r0,$r2
  64427. +#endif
  64428. + subri $r0,$r3,#0x1f
  64429. + srl $r0,$r1,$r0
  64430. + ret5 $lp
  64431. +.LZero:
  64432. + movi55 $r0,#0x0
  64433. + ret5 $lp
  64434. +.LMax:
  64435. + movi55 $r0,#-1
  64436. + ret5 $lp
  64437. +#endif
  64438. .size __fixunssfsi, .-__fixunssfsi
  64439. #endif /* L_fixunssfsi */
  64440. @@ -4037,21 +3920,26 @@
  64441. .global __fixunsdfsi
  64442. .type __fixunsdfsi, @function
  64443. __fixunsdfsi:
  64444. - push $lp
  64445. - pushm $r6, $r6
  64446. -
  64447. +#if defined(__NDS32_EXT_FPU_DP)
  64448. + fd2ui.z $fs0, $fd0
  64449. + fmfsr $r0, $fs0
  64450. + ret5 $lp
  64451. +#else
  64452. +#if defined(__NDS32_EXT_FPU_SP)
  64453. + fmfdr $r0, $fd0
  64454. +#endif
  64455. slli $r3, P1H, #11
  64456. - srli $r6, P1L, #21
  64457. - or $r3, $r3, $r6
  64458. - move $r6, #0x80000000
  64459. - or $r3, $r3, $r6
  64460. - slli $r6, P1H, #1
  64461. - srli $r6, $r6, #21
  64462. - subri $r2, $r6, #0x41e
  64463. + srli $r4, P1L, #21
  64464. + or $r3, $r3, $r4
  64465. + move $r4, #0x80000000
  64466. + or $r3, $r3, $r4
  64467. + slli $r4, P1H, #1
  64468. + srli $r4, $r4, #21
  64469. + subri $r2, $r4, #0x41e
  64470. sltsi $r15, $r2, #0
  64471. bnezs8 .LNnaninf
  64472. - move $r6, #0x20
  64473. - slt $r15, $r2, $r6
  64474. + move $r4, #0x20
  64475. + slt $r15, $r2, $r4
  64476. bnezs8 .LL73
  64477. move $r3, #0
  64478. .LL73:
  64479. @@ -4061,92 +3949,86 @@
  64480. subri $r3, $r3, #0
  64481. .Li53:
  64482. move $r0, $r3
  64483. -
  64484. -.LN999:
  64485. - popm $r6, $r6
  64486. - pop $lp
  64487. ret5 $lp
  64488. .LNnaninf:
  64489. beqz P1L, .Li54
  64490. ori P1H, P1H, #1
  64491. .Li54:
  64492. - move $r6, #0x7ff00000
  64493. - slt $r15, $r6, P1H
  64494. + move $r4, #0x7ff00000
  64495. + slt $r15, $r4, P1H
  64496. beqzs8 .Li55
  64497. move $r0, #0x80000000
  64498. - j .LN999
  64499. + ret5 $lp
  64500. .Li55:
  64501. move $r0, #-1
  64502. - j .LN999
  64503. + ret5 $lp
  64504. +#endif
  64505. .size __fixunsdfsi, .-__fixunsdfsi
  64506. #endif /* L_fixunsdfsi */
  64507. #ifdef L_fixunssfdi
  64508. -
  64509. -#ifndef __big_endian__
  64510. - #define O1L $r1
  64511. - #define O1H $r2
  64512. -#else
  64513. - #define O1H $r1
  64514. - #define O1L $r2
  64515. -#endif
  64516. .text
  64517. .align 2
  64518. .global __fixunssfdi
  64519. .type __fixunssfdi, @function
  64520. __fixunssfdi:
  64521. - push $lp
  64522. -
  64523. - srli $r3, $r0, #23
  64524. - andi $r3, $r3, #0xff
  64525. - slli O1H, $r0, #8
  64526. - move $r5, #0x80000000
  64527. - or O1H, O1H, $r5
  64528. - move O1L, #0
  64529. - sltsi $r15, $r3, #0xbe
  64530. - beqzs8 .LDinfnan
  64531. - subri $r3, $r3, #0xbe
  64532. -.LL12:
  64533. - move $r5, #0x20
  64534. - slt $r15, $r3, $r5
  64535. - bnezs8 .LL13
  64536. - move O1L, O1H
  64537. - move O1H, #0
  64538. - addi $r3, $r3, #0xffffffe0
  64539. - bnez O1L, .LL12
  64540. -.LL13:
  64541. - beqz $r3, .LL14
  64542. - move $r4, O1H
  64543. - srl O1L, O1L, $r3
  64544. - srl O1H, O1H, $r3
  64545. - subri $r3, $r3, #0x20
  64546. - sll $r4, $r4, $r3
  64547. - or O1L, O1L, $r4
  64548. -.LL14:
  64549. - sltsi $r15, $r0, #0
  64550. - beqzs8 .LDret
  64551. -
  64552. - subri O1H, O1H, #0
  64553. - beqz O1L, .LL15
  64554. - subri O1L, O1L, #0
  64555. - subi45 O1H, #1
  64556. -.LL15:
  64557. -
  64558. -.LDret:
  64559. - move $r0, $r1
  64560. - move $r1, $r2
  64561. -
  64562. -.LD999:
  64563. - pop $lp
  64564. - ret5 $lp
  64565. -
  64566. -.LDinfnan:
  64567. - move O1H, #0x80000000
  64568. - move O1L, #0
  64569. - j .LDret
  64570. +#define INPUT $r0
  64571. +#define EXP $r2
  64572. +#define TMP $r3
  64573. +#define REAL_EXP $r2
  64574. +#ifndef __big_endian__
  64575. +#define MANL $r0
  64576. +#define MANH $r1
  64577. +#else
  64578. +#define MANL $r1
  64579. +#define MANH $r0
  64580. +#endif
  64581. +#if defined(__NDS32_EXT_FPU_SP)
  64582. + fmfsr $r0, $fs0
  64583. +#endif
  64584. + bltz INPUT, .LZero !negative, return 0
  64585. +
  64586. + srli EXP,INPUT,#0x17
  64587. + addi REAL_EXP, EXP,#-127
  64588. + bltz REAL_EXP, .LZero ! too small, return 0
  64589. +
  64590. + sltsi $r15,REAL_EXP,#0x40 ! too large, return Max
  64591. + beqzs8 .LMax
  64592. +
  64593. + slli MANL,INPUT,#0x8
  64594. +#ifdef __NDS32_EXT_PERF__
  64595. + bset MANL,MANL,#0x1f
  64596. +#else
  64597. + sethi TMP,#0x80000
  64598. + or33 MANL,TMP
  64599. +#endif
  64600. + subri TMP,REAL_EXP,#0x1f
  64601. + bltz TMP,.Lgt31 ! real_exp > 32
  64602. +
  64603. + ! real_exp <= 31
  64604. + srl MANL,MANL,TMP
  64605. + movi55 MANH,#0x0
  64606. + ret5 $lp
  64607. +
  64608. +.Lgt31:
  64609. + subri REAL_EXP,REAL_EXP,#0x3f
  64610. + neg33 TMP,TMP
  64611. + srl MANH,MANL,REAL_EXP
  64612. + sll MANL,MANL,TMP
  64613. + beqc TMP, #0x20, .LClrL
  64614. + ret5 $lp
  64615. +.LZero:
  64616. + movi55 MANH,#0x0
  64617. +.LClrL:
  64618. + movi55 MANL,#0x0
  64619. + ret5 $lp
  64620. +.LMax:
  64621. + movi55 MANL,#-1
  64622. + movi55 MANH,#-1
  64623. + ret5 $lp
  64624. .size __fixunssfdi, .-__fixunssfdi
  64625. #endif /* L_fixunssfdi */
  64626. @@ -4170,9 +4052,10 @@
  64627. .global __fixunsdfdi
  64628. .type __fixunsdfdi, @function
  64629. __fixunsdfdi:
  64630. - push $lp
  64631. pushm $r6, $r6
  64632. -
  64633. +#if defined(__NDS32_EXT_FPU_SP)
  64634. + fmfdr $r0, $fd0
  64635. +#endif
  64636. slli $r5, P1H, #1
  64637. srli $r5, $r5, #21
  64638. slli O1H, P1H, #11
  64639. @@ -4213,16 +4096,13 @@
  64640. .LDret:
  64641. move P1L, O1L
  64642. move P1H, O1H
  64643. -
  64644. -.LD999:
  64645. popm $r6, $r6
  64646. - pop $lp
  64647. ret5 $lp
  64648. .LDnaninf:
  64649. move O1H, #0x80000000
  64650. move O1L, #0
  64651. - j .LDret
  64652. + b .LDret
  64653. .size __fixunsdfdi, .-__fixunsdfdi
  64654. #endif /* L_fixunsdfdi */
  64655. @@ -4230,54 +4110,59 @@
  64656. #ifdef L_si_to_sf
  64657. +#define MANTA $r0
  64658. +#define EXPOA $r1
  64659. +
  64660. .text
  64661. .align 2
  64662. .global __floatsisf
  64663. .type __floatsisf, @function
  64664. __floatsisf:
  64665. - push $lp
  64666. -
  64667. - move $r4, #0x80000000
  64668. - and $r2, $r0, $r4
  64669. - beqz $r0, .Li39
  64670. - sltsi $r15, $r0, #0
  64671. - beqzs8 .Li40
  64672. - subri $r0, $r0, #0
  64673. -.Li40:
  64674. - move $r1, #0x9e
  64675. -#ifdef __NDS32_PERF_EXT__
  64676. + beqz $r0, .LKzero ! A is zero
  64677. + move $r4, #0x80000000
  64678. + and $r2, $r0, $r4 ! sign(A)
  64679. + beqz $r2, .LKcont
  64680. + subri $r0, $r0, #0
  64681. +
  64682. + ! abs(A)
  64683. +.LKcont:
  64684. + move EXPOA, #0x9e
  64685. +#ifdef __NDS32_EXT_PERF__
  64686. clz $r3, $r0
  64687. + sll MANTA, MANTA, $r3
  64688. + sub EXPOA, EXPOA, $r3
  64689. #else
  64690. - pushm $r0, $r2
  64691. - pushm $r4, $r5
  64692. - bal __clzsi2
  64693. - move $r3, $r0
  64694. - popm $r4, $r5
  64695. - popm $r0, $r2
  64696. -#endif
  64697. - sub $r1, $r1, $r3
  64698. - sll $r0, $r0, $r3
  64699. -
  64700. - #ADD($r0, $0x80)
  64701. - move $r15, #0x80
  64702. - add $r0, $r0, $r15
  64703. - slt $r15, $r0, $r15
  64704. -
  64705. - #ADDC($r1, $0x0)
  64706. - add $r1, $r1, $r15
  64707. - srai $r4, $r0, #8
  64708. - andi $r4, $r4, #1
  64709. - sub $r0, $r0, $r4
  64710. - slli $r0, $r0, #1
  64711. - srli $r0, $r0, #9
  64712. - slli $r4, $r1, #23
  64713. - or $r0, $r0, $r4
  64714. -.Li39:
  64715. - or $r0, $r0, $r2
  64716. + move $r5, 16
  64717. + move $r3, 0
  64718. +.LKloop:
  64719. + add $r3, $r3, $r5
  64720. + srl $r15, MANTA, $r3
  64721. + bnez $r15, .LKloop2
  64722. + sll MANTA, MANTA, $r5
  64723. + sub EXPOA, EXPOA, $r5
  64724. +.LKloop2:
  64725. + srli $r5, $r5, #1
  64726. + bnez $r5, .LKloop
  64727. +#endif
  64728. +
  64729. + ! do rounding
  64730. + srli $r4, $r4, #24 ! 0x80
  64731. + add MANTA, MANTA, $r4
  64732. + slt $r15, MANTA, $r4
  64733. + add EXPOA, EXPOA, $r15
  64734. + srai $r4, MANTA, #8
  64735. + andi $r4, $r4, #1
  64736. + sub MANTA, MANTA, $r4
  64737. + slli MANTA, MANTA, #1 ! shift out implied 1
  64738. +
  64739. + ! pack
  64740. + srli MANTA, MANTA, #9
  64741. + slli $r4, EXPOA, #23
  64742. + or $r0, MANTA, $r4
  64743. + or $r0, $r0, $r2
  64744. -.LH999:
  64745. - pop $lp
  64746. - ret5 $lp
  64747. +.LKzero:
  64748. + ret5 $lp
  64749. .size __floatsisf, .-__floatsisf
  64750. #endif /* L_si_to_sf */
  64751. @@ -4301,8 +4186,11 @@
  64752. .global __floatsidf
  64753. .type __floatsidf, @function
  64754. __floatsidf:
  64755. - push $lp
  64756. - pushm $r6, $r6
  64757. +#ifdef __NDS32_EXT_PERF__
  64758. + smw.adm $r6, [$sp], $r6, 0
  64759. +#else
  64760. + smw.adm $r6, [$sp], $r6, 2
  64761. +#endif
  64762. move O1L, #0
  64763. move O2H, O1L
  64764. @@ -4321,7 +4209,7 @@
  64765. .Li40:
  64766. move $r3, #0x41e
  64767. #ifndef __big_endian__
  64768. -#ifdef __NDS32_PERF_EXT__
  64769. +#ifdef __NDS32_EXT_PERF__
  64770. clz $r4, $r2
  64771. #else
  64772. pushm $r0, $r3
  64773. @@ -4333,7 +4221,7 @@
  64774. popm $r0, $r3
  64775. #endif
  64776. #else /* __big_endian__ */
  64777. -#ifdef __NDS32_PERF_EXT__
  64778. +#ifdef __NDS32_EXT_PERF__
  64779. clz $r5, $r1
  64780. #else
  64781. pushm $r0, $r4
  64782. @@ -4357,9 +4245,11 @@
  64783. move $r0, $r4
  64784. move $r1, $r5
  64785. -.LH999:
  64786. - popm $r6, $r6
  64787. - pop $lp
  64788. +#ifdef __NDS32_EXT_PERF__
  64789. + lmw.bim $r6, [$sp], $r6, 0
  64790. +#else
  64791. + lmw.bim $r6, [$sp], $r6, 2
  64792. +#endif
  64793. ret5 $lp
  64794. .size __floatsidf, .-__floatsidf
  64795. #endif /* L_si_to_df */
  64796. @@ -4384,8 +4274,11 @@
  64797. .global __floatdisf
  64798. .type __floatdisf, @function
  64799. __floatdisf:
  64800. - push $lp
  64801. - pushm $r6, $r7
  64802. +#ifdef __NDS32_EXT_PERF__
  64803. + smw.adm $r6, [$sp], $r7, 0
  64804. +#else
  64805. + smw.adm $r6, [$sp], $r7, 2
  64806. +#endif
  64807. move $r7, #0x80000000
  64808. and $r5, P1H, $r7
  64809. @@ -4409,14 +4302,14 @@
  64810. bnez P2H, .LL2
  64811. bnez P2L, .LL3
  64812. move $r4, #0
  64813. - j .LL4
  64814. + b .LL4
  64815. .LL3:
  64816. move P2H, P2L
  64817. move P2L, #0
  64818. move $r6, #32
  64819. sub $r4, $r4, $r6
  64820. .LL2:
  64821. -#ifdef __NDS32_PERF_EXT__
  64822. +#ifdef __NDS32_EXT_PERF__
  64823. clz $r6, P2H
  64824. #else
  64825. pushm $r0, $r5
  64826. @@ -4456,8 +4349,11 @@
  64827. or $r0, P2H, $r5
  64828. .LA999:
  64829. - popm $r6, $r7
  64830. - pop $lp
  64831. +#ifdef __NDS32_EXT_PERF__
  64832. + lmw.bim $r6, [$sp], $r7, 0
  64833. +#else
  64834. + lmw.bim $r6, [$sp], $r7, 2
  64835. +#endif
  64836. ret5 $lp
  64837. .size __floatdisf, .-__floatdisf
  64838. #endif /* L_floatdisf */
  64839. @@ -4486,8 +4382,11 @@
  64840. .global __floatdidf
  64841. .type __floatdidf, @function
  64842. __floatdidf:
  64843. - push $lp
  64844. - pushm $r6, $r8
  64845. +#ifdef __NDS32_EXT_PERF__
  64846. + smw.adm $r6, [$sp], $r8, 0
  64847. +#else
  64848. + smw.adm $r6, [$sp], $r8, 2
  64849. +#endif
  64850. move $r4, #0
  64851. move $r7, $r4
  64852. @@ -4511,16 +4410,16 @@
  64853. bnez P2H, .LL2
  64854. bnez P2L, .LL3
  64855. move $r4, #0
  64856. - j .LL4
  64857. + b .LL4
  64858. .LL3:
  64859. move P2H, P2L
  64860. move P2L, #0
  64861. move O1H, #32
  64862. sub $r4, $r4, O1H
  64863. .LL2:
  64864. -#ifdef __NDS32_PERF_EXT__
  64865. +#ifdef __NDS32_EXT_PERF__
  64866. clz O1H, P2H
  64867. -#else /* not __NDS32_PERF_EXT__ */
  64868. +#else /* not __NDS32_EXT_PERF__ */
  64869. /*
  64870. Replace clz with function call.
  64871. clz O1H, P2H
  64872. @@ -4540,7 +4439,7 @@
  64873. move $r5, $r0
  64874. popm $r0, $r4
  64875. #endif
  64876. -#endif /* not __NDS32_PERF_EXT__ */
  64877. +#endif /* not __NDS32_EXT_PERF__ */
  64878. beqz O1H, .LL4
  64879. sub $r4, $r4, O1H
  64880. subri O1L, O1H, #32
  64881. @@ -4581,8 +4480,11 @@
  64882. move P1H, O1H
  64883. .LA999:
  64884. - popm $r6, $r8
  64885. - pop $lp
  64886. +#ifdef __NDS32_EXT_PERF__
  64887. + lmw.bim $r6, [$sp], $r8, 0
  64888. +#else
  64889. + lmw.bim $r6, [$sp], $r8, 2
  64890. +#endif
  64891. ret5 $lp
  64892. .size __floatdidf, .-__floatdidf
  64893. #endif /* L_floatdidf */
  64894. @@ -4591,48 +4493,51 @@
  64895. #ifdef L_floatunsisf
  64896. +#define MANTA $r0
  64897. +#define EXPOA $r1
  64898. +
  64899. .text
  64900. .align 2
  64901. .global __floatunsisf
  64902. .type __floatunsisf, @function
  64903. __floatunsisf:
  64904. - push $lp
  64905. -
  64906. - beqz $r0, .Li41
  64907. - move $r2, #0x9e
  64908. -#ifdef __NDS32_PERF_EXT__
  64909. - clz $r1, $r0
  64910. -#else
  64911. - push $r0
  64912. - pushm $r2, $r5
  64913. - bal __clzsi2
  64914. - move $r1, $r0
  64915. - popm $r2, $r5
  64916. - pop $r0
  64917. -#endif
  64918. -
  64919. - sub $r2, $r2, $r1
  64920. - sll $r0, $r0, $r1
  64921. + beqz $r0, .LKzero ! A is zero
  64922. - #ADD($r0, $0x80)
  64923. - move $r15, #0x80
  64924. - add $r0, $r0, $r15
  64925. - slt $r15, $r0, $r15
  64926. -
  64927. - #ADDC($r2, $0x0)
  64928. - add $r2, $r2, $r15
  64929. - srli $r3, $r0, #8
  64930. - andi $r3, $r3, #1
  64931. - sub $r0, $r0, $r3
  64932. - slli $r0, $r0, #1
  64933. - srli $r0, $r0, #9
  64934. - slli $r3, $r2, #23
  64935. - or $r0, $r0, $r3
  64936. + move EXPOA, #0x9e
  64937. +#ifdef __NDS32_EXT_PERF__
  64938. + clz $r5, $r0
  64939. + sll MANTA, MANTA, $r5
  64940. + sub EXPOA, EXPOA, $r5
  64941. +#else
  64942. + move $r5, 16
  64943. + move $r3, 0
  64944. +.LKloop:
  64945. + add $r3, $r3, $r5
  64946. + srl $r15, MANTA, $r3
  64947. + bnez $r15, .LKloop2
  64948. + sll MANTA, MANTA, $r5
  64949. + sub EXPOA, EXPOA, $r5
  64950. +.LKloop2:
  64951. + srli $r5, $r5, #1
  64952. + bnez $r5, .LKloop
  64953. +#endif
  64954. +
  64955. + ! do rounding
  64956. + addi MANTA, MANTA, #128
  64957. + slti $r15, MANTA, #128
  64958. + add EXPOA, EXPOA, $r15
  64959. + srli $r4, MANTA, #8
  64960. + andi $r4, $r4, #1
  64961. + sub MANTA, MANTA, $r4
  64962. + slli MANTA, MANTA, #1 ! shift out implied 1
  64963. +
  64964. + ! pack
  64965. + srli MANTA, MANTA, #9
  64966. + slli $r4, EXPOA, #23
  64967. + or $r0, MANTA, $r4
  64968. -.Li41:
  64969. -.LI999:
  64970. - pop $lp
  64971. - ret5 $lp
  64972. +.LKzero:
  64973. + ret5 $lp
  64974. .size __floatunsisf, .-__floatunsisf
  64975. #endif /* L_floatunsisf */
  64976. @@ -4656,8 +4561,11 @@
  64977. .global __floatunsidf
  64978. .type __floatunsidf, @function
  64979. __floatunsidf:
  64980. - push $lp
  64981. - pushm $r6, $r6
  64982. +#ifdef __NDS32_EXT_PERF__
  64983. + smw.adm $r6, [$sp], $r6, 0
  64984. +#else
  64985. + smw.adm $r6, [$sp], $r6, 2
  64986. +#endif
  64987. move O1L, #0
  64988. move $r3, O1L
  64989. @@ -4665,7 +4573,7 @@
  64990. beqz O1H, .Li41
  64991. move $r3, #0x41e
  64992. #ifndef __big_endian__
  64993. -#ifdef __NDS32_PERF_EXT__
  64994. +#ifdef __NDS32_EXT_PERF__
  64995. clz $r5, $r2
  64996. #else
  64997. pushm $r0, $r4
  64998. @@ -4675,7 +4583,7 @@
  64999. popm $r0, $r4
  65000. #endif
  65001. #else /* __big_endian__ */
  65002. -#ifdef __NDS32_PERF_EXT__
  65003. +#ifdef __NDS32_EXT_PERF__
  65004. clz $r4, $r1
  65005. #else
  65006. pushm $r0, $r3
  65007. @@ -4700,9 +4608,11 @@
  65008. move $r0, $r4
  65009. move $r1, $r5
  65010. -.LI999:
  65011. - popm $r6, $r6
  65012. - pop $lp
  65013. +#ifdef __NDS32_EXT_PERF__
  65014. + lmw.bim $r6, [$sp], $r6, 0
  65015. +#else
  65016. + lmw.bim $r6, [$sp], $r6, 2
  65017. +#endif
  65018. ret5 $lp
  65019. .size __floatunsidf, .-__floatunsidf
  65020. #endif /* L_floatunsidf */
  65021. @@ -4727,8 +4637,11 @@
  65022. .global __floatundisf
  65023. .type __floatundisf, @function
  65024. __floatundisf:
  65025. - push $lp
  65026. - pushm $r6, $r6
  65027. +#ifdef __NDS32_EXT_PERF__
  65028. + smw.adm $r6, [$sp], $r6, 0
  65029. +#else
  65030. + smw.adm $r6, [$sp], $r6, 2
  65031. +#endif
  65032. move P2H, P1H
  65033. move P2L, P1L
  65034. @@ -4741,14 +4654,14 @@
  65035. bnez P2H, .LL5
  65036. bnez P2L, .LL6
  65037. move $r4, #0
  65038. - j .LL7
  65039. + b .LL7
  65040. .LL6:
  65041. move P2H, P2L
  65042. move P2L, #0
  65043. move $r5, #32
  65044. sub $r4, $r4, $r5
  65045. .LL5:
  65046. -#ifdef __NDS32_PERF_EXT__
  65047. +#ifdef __NDS32_EXT_PERF__
  65048. clz $r5, P2H
  65049. #else
  65050. pushm $r0, $r4
  65051. @@ -4788,8 +4701,11 @@
  65052. move $r0, P2H
  65053. .LB999:
  65054. - popm $r6, $r6
  65055. - pop $lp
  65056. +#ifdef __NDS32_EXT_PERF__
  65057. + lmw.bim $r6, [$sp], $r6, 0
  65058. +#else
  65059. + lmw.bim $r6, [$sp], $r6, 2
  65060. +#endif
  65061. ret5 $lp
  65062. .size __floatundisf, .-__floatundisf
  65063. #endif /* L_floatundisf */
  65064. @@ -4818,8 +4734,11 @@
  65065. .global __floatundidf
  65066. .type __floatundidf, @function
  65067. __floatundidf:
  65068. - push $lp
  65069. - pushm $r6, $r7
  65070. +#ifdef __NDS32_EXT_PERF__
  65071. + smw.adm $r6, [$sp], $r7, 0
  65072. +#else
  65073. + smw.adm $r6, [$sp], $r7, 2
  65074. +#endif
  65075. move $r4, #0
  65076. move P2H, P1H
  65077. @@ -4833,16 +4752,16 @@
  65078. bnez P2H, .LL8
  65079. bnez P2L, .LL9
  65080. move $r4, #0
  65081. - j .LL10
  65082. + b .LL10
  65083. .LL9:
  65084. move P2H, P2L
  65085. move P2L, #0
  65086. move O1H, #32
  65087. sub $r4, $r4, O1H
  65088. .LL8:
  65089. -#ifdef __NDS32_PERF_EXT__
  65090. +#ifdef __NDS32_EXT_PERF__
  65091. clz O1H, P2H
  65092. -#else /* not __NDS32_PERF_EXT__ */
  65093. +#else /* not __NDS32_EXT_PERF__ */
  65094. /*
  65095. Replace clz with function call.
  65096. clz O1H, P2H
  65097. @@ -4862,7 +4781,7 @@
  65098. move $r5, $r0
  65099. popm $r0, $r4
  65100. #endif
  65101. -#endif /* not __NDS32_PERF_EXT__ */
  65102. +#endif /* not __NDS32_EXT_PERF__ */
  65103. beqz O1H, .LL10
  65104. sub $r4, $r4, O1H
  65105. subri O1L, O1H, #32
  65106. @@ -4902,8 +4821,11 @@
  65107. move P1H, O1H
  65108. .LB999:
  65109. - popm $r6, $r7
  65110. - pop $lp
  65111. +#ifdef __NDS32_EXT_PERF__
  65112. + lmw.bim $r6, [$sp], $r7, 0
  65113. +#else
  65114. + lmw.bim $r6, [$sp], $r7, 2
  65115. +#endif
  65116. ret5 $lp
  65117. .size __floatundidf, .-__floatundidf
  65118. #endif /* L_floatundidf */
  65119. @@ -4914,78 +4836,121 @@
  65120. .text
  65121. .align 2
  65122. - .global __cmpsf2
  65123. - .type __cmpsf2, @function
  65124. -__cmpsf2:
  65125. + .global __gtsf2
  65126. + .type __gtsf2, @function
  65127. +__gtsf2:
  65128. + ! ---------------------------------------------------------------------
  65129. + ! int __gtsf2(float a, float b):
  65130. + ! This function returns a value greater than zero if neither argument
  65131. + ! is NaN and a is strictly greater than b.
  65132. + ! ---------------------------------------------------------------------
  65133. + .global __gesf2
  65134. + .type __gesf2, @function
  65135. +__gesf2:
  65136. + ! ---------------------------------------------------------------------
  65137. + ! int __gesf2(float a, float b):
  65138. + ! This function returns a value greater than or equal to zero if
  65139. + ! neither argument is NaN and a is greater than or equal to b.
  65140. + ! ---------------------------------------------------------------------
  65141. + move $r4, #-1
  65142. + b .LA
  65143. +
  65144. .global __eqsf2
  65145. .type __eqsf2, @function
  65146. __eqsf2:
  65147. - .global __ltsf2
  65148. - .type __ltsf2, @function
  65149. -__ltsf2:
  65150. - .global __lesf2
  65151. - .type __lesf2, @function
  65152. -__lesf2:
  65153. + ! ---------------------------------------------------------------------
  65154. + ! int __eqsf2(float a, float b):
  65155. + ! This function returns zero value if neither argument is NaN,
  65156. + ! and a and b are equal.
  65157. + ! ---------------------------------------------------------------------
  65158. .global __nesf2
  65159. .type __nesf2, @function
  65160. __nesf2:
  65161. + ! ---------------------------------------------------------------------
  65162. + ! int __nesf2(float a, float b):
  65163. + ! This function returns a nonzero value if either argument is NaN or if
  65164. + ! a and b are unequal.
  65165. + ! ---------------------------------------------------------------------
  65166. + .global __lesf2
  65167. + .type __lesf2, @function
  65168. +__lesf2:
  65169. + ! ---------------------------------------------------------------------
  65170. + ! int __lesf2(float a, float b):
  65171. + ! This function returns a value less than or equal to zero if neither
  65172. + ! argument is NaN and a is less than b.
  65173. + ! ---------------------------------------------------------------------
  65174. + .global __ltsf2
  65175. + .type __ltsf2, @function
  65176. +__ltsf2:
  65177. + ! ---------------------------------------------------------------------
  65178. + ! int __ltsf2(float a, float b):
  65179. + ! This function returns a value less than zero if neither argument is
  65180. + ! NaN and a is strictly less than b.
  65181. + ! ---------------------------------------------------------------------
  65182. + .global __cmpsf2
  65183. + .type __cmpsf2, @function
  65184. +__cmpsf2:
  65185. + ! ---------------------------------------------------------------------
  65186. + ! int __cmpsf2(float a, float b);
  65187. + ! This function calculates a <=> b. That is, if a is less than b, it
  65188. + ! returns -1; if a if greater than b, it returns 1; and if a and b are
  65189. + ! equal, it returns 0. If either argument is NaN, it returns 1, But you
  65190. + ! should not rely on this; If NaN is a possibility, use higher-level
  65191. + ! comparison function __unordsf2().
  65192. + ! ---------------------------------------------------------------------
  65193. move $r4, #1
  65194. - j .LA
  65195. - .global __gesf2
  65196. - .type __gesf2, @function
  65197. -__gesf2:
  65198. - .global __gtsf2
  65199. - .type __gtsf2, @function
  65200. -__gtsf2:
  65201. - move $r4, #-1
  65202. + .align 2
  65203. .LA:
  65204. - push $lp
  65205. +#ifndef __FAST_MATH__
  65206. + move $r5, #0xff000000
  65207. + slli $r2, $r0, #1
  65208. + slt $r15, $r5, $r2
  65209. + bnez $r15, .LMnan ! a is NaN
  65210. + slli $r3, $r1, #1
  65211. + slt $r15, $r5, $r3
  65212. + bnez $r15, .LMnan ! b is NaN
  65213. +#endif
  65214. + xor $r5, $r0, $r1 ! a and b have same sign?
  65215. + bgez $r5, .LSameSign
  65216. +.LDiffSign:
  65217. +#ifdef __FAST_MATH__
  65218. slli $r2, $r0, #1
  65219. slli $r3, $r1, #1
  65220. - or $r5, $r2, $r3
  65221. - beqz $r5, .LMequ
  65222. - move $r5, #0xff000000
  65223. - slt $r15, $r5, $r2
  65224. - bnezs8 .LMnan
  65225. - slt $r15, $r5, $r3
  65226. - bnezs8 .LMnan
  65227. - srli $r2, $r2, #1
  65228. - sltsi $r15, $r0, #0
  65229. - beqzs8 .Li48
  65230. - subri $r2, $r2, #0
  65231. -.Li48:
  65232. - srli $r3, $r3, #1
  65233. - sltsi $r15, $r1, #0
  65234. - beqzs8 .Li49
  65235. - subri $r3, $r3, #0
  65236. -.Li49:
  65237. - slts $r15, $r2, $r3
  65238. - beqzs8 .Li50
  65239. - move $r0, #-1
  65240. - j .LM999
  65241. -.Li50:
  65242. - slts $r15, $r3, $r2
  65243. - beqzs8 .LMequ
  65244. - move $r0, #1
  65245. - j .LM999
  65246. +#endif
  65247. + or $r2, $r2, $r3
  65248. + beqz $r2, .LMequ ! 0.0f and -0.0f are equal
  65249. + move $r2, #1 ! when a==0.0f, return 1
  65250. + cmovz $r0, $r2, $r0 ! otherwise, simply return a
  65251. + ret5 $lp
  65252. +
  65253. +.LSameSign:
  65254. + sltsi $r15, $r0, 0 ! a < 0 ?
  65255. + bnez $r15, .LSameSignNeg
  65256. +.LSameSignPos:
  65257. + ! a >= 0 && b >= 0, return a - b
  65258. + sub $r0, $r0, $r1
  65259. + ret5 $lp
  65260. +.LSameSignNeg:
  65261. + ! a < 0 && b < 0, return b - a
  65262. + sub $r0, $r1, $r0
  65263. + ret5 $lp
  65264. .LMequ:
  65265. move $r0, #0
  65266. -
  65267. -.LM999:
  65268. - pop $lp
  65269. ret5 $lp
  65270. +#ifndef __FAST_MATH__
  65271. .LMnan:
  65272. move $r0, $r4
  65273. - j .LM999
  65274. + ret5 $lp
  65275. +#endif
  65276. .size __cmpsf2, .-__cmpsf2
  65277. - .size __eqsf2, .-__eqsf2
  65278. .size __ltsf2, .-__ltsf2
  65279. .size __lesf2, .-__lesf2
  65280. .size __nesf2, .-__nesf2
  65281. + .size __eqsf2, .-__eqsf2
  65282. .size __gesf2, .-__gesf2
  65283. .size __gtsf2, .-__gtsf2
  65284. #endif /* L_compare_sf */
  65285. @@ -5005,125 +4970,199 @@
  65286. #define P2H $r3
  65287. #define P2L $r2
  65288. #endif
  65289. +#define W1 $r5
  65290. +#define W0 $r4
  65291. +#ifdef __NDS32_REDUCE_REGS__
  65292. + #define W2 $r6
  65293. + #define W3 $r7
  65294. + #define W4 $r8
  65295. + #define W5 $r9
  65296. +#else
  65297. + #define W2 $r16
  65298. + #define W3 $r17
  65299. + #define W4 $r18
  65300. + #define W5 $r19
  65301. +#endif
  65302. +
  65303. + .text
  65304. .align 2
  65305. .globl __gtdf2
  65306. - .globl __gedf2
  65307. - .globl __ltdf2
  65308. - .globl __ledf2
  65309. - .globl __eqdf2
  65310. - .globl __nedf2
  65311. - .globl __cmpdf2
  65312. .type __gtdf2, @function
  65313. - .type __gedf2, @function
  65314. - .type __ltdf2, @function
  65315. - .type __ledf2, @function
  65316. - .type __eqdf2, @function
  65317. - .type __nedf2, @function
  65318. - .type __cmpdf2, @function
  65319. __gtdf2:
  65320. + ! ---------------------------------------------------------------------
  65321. + ! int __gtdf2(double a, double b):
  65322. + ! This function returns a value greater than zero if neither argument
  65323. + ! is NaN and a is strictly greater than b.
  65324. + ! ---------------------------------------------------------------------
  65325. + .globl __gedf2
  65326. + .type __gedf2, @function
  65327. __gedf2:
  65328. - movi $r4, -1
  65329. - b .L1
  65330. + ! ---------------------------------------------------------------------
  65331. + ! int __gedf2(double a, double b):
  65332. + ! This function returns a value greater than or equal to zero if
  65333. + ! neither argument is NaN and a is greater than or equal to b.
  65334. + ! ---------------------------------------------------------------------
  65335. + move $r4, #-1
  65336. + b .LA
  65337. -__ltdf2:
  65338. + .globl __eqdf2
  65339. + .type __eqdf2, @function
  65340. +__eqdf2:
  65341. + ! ---------------------------------------------------------------------
  65342. + ! int __eqdf2(double a, double b):
  65343. + ! This function returns zero value if neither argument is NaN and and b
  65344. + ! are equal.
  65345. + ! ---------------------------------------------------------------------
  65346. + .globl __nedf2
  65347. + .type __nedf2, @function
  65348. +__nedf2:
  65349. + ! ---------------------------------------------------------------------
  65350. + ! int __nedf2(double a, double b):
  65351. + ! This function returns a nonzero value if either argument is NaN or if
  65352. + ! a and b are unequal.
  65353. + ! ---------------------------------------------------------------------
  65354. + .globl __ledf2
  65355. + .type __ledf2, @function
  65356. __ledf2:
  65357. + ! ---------------------------------------------------------------------
  65358. + ! int __ledf2(double a, double b):
  65359. + ! This function returns a value less than or equal to zero if neither
  65360. + ! argument is NaN and a is less than b.
  65361. + ! ---------------------------------------------------------------------
  65362. + .globl __ltdf2
  65363. + .type __ltdf2, @function
  65364. +__ltdf2:
  65365. + ! ---------------------------------------------------------------------
  65366. + ! int __ltdf2(double a, double b):
  65367. + ! This function returns a value less than zero if neither argument is
  65368. + ! NaN and a is strictly less than b.
  65369. + ! ---------------------------------------------------------------------
  65370. + .globl __cmpdf2
  65371. + .type __cmpdf2, @function
  65372. __cmpdf2:
  65373. -__nedf2:
  65374. -__eqdf2:
  65375. - movi $r4, 1
  65376. -.L1:
  65377. -#if defined (__NDS32_ISA_V3M__)
  65378. - push25 $r10, 0
  65379. -#else
  65380. + ! ---------------------------------------------------------------------
  65381. + ! int __cmpdf2(double a, double b);
  65382. + ! This function calculates a <=> b. That is, if a is less than b, it
  65383. + ! returns -1; if a if greater than b, it returns 1; and if a and b are
  65384. + ! equal, it returns 0. If either argument is NaN, it returns 1, But you
  65385. + ! should not rely on this; If NaN is a possibility, use higher-level
  65386. + ! comparison function __unordsf2().
  65387. + ! ---------------------------------------------------------------------
  65388. + move $r4, #1
  65389. +
  65390. +.LA:
  65391. + move W1, #0
  65392. +#ifdef __NDS32_REDUCE_REGS__
  65393. smw.adm $r6, [$sp], $r9, 0
  65394. #endif
  65395. - sethi $r5, 0x7ff00
  65396. - and $r6, P1H, $r5 ! r6=aExp
  65397. - and $r7, P2H, $r5 ! r7=bExp
  65398. - slli $r8, P1H, 12 ! r8=aSig0
  65399. - slli $r9, P2H, 12 ! r9=bSig0
  65400. - beq $r6, $r5, .L11 ! aExp==0x7ff
  65401. - beq $r7, $r5, .L12 ! bExp==0x7ff
  65402. -.L2:
  65403. - slli $ta, P1H, 1 ! ta=ahigh<<1
  65404. - or $ta, P1L, $ta !
  65405. - xor $r5, P1H, P2H ! r5=ahigh^bhigh
  65406. - beqz $ta, .L3 ! if(ahigh<<1)==0,go .L3
  65407. - !-------------------------------
  65408. - ! (ahigh<<1)!=0 || (bhigh<<1)!=0
  65409. - !-------------------------------
  65410. -.L4:
  65411. - beqz $r5, .L5 ! ahigh==bhigh, go .L5
  65412. - !--------------------
  65413. - ! a != b
  65414. - !--------------------
  65415. -.L6:
  65416. - bltz $r5, .L7 ! if(aSign!=bSign), go .L7
  65417. - !--------------------
  65418. - ! aSign==bSign
  65419. - !--------------------
  65420. - slt $ta, $r6, $r7 ! ta=(aExp<bExp)
  65421. - bne $r6, $r7, .L8 ! if(aExp!=bExp),go .L8
  65422. - slt $ta, $r8, $r9 ! ta=(aSig0<bSig0)
  65423. - bne $r8, $r9, .L8 ! if(aSig0!=bSig0),go .L8
  65424. - slt $ta, P1L, P2L ! ta=(aSig1<bSig1)
  65425. -.L8:
  65426. - beqz $ta, .L10 ! if(|a|>|b|), go .L10
  65427. - nor $r0, P2H, P2H ! if(|a|<|b|),return (~yh)
  65428. -.L14:
  65429. -#if defined (__NDS32_ISA_V3M__)
  65430. - pop25 $r10, 0
  65431. + move W4, #0xffe00000
  65432. + slli W2, P1H, #1
  65433. + slt $r15, W1, P1L
  65434. + add W5, W2, $r15
  65435. + slt $r15, W4, W5
  65436. + bnez $r15, .LMnan ! a is NaN
  65437. + slli W3, P2H, #1
  65438. + slt $r15, W1, P2L
  65439. + add W5, W3, $r15
  65440. + slt $r15, W4, W5
  65441. + bnez $r15, .LMnan ! b is NaN
  65442. + xor W0, P1H, P2H
  65443. + bltz W0, .LMdiff ! a and b same sign?
  65444. +
  65445. + ! same sign
  65446. + sltsi $r15, P1H, 0 ! a<0?
  65447. + bnez $r15, .LMsame
  65448. +
  65449. + sub W0, P1L, P2L
  65450. + slt $r15, P1L, W0
  65451. + sub $r0, P1H, P2H
  65452. + sub $r0, $r0, $r15 ! return a-b
  65453. + slt $r15, W1, W0
  65454. + cmovz $r0, $r15, $r0
  65455. +#ifdef __NDS32_REDUCE_REGS__
  65456. + b .LMret
  65457. +#else
  65458. + ret5 $lp
  65459. +#endif
  65460. +
  65461. +.LMsame:
  65462. + sub W0, P2L, P1L
  65463. + slt $r15, P2L, W0
  65464. + sub $r0, P2H, P1H
  65465. + sub $r0, $r0, $r15 ! return b-a
  65466. + slt $r15, W1, W0
  65467. + cmovz $r0, $r15, $r0
  65468. +#ifdef __NDS32_REDUCE_REGS__
  65469. + b .LMret
  65470. +#else
  65471. + ret5 $lp
  65472. +
  65473. + .align 2
  65474. +#endif
  65475. + ! different sign
  65476. +.LMdiff:
  65477. +#ifdef __NDS32_REDUCE_REGS__
  65478. + or W2, W2, W3 ! 0.0f and -0.0f are equal
  65479. +#else
  65480. + or W1, W2, W3 ! 0.0f and -0.0f are equal
  65481. +#endif
  65482. + or W0, P1L, P2L
  65483. +#ifdef __NDS32_REDUCE_REGS__
  65484. + or W2, W2, W0
  65485. +#else
  65486. + or W1, W1, W0
  65487. +#endif
  65488. +#ifdef __big_endian__
  65489. +#ifdef __NDS32_REDUCE_REGS__
  65490. + beqz W2, .LMequ
  65491. +#else
  65492. + beqz W1, .LMequ
  65493. +#endif
  65494. +
  65495. + movi $r2, #1 ! when high-part(a) is 0, return 1
  65496. + cmovz $r0, $r2, P1H ! otherwise, simply return high-part(a)
  65497. +#else
  65498. +#ifdef __NDS32_REDUCE_REGS__
  65499. + beqz W2, .LMret
  65500. #else
  65501. + beqz W1, .LMret
  65502. +#endif
  65503. +
  65504. + movi $r0, #1 ! when high-part(a) is 0, return 1
  65505. + cmovn $r0, P1H, P1H ! otherwise, simply return high-part(a)
  65506. +#endif
  65507. +
  65508. +.LMret:
  65509. +#ifdef __NDS32_REDUCE_REGS__
  65510. lmw.bim $r6, [$sp], $r9, 0
  65511. - ret
  65512. #endif
  65513. -.L10:
  65514. - ori $r0, P2H, 1 ! return (yh|1)
  65515. - b .L14
  65516. - !--------------------
  65517. - ! (ahigh<<1)=0
  65518. - !--------------------
  65519. -.L3:
  65520. - slli $ta, P2H, 1 ! ta=bhigh<<1
  65521. - or $ta, P2L, $ta !
  65522. - bnez $ta, .L4 ! ta=(bhigh<<1)!=0,go .L4
  65523. -.L5:
  65524. - xor $ta, P1L, P2L ! ta=alow^blow
  65525. - bnez $ta, .L6 ! alow!=blow,go .L6
  65526. - movi $r0, 0 ! a==b, return 0
  65527. - b .L14
  65528. - !--------------------
  65529. - ! aExp=0x7ff;
  65530. - !--------------------
  65531. -.L11:
  65532. - or P1L, P1L, $r8 ! x1=(aSig0|aSig1)
  65533. - bnez P1L, .L13 ! if(a=nan), go.L13
  65534. - xor $ta, $r7, $r5 ! ta=(bExp^0x7ff)
  65535. - bnez $ta, .L2 ! if(bExp!=0x7ff), go .L2
  65536. - !--------------------
  65537. - ! bExp=0x7ff;
  65538. - !--------------------
  65539. -.L12:
  65540. - or $ta, P2L, $r9 ! ta=(bSig0|bSig1)
  65541. - beqz $ta, .L2 ! if(b!=nan), go .L2
  65542. -.L13:
  65543. - move $r0, $r4
  65544. - b .L14
  65545. - !--------------------
  65546. - ! aSign!=bSign
  65547. - !--------------------
  65548. -.L7:
  65549. - ori $r0, P1H, 1 ! if(aSign!=bSign), return (ahigh|1)
  65550. - b .L14
  65551. + ret5 $lp
  65552. - .size __gtdf2, .-__gtdf2
  65553. - .size __gedf2, .-__gedf2
  65554. +#ifdef __big_endian__
  65555. +.LMequ:
  65556. + movi $r0, #0
  65557. +#ifdef __NDS32_REDUCE_REGS__
  65558. + b .LMret
  65559. +#else
  65560. + ret5 $lp
  65561. +#endif
  65562. +#endif
  65563. +
  65564. +.LMnan:
  65565. + move $r0, $r4
  65566. +#ifdef __NDS32_REDUCE_REGS__
  65567. + b .LMret
  65568. +#else
  65569. + ret5 $lp
  65570. +#endif
  65571. + .size __cmpdf2, .-__cmpdf2
  65572. .size __ltdf2, .-__ltdf2
  65573. .size __ledf2, .-__ledf2
  65574. - .size __eqdf2, .-__eqdf2
  65575. .size __nedf2, .-__nedf2
  65576. - .size __cmpdf2, .-__cmpdf2
  65577. + .size __eqdf2, .-__eqdf2
  65578. + .size __gedf2, .-__gedf2
  65579. + .size __gtdf2, .-__gtdf2
  65580. #endif /* L_compare_df */
  65581. @@ -5135,27 +5174,21 @@
  65582. .global __unordsf2
  65583. .type __unordsf2, @function
  65584. __unordsf2:
  65585. - push $lp
  65586. -
  65587. - slli $r2, $r0, #1
  65588. - move $r3, #0xff000000
  65589. - slt $r15, $r3, $r2
  65590. - beqzs8 .Li52
  65591. - move $r0, #1
  65592. - j .LP999
  65593. -.Li52:
  65594. - slli $r2, $r1, #1
  65595. - move $r3, #0xff000000
  65596. - slt $r15, $r3, $r2
  65597. - beqzs8 .Li53
  65598. - move $r0, #1
  65599. - j .LP999
  65600. -.Li53:
  65601. - move $r0, #0
  65602. + ! ---------------------------------------------------------------------
  65603. + ! int __unordsf2(float a, float b):
  65604. + ! This function returns 1 if either argument is NaN, otherwise 0.
  65605. + ! ---------------------------------------------------------------------
  65606. + ! Is a NaN?
  65607. + slli $r0, $r0, #1
  65608. + move $r3, #0xff000000
  65609. + slt $r0, $r3, $r0
  65610. + bnez $r0, .Li67
  65611. + ! a is not NaN. Is b NaN?
  65612. + slli $r1, $r1, #1
  65613. + slt $r0, $r3, $r1
  65614. -.LP999:
  65615. - pop $lp
  65616. - ret5 $lp
  65617. +.Li67:
  65618. + ret5 $lp
  65619. .size __unordsf2, .-__unordsf2
  65620. #endif /* L_unord_sf */
  65621. @@ -5163,50 +5196,47 @@
  65622. #ifdef L_unord_df
  65623. -#ifndef __big_endian__
  65624. - #define P1L $r0
  65625. - #define P1H $r1
  65626. - #define P2L $r2
  65627. - #define P2H $r3
  65628. +#ifdef __big_endian__
  65629. + #define P1H $r0
  65630. + #define P1L $r1
  65631. + #define P2H $r2
  65632. + #define P2L $r3
  65633. #else
  65634. - #define P1H $r0
  65635. - #define P1L $r1
  65636. - #define P2H $r2
  65637. - #define P2L $r3
  65638. + #define P1H $r1
  65639. + #define P1L $r0
  65640. + #define P2H $r3
  65641. + #define P2L $r2
  65642. #endif
  65643. +#define W1 $r5
  65644. +#define W0 $r4
  65645. +
  65646. .text
  65647. .align 2
  65648. .global __unorddf2
  65649. .type __unorddf2, @function
  65650. __unorddf2:
  65651. - push $lp
  65652. + ! ---------------------------------------------------------------------
  65653. + ! int __unorddf2(double a, double b):
  65654. + ! This function returns 1 if either argument is NaN, otherwise 0.
  65655. + ! ---------------------------------------------------------------------
  65656. + ! Is a NaN?
  65657. + slli P1H, P1H, #1
  65658. + move W0, #0
  65659. + slt $r15, W0, P1L
  65660. + add $r0, P1H, $r15
  65661. + move W1, #0xffe00000
  65662. + slt $r0, W1, $r0
  65663. + bnez $r0, .Li69 ! it is NaN
  65664. +
  65665. + ! a is not NaN. Is b NaN?
  65666. + slli P2H, P2H, #1
  65667. + slt $r15, W0, P2L
  65668. + add P2H, P2H, $r15
  65669. + slt $r0, W1, P2H
  65670. - slli $r4, P1H, #1
  65671. - beqz P1L, .Li66
  65672. - addi $r4, $r4, #1
  65673. -.Li66:
  65674. - move $r5, #0xffe00000
  65675. - slt $r15, $r5, $r4
  65676. - beqzs8 .Li67
  65677. - move $r0, #1
  65678. - j .LR999
  65679. -.Li67:
  65680. - slli $r4, P2H, #1
  65681. - beqz P2L, .Li68
  65682. - addi $r4, $r4, #1
  65683. -.Li68:
  65684. - move $r5, #0xffe00000
  65685. - slt $r15, $r5, $r4
  65686. - beqzs8 .Li69
  65687. - move $r0, #1
  65688. - j .LR999
  65689. .Li69:
  65690. - move $r0, #0
  65691. -
  65692. -.LR999:
  65693. - pop $lp
  65694. - ret5 $lp
  65695. - .size __unorddf2, .-__unorddf2
  65696. + ret5 $lp
  65697. + .size __unorddf2, .-__unorddf2
  65698. #endif /* L_unord_df */
  65699. /* ------------------------------------------- */
  65700. /* DPBIT floating point operations for libgcc */
  65701. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib1asmsrc-newlib.S gcc-4.9.4/libgcc/config/nds32/lib1asmsrc-newlib.S
  65702. --- gcc-4.9.4.orig/libgcc/config/nds32/lib1asmsrc-newlib.S 2014-01-02 23:25:22.000000000 +0100
  65703. +++ gcc-4.9.4/libgcc/config/nds32/lib1asmsrc-newlib.S 2016-08-08 20:37:53.750589269 +0200
  65704. @@ -1,5 +1,5 @@
  65705. /* newlib libgcc routines of Andes NDS32 cpu for GNU compiler
  65706. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  65707. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  65708. Contributed by Andes Technology Corporation.
  65709. This file is part of GCC.
  65710. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c gcc-4.9.4/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c
  65711. --- gcc-4.9.4.orig/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c 2014-01-02 23:25:22.000000000 +0100
  65712. +++ gcc-4.9.4/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c 1970-01-01 01:00:00.000000000 +0100
  65713. @@ -1,38 +0,0 @@
  65714. -/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
  65715. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  65716. - Contributed by Andes Technology Corporation.
  65717. -
  65718. - This file is part of GCC.
  65719. -
  65720. - GCC is free software; you can redistribute it and/or modify it
  65721. - under the terms of the GNU General Public License as published
  65722. - by the Free Software Foundation; either version 3, or (at your
  65723. - option) any later version.
  65724. -
  65725. - GCC is distributed in the hope that it will be useful, but WITHOUT
  65726. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  65727. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  65728. - License for more details.
  65729. -
  65730. - Under Section 7 of GPL version 3, you are granted additional
  65731. - permissions described in the GCC Runtime Library Exception, version
  65732. - 3.1, as published by the Free Software Foundation.
  65733. -
  65734. - You should have received a copy of the GNU General Public License and
  65735. - a copy of the GCC Runtime Library Exception along with this program;
  65736. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  65737. - <http://www.gnu.org/licenses/>. */
  65738. -
  65739. -extern int __clzsi2 (int val);
  65740. -int
  65741. -__clzdi2 (long long val)
  65742. -{
  65743. - if (val >> 32)
  65744. - {
  65745. - return __clzsi2 (val >> 32);
  65746. - }
  65747. - else
  65748. - {
  65749. - return __clzsi2 (val) + 32;
  65750. - }
  65751. -}
  65752. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c gcc-4.9.4/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c
  65753. --- gcc-4.9.4.orig/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c 2014-01-02 23:25:22.000000000 +0100
  65754. +++ gcc-4.9.4/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c 1970-01-01 01:00:00.000000000 +0100
  65755. @@ -1,49 +0,0 @@
  65756. -/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
  65757. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  65758. - Contributed by Andes Technology Corporation.
  65759. -
  65760. - This file is part of GCC.
  65761. -
  65762. - GCC is free software; you can redistribute it and/or modify it
  65763. - under the terms of the GNU General Public License as published
  65764. - by the Free Software Foundation; either version 3, or (at your
  65765. - option) any later version.
  65766. -
  65767. - GCC is distributed in the hope that it will be useful, but WITHOUT
  65768. - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  65769. - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  65770. - License for more details.
  65771. -
  65772. - Under Section 7 of GPL version 3, you are granted additional
  65773. - permissions described in the GCC Runtime Library Exception, version
  65774. - 3.1, as published by the Free Software Foundation.
  65775. -
  65776. - You should have received a copy of the GNU General Public License and
  65777. - a copy of the GCC Runtime Library Exception along with this program;
  65778. - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  65779. - <http://www.gnu.org/licenses/>. */
  65780. -
  65781. -int
  65782. -__clzsi2 (int val)
  65783. -{
  65784. - int i = 32;
  65785. - int j = 16;
  65786. - int temp;
  65787. -
  65788. - for (; j; j >>= 1)
  65789. - {
  65790. - if (temp = val >> j)
  65791. - {
  65792. - if (j == 1)
  65793. - {
  65794. - return (i - 2);
  65795. - }
  65796. - else
  65797. - {
  65798. - i -= j;
  65799. - val = temp;
  65800. - }
  65801. - }
  65802. - }
  65803. - return (i - val);
  65804. -}
  65805. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib2src-mculib/_clzdi2.c gcc-4.9.4/libgcc/config/nds32/lib2src-mculib/_clzdi2.c
  65806. --- gcc-4.9.4.orig/libgcc/config/nds32/lib2src-mculib/_clzdi2.c 1970-01-01 01:00:00.000000000 +0100
  65807. +++ gcc-4.9.4/libgcc/config/nds32/lib2src-mculib/_clzdi2.c 2016-08-08 20:37:53.750589269 +0200
  65808. @@ -0,0 +1,39 @@
  65809. +/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
  65810. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  65811. + Contributed by Andes Technology Corporation.
  65812. +
  65813. + This file is part of GCC.
  65814. +
  65815. + GCC is free software; you can redistribute it and/or modify it
  65816. + under the terms of the GNU General Public License as published
  65817. + by the Free Software Foundation; either version 3, or (at your
  65818. + option) any later version.
  65819. +
  65820. + GCC is distributed in the hope that it will be useful, but WITHOUT
  65821. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  65822. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  65823. + License for more details.
  65824. +
  65825. + Under Section 7 of GPL version 3, you are granted additional
  65826. + permissions described in the GCC Runtime Library Exception, version
  65827. + 3.1, as published by the Free Software Foundation.
  65828. +
  65829. + You should have received a copy of the GNU General Public License and
  65830. + a copy of the GCC Runtime Library Exception along with this program;
  65831. + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  65832. + <http://www.gnu.org/licenses/>. */
  65833. +
  65834. +int
  65835. +__clzdi2 (long long val)
  65836. +{
  65837. + unsigned int hi = (unsigned int)(val >> 32);
  65838. +
  65839. + if (hi)
  65840. + {
  65841. + return __builtin_clz (hi);
  65842. + }
  65843. + else
  65844. + {
  65845. + return __builtin_clz ((unsigned int)val) + 32;
  65846. + }
  65847. +}
  65848. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/lib2src-mculib/_clzsi2.S gcc-4.9.4/libgcc/config/nds32/lib2src-mculib/_clzsi2.S
  65849. --- gcc-4.9.4.orig/libgcc/config/nds32/lib2src-mculib/_clzsi2.S 1970-01-01 01:00:00.000000000 +0100
  65850. +++ gcc-4.9.4/libgcc/config/nds32/lib2src-mculib/_clzsi2.S 2016-08-08 20:37:53.750589269 +0200
  65851. @@ -0,0 +1,47 @@
  65852. + .text
  65853. + .align 2
  65854. + .global __clzsi2
  65855. + .type __clzsi2, @function
  65856. +/*
  65857. +# int n = 31;
  65858. +# int shift = 16;
  65859. +#
  65860. +# if (x != 0)
  65861. +# {
  65862. +# do
  65863. +# {
  65864. +# if ((x >> shift))
  65865. +# {
  65866. +# n -= shift;
  65867. +# x >>= shift;
  65868. +# }
  65869. +# shift >>= 1;
  65870. +# }
  65871. +# while (shift > 0);
  65872. +#
  65873. +# return n;
  65874. +# }
  65875. +# else
  65876. +# return (32);
  65877. +*/
  65878. +__clzsi2:
  65879. + beqz38 $r0, .Lzero
  65880. + /* Handel general case. */
  65881. + movi $r1, #16
  65882. + movi $r3, #31
  65883. +.Lloop:
  65884. + sub333 $r4, $r3, $r1
  65885. + srl $r2, $r0, $r1
  65886. + cmovn $r3, $r4, $r2
  65887. + cmovn $r0, $r2, $r2
  65888. + srli45 $r1, #1
  65889. + bnez38 $r1, .Lloop
  65890. +
  65891. + move $r0, $r3
  65892. + ret5
  65893. +
  65894. +.Lzero:
  65895. + /* Handel corner case. (Input value is zero) */
  65896. + movi $r0, #32
  65897. + ret5
  65898. + .size __clzsi2, .-__clzsi2
  65899. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/linux-atomic.c gcc-4.9.4/libgcc/config/nds32/linux-atomic.c
  65900. --- gcc-4.9.4.orig/libgcc/config/nds32/linux-atomic.c 1970-01-01 01:00:00.000000000 +0100
  65901. +++ gcc-4.9.4/libgcc/config/nds32/linux-atomic.c 2016-08-08 20:37:53.750589269 +0200
  65902. @@ -0,0 +1,282 @@
  65903. +/* Linux-specific atomic operations for NDS32 Linux.
  65904. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  65905. +
  65906. +This file is free software; you can redistribute it and/or modify it
  65907. +under the terms of the GNU General Public License as published by the
  65908. +Free Software Foundation; either version 3, or (at your option) any
  65909. +later version.
  65910. +
  65911. +This file is distributed in the hope that it will be useful, but
  65912. +WITHOUT ANY WARRANTY; without even the implied warranty of
  65913. +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  65914. +General Public License for more details.
  65915. +
  65916. +Under Section 7 of GPL version 3, you are granted additional
  65917. +permissions described in the GCC Runtime Library Exception, version
  65918. +3.1, as published by the Free Software Foundation.
  65919. +
  65920. +You should have received a copy of the GNU General Public License and
  65921. +a copy of the GCC Runtime Library Exception along with this program;
  65922. +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  65923. +<http://www.gnu.org/licenses/>. */
  65924. +
  65925. +/* We implement byte, short and int versions of each atomic operation
  65926. + using the kernel helper defined below. There is no support for
  65927. + 64-bit operations yet. */
  65928. +
  65929. +/* This function copy form NDS32 Linux-kernal. */
  65930. +static inline int
  65931. +__kernel_cmpxchg (int oldval, int newval, int *mem)
  65932. +{
  65933. + int temp1, temp2, temp3, offset;
  65934. +
  65935. + asm volatile ("msync\tall\n"
  65936. + "movi\t%0, #0\n"
  65937. + "1:\n"
  65938. + "\tllw\t%1, [%4+%0]\n"
  65939. + "\tsub\t%3, %1, %6\n"
  65940. + "\tcmovz\t%2, %5, %3\n"
  65941. + "\tcmovn\t%2, %1, %3\n"
  65942. + "\tscw\t%2, [%4+%0]\n"
  65943. + "\tbeqz\t%2, 1b\n"
  65944. + : "=&r" (offset), "=&r" (temp3), "=&r" (temp2), "=&r" (temp1)
  65945. + : "r" (mem), "r" (newval), "r" (oldval));
  65946. +
  65947. + return temp2;
  65948. +}
  65949. +
  65950. +#define HIDDEN __attribute__ ((visibility ("hidden")))
  65951. +
  65952. +#ifdef __NDS32_EL__
  65953. +#define INVERT_MASK_1 0
  65954. +#define INVERT_MASK_2 0
  65955. +#else
  65956. +#define INVERT_MASK_1 24
  65957. +#define INVERT_MASK_2 16
  65958. +#endif
  65959. +
  65960. +#define MASK_1 0xffu
  65961. +#define MASK_2 0xffffu
  65962. +
  65963. +#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \
  65964. + int HIDDEN \
  65965. + __sync_fetch_and_##OP##_4 (int *ptr, int val) \
  65966. + { \
  65967. + int success, tmp; \
  65968. + \
  65969. + do { \
  65970. + tmp = *ptr; \
  65971. + success = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \
  65972. + } while (success == 0); \
  65973. + \
  65974. + return tmp; \
  65975. + }
  65976. +
  65977. +FETCH_AND_OP_WORD (add, , +)
  65978. +FETCH_AND_OP_WORD (sub, , -)
  65979. +FETCH_AND_OP_WORD (or, , |)
  65980. +FETCH_AND_OP_WORD (and, , &)
  65981. +FETCH_AND_OP_WORD (xor, , ^)
  65982. +FETCH_AND_OP_WORD (nand, ~, &)
  65983. +
  65984. +#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH
  65985. +#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH
  65986. +
  65987. +/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for
  65988. + subword-sized quantities. */
  65989. +
  65990. +#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN) \
  65991. + TYPE HIDDEN \
  65992. + NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val) \
  65993. + { \
  65994. + int *wordptr = (int *) ((unsigned long) ptr & ~3); \
  65995. + unsigned int mask, shift, oldval, newval; \
  65996. + int success; \
  65997. + \
  65998. + shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
  65999. + mask = MASK_##WIDTH << shift; \
  66000. + \
  66001. + do { \
  66002. + oldval = *wordptr; \
  66003. + newval = ((PFX_OP (((oldval & mask) >> shift) \
  66004. + INF_OP (unsigned int) val)) << shift) & mask; \
  66005. + newval |= oldval & ~mask; \
  66006. + success = __kernel_cmpxchg (oldval, newval, wordptr); \
  66007. + } while (success == 0); \
  66008. + \
  66009. + return (RETURN & mask) >> shift; \
  66010. + }
  66011. +
  66012. +
  66013. +SUBWORD_SYNC_OP (add, , +, unsigned short, 2, oldval)
  66014. +SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, oldval)
  66015. +SUBWORD_SYNC_OP (or, , |, unsigned short, 2, oldval)
  66016. +SUBWORD_SYNC_OP (and, , &, unsigned short, 2, oldval)
  66017. +SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, oldval)
  66018. +SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, oldval)
  66019. +
  66020. +SUBWORD_SYNC_OP (add, , +, unsigned char, 1, oldval)
  66021. +SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, oldval)
  66022. +SUBWORD_SYNC_OP (or, , |, unsigned char, 1, oldval)
  66023. +SUBWORD_SYNC_OP (and, , &, unsigned char, 1, oldval)
  66024. +SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, oldval)
  66025. +SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, oldval)
  66026. +
  66027. +#define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \
  66028. + int HIDDEN \
  66029. + __sync_##OP##_and_fetch_4 (int *ptr, int val) \
  66030. + { \
  66031. + int tmp, success; \
  66032. + \
  66033. + do { \
  66034. + tmp = *ptr; \
  66035. + success = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \
  66036. + } while (success == 0); \
  66037. + \
  66038. + return PFX_OP (tmp INF_OP val); \
  66039. + }
  66040. +
  66041. +OP_AND_FETCH_WORD (add, , +)
  66042. +OP_AND_FETCH_WORD (sub, , -)
  66043. +OP_AND_FETCH_WORD (or, , |)
  66044. +OP_AND_FETCH_WORD (and, , &)
  66045. +OP_AND_FETCH_WORD (xor, , ^)
  66046. +OP_AND_FETCH_WORD (nand, ~, &)
  66047. +
  66048. +SUBWORD_SYNC_OP (add, , +, unsigned short, 2, newval)
  66049. +SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, newval)
  66050. +SUBWORD_SYNC_OP (or, , |, unsigned short, 2, newval)
  66051. +SUBWORD_SYNC_OP (and, , &, unsigned short, 2, newval)
  66052. +SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, newval)
  66053. +SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, newval)
  66054. +
  66055. +SUBWORD_SYNC_OP (add, , +, unsigned char, 1, newval)
  66056. +SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, newval)
  66057. +SUBWORD_SYNC_OP (or, , |, unsigned char, 1, newval)
  66058. +SUBWORD_SYNC_OP (and, , &, unsigned char, 1, newval)
  66059. +SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, newval)
  66060. +SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, newval)
  66061. +
  66062. +int HIDDEN
  66063. +__sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
  66064. +{
  66065. + int actual_oldval, succ;
  66066. +
  66067. + while (1)
  66068. + {
  66069. + actual_oldval = *ptr;
  66070. +
  66071. + if (oldval != actual_oldval)
  66072. + return actual_oldval;
  66073. +
  66074. + succ = __kernel_cmpxchg (actual_oldval, newval, ptr);
  66075. +
  66076. + if (succ)
  66077. + return oldval;
  66078. + }
  66079. +}
  66080. +
  66081. +#define SUBWORD_VAL_CAS(TYPE, WIDTH) \
  66082. + TYPE HIDDEN \
  66083. + __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
  66084. + TYPE newval) \
  66085. + { \
  66086. + int *wordptr = (int *)((unsigned long) ptr & ~3), succ; \
  66087. + unsigned int mask, shift, actual_oldval, actual_newval; \
  66088. + \
  66089. + shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
  66090. + mask = MASK_##WIDTH << shift; \
  66091. + \
  66092. + while (1) \
  66093. + { \
  66094. + actual_oldval = *wordptr; \
  66095. + \
  66096. + if (((actual_oldval & mask) >> shift) != (unsigned int) oldval) \
  66097. + return (actual_oldval & mask) >> shift; \
  66098. + \
  66099. + actual_newval = (actual_oldval & ~mask) \
  66100. + | (((unsigned int) newval << shift) & mask); \
  66101. + \
  66102. + succ = __kernel_cmpxchg (actual_oldval, actual_newval, \
  66103. + wordptr); \
  66104. + \
  66105. + if (succ) \
  66106. + return oldval; \
  66107. + } \
  66108. + }
  66109. +
  66110. +SUBWORD_VAL_CAS (unsigned short, 2)
  66111. +SUBWORD_VAL_CAS (unsigned char, 1)
  66112. +
  66113. +typedef unsigned char bool;
  66114. +
  66115. +bool HIDDEN
  66116. +__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval)
  66117. +{
  66118. + int success = __kernel_cmpxchg (oldval, newval, ptr);
  66119. + return (success == 0);
  66120. +}
  66121. +
  66122. +#define SUBWORD_BOOL_CAS(TYPE, WIDTH) \
  66123. + bool HIDDEN \
  66124. + __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
  66125. + TYPE newval) \
  66126. + { \
  66127. + TYPE actual_oldval \
  66128. + = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval); \
  66129. + return (oldval == actual_oldval); \
  66130. + }
  66131. +
  66132. +SUBWORD_BOOL_CAS (unsigned short, 2)
  66133. +SUBWORD_BOOL_CAS (unsigned char, 1)
  66134. +
  66135. +int HIDDEN
  66136. +__sync_lock_test_and_set_4 (int *ptr, int val)
  66137. +{
  66138. + int success, oldval;
  66139. +
  66140. + do {
  66141. + oldval = *ptr;
  66142. + success = __kernel_cmpxchg (oldval, val, ptr);
  66143. + } while (success == 0);
  66144. +
  66145. + return oldval;
  66146. +}
  66147. +
  66148. +#define SUBWORD_TEST_AND_SET(TYPE, WIDTH) \
  66149. + TYPE HIDDEN \
  66150. + __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \
  66151. + { \
  66152. + int success; \
  66153. + unsigned int oldval, newval, shift, mask; \
  66154. + int *wordptr = (int *) ((unsigned long) ptr & ~3); \
  66155. + \
  66156. + shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \
  66157. + mask = MASK_##WIDTH << shift; \
  66158. + \
  66159. + do { \
  66160. + oldval = *wordptr; \
  66161. + newval = (oldval & ~mask) \
  66162. + | (((unsigned int) val << shift) & mask); \
  66163. + success = __kernel_cmpxchg (oldval, newval, wordptr); \
  66164. + } while (success == 0); \
  66165. + \
  66166. + return (oldval & mask) >> shift; \
  66167. + }
  66168. +
  66169. +SUBWORD_TEST_AND_SET (unsigned short, 2)
  66170. +SUBWORD_TEST_AND_SET (unsigned char, 1)
  66171. +
  66172. +#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \
  66173. + void HIDDEN \
  66174. + __sync_lock_release_##WIDTH (TYPE *ptr) \
  66175. + { \
  66176. + /* All writes before this point must be seen before we release \
  66177. + the lock itself. */ \
  66178. + __builtin_nds32_msync_all (); \
  66179. + *ptr = 0; \
  66180. + }
  66181. +
  66182. +SYNC_LOCK_RELEASE (int, 4)
  66183. +SYNC_LOCK_RELEASE (short, 2)
  66184. +SYNC_LOCK_RELEASE (char, 1)
  66185. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/linux-unwind.h gcc-4.9.4/libgcc/config/nds32/linux-unwind.h
  66186. --- gcc-4.9.4.orig/libgcc/config/nds32/linux-unwind.h 1970-01-01 01:00:00.000000000 +0100
  66187. +++ gcc-4.9.4/libgcc/config/nds32/linux-unwind.h 2016-08-08 20:37:53.750589269 +0200
  66188. @@ -0,0 +1,151 @@
  66189. +/* DWARF2 EH unwinding support for NDS32 Linux signal frame.
  66190. + Copyright (C) 2014-2015 Free Software Foundation, Inc.
  66191. + Contributed by Andes Technology Corporation.
  66192. +
  66193. + This file is part of GCC.
  66194. +
  66195. + GCC is free software; you can redistribute it and/or modify it
  66196. + under the terms of the GNU General Public License as published
  66197. + by the Free Software Foundation; either version 3, or (at your
  66198. + option) any later version.
  66199. +
  66200. + GCC is distributed in the hope that it will be useful, but WITHOUT
  66201. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  66202. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  66203. + License for more details.
  66204. +
  66205. + Under Section 7 of GPL version 3, you are granted additional
  66206. + permissions described in the GCC Runtime Library Exception, version
  66207. + 3.1, as published by the Free Software Foundation.
  66208. +
  66209. + You should have received a copy of the GNU General Public License and
  66210. + a copy of the GCC Runtime Library Exception along with this program;
  66211. + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
  66212. + <http://www.gnu.org/licenses/>. */
  66213. +
  66214. +#ifndef inhibit_libc
  66215. +
  66216. +/* Do code reading to identify a signal frame, and set the frame
  66217. + state data appropriately. See unwind-dw2.c for the structs.
  66218. + The corresponding bits in the Linux kernel are in
  66219. + arch/nds32/kernel/signal.c. */
  66220. +
  66221. +#include <signal.h>
  66222. +#include <asm/unistd.h>
  66223. +
  66224. +/* Exactly the same layout as the kernel structures, unique names. */
  66225. +
  66226. +/* arch/nds32/kernel/signal.c */
  66227. +struct _sigframe {
  66228. + struct ucontext uc;
  66229. + unsigned long retcode;
  66230. +};
  66231. +
  66232. +struct _rt_sigframe {
  66233. + siginfo_t info;
  66234. + struct _sigframe sig;
  66235. +};
  66236. +
  66237. +#define MD_FALLBACK_FRAME_STATE_FOR nds32_fallback_frame_state
  66238. +
  66239. +/* This function is supposed to be invoked by uw_frame_state_for()
  66240. + when there is no unwind data available.
  66241. +
  66242. + Generally, given the _Unwind_Context CONTEXT for a stack frame,
  66243. + we need to look up its caller and decode information into FS.
  66244. + However, if the exception handling happens within a signal handler,
  66245. + the return address of signal handler is a special module, which
  66246. + contains signal return syscall and has no FDE in the .eh_frame section.
  66247. + We need to implement MD_FALLBACK_FRAME_STATE_FOR so that we can
  66248. + unwind through signal frames. */
  66249. +static _Unwind_Reason_Code
  66250. +nds32_fallback_frame_state (struct _Unwind_Context *context,
  66251. + _Unwind_FrameState *fs)
  66252. +{
  66253. + u_int32_t *pc = (u_int32_t *) context->ra;
  66254. + struct sigcontext *sc_;
  66255. + _Unwind_Ptr new_cfa;
  66256. +
  66257. +#ifdef __NDS32_EB__
  66258. +#error "Signal handler is not supported for force unwind."
  66259. +#endif
  66260. +
  66261. + /* Check if we are going through a signal handler.
  66262. + See arch/nds32/kernel/signal.c implementation.
  66263. + SWI_SYS_SIGRETURN -> (0xeb0e0a64)
  66264. + SWI_SYS_RT_SIGRETURN -> (0xab150a64)
  66265. + FIXME: Currently we only handle little endian (EL) case. */
  66266. + if (pc[0] == 0xeb0e0a64)
  66267. + {
  66268. + /* Using '_sigfame' memory address to locate kernal's sigcontext.
  66269. + The sigcontext structures in arch/nds32/include/asm/sigcontext.h. */
  66270. + struct _sigframe *rt_;
  66271. + rt_ = context->cfa;
  66272. + sc_ = &rt_->uc.uc_mcontext;
  66273. + }
  66274. + else if (pc[0] == 0xab150a64)
  66275. + {
  66276. + /* Using '_sigfame' memory address to locate kernal's sigcontext. */
  66277. + struct _rt_sigframe *rt_;
  66278. + rt_ = context->cfa;
  66279. + sc_ = &rt_->sig.uc.uc_mcontext;
  66280. + }
  66281. + else
  66282. + return _URC_END_OF_STACK;
  66283. +
  66284. + /* Update cfa from sigcontext. */
  66285. + new_cfa = (_Unwind_Ptr) sc_;
  66286. + fs->regs.cfa_how = CFA_REG_OFFSET;
  66287. + fs->regs.cfa_reg = STACK_POINTER_REGNUM;
  66288. + fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
  66289. +
  66290. +#define NDS32_PUT_FS_REG(NUM, NAME) \
  66291. + (fs->regs.reg[NUM].how = REG_SAVED_OFFSET, \
  66292. + fs->regs.reg[NUM].loc.offset = (_Unwind_Ptr) &(sc_->NAME) - new_cfa)
  66293. +
  66294. + /* Restore all registers value. */
  66295. + NDS32_PUT_FS_REG (0, nds32_r0);
  66296. + NDS32_PUT_FS_REG (1, nds32_r1);
  66297. + NDS32_PUT_FS_REG (2, nds32_r2);
  66298. + NDS32_PUT_FS_REG (3, nds32_r3);
  66299. + NDS32_PUT_FS_REG (4, nds32_r4);
  66300. + NDS32_PUT_FS_REG (5, nds32_r5);
  66301. + NDS32_PUT_FS_REG (6, nds32_r6);
  66302. + NDS32_PUT_FS_REG (7, nds32_r7);
  66303. + NDS32_PUT_FS_REG (8, nds32_r8);
  66304. + NDS32_PUT_FS_REG (9, nds32_r9);
  66305. + NDS32_PUT_FS_REG (10, nds32_r10);
  66306. + NDS32_PUT_FS_REG (11, nds32_r11);
  66307. + NDS32_PUT_FS_REG (12, nds32_r12);
  66308. + NDS32_PUT_FS_REG (13, nds32_r13);
  66309. + NDS32_PUT_FS_REG (14, nds32_r14);
  66310. + NDS32_PUT_FS_REG (15, nds32_r15);
  66311. + NDS32_PUT_FS_REG (16, nds32_r16);
  66312. + NDS32_PUT_FS_REG (17, nds32_r17);
  66313. + NDS32_PUT_FS_REG (18, nds32_r18);
  66314. + NDS32_PUT_FS_REG (19, nds32_r19);
  66315. + NDS32_PUT_FS_REG (20, nds32_r20);
  66316. + NDS32_PUT_FS_REG (21, nds32_r21);
  66317. + NDS32_PUT_FS_REG (22, nds32_r22);
  66318. + NDS32_PUT_FS_REG (23, nds32_r23);
  66319. + NDS32_PUT_FS_REG (24, nds32_r24);
  66320. + NDS32_PUT_FS_REG (25, nds32_r25);
  66321. +
  66322. + NDS32_PUT_FS_REG (28, nds32_fp);
  66323. + NDS32_PUT_FS_REG (29, nds32_gp);
  66324. + NDS32_PUT_FS_REG (30, nds32_lr);
  66325. + NDS32_PUT_FS_REG (31, nds32_sp);
  66326. +
  66327. + /* Restore PC, point to trigger signal instruction. */
  66328. + NDS32_PUT_FS_REG (32, nds32_ipc);
  66329. +
  66330. +#undef NDS32_PUT_FS_REG
  66331. +
  66332. + /* The retaddr is PC, use PC to find FDE. */
  66333. + fs->retaddr_column = 32;
  66334. + fs->signal_frame = 1;
  66335. +
  66336. + return _URC_NO_REASON;
  66337. +}
  66338. +
  66339. +#endif
  66340. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/sfp-machine.h gcc-4.9.4/libgcc/config/nds32/sfp-machine.h
  66341. --- gcc-4.9.4.orig/libgcc/config/nds32/sfp-machine.h 2014-02-13 00:24:49.000000000 +0100
  66342. +++ gcc-4.9.4/libgcc/config/nds32/sfp-machine.h 2016-08-08 20:37:53.750589269 +0200
  66343. @@ -1,6 +1,6 @@
  66344. /* Machine settings for software floating-point emulation
  66345. of Andes NDS32 cpu for GNU compiler
  66346. - Copyright (C) 2012-2014 Free Software Foundation, Inc.
  66347. + Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66348. Contributed by Andes Technology Corporation.
  66349. This file is part of GNU C Library.
  66350. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-crtstuff gcc-4.9.4/libgcc/config/nds32/t-crtstuff
  66351. --- gcc-4.9.4.orig/libgcc/config/nds32/t-crtstuff 1970-01-01 01:00:00.000000000 +0100
  66352. +++ gcc-4.9.4/libgcc/config/nds32/t-crtstuff 2016-08-08 20:37:53.750589269 +0200
  66353. @@ -0,0 +1,5 @@
  66354. +# crtend*.o cannot be compiled without -fno-asynchronous-unwind-tables,
  66355. +# because then __FRAME_END__ might not be the last thing in .eh_frame
  66356. +# section.
  66357. +CRTSTUFF_T_CFLAGS += -fno-asynchronous-unwind-tables
  66358. +CRTSTUFF_T_CFLAGS_S += -fno-asynchronous-unwind-tables
  66359. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32 gcc-4.9.4/libgcc/config/nds32/t-nds32
  66360. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32 2014-01-02 23:25:22.000000000 +0100
  66361. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32 2016-08-08 20:37:53.750589269 +0200
  66362. @@ -1,5 +1,5 @@
  66363. # Rules of libgcc and crtstuff of Andes NDS32 cpu for GNU compiler
  66364. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  66365. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66366. # Contributed by Andes Technology Corporation.
  66367. #
  66368. # This file is part of GCC.
  66369. @@ -26,33 +26,22 @@
  66370. # Make sure the linker script include these two objects
  66371. # for building .ctors/.dtors sections.
  66372. -# Use -DCRT_BEGIN to create beginning parts of .init and .fini content
  66373. -# Make sure you are building crtbegin1.o with -O0 optimization,
  66374. -# otherwise the static function will be optimized out
  66375. +# Use -DCRT_BEGIN to create beginning parts of .init and .fini content.
  66376. crtbegin1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
  66377. $(GCC_FOR_TARGET) $(INCLUDES) \
  66378. $(CFLAGS) \
  66379. -DCRT_BEGIN \
  66380. -finhibit-size-directive -fno-inline-functions \
  66381. - -O0 -c $(srcdir)/config/nds32/initfini.c -o crtbegin1.o
  66382. + -fno-toplevel-reorder \
  66383. + -Os -c $(srcdir)/config/nds32/initfini.c -o crtbegin1.o
  66384. -# Use -DCRT_END to create ending parts of .init and .fini content
  66385. -# Make sure you are building crtend1.o with -O0 optimization,
  66386. -# otherwise the static function will be optimized out
  66387. +# Use -DCRT_END to create ending parts of .init and .fini content.
  66388. crtend1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
  66389. $(GCC_FOR_TARGET) $(INCLUDES) \
  66390. $(CFLAGS) \
  66391. -DCRT_END \
  66392. -finhibit-size-directive -fno-inline-functions \
  66393. - -O0 -c $(srcdir)/config/nds32/initfini.c -o crtend1.o
  66394. -
  66395. -# Use this rule if and only if your crt0.o does not come from library
  66396. -# Also, be sure to add 'crtzero.o' in extra_parts in libgcc/config.host
  66397. -# and change STARTFILE_SPEC in nds32.h
  66398. -#
  66399. -#crtzero.o: $(srcdir)/config/nds32/crtzero.S $(GCC_PASSES) $(CONFIG_H)
  66400. -# $(GCC_FOR_TARGET) $(INCLUDES) \
  66401. -# -c $(srcdir)/config/nds32/crtzero.S -o crtzero.o
  66402. -
  66403. + -fno-toplevel-reorder \
  66404. + -Os -c $(srcdir)/config/nds32/initfini.c -o crtend1.o
  66405. # ------------------------------------------------------------------------
  66406. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-glibc gcc-4.9.4/libgcc/config/nds32/t-nds32-glibc
  66407. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-glibc 1970-01-01 01:00:00.000000000 +0100
  66408. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-glibc 2016-08-08 20:37:53.750589269 +0200
  66409. @@ -0,0 +1,34 @@
  66410. +# Rules of glibc library makefile of Andes NDS32 cpu for GNU compiler
  66411. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66412. +# Contributed by Andes Technology Corporation.
  66413. +#
  66414. +# This file is part of GCC.
  66415. +#
  66416. +# GCC is free software; you can redistribute it and/or modify it
  66417. +# under the terms of the GNU General Public License as published
  66418. +# by the Free Software Foundation; either version 3, or (at your
  66419. +# option) any later version.
  66420. +#
  66421. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  66422. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  66423. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  66424. +# License for more details.
  66425. +#
  66426. +# You should have received a copy of the GNU General Public License
  66427. +# along with GCC; see the file COPYING3. If not see
  66428. +# <http://www.gnu.org/licenses/>.
  66429. +
  66430. +# Compiler flags to use when compiling 'libgcc2.c'
  66431. +HOST_LIBGCC2_CFLAGS = -O2 -fPIC
  66432. +LIB2ADD += $(srcdir)/config/nds32/linux-atomic.c
  66433. +
  66434. +#LIB1ASMSRC = nds32/lib1asmsrc-newlib.S
  66435. +#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3
  66436. +
  66437. +# List of functions not to build from libgcc2.c.
  66438. +#LIB2FUNCS_EXCLUDE = _clzsi2
  66439. +
  66440. +# List of extra C and assembler files(*.S) to add to static libgcc2.
  66441. +#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c
  66442. +
  66443. +# ------------------------------------------------------------------------
  66444. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-isr gcc-4.9.4/libgcc/config/nds32/t-nds32-isr
  66445. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-isr 2014-01-02 23:25:22.000000000 +0100
  66446. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-isr 2016-08-08 20:37:53.750589269 +0200
  66447. @@ -1,5 +1,5 @@
  66448. # Rules of c-isr library stuff of Andes NDS32 cpu for GNU compiler
  66449. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  66450. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66451. # Contributed by Andes Technology Corporation.
  66452. #
  66453. # This file is part of GCC.
  66454. @@ -23,11 +23,15 @@
  66455. # Makfile fragment rules for libnds32_isr.a to support ISR attribute extension
  66456. ###############################################################################
  66457. -# basic flags setting
  66458. -ISR_CFLAGS = $(CFLAGS) -c
  66459. +# Basic flags setting.
  66460. +ifneq ($(filter -mext-dsp,$(CFLAGS)),)
  66461. +ISR_CFLAGS = $(CFLAGS) -mno-force-no-ext-zol -mext-zol -c
  66462. +else
  66463. +ISR_CFLAGS = $(CFLAGS) -mno-force-no-ext-zol -c
  66464. +endif
  66465. -# the object files we would like to create
  66466. -LIBNDS32_ISR_16B_OBJS = \
  66467. +# The object files we would like to create.
  66468. +LIBNDS32_ISR_VEC_OBJS = \
  66469. vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \
  66470. vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \
  66471. vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \
  66472. @@ -46,40 +50,9 @@
  66473. vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \
  66474. vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \
  66475. vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \
  66476. - vec_vid72.o \
  66477. - excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
  66478. - excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
  66479. - intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
  66480. - intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
  66481. - reset.o
  66482. -
  66483. -LIBNDS32_ISR_4B_OBJS = \
  66484. - vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \
  66485. - vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \
  66486. - vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \
  66487. - vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \
  66488. - vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \
  66489. - vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \
  66490. - vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \
  66491. - vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \
  66492. - vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \
  66493. - vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \
  66494. - vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \
  66495. - vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \
  66496. - vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \
  66497. - vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \
  66498. - vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \
  66499. - vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \
  66500. - vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \
  66501. - vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \
  66502. - vec_vid72_4b.o \
  66503. - excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \
  66504. - excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \
  66505. - intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \
  66506. - intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \
  66507. - reset_4b.o
  66508. + vec_vid72.o
  66509. -LIBNDS32_ISR_COMMON_OBJS = \
  66510. +LIBNDS32_ISR_JMP_OBJS = \
  66511. jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \
  66512. jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \
  66513. jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \
  66514. @@ -98,29 +71,32 @@
  66515. jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \
  66516. jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \
  66517. jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \
  66518. - jmptbl_vid72.o \
  66519. + jmptbl_vid72.o
  66520. +
  66521. +LIBNDS32_ISR_COMMON_OBJS = \
  66522. + excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
  66523. + excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
  66524. + intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
  66525. + intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
  66526. + reset.o \
  66527. nmih.o \
  66528. wrh.o
  66529. -LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
  66530. -
  66531. +LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
  66532. -# Build common objects for ISR library
  66533. -nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
  66534. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
  66535. -wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
  66536. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
  66537. -jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
  66538. +# Build vector vid objects for ISR library.
  66539. +vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
  66540. $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
  66541. -
  66542. -# Build 16b version objects for ISR library. (no "_4b" postfix string)
  66543. -vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
  66544. +# Build jump table objects for ISR library.
  66545. +jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
  66546. $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
  66547. +
  66548. +# Build commen objects for ISR library.
  66549. excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
  66550. $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o
  66551. @@ -160,48 +136,12 @@
  66552. reset.o: $(srcdir)/config/nds32/isr-library/reset.S
  66553. $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o
  66554. -# Build 4b version objects for ISR library.
  66555. -vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S
  66556. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
  66557. -
  66558. -excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66559. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o
  66560. -
  66561. -excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66562. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o
  66563. -
  66564. -excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66565. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o
  66566. -
  66567. -excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66568. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o
  66569. -
  66570. -excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66571. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o
  66572. -
  66573. -excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
  66574. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o
  66575. -
  66576. -intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66577. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o
  66578. -
  66579. -intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66580. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o
  66581. -
  66582. -intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66583. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o
  66584. -
  66585. -intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66586. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o
  66587. -
  66588. -intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66589. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o
  66590. +nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
  66591. + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
  66592. -intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
  66593. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o
  66594. +wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
  66595. + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
  66596. -reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S
  66597. - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o
  66598. # The rule to create libnds32_isr.a file
  66599. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib
  66600. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib 2014-01-02 23:25:22.000000000 +0100
  66601. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib 1970-01-01 01:00:00.000000000 +0100
  66602. @@ -1,77 +0,0 @@
  66603. -# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler
  66604. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  66605. -# Contributed by Andes Technology Corporation.
  66606. -#
  66607. -# This file is part of GCC.
  66608. -#
  66609. -# GCC is free software; you can redistribute it and/or modify it
  66610. -# under the terms of the GNU General Public License as published
  66611. -# by the Free Software Foundation; either version 3, or (at your
  66612. -# option) any later version.
  66613. -#
  66614. -# GCC is distributed in the hope that it will be useful, but WITHOUT
  66615. -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  66616. -# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  66617. -# License for more details.
  66618. -#
  66619. -# You should have received a copy of the GNU General Public License
  66620. -# along with GCC; see the file COPYING3. If not see
  66621. -# <http://www.gnu.org/licenses/>.
  66622. -
  66623. -# Compiler flags to use when compiling 'libgcc2.c'
  66624. -HOST_LIBGCC2_CFLAGS = -Os
  66625. -
  66626. -
  66627. -LIB1ASMSRC = nds32/lib1asmsrc-mculib.S
  66628. -
  66629. -LIB1ASMFUNCS = \
  66630. - _addsub_sf \
  66631. - _sf_to_si \
  66632. - _divsi3 \
  66633. - _divdi3 \
  66634. - _modsi3 \
  66635. - _moddi3 \
  66636. - _mulsi3 \
  66637. - _udivsi3 \
  66638. - _udivdi3 \
  66639. - _udivmoddi4 \
  66640. - _umodsi3 \
  66641. - _umoddi3 \
  66642. - _muldi3 \
  66643. - _addsub_df \
  66644. - _mul_sf \
  66645. - _mul_df \
  66646. - _div_sf \
  66647. - _div_df \
  66648. - _negate_sf \
  66649. - _negate_df \
  66650. - _sf_to_df \
  66651. - _df_to_sf \
  66652. - _df_to_si \
  66653. - _fixsfdi \
  66654. - _fixdfdi \
  66655. - _fixunssfsi \
  66656. - _fixunsdfsi \
  66657. - _fixunssfdi \
  66658. - _fixunsdfdi \
  66659. - _si_to_sf \
  66660. - _si_to_df \
  66661. - _floatdisf \
  66662. - _floatdidf \
  66663. - _floatunsisf \
  66664. - _floatunsidf \
  66665. - _floatundisf \
  66666. - _floatundidf \
  66667. - _compare_sf \
  66668. - _compare_df \
  66669. - _unord_sf \
  66670. - _unord_df
  66671. -
  66672. -# List of functions not to build from libgcc2.c.
  66673. -LIB2FUNCS_EXCLUDE = _clzsi2 _clzdi2
  66674. -
  66675. -# List of extra C and assembler files(*.S) to add to static libgcc2.
  66676. -LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzsi2.c
  66677. -LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzdi2.c
  66678. -
  66679. -# ------------------------------------------------------------------------
  66680. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib-generic gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib-generic
  66681. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib-generic 1970-01-01 01:00:00.000000000 +0100
  66682. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib-generic 2016-08-08 20:37:53.750589269 +0200
  66683. @@ -0,0 +1,78 @@
  66684. +# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler
  66685. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66686. +# Contributed by Andes Technology Corporation.
  66687. +#
  66688. +# This file is part of GCC.
  66689. +#
  66690. +# GCC is free software; you can redistribute it and/or modify it
  66691. +# under the terms of the GNU General Public License as published
  66692. +# by the Free Software Foundation; either version 3, or (at your
  66693. +# option) any later version.
  66694. +#
  66695. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  66696. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  66697. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  66698. +# License for more details.
  66699. +#
  66700. +# You should have received a copy of the GNU General Public License
  66701. +# along with GCC; see the file COPYING3. If not see
  66702. +# <http://www.gnu.org/licenses/>.
  66703. +
  66704. +# Compiler flags to use when compiling 'libgcc2.c'
  66705. +HOST_LIBGCC2_CFLAGS = -Os
  66706. +
  66707. +
  66708. +LIB1ASMSRC = nds32/lib1asmsrc-mculib.S
  66709. +
  66710. +LIB1ASMFUNCS = \
  66711. + _addsub_sf \
  66712. + _divsi3 \
  66713. + _divdi3 \
  66714. + _modsi3 \
  66715. + _moddi3 \
  66716. + _mulsi3 \
  66717. + _udivsi3 \
  66718. + _udivdi3 \
  66719. + _umul_ppmm \
  66720. + _udivmoddi4 \
  66721. + _umodsi3 \
  66722. + _umoddi3 \
  66723. + _muldi3 \
  66724. + _addsub_df \
  66725. + _mul_sf \
  66726. + _mul_df \
  66727. + _div_sf \
  66728. + _div_df \
  66729. + _negate_sf \
  66730. + _negate_df \
  66731. + _sf_to_df \
  66732. + _df_to_sf \
  66733. + _fixsfdi \
  66734. + _fixsfsi \
  66735. + _fixdfdi \
  66736. + _fixdfsi \
  66737. + _fixunssfsi \
  66738. + _fixunsdfsi \
  66739. + _fixunssfdi \
  66740. + _fixunsdfdi \
  66741. + _si_to_sf \
  66742. + _si_to_df \
  66743. + _floatdisf \
  66744. + _floatdidf \
  66745. + _floatunsisf \
  66746. + _floatunsidf \
  66747. + _floatundisf \
  66748. + _floatundidf \
  66749. + _compare_sf \
  66750. + _compare_df \
  66751. + _unord_sf \
  66752. + _unord_df
  66753. +
  66754. +# List of functions not to build from libgcc2.c.
  66755. +LIB2FUNCS_EXCLUDE = _clzdi2 _clzsi2
  66756. +
  66757. +# List of extra C and assembler files(*.S) to add to static libgcc2.
  66758. +LIB2ADD_ST += $(srcdir)/config/nds32/lib2src-mculib/_clzdi2.c
  66759. +LIB2ADD_ST += $(srcdir)/config/nds32/lib2src-mculib/_clzsi2.S
  66760. +
  66761. +# ------------------------------------------------------------------------
  66762. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib-softfp gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib-softfp
  66763. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-mculib-softfp 1970-01-01 01:00:00.000000000 +0100
  66764. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-mculib-softfp 2016-08-08 20:37:53.750589269 +0200
  66765. @@ -0,0 +1,56 @@
  66766. +# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler
  66767. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66768. +# Contributed by Andes Technology Corporation.
  66769. +#
  66770. +# This file is part of GCC.
  66771. +#
  66772. +# GCC is free software; you can redistribute it and/or modify it
  66773. +# under the terms of the GNU General Public License as published
  66774. +# by the Free Software Foundation; either version 3, or (at your
  66775. +# option) any later version.
  66776. +#
  66777. +# GCC is distributed in the hope that it will be useful, but WITHOUT
  66778. +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  66779. +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  66780. +# License for more details.
  66781. +#
  66782. +# You should have received a copy of the GNU General Public License
  66783. +# along with GCC; see the file COPYING3. If not see
  66784. +# <http://www.gnu.org/licenses/>.
  66785. +
  66786. +# Compiler flags to use when compiling 'libgcc2.c'
  66787. +HOST_LIBGCC2_CFLAGS = -Os
  66788. +
  66789. +LIB1ASMSRC = nds32/lib1asmsrc-mculib.S
  66790. +
  66791. +LIB1ASMFUNCS = \
  66792. + _addsub_sf \
  66793. + _divsi3 \
  66794. + _divdi3 \
  66795. + _modsi3 \
  66796. + _moddi3 \
  66797. + _mulsi3 \
  66798. + _udivsi3 \
  66799. + _udivdi3 \
  66800. + _umul_ppmm \
  66801. + _udivmoddi4 \
  66802. + _umodsi3 \
  66803. + _umoddi3 \
  66804. + _muldi3 \
  66805. + _fixsfdi \
  66806. + _fixdfdi \
  66807. + _fixsfsi \
  66808. + _fixdfsi \
  66809. + _fixunssfsi \
  66810. + _fixunsdfsi \
  66811. + _fixunssfdi \
  66812. + _fixunsdfdi
  66813. +
  66814. +# List of functions not to build from libgcc2.c.
  66815. +LIB2FUNCS_EXCLUDE = _clzdi2 _clzsi2
  66816. +
  66817. +# List of extra C and assembler files(*.S) to add to static libgcc2.
  66818. +LIB2ADD_ST += $(srcdir)/config/nds32/lib2src-mculib/_clzdi2.c
  66819. +LIB2ADD_ST += $(srcdir)/config/nds32/lib2src-mculib/_clzsi2.S
  66820. +
  66821. +# ------------------------------------------------------------------------
  66822. diff -Nur gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-newlib gcc-4.9.4/libgcc/config/nds32/t-nds32-newlib
  66823. --- gcc-4.9.4.orig/libgcc/config/nds32/t-nds32-newlib 2014-01-02 23:25:22.000000000 +0100
  66824. +++ gcc-4.9.4/libgcc/config/nds32/t-nds32-newlib 2016-08-08 20:37:53.750589269 +0200
  66825. @@ -1,5 +1,5 @@
  66826. # Rules of newlib library makefile of Andes NDS32 cpu for GNU compiler
  66827. -# Copyright (C) 2012-2014 Free Software Foundation, Inc.
  66828. +# Copyright (C) 2012-2015 Free Software Foundation, Inc.
  66829. # Contributed by Andes Technology Corporation.
  66830. #
  66831. # This file is part of GCC.
  66832. diff -Nur gcc-4.9.4.orig/libgcc/config.host gcc-4.9.4/libgcc/config.host
  66833. --- gcc-4.9.4.orig/libgcc/config.host 2016-05-17 08:22:28.000000000 +0200
  66834. +++ gcc-4.9.4/libgcc/config.host 2016-08-08 20:37:53.754589424 +0200
  66835. @@ -874,6 +874,23 @@
  66836. msp430*-*-elf)
  66837. tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430"
  66838. ;;
  66839. +nds32*-linux*)
  66840. + # Basic makefile fragment and extra_parts for crt stuff.
  66841. + # We also append c-isr library implementation.
  66842. + tmake_file="${tmake_file} t-slibgcc-libgcc"
  66843. + tmake_file="${tmake_file} nds32/t-nds32-glibc nds32/t-crtstuff t-softfp-sfdf t-softfp"
  66844. + # The header file of defining MD_FALLBACK_FRAME_STATE_FOR.
  66845. + md_unwind_header=nds32/linux-unwind.h
  66846. + # Append library definition makefile fragment according to --with-nds32-lib=X setting.
  66847. + case "${with_nds32_lib}" in
  66848. + "" )
  66849. + ;;
  66850. + *)
  66851. + echo "Cannot accept --with-nds32-lib= for linux toolchain" 1>&2
  66852. + exit 1
  66853. + ;;
  66854. + esac
  66855. + ;;
  66856. nds32*-elf*)
  66857. # Basic makefile fragment and extra_parts for crt stuff.
  66858. # We also append c-isr library implementation.
  66859. @@ -887,9 +904,19 @@
  66860. tmake_file="${tmake_file} nds32/t-nds32-newlib t-softfp-sfdf t-softfp"
  66861. ;;
  66862. mculib)
  66863. - # Append library definition makefile fragment t-nds32-mculib.
  66864. + case "${with_arch}" in
  66865. + "" | v2 | v2j | v3 | v3j | v3m)
  66866. + # Append library definition makefile fragment t-nds32-mculib-generic.
  66867. # The software floating point library is included in mculib.
  66868. - tmake_file="${tmake_file} nds32/t-nds32-mculib"
  66869. + tmake_file="${tmake_file} nds32/t-nds32-mculib-generic"
  66870. + ;;
  66871. + v3f | v3s)
  66872. + # Append library definition makefile fragment t-nds32-mculib-softfp.
  66873. + # Append mculib do not support ABI2FP_PLUS,
  66874. + # so using'soft-fp' software floating point make rule fragment provided by gcc.
  66875. + tmake_file="${tmake_file} nds32/t-nds32-mculib-softfp t-softfp-sfdf t-softfp"
  66876. + ;;
  66877. + esac
  66878. ;;
  66879. *)
  66880. echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
  66881. diff -Nur gcc-4.9.4.orig/libiberty/config.status gcc-4.9.4/libiberty/config.status
  66882. --- gcc-4.9.4.orig/libiberty/config.status 1970-01-01 01:00:00.000000000 +0100
  66883. +++ gcc-4.9.4/libiberty/config.status 2016-08-08 20:37:53.866593761 +0200
  66884. @@ -0,0 +1,1200 @@
  66885. +#! /bin/sh
  66886. +# Generated by configure.
  66887. +# Run this file to recreate the current configuration.
  66888. +# Compiler output produced by configure, useful for debugging
  66889. +# configure, is in config.log if it exists.
  66890. +
  66891. +debug=false
  66892. +ac_cs_recheck=false
  66893. +ac_cs_silent=false
  66894. +
  66895. +SHELL=${CONFIG_SHELL-/bin/sh}
  66896. +export SHELL
  66897. +## -------------------- ##
  66898. +## M4sh Initialization. ##
  66899. +## -------------------- ##
  66900. +
  66901. +# Be more Bourne compatible
  66902. +DUALCASE=1; export DUALCASE # for MKS sh
  66903. +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
  66904. + emulate sh
  66905. + NULLCMD=:
  66906. + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
  66907. + # is contrary to our usage. Disable this feature.
  66908. + alias -g '${1+"$@"}'='"$@"'
  66909. + setopt NO_GLOB_SUBST
  66910. +else
  66911. + case `(set -o) 2>/dev/null` in #(
  66912. + *posix*) :
  66913. + set -o posix ;; #(
  66914. + *) :
  66915. + ;;
  66916. +esac
  66917. +fi
  66918. +
  66919. +
  66920. +as_nl='
  66921. +'
  66922. +export as_nl
  66923. +# Printing a long string crashes Solaris 7 /usr/bin/printf.
  66924. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
  66925. +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
  66926. +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
  66927. +# Prefer a ksh shell builtin over an external printf program on Solaris,
  66928. +# but without wasting forks for bash or zsh.
  66929. +if test -z "$BASH_VERSION$ZSH_VERSION" \
  66930. + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
  66931. + as_echo='print -r --'
  66932. + as_echo_n='print -rn --'
  66933. +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
  66934. + as_echo='printf %s\n'
  66935. + as_echo_n='printf %s'
  66936. +else
  66937. + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
  66938. + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
  66939. + as_echo_n='/usr/ucb/echo -n'
  66940. + else
  66941. + as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
  66942. + as_echo_n_body='eval
  66943. + arg=$1;
  66944. + case $arg in #(
  66945. + *"$as_nl"*)
  66946. + expr "X$arg" : "X\\(.*\\)$as_nl";
  66947. + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
  66948. + esac;
  66949. + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
  66950. + '
  66951. + export as_echo_n_body
  66952. + as_echo_n='sh -c $as_echo_n_body as_echo'
  66953. + fi
  66954. + export as_echo_body
  66955. + as_echo='sh -c $as_echo_body as_echo'
  66956. +fi
  66957. +
  66958. +# The user is always right.
  66959. +if test "${PATH_SEPARATOR+set}" != set; then
  66960. + PATH_SEPARATOR=:
  66961. + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
  66962. + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
  66963. + PATH_SEPARATOR=';'
  66964. + }
  66965. +fi
  66966. +
  66967. +
  66968. +# IFS
  66969. +# We need space, tab and new line, in precisely that order. Quoting is
  66970. +# there to prevent editors from complaining about space-tab.
  66971. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word
  66972. +# splitting by setting IFS to empty value.)
  66973. +IFS=" "" $as_nl"
  66974. +
  66975. +# Find who we are. Look in the path if we contain no directory separator.
  66976. +case $0 in #((
  66977. + *[\\/]* ) as_myself=$0 ;;
  66978. + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
  66979. +for as_dir in $PATH
  66980. +do
  66981. + IFS=$as_save_IFS
  66982. + test -z "$as_dir" && as_dir=.
  66983. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
  66984. + done
  66985. +IFS=$as_save_IFS
  66986. +
  66987. + ;;
  66988. +esac
  66989. +# We did not find ourselves, most probably we were run as `sh COMMAND'
  66990. +# in which case we are not to be found in the path.
  66991. +if test "x$as_myself" = x; then
  66992. + as_myself=$0
  66993. +fi
  66994. +if test ! -f "$as_myself"; then
  66995. + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
  66996. + exit 1
  66997. +fi
  66998. +
  66999. +# Unset variables that we do not need and which cause bugs (e.g. in
  67000. +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
  67001. +# suppresses any "Segmentation fault" message there. '((' could
  67002. +# trigger a bug in pdksh 5.2.14.
  67003. +for as_var in BASH_ENV ENV MAIL MAILPATH
  67004. +do eval test x\${$as_var+set} = xset \
  67005. + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
  67006. +done
  67007. +PS1='$ '
  67008. +PS2='> '
  67009. +PS4='+ '
  67010. +
  67011. +# NLS nuisances.
  67012. +LC_ALL=C
  67013. +export LC_ALL
  67014. +LANGUAGE=C
  67015. +export LANGUAGE
  67016. +
  67017. +# CDPATH.
  67018. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
  67019. +
  67020. +
  67021. +# as_fn_error ERROR [LINENO LOG_FD]
  67022. +# ---------------------------------
  67023. +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
  67024. +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
  67025. +# script with status $?, using 1 if that was 0.
  67026. +as_fn_error ()
  67027. +{
  67028. + as_status=$?; test $as_status -eq 0 && as_status=1
  67029. + if test "$3"; then
  67030. + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
  67031. + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
  67032. + fi
  67033. + $as_echo "$as_me: error: $1" >&2
  67034. + as_fn_exit $as_status
  67035. +} # as_fn_error
  67036. +
  67037. +
  67038. +# as_fn_set_status STATUS
  67039. +# -----------------------
  67040. +# Set $? to STATUS, without forking.
  67041. +as_fn_set_status ()
  67042. +{
  67043. + return $1
  67044. +} # as_fn_set_status
  67045. +
  67046. +# as_fn_exit STATUS
  67047. +# -----------------
  67048. +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
  67049. +as_fn_exit ()
  67050. +{
  67051. + set +e
  67052. + as_fn_set_status $1
  67053. + exit $1
  67054. +} # as_fn_exit
  67055. +
  67056. +# as_fn_unset VAR
  67057. +# ---------------
  67058. +# Portably unset VAR.
  67059. +as_fn_unset ()
  67060. +{
  67061. + { eval $1=; unset $1;}
  67062. +}
  67063. +as_unset=as_fn_unset
  67064. +# as_fn_append VAR VALUE
  67065. +# ----------------------
  67066. +# Append the text in VALUE to the end of the definition contained in VAR. Take
  67067. +# advantage of any shell optimizations that allow amortized linear growth over
  67068. +# repeated appends, instead of the typical quadratic growth present in naive
  67069. +# implementations.
  67070. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
  67071. + eval 'as_fn_append ()
  67072. + {
  67073. + eval $1+=\$2
  67074. + }'
  67075. +else
  67076. + as_fn_append ()
  67077. + {
  67078. + eval $1=\$$1\$2
  67079. + }
  67080. +fi # as_fn_append
  67081. +
  67082. +# as_fn_arith ARG...
  67083. +# ------------------
  67084. +# Perform arithmetic evaluation on the ARGs, and store the result in the
  67085. +# global $as_val. Take advantage of shells that can avoid forks. The arguments
  67086. +# must be portable across $(()) and expr.
  67087. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
  67088. + eval 'as_fn_arith ()
  67089. + {
  67090. + as_val=$(( $* ))
  67091. + }'
  67092. +else
  67093. + as_fn_arith ()
  67094. + {
  67095. + as_val=`expr "$@" || test $? -eq 1`
  67096. + }
  67097. +fi # as_fn_arith
  67098. +
  67099. +
  67100. +if expr a : '\(a\)' >/dev/null 2>&1 &&
  67101. + test "X`expr 00001 : '.*\(...\)'`" = X001; then
  67102. + as_expr=expr
  67103. +else
  67104. + as_expr=false
  67105. +fi
  67106. +
  67107. +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
  67108. + as_basename=basename
  67109. +else
  67110. + as_basename=false
  67111. +fi
  67112. +
  67113. +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
  67114. + as_dirname=dirname
  67115. +else
  67116. + as_dirname=false
  67117. +fi
  67118. +
  67119. +as_me=`$as_basename -- "$0" ||
  67120. +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
  67121. + X"$0" : 'X\(//\)$' \| \
  67122. + X"$0" : 'X\(/\)' \| . 2>/dev/null ||
  67123. +$as_echo X/"$0" |
  67124. + sed '/^.*\/\([^/][^/]*\)\/*$/{
  67125. + s//\1/
  67126. + q
  67127. + }
  67128. + /^X\/\(\/\/\)$/{
  67129. + s//\1/
  67130. + q
  67131. + }
  67132. + /^X\/\(\/\).*/{
  67133. + s//\1/
  67134. + q
  67135. + }
  67136. + s/.*/./; q'`
  67137. +
  67138. +# Avoid depending upon Character Ranges.
  67139. +as_cr_letters='abcdefghijklmnopqrstuvwxyz'
  67140. +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
  67141. +as_cr_Letters=$as_cr_letters$as_cr_LETTERS
  67142. +as_cr_digits='0123456789'
  67143. +as_cr_alnum=$as_cr_Letters$as_cr_digits
  67144. +
  67145. +ECHO_C= ECHO_N= ECHO_T=
  67146. +case `echo -n x` in #(((((
  67147. +-n*)
  67148. + case `echo 'xy\c'` in
  67149. + *c*) ECHO_T=' ';; # ECHO_T is single tab character.
  67150. + xy) ECHO_C='\c';;
  67151. + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null
  67152. + ECHO_T=' ';;
  67153. + esac;;
  67154. +*)
  67155. + ECHO_N='-n';;
  67156. +esac
  67157. +
  67158. +rm -f conf$$ conf$$.exe conf$$.file
  67159. +if test -d conf$$.dir; then
  67160. + rm -f conf$$.dir/conf$$.file
  67161. +else
  67162. + rm -f conf$$.dir
  67163. + mkdir conf$$.dir 2>/dev/null
  67164. +fi
  67165. +if (echo >conf$$.file) 2>/dev/null; then
  67166. + if ln -s conf$$.file conf$$ 2>/dev/null; then
  67167. + as_ln_s='ln -s'
  67168. + # ... but there are two gotchas:
  67169. + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
  67170. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
  67171. + # In both cases, we have to default to `cp -p'.
  67172. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
  67173. + as_ln_s='cp -p'
  67174. + elif ln conf$$.file conf$$ 2>/dev/null; then
  67175. + as_ln_s=ln
  67176. + else
  67177. + as_ln_s='cp -p'
  67178. + fi
  67179. +else
  67180. + as_ln_s='cp -p'
  67181. +fi
  67182. +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
  67183. +rmdir conf$$.dir 2>/dev/null
  67184. +
  67185. +
  67186. +# as_fn_mkdir_p
  67187. +# -------------
  67188. +# Create "$as_dir" as a directory, including parents if necessary.
  67189. +as_fn_mkdir_p ()
  67190. +{
  67191. +
  67192. + case $as_dir in #(
  67193. + -*) as_dir=./$as_dir;;
  67194. + esac
  67195. + test -d "$as_dir" || eval $as_mkdir_p || {
  67196. + as_dirs=
  67197. + while :; do
  67198. + case $as_dir in #(
  67199. + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
  67200. + *) as_qdir=$as_dir;;
  67201. + esac
  67202. + as_dirs="'$as_qdir' $as_dirs"
  67203. + as_dir=`$as_dirname -- "$as_dir" ||
  67204. +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
  67205. + X"$as_dir" : 'X\(//\)[^/]' \| \
  67206. + X"$as_dir" : 'X\(//\)$' \| \
  67207. + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
  67208. +$as_echo X"$as_dir" |
  67209. + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
  67210. + s//\1/
  67211. + q
  67212. + }
  67213. + /^X\(\/\/\)[^/].*/{
  67214. + s//\1/
  67215. + q
  67216. + }
  67217. + /^X\(\/\/\)$/{
  67218. + s//\1/
  67219. + q
  67220. + }
  67221. + /^X\(\/\).*/{
  67222. + s//\1/
  67223. + q
  67224. + }
  67225. + s/.*/./; q'`
  67226. + test -d "$as_dir" && break
  67227. + done
  67228. + test -z "$as_dirs" || eval "mkdir $as_dirs"
  67229. + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
  67230. +
  67231. +
  67232. +} # as_fn_mkdir_p
  67233. +if mkdir -p . 2>/dev/null; then
  67234. + as_mkdir_p='mkdir -p "$as_dir"'
  67235. +else
  67236. + test -d ./-p && rmdir ./-p
  67237. + as_mkdir_p=false
  67238. +fi
  67239. +
  67240. +if test -x / >/dev/null 2>&1; then
  67241. + as_test_x='test -x'
  67242. +else
  67243. + if ls -dL / >/dev/null 2>&1; then
  67244. + as_ls_L_option=L
  67245. + else
  67246. + as_ls_L_option=
  67247. + fi
  67248. + as_test_x='
  67249. + eval sh -c '\''
  67250. + if test -d "$1"; then
  67251. + test -d "$1/.";
  67252. + else
  67253. + case $1 in #(
  67254. + -*)set "./$1";;
  67255. + esac;
  67256. + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #((
  67257. + ???[sx]*):;;*)false;;esac;fi
  67258. + '\'' sh
  67259. + '
  67260. +fi
  67261. +as_executable_p=$as_test_x
  67262. +
  67263. +# Sed expression to map a string onto a valid CPP name.
  67264. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
  67265. +
  67266. +# Sed expression to map a string onto a valid variable name.
  67267. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
  67268. +
  67269. +
  67270. +exec 6>&1
  67271. +## ----------------------------------- ##
  67272. +## Main body of $CONFIG_STATUS script. ##
  67273. +## ----------------------------------- ##
  67274. +# Save the log message, to keep $0 and so on meaningful, and to
  67275. +# report actual input values of CONFIG_FILES etc. instead of their
  67276. +# values after options handling.
  67277. +ac_log="
  67278. +This file was extended by $as_me, which was
  67279. +generated by GNU Autoconf 2.64. Invocation command line was
  67280. +
  67281. + CONFIG_FILES = $CONFIG_FILES
  67282. + CONFIG_HEADERS = $CONFIG_HEADERS
  67283. + CONFIG_LINKS = $CONFIG_LINKS
  67284. + CONFIG_COMMANDS = $CONFIG_COMMANDS
  67285. + $ $0 $@
  67286. +
  67287. +on `(hostname || uname -n) 2>/dev/null | sed 1q`
  67288. +"
  67289. +
  67290. +# Files that config.status was made for.
  67291. +config_files=" Makefile testsuite/Makefile"
  67292. +config_headers=" config.h:config.in"
  67293. +config_commands=" default"
  67294. +
  67295. +ac_cs_usage="\
  67296. +\`$as_me' instantiates files and other configuration actions
  67297. +from templates according to the current configuration. Unless the files
  67298. +and actions are specified as TAGs, all are instantiated by default.
  67299. +
  67300. +Usage: $0 [OPTION]... [TAG]...
  67301. +
  67302. + -h, --help print this help, then exit
  67303. + -V, --version print version number and configuration settings, then exit
  67304. + -q, --quiet, --silent
  67305. + do not print progress messages
  67306. + -d, --debug don't remove temporary files
  67307. + --recheck update $as_me by reconfiguring in the same conditions
  67308. + --file=FILE[:TEMPLATE]
  67309. + instantiate the configuration file FILE
  67310. + --header=FILE[:TEMPLATE]
  67311. + instantiate the configuration header FILE
  67312. +
  67313. +Configuration files:
  67314. +$config_files
  67315. +
  67316. +Configuration headers:
  67317. +$config_headers
  67318. +
  67319. +Configuration commands:
  67320. +$config_commands
  67321. +
  67322. +Report bugs to the package provider."
  67323. +
  67324. +ac_cs_version="\
  67325. +config.status
  67326. +configured by ./configure, generated by GNU Autoconf 2.64,
  67327. + with options \"'--host=nds32le-linux' '--prefix=/home/users/kito/toolchain/nds32le-linux-glibc-v3/nds32le-linux/sysroot/usr' 'CC=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'LD=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'RANLIB=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ranlib' 'AR=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ar' '--enable-install-libiberty' 'host_alias=nds32le-linux'\"
  67328. +
  67329. +Copyright (C) 2009 Free Software Foundation, Inc.
  67330. +This config.status script is free software; the Free Software Foundation
  67331. +gives unlimited permission to copy, distribute and modify it."
  67332. +
  67333. +ac_pwd='/home/users/kito/build-system-3/source-packages/gcc-4.9.3/libiberty'
  67334. +srcdir='.'
  67335. +INSTALL='/usr/bin/install -c'
  67336. +test -n "$AWK" || AWK=awk
  67337. +# The default lists apply if the user does not specify any file.
  67338. +ac_need_defaults=:
  67339. +while test $# != 0
  67340. +do
  67341. + case $1 in
  67342. + --*=*)
  67343. + ac_option=`expr "X$1" : 'X\([^=]*\)='`
  67344. + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
  67345. + ac_shift=:
  67346. + ;;
  67347. + *)
  67348. + ac_option=$1
  67349. + ac_optarg=$2
  67350. + ac_shift=shift
  67351. + ;;
  67352. + esac
  67353. +
  67354. + case $ac_option in
  67355. + # Handling of the options.
  67356. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
  67357. + ac_cs_recheck=: ;;
  67358. + --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
  67359. + $as_echo "$ac_cs_version"; exit ;;
  67360. + --debug | --debu | --deb | --de | --d | -d )
  67361. + debug=: ;;
  67362. + --file | --fil | --fi | --f )
  67363. + $ac_shift
  67364. + case $ac_optarg in
  67365. + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
  67366. + esac
  67367. + as_fn_append CONFIG_FILES " '$ac_optarg'"
  67368. + ac_need_defaults=false;;
  67369. + --header | --heade | --head | --hea )
  67370. + $ac_shift
  67371. + case $ac_optarg in
  67372. + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
  67373. + esac
  67374. + as_fn_append CONFIG_HEADERS " '$ac_optarg'"
  67375. + ac_need_defaults=false;;
  67376. + --he | --h)
  67377. + # Conflict between --help and --header
  67378. + as_fn_error "ambiguous option: \`$1'
  67379. +Try \`$0 --help' for more information.";;
  67380. + --help | --hel | -h )
  67381. + $as_echo "$ac_cs_usage"; exit ;;
  67382. + -q | -quiet | --quiet | --quie | --qui | --qu | --q \
  67383. + | -silent | --silent | --silen | --sile | --sil | --si | --s)
  67384. + ac_cs_silent=: ;;
  67385. +
  67386. + # This is an error.
  67387. + -*) as_fn_error "unrecognized option: \`$1'
  67388. +Try \`$0 --help' for more information." ;;
  67389. +
  67390. + *) as_fn_append ac_config_targets " $1"
  67391. + ac_need_defaults=false ;;
  67392. +
  67393. + esac
  67394. + shift
  67395. +done
  67396. +
  67397. +ac_configure_extra_args=
  67398. +
  67399. +if $ac_cs_silent; then
  67400. + exec 6>/dev/null
  67401. + ac_configure_extra_args="$ac_configure_extra_args --silent"
  67402. +fi
  67403. +
  67404. +if $ac_cs_recheck; then
  67405. + set X '/bin/sh' './configure' '--host=nds32le-linux' '--prefix=/home/users/kito/toolchain/nds32le-linux-glibc-v3/nds32le-linux/sysroot/usr' 'CC=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'LD=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'RANLIB=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ranlib' 'AR=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ar' '--enable-install-libiberty' 'host_alias=nds32le-linux' $ac_configure_extra_args --no-create --no-recursion
  67406. + shift
  67407. + $as_echo "running CONFIG_SHELL=/bin/sh $*" >&6
  67408. + CONFIG_SHELL='/bin/sh'
  67409. + export CONFIG_SHELL
  67410. + exec "$@"
  67411. +fi
  67412. +
  67413. +exec 5>>config.log
  67414. +{
  67415. + echo
  67416. + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
  67417. +## Running $as_me. ##
  67418. +_ASBOX
  67419. + $as_echo "$ac_log"
  67420. +} >&5
  67421. +
  67422. +#
  67423. +# INIT-COMMANDS
  67424. +#
  67425. +srcdir=.
  67426. +host=nds32le-unknown-linux-gnu
  67427. +target=
  67428. +with_target_subdir=
  67429. +with_multisubdir=
  67430. +ac_configure_args="--enable-multilib '--host=nds32le-linux' '--prefix=/home/users/kito/toolchain/nds32le-linux-glibc-v3/nds32le-linux/sysroot/usr' 'CC=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'LD=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc' 'RANLIB=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ranlib' 'AR=/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ar' '--enable-install-libiberty' 'host_alias=nds32le-linux'"
  67431. +CONFIG_SHELL=/bin/sh
  67432. +ORIGINAL_LD_FOR_MULTILIBS="/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc"
  67433. +libiberty_topdir=./..
  67434. +
  67435. +
  67436. +
  67437. +# Handling of arguments.
  67438. +for ac_config_target in $ac_config_targets
  67439. +do
  67440. + case $ac_config_target in
  67441. + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
  67442. + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
  67443. + "testsuite/Makefile") CONFIG_FILES="$CONFIG_FILES testsuite/Makefile" ;;
  67444. + "default") CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;;
  67445. +
  67446. + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
  67447. + esac
  67448. +done
  67449. +
  67450. +
  67451. +# If the user did not use the arguments to specify the items to instantiate,
  67452. +# then the envvar interface is used. Set only those that are not.
  67453. +# We use the long form for the default assignment because of an extremely
  67454. +# bizarre bug on SunOS 4.1.3.
  67455. +if $ac_need_defaults; then
  67456. + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
  67457. + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
  67458. + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
  67459. +fi
  67460. +
  67461. +# Have a temporary directory for convenience. Make it in the build tree
  67462. +# simply because there is no reason against having it here, and in addition,
  67463. +# creating and moving files from /tmp can sometimes cause problems.
  67464. +# Hook for its removal unless debugging.
  67465. +# Note that there is a small window in which the directory will not be cleaned:
  67466. +# after its creation but before its name has been assigned to `$tmp'.
  67467. +$debug ||
  67468. +{
  67469. + tmp=
  67470. + trap 'exit_status=$?
  67471. + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status
  67472. +' 0
  67473. + trap 'as_fn_exit 1' 1 2 13 15
  67474. +}
  67475. +# Create a (secure) tmp directory for tmp files.
  67476. +
  67477. +{
  67478. + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
  67479. + test -n "$tmp" && test -d "$tmp"
  67480. +} ||
  67481. +{
  67482. + tmp=./conf$$-$RANDOM
  67483. + (umask 077 && mkdir "$tmp")
  67484. +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5
  67485. +
  67486. +# Set up the scripts for CONFIG_FILES section.
  67487. +# No need to generate them if there are no CONFIG_FILES.
  67488. +# This happens for instance with `./config.status config.h'.
  67489. +if test -n "$CONFIG_FILES"; then
  67490. +
  67491. +if $AWK 'BEGIN { getline <"/dev/null" }' </dev/null 2>/dev/null; then
  67492. + ac_cs_awk_getline=:
  67493. + ac_cs_awk_pipe_init=
  67494. + ac_cs_awk_read_file='
  67495. + while ((getline aline < (F[key])) > 0)
  67496. + print(aline)
  67497. + close(F[key])'
  67498. + ac_cs_awk_pipe_fini=
  67499. +else
  67500. + ac_cs_awk_getline=false
  67501. + ac_cs_awk_pipe_init="print \"cat <<'|#_!!_#|' &&\""
  67502. + ac_cs_awk_read_file='
  67503. + print "|#_!!_#|"
  67504. + print "cat " F[key] " &&"
  67505. + '$ac_cs_awk_pipe_init
  67506. + # The final `:' finishes the AND list.
  67507. + ac_cs_awk_pipe_fini='END { print "|#_!!_#|"; print ":" }'
  67508. +fi
  67509. +ac_cr=`echo X | tr X '\015'`
  67510. +# On cygwin, bash can eat \r inside `` if the user requested igncr.
  67511. +# But we know of no other shell where ac_cr would be empty at this
  67512. +# point, so we can use a bashism as a fallback.
  67513. +if test "x$ac_cr" = x; then
  67514. + eval ac_cr=\$\'\\r\'
  67515. +fi
  67516. +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
  67517. +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
  67518. + ac_cs_awk_cr='\r'
  67519. +else
  67520. + ac_cs_awk_cr=$ac_cr
  67521. +fi
  67522. +
  67523. +echo 'BEGIN {' >"$tmp/subs1.awk" &&
  67524. +cat >>"$tmp/subs1.awk" <<\_ACAWK &&
  67525. +F["host_makefile_frag"]="xhost-mkfrag"
  67526. +_ACAWK
  67527. +cat >>"$tmp/subs1.awk" <<\_ACAWK &&
  67528. +S["LTLIBOBJS"]=" ${LIBOBJDIR}./setproctitle$U.lo"
  67529. +S["INSTALL_DEST"]="libdir"
  67530. +S["pexecute"]="pex-unix"
  67531. +S["target_header_dir"]="libiberty"
  67532. +S["CHECK"]="really-check"
  67533. +S["LIBOBJS"]=" ${LIBOBJDIR}./setproctitle$U.o"
  67534. +S["PICFLAG"]=""
  67535. +S["INSTALL_DATA"]="${INSTALL} -m 644"
  67536. +S["INSTALL_SCRIPT"]="${INSTALL}"
  67537. +S["INSTALL_PROGRAM"]="${INSTALL}"
  67538. +S["EGREP"]="/usr/bin/grep -E"
  67539. +S["GREP"]="/usr/bin/grep"
  67540. +S["OUTPUT_OPTION"]="-o $@"
  67541. +S["NO_MINUS_C_MINUS_O"]=""
  67542. +S["ac_libiberty_warn_cflags"]="-W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic "
  67543. +S["CPP"]="/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc -E"
  67544. +S["OBJEXT"]="o"
  67545. +S["EXEEXT"]=""
  67546. +S["ac_ct_CC"]=""
  67547. +S["CPPFLAGS"]=""
  67548. +S["LDFLAGS"]=""
  67549. +S["CFLAGS"]="-g -O2"
  67550. +S["CC"]="/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc"
  67551. +S["RANLIB"]="/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ranlib"
  67552. +S["AR"]="/home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ar"
  67553. +S["host_os"]="linux-gnu"
  67554. +S["host_vendor"]="unknown"
  67555. +S["host_cpu"]="nds32le"
  67556. +S["host"]="nds32le-unknown-linux-gnu"
  67557. +S["build_os"]="linux-gnu"
  67558. +S["build_vendor"]="unknown"
  67559. +S["build_cpu"]="x86_64"
  67560. +S["build"]="x86_64-unknown-linux-gnu"
  67561. +S["HAVE_PERL"]=""
  67562. +S["PERL"]="perl"
  67563. +S["BUILD_INFO"]="info"
  67564. +S["MAKEINFO"]="makeinfo"
  67565. +S["NOTMAINT"]=""
  67566. +S["MAINT"]="#"
  67567. +S["libiberty_topdir"]="./.."
  67568. +S["target_alias"]=""
  67569. +S["host_alias"]="nds32le-linux"
  67570. +S["build_alias"]=""
  67571. +S["LIBS"]=""
  67572. +S["ECHO_T"]=""
  67573. +S["ECHO_N"]="-n"
  67574. +S["ECHO_C"]=""
  67575. +S["DEFS"]="-DHAVE_CONFIG_H"
  67576. +S["mandir"]="${datarootdir}/man"
  67577. +S["localedir"]="${datarootdir}/locale"
  67578. +S["libdir"]="${exec_prefix}/lib"
  67579. +S["psdir"]="${docdir}"
  67580. +S["pdfdir"]="${docdir}"
  67581. +S["dvidir"]="${docdir}"
  67582. +S["htmldir"]="${docdir}"
  67583. +S["infodir"]="${datarootdir}/info"
  67584. +S["docdir"]="${datarootdir}/doc/${PACKAGE}"
  67585. +S["oldincludedir"]="/usr/include"
  67586. +S["includedir"]="${prefix}/include"
  67587. +S["localstatedir"]="${prefix}/var"
  67588. +S["sharedstatedir"]="${prefix}/com"
  67589. +S["sysconfdir"]="${prefix}/etc"
  67590. +S["datadir"]="${datarootdir}"
  67591. +S["datarootdir"]="${prefix}/share"
  67592. +S["libexecdir"]="${exec_prefix}/libexec"
  67593. +S["sbindir"]="${exec_prefix}/sbin"
  67594. +S["bindir"]="${exec_prefix}/bin"
  67595. +S["program_transform_name"]="s,x,x,"
  67596. +S["prefix"]="/home/users/kito/toolchain/nds32le-linux-glibc-v3/nds32le-linux/sysroot/usr"
  67597. +S["exec_prefix"]="${prefix}"
  67598. +S["PACKAGE_URL"]=""
  67599. +S["PACKAGE_BUGREPORT"]=""
  67600. +S["PACKAGE_STRING"]=""
  67601. +S["PACKAGE_VERSION"]=""
  67602. +S["PACKAGE_TARNAME"]=""
  67603. +S["PACKAGE_NAME"]=""
  67604. +S["PATH_SEPARATOR"]=":"
  67605. +S["SHELL"]="/bin/sh"
  67606. +_ACAWK
  67607. +cat >>"$tmp/subs1.awk" <<_ACAWK &&
  67608. + for (key in S) S_is_set[key] = 1
  67609. + FS = ""
  67610. + $ac_cs_awk_pipe_init
  67611. +}
  67612. +{
  67613. + line = $ 0
  67614. + nfields = split(line, field, "@")
  67615. + substed = 0
  67616. + len = length(field[1])
  67617. + for (i = 2; i < nfields; i++) {
  67618. + key = field[i]
  67619. + keylen = length(key)
  67620. + if (S_is_set[key]) {
  67621. + value = S[key]
  67622. + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
  67623. + len += length(value) + length(field[++i])
  67624. + substed = 1
  67625. + } else
  67626. + len += 1 + keylen
  67627. + }
  67628. + if (nfields == 3 && !substed) {
  67629. + key = field[2]
  67630. + if (F[key] != "" && line ~ /^[ ]*@.*@[ ]*$/) {
  67631. + $ac_cs_awk_read_file
  67632. + next
  67633. + }
  67634. + }
  67635. + print line
  67636. +}
  67637. +$ac_cs_awk_pipe_fini
  67638. +_ACAWK
  67639. +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
  67640. + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
  67641. +else
  67642. + cat
  67643. +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \
  67644. + || as_fn_error "could not setup config files machinery" "$LINENO" 5
  67645. +fi # test -n "$CONFIG_FILES"
  67646. +
  67647. +# Set up the scripts for CONFIG_HEADERS section.
  67648. +# No need to generate them if there are no CONFIG_HEADERS.
  67649. +# This happens for instance with `./config.status Makefile'.
  67650. +if test -n "$CONFIG_HEADERS"; then
  67651. +cat >"$tmp/defines.awk" <<\_ACAWK ||
  67652. +BEGIN {
  67653. +D["PACKAGE_NAME"]=" \"\""
  67654. +D["PACKAGE_TARNAME"]=" \"\""
  67655. +D["PACKAGE_VERSION"]=" \"\""
  67656. +D["PACKAGE_STRING"]=" \"\""
  67657. +D["PACKAGE_BUGREPORT"]=" \"\""
  67658. +D["PACKAGE_URL"]=" \"\""
  67659. +D["_FILE_OFFSET_BITS"]=" 64"
  67660. +D["STDC_HEADERS"]=" 1"
  67661. +D["HAVE_SYS_TYPES_H"]=" 1"
  67662. +D["HAVE_SYS_STAT_H"]=" 1"
  67663. +D["HAVE_STDLIB_H"]=" 1"
  67664. +D["HAVE_STRING_H"]=" 1"
  67665. +D["HAVE_MEMORY_H"]=" 1"
  67666. +D["HAVE_STRINGS_H"]=" 1"
  67667. +D["HAVE_INTTYPES_H"]=" 1"
  67668. +D["HAVE_STDINT_H"]=" 1"
  67669. +D["HAVE_UNISTD_H"]=" 1"
  67670. +D["HAVE_SYS_FILE_H"]=" 1"
  67671. +D["HAVE_SYS_PARAM_H"]=" 1"
  67672. +D["HAVE_LIMITS_H"]=" 1"
  67673. +D["HAVE_STDLIB_H"]=" 1"
  67674. +D["HAVE_MALLOC_H"]=" 1"
  67675. +D["HAVE_STRING_H"]=" 1"
  67676. +D["HAVE_UNISTD_H"]=" 1"
  67677. +D["HAVE_STRINGS_H"]=" 1"
  67678. +D["HAVE_SYS_TIME_H"]=" 1"
  67679. +D["HAVE_TIME_H"]=" 1"
  67680. +D["HAVE_SYS_RESOURCE_H"]=" 1"
  67681. +D["HAVE_SYS_STAT_H"]=" 1"
  67682. +D["HAVE_SYS_MMAN_H"]=" 1"
  67683. +D["HAVE_FCNTL_H"]=" 1"
  67684. +D["HAVE_ALLOCA_H"]=" 1"
  67685. +D["HAVE_SYS_SYSINFO_H"]=" 1"
  67686. +D["HAVE_SYS_SYSCTL_H"]=" 1"
  67687. +D["HAVE_STDINT_H"]=" 1"
  67688. +D["HAVE_STDIO_EXT_H"]=" 1"
  67689. +D["HAVE_SYS_PRCTL_H"]=" 1"
  67690. +D["HAVE_SYS_WAIT_H"]=" 1"
  67691. +D["TIME_WITH_SYS_TIME"]=" 1"
  67692. +D["SIZEOF_INT"]=" 4"
  67693. +D["UNSIGNED_64BIT_TYPE"]=" uint64_t"
  67694. +D["HAVE_INTPTR_T"]=" 1"
  67695. +D["HAVE_UINTPTR_T"]=" 1"
  67696. +D["HAVE_UINTPTR_T"]=" 1"
  67697. +D["HAVE_ASPRINTF"]=" 1"
  67698. +D["HAVE_ATEXIT"]=" 1"
  67699. +D["HAVE_BASENAME"]=" 1"
  67700. +D["HAVE_BCMP"]=" 1"
  67701. +D["HAVE_BCOPY"]=" 1"
  67702. +D["HAVE_BSEARCH"]=" 1"
  67703. +D["HAVE_BZERO"]=" 1"
  67704. +D["HAVE_CALLOC"]=" 1"
  67705. +D["HAVE_CLOCK"]=" 1"
  67706. +D["HAVE_FFS"]=" 1"
  67707. +D["HAVE_GETCWD"]=" 1"
  67708. +D["HAVE_GETPAGESIZE"]=" 1"
  67709. +D["HAVE_GETTIMEOFDAY"]=" 1"
  67710. +D["HAVE_INDEX"]=" 1"
  67711. +D["HAVE_INSQUE"]=" 1"
  67712. +D["HAVE_MEMCHR"]=" 1"
  67713. +D["HAVE_MEMCMP"]=" 1"
  67714. +D["HAVE_MEMCPY"]=" 1"
  67715. +D["HAVE_MEMMEM"]=" 1"
  67716. +D["HAVE_MEMMOVE"]=" 1"
  67717. +D["HAVE_MEMPCPY"]=" 1"
  67718. +D["HAVE_MEMSET"]=" 1"
  67719. +D["HAVE_MKSTEMPS"]=" 1"
  67720. +D["HAVE_PUTENV"]=" 1"
  67721. +D["HAVE_RANDOM"]=" 1"
  67722. +D["HAVE_RENAME"]=" 1"
  67723. +D["HAVE_RINDEX"]=" 1"
  67724. +D["HAVE_SETENV"]=" 1"
  67725. +D["HAVE_SNPRINTF"]=" 1"
  67726. +D["HAVE_SIGSETMASK"]=" 1"
  67727. +D["HAVE_STPCPY"]=" 1"
  67728. +D["HAVE_STPNCPY"]=" 1"
  67729. +D["HAVE_STRCASECMP"]=" 1"
  67730. +D["HAVE_STRCHR"]=" 1"
  67731. +D["HAVE_STRDUP"]=" 1"
  67732. +D["HAVE_STRNCASECMP"]=" 1"
  67733. +D["HAVE_STRNDUP"]=" 1"
  67734. +D["HAVE_STRNLEN"]=" 1"
  67735. +D["HAVE_STRRCHR"]=" 1"
  67736. +D["HAVE_STRSTR"]=" 1"
  67737. +D["HAVE_STRTOD"]=" 1"
  67738. +D["HAVE_STRTOL"]=" 1"
  67739. +D["HAVE_STRTOUL"]=" 1"
  67740. +D["HAVE_STRVERSCMP"]=" 1"
  67741. +D["HAVE_TMPNAM"]=" 1"
  67742. +D["HAVE_VASPRINTF"]=" 1"
  67743. +D["HAVE_VFPRINTF"]=" 1"
  67744. +D["HAVE_VPRINTF"]=" 1"
  67745. +D["HAVE_VSNPRINTF"]=" 1"
  67746. +D["HAVE_VSPRINTF"]=" 1"
  67747. +D["HAVE_WAITPID"]=" 1"
  67748. +D["STACK_DIRECTION"]=" 0"
  67749. +D["HAVE_FORK"]=" 1"
  67750. +D["HAVE_VFORK"]=" 1"
  67751. +D["HAVE_WORKING_VFORK"]=" 1"
  67752. +D["HAVE_WORKING_FORK"]=" 1"
  67753. +D["HAVE_SYS_ERRLIST"]=" 1"
  67754. +D["HAVE_SYS_NERR"]=" 1"
  67755. +D["HAVE_SYS_SIGLIST"]=" 1"
  67756. +D["HAVE___FSETLOCKING"]=" 1"
  67757. +D["HAVE_CANONICALIZE_FILE_NAME"]=" 1"
  67758. +D["HAVE_DUP3"]=" 1"
  67759. +D["HAVE_GETRLIMIT"]=" 1"
  67760. +D["HAVE_GETRUSAGE"]=" 1"
  67761. +D["HAVE_GETTIMEOFDAY"]=" 1"
  67762. +D["HAVE_ON_EXIT"]=" 1"
  67763. +D["HAVE_PSIGNAL"]=" 1"
  67764. +D["HAVE_REALPATH"]=" 1"
  67765. +D["HAVE_SETRLIMIT"]=" 1"
  67766. +D["HAVE_SBRK"]=" 1"
  67767. +D["HAVE_STRERROR"]=" 1"
  67768. +D["HAVE_STRSIGNAL"]=" 1"
  67769. +D["HAVE_SYSCONF"]=" 1"
  67770. +D["HAVE_SYSCTL"]=" 1"
  67771. +D["HAVE_TIMES"]=" 1"
  67772. +D["HAVE_WAIT3"]=" 1"
  67773. +D["HAVE_WAIT4"]=" 1"
  67774. +D["HAVE_DECL_BASENAME"]=" 0"
  67775. +D["HAVE_DECL_FFS"]=" 1"
  67776. +D["HAVE_DECL_ASPRINTF"]=" 0"
  67777. +D["HAVE_DECL_VASPRINTF"]=" 0"
  67778. +D["HAVE_DECL_SNPRINTF"]=" 1"
  67779. +D["HAVE_DECL_VSNPRINTF"]=" 1"
  67780. +D["HAVE_DECL_CALLOC"]=" 1"
  67781. +D["HAVE_DECL_GETENV"]=" 1"
  67782. +D["HAVE_DECL_GETOPT"]=" 1"
  67783. +D["HAVE_DECL_MALLOC"]=" 1"
  67784. +D["HAVE_DECL_REALLOC"]=" 1"
  67785. +D["HAVE_DECL_SBRK"]=" 1"
  67786. +D["HAVE_DECL_STRVERSCMP"]=" 0"
  67787. +D["NEED_DECLARATION_CANONICALIZE_FILE_NAME"]=" 1"
  67788. +D["HAVE_STDLIB_H"]=" 1"
  67789. +D["HAVE_UNISTD_H"]=" 1"
  67790. +D["HAVE_GETPAGESIZE"]=" 1"
  67791. + for (key in D) D_is_set[key] = 1
  67792. + FS = ""
  67793. +}
  67794. +/^[\t ]*#[\t ]*(define|undef)[\t ]+[_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ][_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789]*([\t (]|$)/ {
  67795. + line = $ 0
  67796. + split(line, arg, " ")
  67797. + if (arg[1] == "#") {
  67798. + defundef = arg[2]
  67799. + mac1 = arg[3]
  67800. + } else {
  67801. + defundef = substr(arg[1], 2)
  67802. + mac1 = arg[2]
  67803. + }
  67804. + split(mac1, mac2, "(") #)
  67805. + macro = mac2[1]
  67806. + prefix = substr(line, 1, index(line, defundef) - 1)
  67807. + if (D_is_set[macro]) {
  67808. + # Preserve the white space surrounding the "#".
  67809. + print prefix "define", macro P[macro] D[macro]
  67810. + next
  67811. + } else {
  67812. + # Replace #undef with comments. This is necessary, for example,
  67813. + # in the case of _POSIX_SOURCE, which is predefined and required
  67814. + # on some systems where configure will not decide to define it.
  67815. + if (defundef == "undef") {
  67816. + print "/*", prefix defundef, macro, "*/"
  67817. + next
  67818. + }
  67819. + }
  67820. +}
  67821. +{ print }
  67822. +_ACAWK
  67823. + as_fn_error "could not setup config headers machinery" "$LINENO" 5
  67824. +fi # test -n "$CONFIG_HEADERS"
  67825. +
  67826. +
  67827. +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS"
  67828. +shift
  67829. +for ac_tag
  67830. +do
  67831. + case $ac_tag in
  67832. + :[FHLC]) ac_mode=$ac_tag; continue;;
  67833. + esac
  67834. + case $ac_mode$ac_tag in
  67835. + :[FHL]*:*);;
  67836. + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;;
  67837. + :[FH]-) ac_tag=-:-;;
  67838. + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
  67839. + esac
  67840. + ac_save_IFS=$IFS
  67841. + IFS=:
  67842. + set x $ac_tag
  67843. + IFS=$ac_save_IFS
  67844. + shift
  67845. + ac_file=$1
  67846. + shift
  67847. +
  67848. + case $ac_mode in
  67849. + :L) ac_source=$1;;
  67850. + :[FH])
  67851. + ac_file_inputs=
  67852. + for ac_f
  67853. + do
  67854. + case $ac_f in
  67855. + -) ac_f="$tmp/stdin";;
  67856. + *) # Look for the file first in the build tree, then in the source tree
  67857. + # (if the path is not absolute). The absolute path cannot be DOS-style,
  67858. + # because $ac_f cannot contain `:'.
  67859. + test -f "$ac_f" ||
  67860. + case $ac_f in
  67861. + [\\/$]*) false;;
  67862. + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
  67863. + esac ||
  67864. + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;;
  67865. + esac
  67866. + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
  67867. + as_fn_append ac_file_inputs " '$ac_f'"
  67868. + done
  67869. +
  67870. + # Let's still pretend it is `configure' which instantiates (i.e., don't
  67871. + # use $as_me), people would be surprised to read:
  67872. + # /* config.h. Generated by config.status. */
  67873. + configure_input='Generated from '`
  67874. + $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
  67875. + `' by configure.'
  67876. + if test x"$ac_file" != x-; then
  67877. + configure_input="$ac_file. $configure_input"
  67878. + { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
  67879. +$as_echo "$as_me: creating $ac_file" >&6;}
  67880. + fi
  67881. + # Neutralize special characters interpreted by sed in replacement strings.
  67882. + case $configure_input in #(
  67883. + *\&* | *\|* | *\\* )
  67884. + ac_sed_conf_input=`$as_echo "$configure_input" |
  67885. + sed 's/[\\\\&|]/\\\\&/g'`;; #(
  67886. + *) ac_sed_conf_input=$configure_input;;
  67887. + esac
  67888. +
  67889. + case $ac_tag in
  67890. + *:-:* | *:-) cat >"$tmp/stdin" \
  67891. + || as_fn_error "could not create $ac_file" "$LINENO" 5 ;;
  67892. + esac
  67893. + ;;
  67894. + esac
  67895. +
  67896. + ac_dir=`$as_dirname -- "$ac_file" ||
  67897. +$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
  67898. + X"$ac_file" : 'X\(//\)[^/]' \| \
  67899. + X"$ac_file" : 'X\(//\)$' \| \
  67900. + X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
  67901. +$as_echo X"$ac_file" |
  67902. + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
  67903. + s//\1/
  67904. + q
  67905. + }
  67906. + /^X\(\/\/\)[^/].*/{
  67907. + s//\1/
  67908. + q
  67909. + }
  67910. + /^X\(\/\/\)$/{
  67911. + s//\1/
  67912. + q
  67913. + }
  67914. + /^X\(\/\).*/{
  67915. + s//\1/
  67916. + q
  67917. + }
  67918. + s/.*/./; q'`
  67919. + as_dir="$ac_dir"; as_fn_mkdir_p
  67920. + ac_builddir=.
  67921. +
  67922. +case "$ac_dir" in
  67923. +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
  67924. +*)
  67925. + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
  67926. + # A ".." for each directory in $ac_dir_suffix.
  67927. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
  67928. + case $ac_top_builddir_sub in
  67929. + "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
  67930. + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;;
  67931. + esac ;;
  67932. +esac
  67933. +ac_abs_top_builddir=$ac_pwd
  67934. +ac_abs_builddir=$ac_pwd$ac_dir_suffix
  67935. +# for backward compatibility:
  67936. +ac_top_builddir=$ac_top_build_prefix
  67937. +
  67938. +case $srcdir in
  67939. + .) # We are building in place.
  67940. + ac_srcdir=.
  67941. + ac_top_srcdir=$ac_top_builddir_sub
  67942. + ac_abs_top_srcdir=$ac_pwd ;;
  67943. + [\\/]* | ?:[\\/]* ) # Absolute name.
  67944. + ac_srcdir=$srcdir$ac_dir_suffix;
  67945. + ac_top_srcdir=$srcdir
  67946. + ac_abs_top_srcdir=$srcdir ;;
  67947. + *) # Relative name.
  67948. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
  67949. + ac_top_srcdir=$ac_top_build_prefix$srcdir
  67950. + ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
  67951. +esac
  67952. +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
  67953. +
  67954. +
  67955. + case $ac_mode in
  67956. + :F)
  67957. + #
  67958. + # CONFIG_FILE
  67959. + #
  67960. +
  67961. + case $INSTALL in
  67962. + [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
  67963. + *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
  67964. + esac
  67965. +# If the template does not know about datarootdir, expand it.
  67966. +# FIXME: This hack should be removed a few years after 2.60.
  67967. +ac_datarootdir_hack=; ac_datarootdir_seen=
  67968. +ac_sed_dataroot='
  67969. +/datarootdir/ {
  67970. + p
  67971. + q
  67972. +}
  67973. +/@datadir@/p
  67974. +/@docdir@/p
  67975. +/@infodir@/p
  67976. +/@localedir@/p
  67977. +/@mandir@/p'
  67978. +case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
  67979. +*datarootdir*) ac_datarootdir_seen=yes;;
  67980. +*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
  67981. + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
  67982. +$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
  67983. + ac_datarootdir_hack='
  67984. + s&@datadir@&${datarootdir}&g
  67985. + s&@docdir@&${datarootdir}/doc/${PACKAGE}&g
  67986. + s&@infodir@&${datarootdir}/info&g
  67987. + s&@localedir@&${datarootdir}/locale&g
  67988. + s&@mandir@&${datarootdir}/man&g
  67989. + s&\${datarootdir}&${prefix}/share&g' ;;
  67990. +esac
  67991. +ac_sed_extra="/^[ ]*VPATH[ ]*=/{
  67992. +s/:*\$(srcdir):*/:/
  67993. +s/:*\${srcdir}:*/:/
  67994. +s/:*@srcdir@:*/:/
  67995. +s/^\([^=]*=[ ]*\):*/\1/
  67996. +s/:*$//
  67997. +s/^[^=]*=[ ]*$//
  67998. +}
  67999. +
  68000. +:t
  68001. +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
  68002. +s|@configure_input@|$ac_sed_conf_input|;t t
  68003. +s&@top_builddir@&$ac_top_builddir_sub&;t t
  68004. +s&@top_build_prefix@&$ac_top_build_prefix&;t t
  68005. +s&@srcdir@&$ac_srcdir&;t t
  68006. +s&@abs_srcdir@&$ac_abs_srcdir&;t t
  68007. +s&@top_srcdir@&$ac_top_srcdir&;t t
  68008. +s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
  68009. +s&@builddir@&$ac_builddir&;t t
  68010. +s&@abs_builddir@&$ac_abs_builddir&;t t
  68011. +s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
  68012. +s&@INSTALL@&$ac_INSTALL&;t t
  68013. +$ac_datarootdir_hack
  68014. +"
  68015. +eval sed \"\$ac_sed_extra\" "$ac_file_inputs" |
  68016. +if $ac_cs_awk_getline; then
  68017. + $AWK -f "$tmp/subs.awk"
  68018. +else
  68019. + $AWK -f "$tmp/subs.awk" | $SHELL
  68020. +fi >$tmp/out \
  68021. + || as_fn_error "could not create $ac_file" "$LINENO" 5
  68022. +
  68023. +test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
  68024. + { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
  68025. + { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
  68026. + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
  68027. +which seems to be undefined. Please make sure it is defined." >&5
  68028. +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
  68029. +which seems to be undefined. Please make sure it is defined." >&2;}
  68030. +
  68031. + rm -f "$tmp/stdin"
  68032. + case $ac_file in
  68033. + -) cat "$tmp/out" && rm -f "$tmp/out";;
  68034. + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";;
  68035. + esac \
  68036. + || as_fn_error "could not create $ac_file" "$LINENO" 5
  68037. + ;;
  68038. + :H)
  68039. + #
  68040. + # CONFIG_HEADER
  68041. + #
  68042. + if test x"$ac_file" != x-; then
  68043. + {
  68044. + $as_echo "/* $configure_input */" \
  68045. + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
  68046. + } >"$tmp/config.h" \
  68047. + || as_fn_error "could not create $ac_file" "$LINENO" 5
  68048. + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
  68049. + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
  68050. +$as_echo "$as_me: $ac_file is unchanged" >&6;}
  68051. + else
  68052. + rm -f "$ac_file"
  68053. + mv "$tmp/config.h" "$ac_file" \
  68054. + || as_fn_error "could not create $ac_file" "$LINENO" 5
  68055. + fi
  68056. + else
  68057. + $as_echo "/* $configure_input */" \
  68058. + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \
  68059. + || as_fn_error "could not create -" "$LINENO" 5
  68060. + fi
  68061. + ;;
  68062. +
  68063. + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5
  68064. +$as_echo "$as_me: executing $ac_file commands" >&6;}
  68065. + ;;
  68066. + esac
  68067. +
  68068. +
  68069. + case $ac_file$ac_mode in
  68070. + "default":C) test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h
  68071. +if test -n "$CONFIG_FILES"; then
  68072. + if test -n "${with_target_subdir}"; then
  68073. + # FIXME: We shouldn't need to set ac_file
  68074. + ac_file=Makefile
  68075. + LD="${ORIGINAL_LD_FOR_MULTILIBS}"
  68076. + . ${libiberty_topdir}/config-ml.in
  68077. + fi
  68078. +fi ;;
  68079. +
  68080. + esac
  68081. +done # for ac_tag
  68082. +
  68083. +
  68084. +as_fn_exit 0
  68085. diff -Nur gcc-4.9.4.orig/libiberty/Makefile gcc-4.9.4/libiberty/Makefile
  68086. --- gcc-4.9.4.orig/libiberty/Makefile 1970-01-01 01:00:00.000000000 +0100
  68087. +++ gcc-4.9.4/libiberty/Makefile 2016-08-08 20:37:53.866593761 +0200
  68088. @@ -0,0 +1,1282 @@
  68089. +# Makefile for the libiberty library.
  68090. +# Originally written by K. Richard Pixley <rich@cygnus.com>.
  68091. +#
  68092. +# Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
  68093. +# 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
  68094. +# Free Software Foundation
  68095. +#
  68096. +# This file is part of the libiberty library.
  68097. +# Libiberty is free software; you can redistribute it and/or
  68098. +# modify it under the terms of the GNU Library General Public
  68099. +# License as published by the Free Software Foundation; either
  68100. +# version 2 of the License, or (at your option) any later version.
  68101. +#
  68102. +# Libiberty is distributed in the hope that it will be useful,
  68103. +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  68104. +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  68105. +# Library General Public License for more details.
  68106. +#
  68107. +# You should have received a copy of the GNU Library General Public
  68108. +# License along with libiberty; see the file COPYING.LIB. If not,
  68109. +# write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
  68110. +# Boston, MA 02110-1301, USA.
  68111. +
  68112. +libiberty_topdir = ./..
  68113. +srcdir = .
  68114. +
  68115. +prefix = /home/users/kito/toolchain/nds32le-linux-glibc-v3/nds32le-linux/sysroot/usr
  68116. +
  68117. +exec_prefix = ${prefix}
  68118. +bindir = ${exec_prefix}/bin
  68119. +libdir = ${exec_prefix}/lib
  68120. +includedir = ${prefix}/include
  68121. +target_header_dir = libiberty
  68122. +objext = o
  68123. +
  68124. +SHELL = /bin/sh
  68125. +
  68126. +# Multilib support variables.
  68127. +MULTISRCTOP =
  68128. +MULTIBUILDTOP =
  68129. +MULTIDIRS =
  68130. +MULTISUBDIR =
  68131. +MULTIDO = true
  68132. +MULTICLEAN = true
  68133. +
  68134. +INSTALL = /usr/bin/install -c
  68135. +INSTALL_PROGRAM = ${INSTALL}
  68136. +INSTALL_DATA = ${INSTALL} -m 644
  68137. +mkinstalldirs = $(SHELL) $(libiberty_topdir)/mkinstalldirs
  68138. +
  68139. +# Some compilers can't handle cc -c blah.c -o foo/blah.o.
  68140. +OUTPUT_OPTION = -o $@
  68141. +
  68142. +AR = /home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ar
  68143. +AR_FLAGS = rc
  68144. +
  68145. +CC = /home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc
  68146. +CFLAGS = -g -O2
  68147. +CPPFLAGS =
  68148. +RANLIB = /home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-ranlib
  68149. +MAKEINFO = makeinfo
  68150. +PERL = perl
  68151. +
  68152. +PICFLAG =
  68153. +
  68154. +MAKEOVERRIDES =
  68155. +
  68156. +TARGETLIB = ./libiberty.a
  68157. +TESTLIB = ./testlib.a
  68158. +
  68159. +LIBOBJS = ${LIBOBJDIR}./setproctitle$U.o
  68160. +
  68161. +# A configuration can specify extra .o files that should be included,
  68162. +# even if they are in libc. (Perhaps the libc version is buggy.)
  68163. +EXTRA_OFILES =
  68164. +
  68165. +# Flags to pass to a recursive make.
  68166. +FLAGS_TO_PASS = \
  68167. + "AR=$(AR)" \
  68168. + "AR_FLAGS=$(AR_FLAGS)" \
  68169. + "CC=$(CC)" \
  68170. + "CFLAGS=$(CFLAGS)" \
  68171. + "CPPFLAGS=$(CPPFLAGS)" \
  68172. + "DESTDIR=$(DESTDIR)" \
  68173. + "EXTRA_OFILES=$(EXTRA_OFILES)" \
  68174. + "HDEFINES=$(HDEFINES)" \
  68175. + "INSTALL=$(INSTALL)" \
  68176. + "INSTALL_DATA=$(INSTALL_DATA)" \
  68177. + "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \
  68178. + "LDFLAGS=$(LDFLAGS)" \
  68179. + "LOADLIBES=$(LOADLIBES)" \
  68180. + "RANLIB=$(RANLIB)" \
  68181. + "SHELL=$(SHELL)" \
  68182. + "prefix=$(prefix)" \
  68183. + "exec_prefix=$(exec_prefix)" \
  68184. + "libdir=$(libdir)" \
  68185. + "libsubdir=$(libsubdir)" \
  68186. + "tooldir=$(tooldir)"
  68187. +
  68188. +# Subdirectories to recurse into. We need to override this during cleaning
  68189. +SUBDIRS = testsuite
  68190. +
  68191. +# FIXME: add info once we're sure it works for everyone.
  68192. +all: stamp-picdir $(TARGETLIB) required-list all-subdir
  68193. + @: $(MAKE) ; $(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=all
  68194. +
  68195. +.PHONY: check installcheck
  68196. +check: check-subdir
  68197. +installcheck: installcheck-subdir
  68198. +
  68199. +# Warning: this fragment is automatically generated
  68200. +enable_shared = no
  68201. +
  68202. +INCDIR=$(srcdir)/$(MULTISRCTOP)../include
  68203. +
  68204. +COMPILE.c = $(CC) -c -DHAVE_CONFIG_H $(CFLAGS) $(CPPFLAGS) -I. -I$(INCDIR) $(HDEFINES) -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic
  68205. +
  68206. +# Just to make sure we don't use a built-in rule with VPATH
  68207. +.c.$(objext):
  68208. + false
  68209. +
  68210. +# NOTE: If you add new files to the library, add them to this list
  68211. +# (alphabetical), and add them to REQUIRED_OFILES, or
  68212. +# CONFIGURED_OFILES and funcs in configure.ac. Also run "make maint-deps"
  68213. +# to build the new rules.
  68214. +CFILES = alloca.c argv.c asprintf.c atexit.c \
  68215. + basename.c bcmp.c bcopy.c bsearch.c bzero.c \
  68216. + calloc.c choose-temp.c clock.c concat.c cp-demangle.c \
  68217. + cp-demint.c cplus-dem.c crc32.c \
  68218. + dwarfnames.c dyn-string.c \
  68219. + fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \
  68220. + fnmatch.c fopen_unlocked.c \
  68221. + getcwd.c getopt.c getopt1.c getpagesize.c getpwd.c getruntime.c \
  68222. + gettimeofday.c \
  68223. + hashtab.c hex.c \
  68224. + index.c insque.c \
  68225. + lbasename.c \
  68226. + lrealpath.c \
  68227. + make-relative-prefix.c \
  68228. + make-temp-file.c md5.c memchr.c memcmp.c memcpy.c memmem.c \
  68229. + memmove.c mempcpy.c memset.c mkstemps.c \
  68230. + objalloc.c obstack.c \
  68231. + partition.c pexecute.c \
  68232. + pex-common.c pex-djgpp.c pex-msdos.c pex-one.c \
  68233. + pex-unix.c pex-win32.c \
  68234. + physmem.c putenv.c \
  68235. + random.c regex.c rename.c rindex.c \
  68236. + safe-ctype.c setenv.c setproctitle.c sha1.c sigsetmask.c \
  68237. + simple-object.c simple-object-coff.c simple-object-elf.c \
  68238. + simple-object-mach-o.c simple-object-xcoff.c \
  68239. + snprintf.c sort.c \
  68240. + spaces.c splay-tree.c stack-limit.c stpcpy.c stpncpy.c \
  68241. + strcasecmp.c strchr.c strdup.c strerror.c strncasecmp.c \
  68242. + strncmp.c strrchr.c strsignal.c strstr.c strtod.c strtol.c \
  68243. + strtoul.c strndup.c strnlen.c strverscmp.c \
  68244. + timeval-utils.c tmpnam.c \
  68245. + unlink-if-ordinary.c \
  68246. + vasprintf.c vfork.c vfprintf.c vprintf.c vsnprintf.c vsprintf.c \
  68247. + waitpid.c \
  68248. + xatexit.c xexit.c xmalloc.c xmemdup.c xstrdup.c xstrerror.c \
  68249. + xstrndup.c
  68250. +
  68251. +# These are always included in the library. The first four are listed
  68252. +# first and by compile time to optimize parallel builds.
  68253. +REQUIRED_OFILES = \
  68254. + ./regex.$(objext) ./cplus-dem.$(objext) ./cp-demangle.$(objext) \
  68255. + ./md5.$(objext) ./sha1.$(objext) ./alloca.$(objext) \
  68256. + ./argv.$(objext) \
  68257. + ./choose-temp.$(objext) ./concat.$(objext) \
  68258. + ./cp-demint.$(objext) ./crc32.$(objext) \
  68259. + ./dwarfnames.$(objext) ./dyn-string.$(objext) \
  68260. + ./fdmatch.$(objext) ./fibheap.$(objext) \
  68261. + ./filename_cmp.$(objext) ./floatformat.$(objext) \
  68262. + ./fnmatch.$(objext) ./fopen_unlocked.$(objext) \
  68263. + ./getopt.$(objext) ./getopt1.$(objext) ./getpwd.$(objext) \
  68264. + ./getruntime.$(objext) ./hashtab.$(objext) ./hex.$(objext) \
  68265. + ./lbasename.$(objext) ./lrealpath.$(objext) \
  68266. + ./make-relative-prefix.$(objext) ./make-temp-file.$(objext) \
  68267. + ./objalloc.$(objext) \
  68268. + ./obstack.$(objext) \
  68269. + ./partition.$(objext) ./pexecute.$(objext) ./physmem.$(objext) \
  68270. + ./pex-common.$(objext) ./pex-one.$(objext) \
  68271. + ./pex-unix.$(objext) \
  68272. + ./safe-ctype.$(objext) \
  68273. + ./simple-object.$(objext) ./simple-object-coff.$(objext) \
  68274. + ./simple-object-elf.$(objext) ./simple-object-mach-o.$(objext) \
  68275. + ./simple-object-xcoff.$(objext) \
  68276. + ./sort.$(objext) ./spaces.$(objext) \
  68277. + ./splay-tree.$(objext) ./stack-limit.$(objext) \
  68278. + ./strerror.$(objext) ./strsignal.$(objext) \
  68279. + ./timeval-utils.$(objext) ./unlink-if-ordinary.$(objext) \
  68280. + ./xatexit.$(objext) ./xexit.$(objext) ./xmalloc.$(objext) \
  68281. + ./xmemdup.$(objext) ./xstrdup.$(objext) ./xstrerror.$(objext) \
  68282. + ./xstrndup.$(objext)
  68283. +
  68284. +# These are all the objects that configure may add to the library via
  68285. +# $funcs or EXTRA_OFILES. This list exists here only for "make
  68286. +# maint-missing" and "make check".
  68287. +CONFIGURED_OFILES = ./asprintf.$(objext) ./atexit.$(objext) \
  68288. + ./basename.$(objext) ./bcmp.$(objext) ./bcopy.$(objext) \
  68289. + ./bsearch.$(objext) ./bzero.$(objext) \
  68290. + ./calloc.$(objext) ./clock.$(objext) ./copysign.$(objext) \
  68291. + ./_doprnt.$(objext) \
  68292. + ./ffs.$(objext) \
  68293. + ./getcwd.$(objext) ./getpagesize.$(objext) \
  68294. + ./gettimeofday.$(objext) \
  68295. + ./index.$(objext) ./insque.$(objext) \
  68296. + ./memchr.$(objext) ./memcmp.$(objext) ./memcpy.$(objext) \
  68297. + ./memmem.$(objext) ./memmove.$(objext) \
  68298. + ./mempcpy.$(objext) ./memset.$(objext) ./mkstemps.$(objext) \
  68299. + ./pex-djgpp.$(objext) ./pex-msdos.$(objext) \
  68300. + ./pex-unix.$(objext) ./pex-win32.$(objext) \
  68301. + ./putenv.$(objext) \
  68302. + ./random.$(objext) ./rename.$(objext) ./rindex.$(objext) \
  68303. + ./setenv.$(objext) \
  68304. + ./setproctitle.$(objext) \
  68305. + ./sigsetmask.$(objext) ./snprintf.$(objext) \
  68306. + ./stpcpy.$(objext) ./stpncpy.$(objext) ./strcasecmp.$(objext) \
  68307. + ./strchr.$(objext) ./strdup.$(objext) ./strncasecmp.$(objext) \
  68308. + ./strncmp.$(objext) ./strndup.$(objext) ./strnlen.$(objext) \
  68309. + ./strrchr.$(objext) ./strstr.$(objext) ./strtod.$(objext) \
  68310. + ./strtol.$(objext) ./strtoul.$(objext) ./strverscmp.$(objext) \
  68311. + ./tmpnam.$(objext) \
  68312. + ./vasprintf.$(objext) ./vfork.$(objext) ./vfprintf.$(objext) \
  68313. + ./vprintf.$(objext) ./vsnprintf.$(objext) ./vsprintf.$(objext) \
  68314. + ./waitpid.$(objext)
  68315. +
  68316. +# These files are installed if the library has been configured to do so.
  68317. +INSTALLED_HEADERS = \
  68318. + $(INCDIR)/ansidecl.h \
  68319. + $(INCDIR)/demangle.h \
  68320. + $(INCDIR)/dyn-string.h \
  68321. + $(INCDIR)/fibheap.h \
  68322. + $(INCDIR)/floatformat.h \
  68323. + $(INCDIR)/hashtab.h \
  68324. + $(INCDIR)/libiberty.h \
  68325. + $(INCDIR)/objalloc.h \
  68326. + $(INCDIR)/partition.h \
  68327. + $(INCDIR)/safe-ctype.h \
  68328. + $(INCDIR)/sort.h \
  68329. + $(INCDIR)/splay-tree.h \
  68330. + $(INCDIR)/timeval-utils.h
  68331. +
  68332. +$(TARGETLIB): $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS)
  68333. + -rm -f $(TARGETLIB) pic/$(TARGETLIB)
  68334. + $(AR) $(AR_FLAGS) $(TARGETLIB) \
  68335. + $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS)
  68336. + $(RANLIB) $(TARGETLIB)
  68337. + if [ x"$(PICFLAG)" != x ]; then \
  68338. + cd pic; \
  68339. + $(AR) $(AR_FLAGS) $(TARGETLIB) \
  68340. + $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS); \
  68341. + $(RANLIB) $(TARGETLIB); \
  68342. + cd ..; \
  68343. + else true; fi
  68344. +
  68345. +$(TESTLIB): $(REQUIRED_OFILES) $(CONFIGURED_OFILES)
  68346. + -rm -f $(TESTLIB)
  68347. + $(AR) $(AR_FLAGS) $(TESTLIB) \
  68348. + $(REQUIRED_OFILES) $(CONFIGURED_OFILES)
  68349. + $(RANLIB) $(TESTLIB)
  68350. +
  68351. +info: libiberty.info info-subdir
  68352. +install-info: install-info-subdir
  68353. +clean-info: clean-info-subdir
  68354. +dvi: libiberty.dvi dvi-subdir
  68355. +
  68356. +LIBIBERTY_PDFFILES = libiberty.pdf
  68357. +
  68358. +pdf: $(LIBIBERTY_PDFFILES) pdf-subdir
  68359. +
  68360. +.PHONY: install-pdf
  68361. +
  68362. +pdf__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
  68363. +
  68364. +install-pdf: $(LIBIBERTY_PDFFILES)
  68365. + @$(NORMAL_INSTALL)
  68366. + test -z "$(pdfdir)" || $(mkinstalldirs) "$(DESTDIR)$(pdfdir)"
  68367. + @list='$(LIBIBERTY_PDFFILES)'; for p in $$list; do \
  68368. + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
  68369. + f=$(pdf__strip_dir) \
  68370. + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(pdfdir)/$$f'"; \
  68371. + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(pdfdir)/$$f"; \
  68372. + done
  68373. +
  68374. +# html, install-html targets
  68375. +HTMLS = libiberty.html
  68376. +
  68377. +html: $(HTMLS)
  68378. +
  68379. +.PHONY: install-html install-html-am
  68380. +
  68381. +NORMAL_INSTALL = :
  68382. +mkdir_p = mkdir -p --
  68383. +
  68384. +html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
  68385. +
  68386. +install-html: install-html-am
  68387. +
  68388. +install-html-am: $(HTMLS)
  68389. + @$(NORMAL_INSTALL)
  68390. + test -z "$(htmldir)" || $(mkdir_p) "$(DESTDIR)$(htmldir)"
  68391. + @list='$(HTMLS)'; for p in $$list; do \
  68392. + if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \
  68393. + f=$(html__strip_dir) \
  68394. + if test -d "$$d$$p"; then \
  68395. + echo " $(mkdir_p) '$(DESTDIR)$(htmldir)/$$f'"; \
  68396. + $(mkdir_p) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \
  68397. + echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \
  68398. + $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \
  68399. + else \
  68400. + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \
  68401. + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \
  68402. + fi; \
  68403. + done
  68404. +
  68405. +TEXISRC = \
  68406. + $(srcdir)/libiberty.texi \
  68407. + $(srcdir)/copying-lib.texi \
  68408. + $(srcdir)/obstacks.texi \
  68409. + $(srcdir)/functions.texi
  68410. +
  68411. +# Additional files that have texi snippets that need to be collected
  68412. +# and sorted. Some are here because the sources are imported from
  68413. +# elsewhere. Others represent headers in ../include.
  68414. +TEXIFILES = fnmatch.txh pexecute.txh simple-object.txh
  68415. +
  68416. +libiberty.info : $(srcdir)/libiberty.texi $(TEXISRC)
  68417. + $(MAKEINFO) -I$(srcdir) $(srcdir)/libiberty.texi
  68418. +
  68419. +libiberty.dvi : $(srcdir)/libiberty.texi $(TEXISRC)
  68420. + texi2dvi $(srcdir)/libiberty.texi
  68421. +
  68422. +libiberty.pdf : $(srcdir)/libiberty.texi $(TEXISRC)
  68423. + texi2pdf $(srcdir)/libiberty.texi
  68424. +
  68425. +libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)
  68426. + $(MAKEINFO) --no-split --html -I$(srcdir) -o $@ $<
  68427. +
  68428. +#$(srcdir)/functions.texi : stamp-functions
  68429. +# @true
  68430. +
  68431. +#stamp-functions : $(CFILES:%=$(srcdir)/%) $(TEXIFILES:%=$(srcdir)/%) $(srcdir)/gather-docs Makefile
  68432. +# $(PERL) $(srcdir)/gather-docs $(srcdir) $(srcdir)/functions.texi $(CFILES) $(TEXIFILES)
  68433. +# echo stamp > stamp-functions
  68434. +
  68435. +INSTALL_DEST = libdir
  68436. +install: install_to_$(INSTALL_DEST) install-subdir
  68437. +install-strip: install
  68438. +
  68439. +.PHONY: install install-strip
  68440. +
  68441. +# This is tricky. Even though CC in the Makefile contains
  68442. +# multilib-specific flags, it's overridden by FLAGS_TO_PASS from the
  68443. +# default multilib, so we have to take CFLAGS into account as well,
  68444. +# since it will be passed the multilib flags.
  68445. +MULTIOSDIR = `$(CC) $(CFLAGS) -print-multi-os-directory`
  68446. +install_to_libdir: all
  68447. + if test -n "${target_header_dir}"; then \
  68448. + ${mkinstalldirs} $(DESTDIR)$(libdir)/$(MULTIOSDIR); \
  68449. + $(INSTALL_DATA) $(TARGETLIB) $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB)n; \
  68450. + ( cd $(DESTDIR)$(libdir)/$(MULTIOSDIR) ; chmod 644 $(TARGETLIB)n ;$(RANLIB) $(TARGETLIB)n ); \
  68451. + mv -f $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB)n $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB); \
  68452. + case "${target_header_dir}" in \
  68453. + /*) thd=${target_header_dir};; \
  68454. + *) thd=${includedir}/${target_header_dir};; \
  68455. + esac; \
  68456. + ${mkinstalldirs} $(DESTDIR)$${thd}; \
  68457. + for h in ${INSTALLED_HEADERS}; do \
  68458. + ${INSTALL_DATA} $$h $(DESTDIR)$${thd}; \
  68459. + done; \
  68460. + fi
  68461. + @$(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=install
  68462. +
  68463. +install_to_tooldir: all
  68464. + ${mkinstalldirs} $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)
  68465. + $(INSTALL_DATA) $(TARGETLIB) $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB)n
  68466. + ( cd $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR) ; chmod 644 $(TARGETLIB)n; $(RANLIB) $(TARGETLIB)n )
  68467. + mv -f $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB)n $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB)
  68468. + @$(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=install
  68469. +
  68470. +# required-list was used when building a shared bfd/opcodes/libiberty
  68471. +# library. I don't know if it used by anything currently.
  68472. +required-list: Makefile
  68473. + echo $(REQUIRED_OFILES) > required-list
  68474. +
  68475. +stamp-picdir:
  68476. + if [ x"$(PICFLAG)" != x ] && [ ! -d pic ]; then \
  68477. + mkdir pic; \
  68478. + else true; fi
  68479. + touch stamp-picdir
  68480. +
  68481. +.PHONY: all etags tags ls clean stage1 stage2
  68482. +
  68483. +etags tags: TAGS etags-subdir
  68484. +
  68485. +TAGS: $(CFILES)
  68486. + etags `for i in $(CFILES); do echo $(srcdir)/$$i ; done`
  68487. +
  68488. +# The standalone demangler (c++filt) has been moved to binutils.
  68489. +# But make this target work anyway for demangler hacking.
  68490. +demangle: $(ALL) $(srcdir)/cp-demangle.c
  68491. + @echo "The standalone demangler, now named c++filt, is now"
  68492. + @echo "a part of binutils."
  68493. + $(CC) -DHAVE_CONFIG_H $(CFLAGS) $(CPPFLAGS) -I. -I$(INCDIR) $(HDEFINES) \
  68494. + $(srcdir)/cp-demangle.c -DSTANDALONE_DEMANGLER $(TARGETLIB) -o $@
  68495. +
  68496. +ls:
  68497. + @echo Makefile $(CFILES)
  68498. +
  68499. +# Various targets for maintainers.
  68500. +
  68501. +maint-missing :
  68502. + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) missing $(CFILES) $(REQUIRED_OFILES) $(CONFIGURED_OFILES)
  68503. +
  68504. +maint-buildall : $(REQUIRED_OFILES) $(CONFIGURED_OFILES)
  68505. + @true
  68506. +
  68507. +maint-undoc : $(srcdir)/functions.texi
  68508. + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) undoc
  68509. +
  68510. +maint-deps :
  68511. + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) deps $(INCDIR)
  68512. +
  68513. +# Need to deal with profiled libraries, too.
  68514. +
  68515. +# Cleaning has to be done carefully to ensure that we don't clean our SUBDIRS
  68516. +# multiple times, hence our explicit recursion with an empty SUBDIRS.
  68517. +mostlyclean: mostlyclean-subdir
  68518. + -rm -rf *.$(objext) pic core errs \#* *.E a.out
  68519. + -rm -f errors dummy config.h stamp-*
  68520. + -rm -f $(CONFIG_H) stamp-picdir
  68521. + -rm -f libiberty.aux libiberty.cp libiberty.cps libiberty.fn libiberty.ky
  68522. + -rm -f libiberty.log libiberty.tmp libiberty.tps libiberty.pg
  68523. + -rm -f libiberty.pgs libiberty.toc libiberty.tp libiberty.tpl libiberty.vr
  68524. + -rm -f libtexi.stamp
  68525. + @$(MULTICLEAN) multi-clean DO=mostlyclean
  68526. +clean: clean-subdir
  68527. + $(MAKE) SUBDIRS="" mostlyclean
  68528. + -rm -f *.a required-list tmpmulti.out
  68529. + -rm -f libiberty.dvi libiberty.pdf libiberty.info* libiberty.html
  68530. + @$(MULTICLEAN) multi-clean DO=clean
  68531. +distclean: distclean-subdir
  68532. + $(MAKE) SUBDIRS="" clean
  68533. + @$(MULTICLEAN) multi-clean DO=distclean
  68534. + -rm -f *~ Makefile config.cache config.status xhost-mkfrag TAGS multilib.out
  68535. + -rm -f config.log
  68536. + -rmdir testsuite 2>/dev/null
  68537. +maintainer-clean realclean: maintainer-clean-subdir
  68538. + $(MAKE) SUBDIRS="" distclean
  68539. +
  68540. +force:
  68541. +
  68542. +Makefile: $(srcdir)/Makefile.in config.status
  68543. + CONFIG_FILES=Makefile CONFIG_HEADERS= $(SHELL) ./config.status
  68544. +
  68545. +# Depending on Makefile makes sure that config.status has been re-run
  68546. +# if needed. This prevents problems with parallel builds.
  68547. +config.h: stamp-h ; @true
  68548. +stamp-h: $(srcdir)/config.in config.status Makefile
  68549. + CONFIG_FILES= CONFIG_HEADERS=config.h:$(srcdir)/config.in $(SHELL) ./config.status
  68550. +
  68551. +config.status: $(srcdir)/configure
  68552. + $(SHELL) ./config.status --recheck
  68553. +
  68554. +AUTOCONF = autoconf
  68555. +configure_deps = $(srcdir)/aclocal.m4 \
  68556. + $(srcdir)/../config/acx.m4 \
  68557. + $(srcdir)/../config/no-executables.m4 \
  68558. + $(srcdir)/../config/override.m4 \
  68559. + $(srcdir)/../config/warnings.m4 \
  68560. +
  68561. +$(srcdir)/configure: # $(srcdir)/configure.ac $(configure_deps)
  68562. + cd $(srcdir) && $(AUTOCONF)
  68563. +
  68564. +# Depending on config.h makes sure that config.status has been re-run
  68565. +# if needed. This prevents problems with parallel builds, in case
  68566. +# subdirectories need to run config.status also.
  68567. +all-subdir check-subdir installcheck-subdir info-subdir \
  68568. +install-info-subdir clean-info-subdir dvi-subdir pdf-subdir install-subdir \
  68569. +etags-subdir mostlyclean-subdir clean-subdir distclean-subdir \
  68570. +maintainer-clean-subdir: config.h
  68571. + @subdirs='$(SUBDIRS)'; \
  68572. + target=`echo $@ | sed -e 's/-subdir//'`; \
  68573. + for dir in $$subdirs ; do \
  68574. + cd $$dir && $(MAKE) $(FLAGS_TO_PASS) $$target; \
  68575. + done
  68576. +
  68577. +$(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS): stamp-picdir
  68578. +$(CONFIGURED_OFILES): stamp-picdir
  68579. +
  68580. +# Don't export variables to the environment, in order to not confuse
  68581. +# configure.
  68582. +.NOEXPORT:
  68583. +
  68584. +# The dependencies in the remainder of this file are automatically
  68585. +# generated by "make maint-deps". Manual edits will be lost.
  68586. +
  68587. +./_doprnt.$(objext): $(srcdir)/_doprnt.c config.h $(INCDIR)/ansidecl.h \
  68588. + $(INCDIR)/safe-ctype.h
  68589. + if [ x"$(PICFLAG)" != x ]; then \
  68590. + $(COMPILE.c) $(PICFLAG) $(srcdir)/_doprnt.c -o pic/$@; \
  68591. + else true; fi
  68592. + $(COMPILE.c) $(srcdir)/_doprnt.c $(OUTPUT_OPTION)
  68593. +
  68594. +./alloca.$(objext): $(srcdir)/alloca.c config.h $(INCDIR)/ansidecl.h \
  68595. + $(INCDIR)/libiberty.h
  68596. + if [ x"$(PICFLAG)" != x ]; then \
  68597. + $(COMPILE.c) $(PICFLAG) $(srcdir)/alloca.c -o pic/$@; \
  68598. + else true; fi
  68599. + $(COMPILE.c) $(srcdir)/alloca.c $(OUTPUT_OPTION)
  68600. +
  68601. +./argv.$(objext): $(srcdir)/argv.c config.h $(INCDIR)/ansidecl.h \
  68602. + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
  68603. + if [ x"$(PICFLAG)" != x ]; then \
  68604. + $(COMPILE.c) $(PICFLAG) $(srcdir)/argv.c -o pic/$@; \
  68605. + else true; fi
  68606. + $(COMPILE.c) $(srcdir)/argv.c $(OUTPUT_OPTION)
  68607. +
  68608. +./asprintf.$(objext): $(srcdir)/asprintf.c config.h $(INCDIR)/ansidecl.h \
  68609. + $(INCDIR)/libiberty.h
  68610. + if [ x"$(PICFLAG)" != x ]; then \
  68611. + $(COMPILE.c) $(PICFLAG) $(srcdir)/asprintf.c -o pic/$@; \
  68612. + else true; fi
  68613. + $(COMPILE.c) $(srcdir)/asprintf.c $(OUTPUT_OPTION)
  68614. +
  68615. +./atexit.$(objext): $(srcdir)/atexit.c config.h
  68616. + if [ x"$(PICFLAG)" != x ]; then \
  68617. + $(COMPILE.c) $(PICFLAG) $(srcdir)/atexit.c -o pic/$@; \
  68618. + else true; fi
  68619. + $(COMPILE.c) $(srcdir)/atexit.c $(OUTPUT_OPTION)
  68620. +
  68621. +./basename.$(objext): $(srcdir)/basename.c config.h $(INCDIR)/ansidecl.h \
  68622. + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
  68623. + if [ x"$(PICFLAG)" != x ]; then \
  68624. + $(COMPILE.c) $(PICFLAG) $(srcdir)/basename.c -o pic/$@; \
  68625. + else true; fi
  68626. + $(COMPILE.c) $(srcdir)/basename.c $(OUTPUT_OPTION)
  68627. +
  68628. +./bcmp.$(objext): $(srcdir)/bcmp.c
  68629. + if [ x"$(PICFLAG)" != x ]; then \
  68630. + $(COMPILE.c) $(PICFLAG) $(srcdir)/bcmp.c -o pic/$@; \
  68631. + else true; fi
  68632. + $(COMPILE.c) $(srcdir)/bcmp.c $(OUTPUT_OPTION)
  68633. +
  68634. +./bcopy.$(objext): $(srcdir)/bcopy.c
  68635. + if [ x"$(PICFLAG)" != x ]; then \
  68636. + $(COMPILE.c) $(PICFLAG) $(srcdir)/bcopy.c -o pic/$@; \
  68637. + else true; fi
  68638. + $(COMPILE.c) $(srcdir)/bcopy.c $(OUTPUT_OPTION)
  68639. +
  68640. +./bsearch.$(objext): $(srcdir)/bsearch.c config.h $(INCDIR)/ansidecl.h
  68641. + if [ x"$(PICFLAG)" != x ]; then \
  68642. + $(COMPILE.c) $(PICFLAG) $(srcdir)/bsearch.c -o pic/$@; \
  68643. + else true; fi
  68644. + $(COMPILE.c) $(srcdir)/bsearch.c $(OUTPUT_OPTION)
  68645. +
  68646. +./bzero.$(objext): $(srcdir)/bzero.c
  68647. + if [ x"$(PICFLAG)" != x ]; then \
  68648. + $(COMPILE.c) $(PICFLAG) $(srcdir)/bzero.c -o pic/$@; \
  68649. + else true; fi
  68650. + $(COMPILE.c) $(srcdir)/bzero.c $(OUTPUT_OPTION)
  68651. +
  68652. +./calloc.$(objext): $(srcdir)/calloc.c $(INCDIR)/ansidecl.h
  68653. + if [ x"$(PICFLAG)" != x ]; then \
  68654. + $(COMPILE.c) $(PICFLAG) $(srcdir)/calloc.c -o pic/$@; \
  68655. + else true; fi
  68656. + $(COMPILE.c) $(srcdir)/calloc.c $(OUTPUT_OPTION)
  68657. +
  68658. +./choose-temp.$(objext): $(srcdir)/choose-temp.c config.h $(INCDIR)/ansidecl.h \
  68659. + $(INCDIR)/libiberty.h
  68660. + if [ x"$(PICFLAG)" != x ]; then \
  68661. + $(COMPILE.c) $(PICFLAG) $(srcdir)/choose-temp.c -o pic/$@; \
  68662. + else true; fi
  68663. + $(COMPILE.c) $(srcdir)/choose-temp.c $(OUTPUT_OPTION)
  68664. +
  68665. +./clock.$(objext): $(srcdir)/clock.c config.h
  68666. + if [ x"$(PICFLAG)" != x ]; then \
  68667. + $(COMPILE.c) $(PICFLAG) $(srcdir)/clock.c -o pic/$@; \
  68668. + else true; fi
  68669. + $(COMPILE.c) $(srcdir)/clock.c $(OUTPUT_OPTION)
  68670. +
  68671. +./concat.$(objext): $(srcdir)/concat.c config.h $(INCDIR)/ansidecl.h \
  68672. + $(INCDIR)/libiberty.h
  68673. + if [ x"$(PICFLAG)" != x ]; then \
  68674. + $(COMPILE.c) $(PICFLAG) $(srcdir)/concat.c -o pic/$@; \
  68675. + else true; fi
  68676. + $(COMPILE.c) $(srcdir)/concat.c $(OUTPUT_OPTION)
  68677. +
  68678. +./copysign.$(objext): $(srcdir)/copysign.c $(INCDIR)/ansidecl.h
  68679. + if [ x"$(PICFLAG)" != x ]; then \
  68680. + $(COMPILE.c) $(PICFLAG) $(srcdir)/copysign.c -o pic/$@; \
  68681. + else true; fi
  68682. + $(COMPILE.c) $(srcdir)/copysign.c $(OUTPUT_OPTION)
  68683. +
  68684. +./cp-demangle.$(objext): $(srcdir)/cp-demangle.c config.h $(INCDIR)/ansidecl.h \
  68685. + $(srcdir)/cp-demangle.h $(INCDIR)/demangle.h \
  68686. + $(INCDIR)/dyn-string.h $(INCDIR)/getopt.h $(INCDIR)/libiberty.h
  68687. + if [ x"$(PICFLAG)" != x ]; then \
  68688. + $(COMPILE.c) $(PICFLAG) $(srcdir)/cp-demangle.c -o pic/$@; \
  68689. + else true; fi
  68690. + $(COMPILE.c) $(srcdir)/cp-demangle.c $(OUTPUT_OPTION)
  68691. +
  68692. +./cp-demint.$(objext): $(srcdir)/cp-demint.c config.h $(INCDIR)/ansidecl.h \
  68693. + $(srcdir)/cp-demangle.h $(INCDIR)/demangle.h \
  68694. + $(INCDIR)/libiberty.h
  68695. + if [ x"$(PICFLAG)" != x ]; then \
  68696. + $(COMPILE.c) $(PICFLAG) $(srcdir)/cp-demint.c -o pic/$@; \
  68697. + else true; fi
  68698. + $(COMPILE.c) $(srcdir)/cp-demint.c $(OUTPUT_OPTION)
  68699. +
  68700. +./cplus-dem.$(objext): $(srcdir)/cplus-dem.c config.h $(INCDIR)/ansidecl.h \
  68701. + $(INCDIR)/demangle.h $(INCDIR)/libiberty.h \
  68702. + $(INCDIR)/safe-ctype.h
  68703. + if [ x"$(PICFLAG)" != x ]; then \
  68704. + $(COMPILE.c) $(PICFLAG) $(srcdir)/cplus-dem.c -o pic/$@; \
  68705. + else true; fi
  68706. + $(COMPILE.c) $(srcdir)/cplus-dem.c $(OUTPUT_OPTION)
  68707. +
  68708. +./crc32.$(objext): $(srcdir)/crc32.c config.h $(INCDIR)/ansidecl.h \
  68709. + $(INCDIR)/libiberty.h
  68710. + if [ x"$(PICFLAG)" != x ]; then \
  68711. + $(COMPILE.c) $(PICFLAG) $(srcdir)/crc32.c -o pic/$@; \
  68712. + else true; fi
  68713. + $(COMPILE.c) $(srcdir)/crc32.c $(OUTPUT_OPTION)
  68714. +
  68715. +./dwarfnames.$(objext): $(srcdir)/dwarfnames.c $(INCDIR)/dwarf2.def \
  68716. + $(INCDIR)/dwarf2.h
  68717. + if [ x"$(PICFLAG)" != x ]; then \
  68718. + $(COMPILE.c) $(PICFLAG) $(srcdir)/dwarfnames.c -o pic/$@; \
  68719. + else true; fi
  68720. + $(COMPILE.c) $(srcdir)/dwarfnames.c $(OUTPUT_OPTION)
  68721. +
  68722. +./dyn-string.$(objext): $(srcdir)/dyn-string.c config.h $(INCDIR)/ansidecl.h \
  68723. + $(INCDIR)/dyn-string.h $(INCDIR)/libiberty.h
  68724. + if [ x"$(PICFLAG)" != x ]; then \
  68725. + $(COMPILE.c) $(PICFLAG) $(srcdir)/dyn-string.c -o pic/$@; \
  68726. + else true; fi
  68727. + $(COMPILE.c) $(srcdir)/dyn-string.c $(OUTPUT_OPTION)
  68728. +
  68729. +./fdmatch.$(objext): $(srcdir)/fdmatch.c config.h $(INCDIR)/ansidecl.h \
  68730. + $(INCDIR)/libiberty.h
  68731. + if [ x"$(PICFLAG)" != x ]; then \
  68732. + $(COMPILE.c) $(PICFLAG) $(srcdir)/fdmatch.c -o pic/$@; \
  68733. + else true; fi
  68734. + $(COMPILE.c) $(srcdir)/fdmatch.c $(OUTPUT_OPTION)
  68735. +
  68736. +./ffs.$(objext): $(srcdir)/ffs.c
  68737. + if [ x"$(PICFLAG)" != x ]; then \
  68738. + $(COMPILE.c) $(PICFLAG) $(srcdir)/ffs.c -o pic/$@; \
  68739. + else true; fi
  68740. + $(COMPILE.c) $(srcdir)/ffs.c $(OUTPUT_OPTION)
  68741. +
  68742. +./fibheap.$(objext): $(srcdir)/fibheap.c config.h $(INCDIR)/ansidecl.h \
  68743. + $(INCDIR)/fibheap.h $(INCDIR)/libiberty.h
  68744. + if [ x"$(PICFLAG)" != x ]; then \
  68745. + $(COMPILE.c) $(PICFLAG) $(srcdir)/fibheap.c -o pic/$@; \
  68746. + else true; fi
  68747. + $(COMPILE.c) $(srcdir)/fibheap.c $(OUTPUT_OPTION)
  68748. +
  68749. +./filename_cmp.$(objext): $(srcdir)/filename_cmp.c config.h $(INCDIR)/ansidecl.h \
  68750. + $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
  68751. + $(INCDIR)/safe-ctype.h
  68752. + if [ x"$(PICFLAG)" != x ]; then \
  68753. + $(COMPILE.c) $(PICFLAG) $(srcdir)/filename_cmp.c -o pic/$@; \
  68754. + else true; fi
  68755. + $(COMPILE.c) $(srcdir)/filename_cmp.c $(OUTPUT_OPTION)
  68756. +
  68757. +./floatformat.$(objext): $(srcdir)/floatformat.c config.h $(INCDIR)/ansidecl.h \
  68758. + $(INCDIR)/floatformat.h $(INCDIR)/libiberty.h
  68759. + if [ x"$(PICFLAG)" != x ]; then \
  68760. + $(COMPILE.c) $(PICFLAG) $(srcdir)/floatformat.c -o pic/$@; \
  68761. + else true; fi
  68762. + $(COMPILE.c) $(srcdir)/floatformat.c $(OUTPUT_OPTION)
  68763. +
  68764. +./fnmatch.$(objext): $(srcdir)/fnmatch.c config.h $(INCDIR)/fnmatch.h \
  68765. + $(INCDIR)/safe-ctype.h
  68766. + if [ x"$(PICFLAG)" != x ]; then \
  68767. + $(COMPILE.c) $(PICFLAG) $(srcdir)/fnmatch.c -o pic/$@; \
  68768. + else true; fi
  68769. + $(COMPILE.c) $(srcdir)/fnmatch.c $(OUTPUT_OPTION)
  68770. +
  68771. +./fopen_unlocked.$(objext): $(srcdir)/fopen_unlocked.c config.h \
  68772. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
  68773. + if [ x"$(PICFLAG)" != x ]; then \
  68774. + $(COMPILE.c) $(PICFLAG) $(srcdir)/fopen_unlocked.c -o pic/$@; \
  68775. + else true; fi
  68776. + $(COMPILE.c) $(srcdir)/fopen_unlocked.c $(OUTPUT_OPTION)
  68777. +
  68778. +./getcwd.$(objext): $(srcdir)/getcwd.c config.h
  68779. + if [ x"$(PICFLAG)" != x ]; then \
  68780. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getcwd.c -o pic/$@; \
  68781. + else true; fi
  68782. + $(COMPILE.c) $(srcdir)/getcwd.c $(OUTPUT_OPTION)
  68783. +
  68784. +./getopt.$(objext): $(srcdir)/getopt.c config.h $(INCDIR)/ansidecl.h \
  68785. + $(INCDIR)/getopt.h
  68786. + if [ x"$(PICFLAG)" != x ]; then \
  68787. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getopt.c -o pic/$@; \
  68788. + else true; fi
  68789. + $(COMPILE.c) $(srcdir)/getopt.c $(OUTPUT_OPTION)
  68790. +
  68791. +./getopt1.$(objext): $(srcdir)/getopt1.c config.h $(INCDIR)/getopt.h
  68792. + if [ x"$(PICFLAG)" != x ]; then \
  68793. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getopt1.c -o pic/$@; \
  68794. + else true; fi
  68795. + $(COMPILE.c) $(srcdir)/getopt1.c $(OUTPUT_OPTION)
  68796. +
  68797. +./getpagesize.$(objext): $(srcdir)/getpagesize.c config.h
  68798. + if [ x"$(PICFLAG)" != x ]; then \
  68799. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getpagesize.c -o pic/$@; \
  68800. + else true; fi
  68801. + $(COMPILE.c) $(srcdir)/getpagesize.c $(OUTPUT_OPTION)
  68802. +
  68803. +./getpwd.$(objext): $(srcdir)/getpwd.c config.h $(INCDIR)/ansidecl.h \
  68804. + $(INCDIR)/libiberty.h
  68805. + if [ x"$(PICFLAG)" != x ]; then \
  68806. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getpwd.c -o pic/$@; \
  68807. + else true; fi
  68808. + $(COMPILE.c) $(srcdir)/getpwd.c $(OUTPUT_OPTION)
  68809. +
  68810. +./getruntime.$(objext): $(srcdir)/getruntime.c config.h $(INCDIR)/ansidecl.h \
  68811. + $(INCDIR)/libiberty.h
  68812. + if [ x"$(PICFLAG)" != x ]; then \
  68813. + $(COMPILE.c) $(PICFLAG) $(srcdir)/getruntime.c -o pic/$@; \
  68814. + else true; fi
  68815. + $(COMPILE.c) $(srcdir)/getruntime.c $(OUTPUT_OPTION)
  68816. +
  68817. +./gettimeofday.$(objext): $(srcdir)/gettimeofday.c config.h $(INCDIR)/ansidecl.h \
  68818. + $(INCDIR)/libiberty.h
  68819. + if [ x"$(PICFLAG)" != x ]; then \
  68820. + $(COMPILE.c) $(PICFLAG) $(srcdir)/gettimeofday.c -o pic/$@; \
  68821. + else true; fi
  68822. + $(COMPILE.c) $(srcdir)/gettimeofday.c $(OUTPUT_OPTION)
  68823. +
  68824. +./hashtab.$(objext): $(srcdir)/hashtab.c config.h $(INCDIR)/ansidecl.h \
  68825. + $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
  68826. + if [ x"$(PICFLAG)" != x ]; then \
  68827. + $(COMPILE.c) $(PICFLAG) $(srcdir)/hashtab.c -o pic/$@; \
  68828. + else true; fi
  68829. + $(COMPILE.c) $(srcdir)/hashtab.c $(OUTPUT_OPTION)
  68830. +
  68831. +./hex.$(objext): $(srcdir)/hex.c config.h $(INCDIR)/ansidecl.h \
  68832. + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
  68833. + if [ x"$(PICFLAG)" != x ]; then \
  68834. + $(COMPILE.c) $(PICFLAG) $(srcdir)/hex.c -o pic/$@; \
  68835. + else true; fi
  68836. + $(COMPILE.c) $(srcdir)/hex.c $(OUTPUT_OPTION)
  68837. +
  68838. +./index.$(objext): $(srcdir)/index.c
  68839. + if [ x"$(PICFLAG)" != x ]; then \
  68840. + $(COMPILE.c) $(PICFLAG) $(srcdir)/index.c -o pic/$@; \
  68841. + else true; fi
  68842. + $(COMPILE.c) $(srcdir)/index.c $(OUTPUT_OPTION)
  68843. +
  68844. +./insque.$(objext): $(srcdir)/insque.c
  68845. + if [ x"$(PICFLAG)" != x ]; then \
  68846. + $(COMPILE.c) $(PICFLAG) $(srcdir)/insque.c -o pic/$@; \
  68847. + else true; fi
  68848. + $(COMPILE.c) $(srcdir)/insque.c $(OUTPUT_OPTION)
  68849. +
  68850. +./lbasename.$(objext): $(srcdir)/lbasename.c config.h $(INCDIR)/ansidecl.h \
  68851. + $(INCDIR)/filenames.h $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h \
  68852. + $(INCDIR)/safe-ctype.h
  68853. + if [ x"$(PICFLAG)" != x ]; then \
  68854. + $(COMPILE.c) $(PICFLAG) $(srcdir)/lbasename.c -o pic/$@; \
  68855. + else true; fi
  68856. + $(COMPILE.c) $(srcdir)/lbasename.c $(OUTPUT_OPTION)
  68857. +
  68858. +./lrealpath.$(objext): $(srcdir)/lrealpath.c config.h $(INCDIR)/ansidecl.h \
  68859. + $(INCDIR)/libiberty.h
  68860. + if [ x"$(PICFLAG)" != x ]; then \
  68861. + $(COMPILE.c) $(PICFLAG) $(srcdir)/lrealpath.c -o pic/$@; \
  68862. + else true; fi
  68863. + $(COMPILE.c) $(srcdir)/lrealpath.c $(OUTPUT_OPTION)
  68864. +
  68865. +./make-relative-prefix.$(objext): $(srcdir)/make-relative-prefix.c config.h \
  68866. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
  68867. + if [ x"$(PICFLAG)" != x ]; then \
  68868. + $(COMPILE.c) $(PICFLAG) $(srcdir)/make-relative-prefix.c -o pic/$@; \
  68869. + else true; fi
  68870. + $(COMPILE.c) $(srcdir)/make-relative-prefix.c $(OUTPUT_OPTION)
  68871. +
  68872. +./make-temp-file.$(objext): $(srcdir)/make-temp-file.c config.h \
  68873. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
  68874. + if [ x"$(PICFLAG)" != x ]; then \
  68875. + $(COMPILE.c) $(PICFLAG) $(srcdir)/make-temp-file.c -o pic/$@; \
  68876. + else true; fi
  68877. + $(COMPILE.c) $(srcdir)/make-temp-file.c $(OUTPUT_OPTION)
  68878. +
  68879. +./md5.$(objext): $(srcdir)/md5.c config.h $(INCDIR)/ansidecl.h $(INCDIR)/md5.h
  68880. + if [ x"$(PICFLAG)" != x ]; then \
  68881. + $(COMPILE.c) $(PICFLAG) $(srcdir)/md5.c -o pic/$@; \
  68882. + else true; fi
  68883. + $(COMPILE.c) $(srcdir)/md5.c $(OUTPUT_OPTION)
  68884. +
  68885. +./memchr.$(objext): $(srcdir)/memchr.c $(INCDIR)/ansidecl.h
  68886. + if [ x"$(PICFLAG)" != x ]; then \
  68887. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memchr.c -o pic/$@; \
  68888. + else true; fi
  68889. + $(COMPILE.c) $(srcdir)/memchr.c $(OUTPUT_OPTION)
  68890. +
  68891. +./memcmp.$(objext): $(srcdir)/memcmp.c $(INCDIR)/ansidecl.h
  68892. + if [ x"$(PICFLAG)" != x ]; then \
  68893. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memcmp.c -o pic/$@; \
  68894. + else true; fi
  68895. + $(COMPILE.c) $(srcdir)/memcmp.c $(OUTPUT_OPTION)
  68896. +
  68897. +./memcpy.$(objext): $(srcdir)/memcpy.c $(INCDIR)/ansidecl.h
  68898. + if [ x"$(PICFLAG)" != x ]; then \
  68899. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memcpy.c -o pic/$@; \
  68900. + else true; fi
  68901. + $(COMPILE.c) $(srcdir)/memcpy.c $(OUTPUT_OPTION)
  68902. +
  68903. +./memmem.$(objext): $(srcdir)/memmem.c config.h
  68904. + if [ x"$(PICFLAG)" != x ]; then \
  68905. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memmem.c -o pic/$@; \
  68906. + else true; fi
  68907. + $(COMPILE.c) $(srcdir)/memmem.c $(OUTPUT_OPTION)
  68908. +
  68909. +./memmove.$(objext): $(srcdir)/memmove.c $(INCDIR)/ansidecl.h
  68910. + if [ x"$(PICFLAG)" != x ]; then \
  68911. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memmove.c -o pic/$@; \
  68912. + else true; fi
  68913. + $(COMPILE.c) $(srcdir)/memmove.c $(OUTPUT_OPTION)
  68914. +
  68915. +./mempcpy.$(objext): $(srcdir)/mempcpy.c $(INCDIR)/ansidecl.h
  68916. + if [ x"$(PICFLAG)" != x ]; then \
  68917. + $(COMPILE.c) $(PICFLAG) $(srcdir)/mempcpy.c -o pic/$@; \
  68918. + else true; fi
  68919. + $(COMPILE.c) $(srcdir)/mempcpy.c $(OUTPUT_OPTION)
  68920. +
  68921. +./memset.$(objext): $(srcdir)/memset.c $(INCDIR)/ansidecl.h
  68922. + if [ x"$(PICFLAG)" != x ]; then \
  68923. + $(COMPILE.c) $(PICFLAG) $(srcdir)/memset.c -o pic/$@; \
  68924. + else true; fi
  68925. + $(COMPILE.c) $(srcdir)/memset.c $(OUTPUT_OPTION)
  68926. +
  68927. +./mkstemps.$(objext): $(srcdir)/mkstemps.c config.h $(INCDIR)/ansidecl.h
  68928. + if [ x"$(PICFLAG)" != x ]; then \
  68929. + $(COMPILE.c) $(PICFLAG) $(srcdir)/mkstemps.c -o pic/$@; \
  68930. + else true; fi
  68931. + $(COMPILE.c) $(srcdir)/mkstemps.c $(OUTPUT_OPTION)
  68932. +
  68933. +./msdos.$(objext): $(srcdir)/msdos.c
  68934. + if [ x"$(PICFLAG)" != x ]; then \
  68935. + $(COMPILE.c) $(PICFLAG) $(srcdir)/msdos.c -o pic/$@; \
  68936. + else true; fi
  68937. + $(COMPILE.c) $(srcdir)/msdos.c $(OUTPUT_OPTION)
  68938. +
  68939. +./objalloc.$(objext): $(srcdir)/objalloc.c config.h $(INCDIR)/ansidecl.h \
  68940. + $(INCDIR)/objalloc.h
  68941. + if [ x"$(PICFLAG)" != x ]; then \
  68942. + $(COMPILE.c) $(PICFLAG) $(srcdir)/objalloc.c -o pic/$@; \
  68943. + else true; fi
  68944. + $(COMPILE.c) $(srcdir)/objalloc.c $(OUTPUT_OPTION)
  68945. +
  68946. +./obstack.$(objext): $(srcdir)/obstack.c config.h $(INCDIR)/obstack.h
  68947. + if [ x"$(PICFLAG)" != x ]; then \
  68948. + $(COMPILE.c) $(PICFLAG) $(srcdir)/obstack.c -o pic/$@; \
  68949. + else true; fi
  68950. + $(COMPILE.c) $(srcdir)/obstack.c $(OUTPUT_OPTION)
  68951. +
  68952. +./partition.$(objext): $(srcdir)/partition.c config.h $(INCDIR)/ansidecl.h \
  68953. + $(INCDIR)/libiberty.h $(INCDIR)/partition.h
  68954. + if [ x"$(PICFLAG)" != x ]; then \
  68955. + $(COMPILE.c) $(PICFLAG) $(srcdir)/partition.c -o pic/$@; \
  68956. + else true; fi
  68957. + $(COMPILE.c) $(srcdir)/partition.c $(OUTPUT_OPTION)
  68958. +
  68959. +./pex-common.$(objext): $(srcdir)/pex-common.c config.h $(INCDIR)/ansidecl.h \
  68960. + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h
  68961. + if [ x"$(PICFLAG)" != x ]; then \
  68962. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-common.c -o pic/$@; \
  68963. + else true; fi
  68964. + $(COMPILE.c) $(srcdir)/pex-common.c $(OUTPUT_OPTION)
  68965. +
  68966. +./pex-djgpp.$(objext): $(srcdir)/pex-djgpp.c config.h $(INCDIR)/ansidecl.h \
  68967. + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h
  68968. + if [ x"$(PICFLAG)" != x ]; then \
  68969. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-djgpp.c -o pic/$@; \
  68970. + else true; fi
  68971. + $(COMPILE.c) $(srcdir)/pex-djgpp.c $(OUTPUT_OPTION)
  68972. +
  68973. +./pex-msdos.$(objext): $(srcdir)/pex-msdos.c config.h $(INCDIR)/ansidecl.h \
  68974. + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h \
  68975. + $(INCDIR)/safe-ctype.h
  68976. + if [ x"$(PICFLAG)" != x ]; then \
  68977. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-msdos.c -o pic/$@; \
  68978. + else true; fi
  68979. + $(COMPILE.c) $(srcdir)/pex-msdos.c $(OUTPUT_OPTION)
  68980. +
  68981. +./pex-one.$(objext): $(srcdir)/pex-one.c config.h $(INCDIR)/ansidecl.h \
  68982. + $(INCDIR)/libiberty.h
  68983. + if [ x"$(PICFLAG)" != x ]; then \
  68984. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-one.c -o pic/$@; \
  68985. + else true; fi
  68986. + $(COMPILE.c) $(srcdir)/pex-one.c $(OUTPUT_OPTION)
  68987. +
  68988. +./pex-unix.$(objext): $(srcdir)/pex-unix.c config.h $(INCDIR)/ansidecl.h \
  68989. + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h
  68990. + if [ x"$(PICFLAG)" != x ]; then \
  68991. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-unix.c -o pic/$@; \
  68992. + else true; fi
  68993. + $(COMPILE.c) $(srcdir)/pex-unix.c $(OUTPUT_OPTION)
  68994. +
  68995. +./pex-win32.$(objext): $(srcdir)/pex-win32.c config.h $(INCDIR)/ansidecl.h \
  68996. + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h
  68997. + if [ x"$(PICFLAG)" != x ]; then \
  68998. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-win32.c -o pic/$@; \
  68999. + else true; fi
  69000. + $(COMPILE.c) $(srcdir)/pex-win32.c $(OUTPUT_OPTION)
  69001. +
  69002. +./pexecute.$(objext): $(srcdir)/pexecute.c config.h $(INCDIR)/ansidecl.h \
  69003. + $(INCDIR)/libiberty.h
  69004. + if [ x"$(PICFLAG)" != x ]; then \
  69005. + $(COMPILE.c) $(PICFLAG) $(srcdir)/pexecute.c -o pic/$@; \
  69006. + else true; fi
  69007. + $(COMPILE.c) $(srcdir)/pexecute.c $(OUTPUT_OPTION)
  69008. +
  69009. +./physmem.$(objext): $(srcdir)/physmem.c config.h $(INCDIR)/ansidecl.h \
  69010. + $(INCDIR)/libiberty.h
  69011. + if [ x"$(PICFLAG)" != x ]; then \
  69012. + $(COMPILE.c) $(PICFLAG) $(srcdir)/physmem.c -o pic/$@; \
  69013. + else true; fi
  69014. + $(COMPILE.c) $(srcdir)/physmem.c $(OUTPUT_OPTION)
  69015. +
  69016. +./putenv.$(objext): $(srcdir)/putenv.c config.h $(INCDIR)/ansidecl.h
  69017. + if [ x"$(PICFLAG)" != x ]; then \
  69018. + $(COMPILE.c) $(PICFLAG) $(srcdir)/putenv.c -o pic/$@; \
  69019. + else true; fi
  69020. + $(COMPILE.c) $(srcdir)/putenv.c $(OUTPUT_OPTION)
  69021. +
  69022. +./random.$(objext): $(srcdir)/random.c $(INCDIR)/ansidecl.h
  69023. + if [ x"$(PICFLAG)" != x ]; then \
  69024. + $(COMPILE.c) $(PICFLAG) $(srcdir)/random.c -o pic/$@; \
  69025. + else true; fi
  69026. + $(COMPILE.c) $(srcdir)/random.c $(OUTPUT_OPTION)
  69027. +
  69028. +./regex.$(objext): $(srcdir)/regex.c config.h $(INCDIR)/ansidecl.h \
  69029. + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
  69030. + if [ x"$(PICFLAG)" != x ]; then \
  69031. + $(COMPILE.c) $(PICFLAG) $(srcdir)/regex.c -o pic/$@; \
  69032. + else true; fi
  69033. + $(COMPILE.c) $(srcdir)/regex.c $(OUTPUT_OPTION)
  69034. +
  69035. +./rename.$(objext): $(srcdir)/rename.c config.h $(INCDIR)/ansidecl.h
  69036. + if [ x"$(PICFLAG)" != x ]; then \
  69037. + $(COMPILE.c) $(PICFLAG) $(srcdir)/rename.c -o pic/$@; \
  69038. + else true; fi
  69039. + $(COMPILE.c) $(srcdir)/rename.c $(OUTPUT_OPTION)
  69040. +
  69041. +./rindex.$(objext): $(srcdir)/rindex.c
  69042. + if [ x"$(PICFLAG)" != x ]; then \
  69043. + $(COMPILE.c) $(PICFLAG) $(srcdir)/rindex.c -o pic/$@; \
  69044. + else true; fi
  69045. + $(COMPILE.c) $(srcdir)/rindex.c $(OUTPUT_OPTION)
  69046. +
  69047. +./safe-ctype.$(objext): $(srcdir)/safe-ctype.c $(INCDIR)/ansidecl.h \
  69048. + $(INCDIR)/safe-ctype.h
  69049. + if [ x"$(PICFLAG)" != x ]; then \
  69050. + $(COMPILE.c) $(PICFLAG) $(srcdir)/safe-ctype.c -o pic/$@; \
  69051. + else true; fi
  69052. + $(COMPILE.c) $(srcdir)/safe-ctype.c $(OUTPUT_OPTION)
  69053. +
  69054. +./setenv.$(objext): $(srcdir)/setenv.c config.h $(INCDIR)/ansidecl.h
  69055. + if [ x"$(PICFLAG)" != x ]; then \
  69056. + $(COMPILE.c) $(PICFLAG) $(srcdir)/setenv.c -o pic/$@; \
  69057. + else true; fi
  69058. + $(COMPILE.c) $(srcdir)/setenv.c $(OUTPUT_OPTION)
  69059. +
  69060. +./setproctitle.$(objext): $(srcdir)/setproctitle.c config.h $(INCDIR)/ansidecl.h
  69061. + if [ x"$(PICFLAG)" != x ]; then \
  69062. + $(COMPILE.c) $(PICFLAG) $(srcdir)/setproctitle.c -o pic/$@; \
  69063. + else true; fi
  69064. + $(COMPILE.c) $(srcdir)/setproctitle.c $(OUTPUT_OPTION)
  69065. +
  69066. +./sha1.$(objext): $(srcdir)/sha1.c config.h $(INCDIR)/ansidecl.h $(INCDIR)/sha1.h
  69067. + if [ x"$(PICFLAG)" != x ]; then \
  69068. + $(COMPILE.c) $(PICFLAG) $(srcdir)/sha1.c -o pic/$@; \
  69069. + else true; fi
  69070. + $(COMPILE.c) $(srcdir)/sha1.c $(OUTPUT_OPTION)
  69071. +
  69072. +./sigsetmask.$(objext): $(srcdir)/sigsetmask.c $(INCDIR)/ansidecl.h
  69073. + if [ x"$(PICFLAG)" != x ]; then \
  69074. + $(COMPILE.c) $(PICFLAG) $(srcdir)/sigsetmask.c -o pic/$@; \
  69075. + else true; fi
  69076. + $(COMPILE.c) $(srcdir)/sigsetmask.c $(OUTPUT_OPTION)
  69077. +
  69078. +./simple-object-coff.$(objext): $(srcdir)/simple-object-coff.c config.h \
  69079. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
  69080. + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h
  69081. + if [ x"$(PICFLAG)" != x ]; then \
  69082. + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-coff.c -o pic/$@; \
  69083. + else true; fi
  69084. + $(COMPILE.c) $(srcdir)/simple-object-coff.c $(OUTPUT_OPTION)
  69085. +
  69086. +./simple-object-elf.$(objext): $(srcdir)/simple-object-elf.c config.h \
  69087. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
  69088. + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h
  69089. + if [ x"$(PICFLAG)" != x ]; then \
  69090. + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-elf.c -o pic/$@; \
  69091. + else true; fi
  69092. + $(COMPILE.c) $(srcdir)/simple-object-elf.c $(OUTPUT_OPTION)
  69093. +
  69094. +./simple-object-mach-o.$(objext): $(srcdir)/simple-object-mach-o.c config.h \
  69095. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
  69096. + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h
  69097. + if [ x"$(PICFLAG)" != x ]; then \
  69098. + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-mach-o.c -o pic/$@; \
  69099. + else true; fi
  69100. + $(COMPILE.c) $(srcdir)/simple-object-mach-o.c $(OUTPUT_OPTION)
  69101. +
  69102. +./simple-object-xcoff.$(objext): $(srcdir)/simple-object-xcoff.c config.h \
  69103. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
  69104. + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h
  69105. + if [ x"$(PICFLAG)" != x ]; then \
  69106. + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-xcoff.c -o pic/$@; \
  69107. + else true; fi
  69108. + $(COMPILE.c) $(srcdir)/simple-object-xcoff.c $(OUTPUT_OPTION)
  69109. +
  69110. +./simple-object.$(objext): $(srcdir)/simple-object.c config.h \
  69111. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
  69112. + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h
  69113. + if [ x"$(PICFLAG)" != x ]; then \
  69114. + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object.c -o pic/$@; \
  69115. + else true; fi
  69116. + $(COMPILE.c) $(srcdir)/simple-object.c $(OUTPUT_OPTION)
  69117. +
  69118. +./snprintf.$(objext): $(srcdir)/snprintf.c $(INCDIR)/ansidecl.h
  69119. + if [ x"$(PICFLAG)" != x ]; then \
  69120. + $(COMPILE.c) $(PICFLAG) $(srcdir)/snprintf.c -o pic/$@; \
  69121. + else true; fi
  69122. + $(COMPILE.c) $(srcdir)/snprintf.c $(OUTPUT_OPTION)
  69123. +
  69124. +./sort.$(objext): $(srcdir)/sort.c config.h $(INCDIR)/ansidecl.h \
  69125. + $(INCDIR)/libiberty.h $(INCDIR)/sort.h
  69126. + if [ x"$(PICFLAG)" != x ]; then \
  69127. + $(COMPILE.c) $(PICFLAG) $(srcdir)/sort.c -o pic/$@; \
  69128. + else true; fi
  69129. + $(COMPILE.c) $(srcdir)/sort.c $(OUTPUT_OPTION)
  69130. +
  69131. +./spaces.$(objext): $(srcdir)/spaces.c config.h $(INCDIR)/ansidecl.h \
  69132. + $(INCDIR)/libiberty.h
  69133. + if [ x"$(PICFLAG)" != x ]; then \
  69134. + $(COMPILE.c) $(PICFLAG) $(srcdir)/spaces.c -o pic/$@; \
  69135. + else true; fi
  69136. + $(COMPILE.c) $(srcdir)/spaces.c $(OUTPUT_OPTION)
  69137. +
  69138. +./splay-tree.$(objext): $(srcdir)/splay-tree.c config.h $(INCDIR)/ansidecl.h \
  69139. + $(INCDIR)/libiberty.h $(INCDIR)/splay-tree.h
  69140. + if [ x"$(PICFLAG)" != x ]; then \
  69141. + $(COMPILE.c) $(PICFLAG) $(srcdir)/splay-tree.c -o pic/$@; \
  69142. + else true; fi
  69143. + $(COMPILE.c) $(srcdir)/splay-tree.c $(OUTPUT_OPTION)
  69144. +
  69145. +./stack-limit.$(objext): $(srcdir)/stack-limit.c config.h $(INCDIR)/ansidecl.h
  69146. + if [ x"$(PICFLAG)" != x ]; then \
  69147. + $(COMPILE.c) $(PICFLAG) $(srcdir)/stack-limit.c -o pic/$@; \
  69148. + else true; fi
  69149. + $(COMPILE.c) $(srcdir)/stack-limit.c $(OUTPUT_OPTION)
  69150. +
  69151. +./stpcpy.$(objext): $(srcdir)/stpcpy.c $(INCDIR)/ansidecl.h
  69152. + if [ x"$(PICFLAG)" != x ]; then \
  69153. + $(COMPILE.c) $(PICFLAG) $(srcdir)/stpcpy.c -o pic/$@; \
  69154. + else true; fi
  69155. + $(COMPILE.c) $(srcdir)/stpcpy.c $(OUTPUT_OPTION)
  69156. +
  69157. +./stpncpy.$(objext): $(srcdir)/stpncpy.c $(INCDIR)/ansidecl.h
  69158. + if [ x"$(PICFLAG)" != x ]; then \
  69159. + $(COMPILE.c) $(PICFLAG) $(srcdir)/stpncpy.c -o pic/$@; \
  69160. + else true; fi
  69161. + $(COMPILE.c) $(srcdir)/stpncpy.c $(OUTPUT_OPTION)
  69162. +
  69163. +./strcasecmp.$(objext): $(srcdir)/strcasecmp.c $(INCDIR)/ansidecl.h
  69164. + if [ x"$(PICFLAG)" != x ]; then \
  69165. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strcasecmp.c -o pic/$@; \
  69166. + else true; fi
  69167. + $(COMPILE.c) $(srcdir)/strcasecmp.c $(OUTPUT_OPTION)
  69168. +
  69169. +./strchr.$(objext): $(srcdir)/strchr.c $(INCDIR)/ansidecl.h
  69170. + if [ x"$(PICFLAG)" != x ]; then \
  69171. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strchr.c -o pic/$@; \
  69172. + else true; fi
  69173. + $(COMPILE.c) $(srcdir)/strchr.c $(OUTPUT_OPTION)
  69174. +
  69175. +./strdup.$(objext): $(srcdir)/strdup.c $(INCDIR)/ansidecl.h
  69176. + if [ x"$(PICFLAG)" != x ]; then \
  69177. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strdup.c -o pic/$@; \
  69178. + else true; fi
  69179. + $(COMPILE.c) $(srcdir)/strdup.c $(OUTPUT_OPTION)
  69180. +
  69181. +./strerror.$(objext): $(srcdir)/strerror.c config.h $(INCDIR)/ansidecl.h \
  69182. + $(INCDIR)/libiberty.h
  69183. + if [ x"$(PICFLAG)" != x ]; then \
  69184. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strerror.c -o pic/$@; \
  69185. + else true; fi
  69186. + $(COMPILE.c) $(srcdir)/strerror.c $(OUTPUT_OPTION)
  69187. +
  69188. +./strncasecmp.$(objext): $(srcdir)/strncasecmp.c $(INCDIR)/ansidecl.h
  69189. + if [ x"$(PICFLAG)" != x ]; then \
  69190. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strncasecmp.c -o pic/$@; \
  69191. + else true; fi
  69192. + $(COMPILE.c) $(srcdir)/strncasecmp.c $(OUTPUT_OPTION)
  69193. +
  69194. +./strncmp.$(objext): $(srcdir)/strncmp.c $(INCDIR)/ansidecl.h
  69195. + if [ x"$(PICFLAG)" != x ]; then \
  69196. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strncmp.c -o pic/$@; \
  69197. + else true; fi
  69198. + $(COMPILE.c) $(srcdir)/strncmp.c $(OUTPUT_OPTION)
  69199. +
  69200. +./strndup.$(objext): $(srcdir)/strndup.c $(INCDIR)/ansidecl.h
  69201. + if [ x"$(PICFLAG)" != x ]; then \
  69202. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strndup.c -o pic/$@; \
  69203. + else true; fi
  69204. + $(COMPILE.c) $(srcdir)/strndup.c $(OUTPUT_OPTION)
  69205. +
  69206. +./strnlen.$(objext): $(srcdir)/strnlen.c config.h
  69207. + if [ x"$(PICFLAG)" != x ]; then \
  69208. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strnlen.c -o pic/$@; \
  69209. + else true; fi
  69210. + $(COMPILE.c) $(srcdir)/strnlen.c $(OUTPUT_OPTION)
  69211. +
  69212. +./strrchr.$(objext): $(srcdir)/strrchr.c $(INCDIR)/ansidecl.h
  69213. + if [ x"$(PICFLAG)" != x ]; then \
  69214. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strrchr.c -o pic/$@; \
  69215. + else true; fi
  69216. + $(COMPILE.c) $(srcdir)/strrchr.c $(OUTPUT_OPTION)
  69217. +
  69218. +./strsignal.$(objext): $(srcdir)/strsignal.c config.h $(INCDIR)/ansidecl.h \
  69219. + $(INCDIR)/libiberty.h
  69220. + if [ x"$(PICFLAG)" != x ]; then \
  69221. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strsignal.c -o pic/$@; \
  69222. + else true; fi
  69223. + $(COMPILE.c) $(srcdir)/strsignal.c $(OUTPUT_OPTION)
  69224. +
  69225. +./strstr.$(objext): $(srcdir)/strstr.c
  69226. + if [ x"$(PICFLAG)" != x ]; then \
  69227. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strstr.c -o pic/$@; \
  69228. + else true; fi
  69229. + $(COMPILE.c) $(srcdir)/strstr.c $(OUTPUT_OPTION)
  69230. +
  69231. +./strtod.$(objext): $(srcdir)/strtod.c $(INCDIR)/ansidecl.h \
  69232. + $(INCDIR)/safe-ctype.h
  69233. + if [ x"$(PICFLAG)" != x ]; then \
  69234. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtod.c -o pic/$@; \
  69235. + else true; fi
  69236. + $(COMPILE.c) $(srcdir)/strtod.c $(OUTPUT_OPTION)
  69237. +
  69238. +./strtol.$(objext): $(srcdir)/strtol.c config.h $(INCDIR)/safe-ctype.h
  69239. + if [ x"$(PICFLAG)" != x ]; then \
  69240. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtol.c -o pic/$@; \
  69241. + else true; fi
  69242. + $(COMPILE.c) $(srcdir)/strtol.c $(OUTPUT_OPTION)
  69243. +
  69244. +./strtoul.$(objext): $(srcdir)/strtoul.c config.h $(INCDIR)/ansidecl.h \
  69245. + $(INCDIR)/safe-ctype.h
  69246. + if [ x"$(PICFLAG)" != x ]; then \
  69247. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtoul.c -o pic/$@; \
  69248. + else true; fi
  69249. + $(COMPILE.c) $(srcdir)/strtoul.c $(OUTPUT_OPTION)
  69250. +
  69251. +./strverscmp.$(objext): $(srcdir)/strverscmp.c $(INCDIR)/ansidecl.h \
  69252. + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
  69253. + if [ x"$(PICFLAG)" != x ]; then \
  69254. + $(COMPILE.c) $(PICFLAG) $(srcdir)/strverscmp.c -o pic/$@; \
  69255. + else true; fi
  69256. + $(COMPILE.c) $(srcdir)/strverscmp.c $(OUTPUT_OPTION)
  69257. +
  69258. +./timeval-utils.$(objext): $(srcdir)/timeval-utils.c config.h \
  69259. + $(INCDIR)/timeval-utils.h
  69260. + if [ x"$(PICFLAG)" != x ]; then \
  69261. + $(COMPILE.c) $(PICFLAG) $(srcdir)/timeval-utils.c -o pic/$@; \
  69262. + else true; fi
  69263. + $(COMPILE.c) $(srcdir)/timeval-utils.c $(OUTPUT_OPTION)
  69264. +
  69265. +./tmpnam.$(objext): $(srcdir)/tmpnam.c
  69266. + if [ x"$(PICFLAG)" != x ]; then \
  69267. + $(COMPILE.c) $(PICFLAG) $(srcdir)/tmpnam.c -o pic/$@; \
  69268. + else true; fi
  69269. + $(COMPILE.c) $(srcdir)/tmpnam.c $(OUTPUT_OPTION)
  69270. +
  69271. +./unlink-if-ordinary.$(objext): $(srcdir)/unlink-if-ordinary.c config.h \
  69272. + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
  69273. + if [ x"$(PICFLAG)" != x ]; then \
  69274. + $(COMPILE.c) $(PICFLAG) $(srcdir)/unlink-if-ordinary.c -o pic/$@; \
  69275. + else true; fi
  69276. + $(COMPILE.c) $(srcdir)/unlink-if-ordinary.c $(OUTPUT_OPTION)
  69277. +
  69278. +./vasprintf.$(objext): $(srcdir)/vasprintf.c config.h $(INCDIR)/ansidecl.h \
  69279. + $(INCDIR)/libiberty.h
  69280. + if [ x"$(PICFLAG)" != x ]; then \
  69281. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vasprintf.c -o pic/$@; \
  69282. + else true; fi
  69283. + $(COMPILE.c) $(srcdir)/vasprintf.c $(OUTPUT_OPTION)
  69284. +
  69285. +./vfork.$(objext): $(srcdir)/vfork.c $(INCDIR)/ansidecl.h
  69286. + if [ x"$(PICFLAG)" != x ]; then \
  69287. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vfork.c -o pic/$@; \
  69288. + else true; fi
  69289. + $(COMPILE.c) $(srcdir)/vfork.c $(OUTPUT_OPTION)
  69290. +
  69291. +./vfprintf.$(objext): $(srcdir)/vfprintf.c $(INCDIR)/ansidecl.h
  69292. + if [ x"$(PICFLAG)" != x ]; then \
  69293. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vfprintf.c -o pic/$@; \
  69294. + else true; fi
  69295. + $(COMPILE.c) $(srcdir)/vfprintf.c $(OUTPUT_OPTION)
  69296. +
  69297. +./vprintf.$(objext): $(srcdir)/vprintf.c $(INCDIR)/ansidecl.h
  69298. + if [ x"$(PICFLAG)" != x ]; then \
  69299. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vprintf.c -o pic/$@; \
  69300. + else true; fi
  69301. + $(COMPILE.c) $(srcdir)/vprintf.c $(OUTPUT_OPTION)
  69302. +
  69303. +./vsnprintf.$(objext): $(srcdir)/vsnprintf.c config.h $(INCDIR)/ansidecl.h \
  69304. + $(INCDIR)/libiberty.h
  69305. + if [ x"$(PICFLAG)" != x ]; then \
  69306. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vsnprintf.c -o pic/$@; \
  69307. + else true; fi
  69308. + $(COMPILE.c) $(srcdir)/vsnprintf.c $(OUTPUT_OPTION)
  69309. +
  69310. +./vsprintf.$(objext): $(srcdir)/vsprintf.c $(INCDIR)/ansidecl.h
  69311. + if [ x"$(PICFLAG)" != x ]; then \
  69312. + $(COMPILE.c) $(PICFLAG) $(srcdir)/vsprintf.c -o pic/$@; \
  69313. + else true; fi
  69314. + $(COMPILE.c) $(srcdir)/vsprintf.c $(OUTPUT_OPTION)
  69315. +
  69316. +./waitpid.$(objext): $(srcdir)/waitpid.c config.h $(INCDIR)/ansidecl.h
  69317. + if [ x"$(PICFLAG)" != x ]; then \
  69318. + $(COMPILE.c) $(PICFLAG) $(srcdir)/waitpid.c -o pic/$@; \
  69319. + else true; fi
  69320. + $(COMPILE.c) $(srcdir)/waitpid.c $(OUTPUT_OPTION)
  69321. +
  69322. +./xatexit.$(objext): $(srcdir)/xatexit.c config.h $(INCDIR)/ansidecl.h \
  69323. + $(INCDIR)/libiberty.h
  69324. + if [ x"$(PICFLAG)" != x ]; then \
  69325. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xatexit.c -o pic/$@; \
  69326. + else true; fi
  69327. + $(COMPILE.c) $(srcdir)/xatexit.c $(OUTPUT_OPTION)
  69328. +
  69329. +./xexit.$(objext): $(srcdir)/xexit.c config.h $(INCDIR)/ansidecl.h \
  69330. + $(INCDIR)/libiberty.h
  69331. + if [ x"$(PICFLAG)" != x ]; then \
  69332. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xexit.c -o pic/$@; \
  69333. + else true; fi
  69334. + $(COMPILE.c) $(srcdir)/xexit.c $(OUTPUT_OPTION)
  69335. +
  69336. +./xmalloc.$(objext): $(srcdir)/xmalloc.c config.h $(INCDIR)/ansidecl.h \
  69337. + $(INCDIR)/libiberty.h
  69338. + if [ x"$(PICFLAG)" != x ]; then \
  69339. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xmalloc.c -o pic/$@; \
  69340. + else true; fi
  69341. + $(COMPILE.c) $(srcdir)/xmalloc.c $(OUTPUT_OPTION)
  69342. +
  69343. +./xmemdup.$(objext): $(srcdir)/xmemdup.c config.h $(INCDIR)/ansidecl.h \
  69344. + $(INCDIR)/libiberty.h
  69345. + if [ x"$(PICFLAG)" != x ]; then \
  69346. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xmemdup.c -o pic/$@; \
  69347. + else true; fi
  69348. + $(COMPILE.c) $(srcdir)/xmemdup.c $(OUTPUT_OPTION)
  69349. +
  69350. +./xstrdup.$(objext): $(srcdir)/xstrdup.c config.h $(INCDIR)/ansidecl.h \
  69351. + $(INCDIR)/libiberty.h
  69352. + if [ x"$(PICFLAG)" != x ]; then \
  69353. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrdup.c -o pic/$@; \
  69354. + else true; fi
  69355. + $(COMPILE.c) $(srcdir)/xstrdup.c $(OUTPUT_OPTION)
  69356. +
  69357. +./xstrerror.$(objext): $(srcdir)/xstrerror.c config.h $(INCDIR)/ansidecl.h \
  69358. + $(INCDIR)/libiberty.h
  69359. + if [ x"$(PICFLAG)" != x ]; then \
  69360. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrerror.c -o pic/$@; \
  69361. + else true; fi
  69362. + $(COMPILE.c) $(srcdir)/xstrerror.c $(OUTPUT_OPTION)
  69363. +
  69364. +./xstrndup.$(objext): $(srcdir)/xstrndup.c config.h $(INCDIR)/ansidecl.h \
  69365. + $(INCDIR)/libiberty.h
  69366. + if [ x"$(PICFLAG)" != x ]; then \
  69367. + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrndup.c -o pic/$@; \
  69368. + else true; fi
  69369. + $(COMPILE.c) $(srcdir)/xstrndup.c $(OUTPUT_OPTION)
  69370. +
  69371. diff -Nur gcc-4.9.4.orig/libiberty/required-list gcc-4.9.4/libiberty/required-list
  69372. --- gcc-4.9.4.orig/libiberty/required-list 1970-01-01 01:00:00.000000000 +0100
  69373. +++ gcc-4.9.4/libiberty/required-list 2016-08-08 20:37:53.866593761 +0200
  69374. @@ -0,0 +1 @@
  69375. +./regex.o ./cplus-dem.o ./cp-demangle.o ./md5.o ./sha1.o ./alloca.o ./argv.o ./choose-temp.o ./concat.o ./cp-demint.o ./crc32.o ./dwarfnames.o ./dyn-string.o ./fdmatch.o ./fibheap.o ./filename_cmp.o ./floatformat.o ./fnmatch.o ./fopen_unlocked.o ./getopt.o ./getopt1.o ./getpwd.o ./getruntime.o ./hashtab.o ./hex.o ./lbasename.o ./lrealpath.o ./make-relative-prefix.o ./make-temp-file.o ./objalloc.o ./obstack.o ./partition.o ./pexecute.o ./physmem.o ./pex-common.o ./pex-one.o ./pex-unix.o ./safe-ctype.o ./simple-object.o ./simple-object-coff.o ./simple-object-elf.o ./simple-object-mach-o.o ./simple-object-xcoff.o ./sort.o ./spaces.o ./splay-tree.o ./stack-limit.o ./strerror.o ./strsignal.o ./timeval-utils.o ./unlink-if-ordinary.o ./xatexit.o ./xexit.o ./xmalloc.o ./xmemdup.o ./xstrdup.o ./xstrerror.o ./xstrndup.o
  69376. diff -Nur gcc-4.9.4.orig/libiberty/stamp-h gcc-4.9.4/libiberty/stamp-h
  69377. --- gcc-4.9.4.orig/libiberty/stamp-h 1970-01-01 01:00:00.000000000 +0100
  69378. +++ gcc-4.9.4/libiberty/stamp-h 2016-08-08 20:37:53.866593761 +0200
  69379. @@ -0,0 +1 @@
  69380. +timestamp
  69381. diff -Nur gcc-4.9.4.orig/libiberty/testsuite/Makefile gcc-4.9.4/libiberty/testsuite/Makefile
  69382. --- gcc-4.9.4.orig/libiberty/testsuite/Makefile 1970-01-01 01:00:00.000000000 +0100
  69383. +++ gcc-4.9.4/libiberty/testsuite/Makefile 2016-08-08 20:37:53.870593915 +0200
  69384. @@ -0,0 +1,92 @@
  69385. +#
  69386. +# Makefile
  69387. +# Copyright (C) 1999, 2002, 2006
  69388. +# Free Software Foundation
  69389. +#
  69390. +# This file is part of the libiberty library.
  69391. +# Libiberty is free software; you can redistribute it and/or
  69392. +# modify it under the terms of the GNU Library General Public
  69393. +# License as published by the Free Software Foundation; either
  69394. +# version 2 of the License, or (at your option) any later version.
  69395. +#
  69396. +# Libiberty is distributed in the hope that it will be useful,
  69397. +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  69398. +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  69399. +# Library General Public License for more details.
  69400. +#
  69401. +# You should have received a copy of the GNU Library General Public
  69402. +# License along with libiberty; see the file COPYING.LIB. If not,
  69403. +# write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  69404. +# Boston, MA 02110-1301, USA.
  69405. +#
  69406. +
  69407. +# This file was written by Tom Tromey <tromey@cygnus.com>.
  69408. +
  69409. +#
  69410. +# Makefile for libiberty/testsuite directory
  69411. +#
  69412. +
  69413. +srcdir = .
  69414. +
  69415. +
  69416. +SHELL = /bin/sh
  69417. +
  69418. +CC = /home/users/kito/toolchain/nds32le-linux-glibc-v3/bin/nds32le-linux-gcc
  69419. +CFLAGS = -g -O2
  69420. +LIBCFLAGS = $(CFLAGS)
  69421. +
  69422. +# Multilib support variables.
  69423. +MULTISRCTOP =
  69424. +
  69425. +INCDIR=$(srcdir)/../$(MULTISRCTOP)../include
  69426. +
  69427. +all:
  69428. +
  69429. +# CHECK is set to "really_check" or the empty string by configure.
  69430. +check: really-check
  69431. +
  69432. +really-check: check-cplus-dem check-pexecute check-expandargv
  69433. +
  69434. +# Run some tests of the demangler.
  69435. +check-cplus-dem: test-demangle $(srcdir)/demangle-expected
  69436. + ./test-demangle < $(srcdir)/demangle-expected
  69437. +
  69438. +# Check the pexecute code.
  69439. +check-pexecute: test-pexecute
  69440. + ./test-pexecute
  69441. +
  69442. +# Check the expandargv functionality
  69443. +check-expandargv: test-expandargv
  69444. + ./test-expandargv
  69445. +
  69446. +TEST_COMPILE = $(CC) -DHAVE_CONFIG_H $(LIBCFLAGS) -I.. -I$(INCDIR) $(HDEFINES)
  69447. +test-demangle: $(srcdir)/test-demangle.c ../libiberty.a
  69448. + $(TEST_COMPILE) -o test-demangle \
  69449. + $(srcdir)/test-demangle.c ../libiberty.a
  69450. +
  69451. +test-pexecute: $(srcdir)/test-pexecute.c ../libiberty.a
  69452. + $(TEST_COMPILE) -DHAVE_CONFIG_H -I.. -o test-pexecute \
  69453. + $(srcdir)/test-pexecute.c ../libiberty.a
  69454. +
  69455. +test-expandargv: $(srcdir)/test-expandargv.c ../libiberty.a
  69456. + $(TEST_COMPILE) -DHAVE_CONFIG_H -I.. -o test-expandargv \
  69457. + $(srcdir)/test-expandargv.c ../libiberty.a
  69458. +
  69459. +# Standard (either GNU or Cygnus) rules we don't use.
  69460. +html install-html info install-info clean-info dvi pdf install-pdf \
  69461. +install etags tags installcheck:
  69462. +
  69463. +# The standard clean rules.
  69464. +mostlyclean:
  69465. + rm -f test-demangle
  69466. + rm -f test-pexecute
  69467. + rm -f test-expandargv
  69468. + rm -f core
  69469. +clean: mostlyclean
  69470. +distclean: clean
  69471. + rm -f Makefile
  69472. +maintainer-clean realclean: distclean
  69473. +
  69474. +Makefile: $(srcdir)/Makefile.in ../config.status
  69475. + CONFIG_FILES=testsuite/Makefile CONFIG_HEADERS= \
  69476. + cd .. && $(SHELL) ./config.status
  69477. diff -Nur gcc-4.9.4.orig/libiberty/xhost-mkfrag gcc-4.9.4/libiberty/xhost-mkfrag
  69478. --- gcc-4.9.4.orig/libiberty/xhost-mkfrag 1970-01-01 01:00:00.000000000 +0100
  69479. +++ gcc-4.9.4/libiberty/xhost-mkfrag 2016-08-08 20:37:53.870593915 +0200
  69480. @@ -0,0 +1,2 @@
  69481. +# Warning: this fragment is automatically generated
  69482. +enable_shared = no