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riscv64: add support for nommu target systems

Waldemar Brodkorb 2 years ago
parent
commit
fe32260dec

+ 3 - 3
mk/vars.mk

@@ -171,9 +171,9 @@ endif
 endif
 
 ifeq ($(ADK_TARGET_BINFMT_FLAT),y)
-TARGET_LDFLAGS+=	-Wl,-elf2flt
-TARGET_CFLAGS+=		-Wl,-elf2flt
-TARGET_CXXFLAGS+=	-Wl,-elf2flt
+TARGET_LDFLAGS+=	-Wl,-elf2flt=-r
+TARGET_CFLAGS+=		-Wl,-elf2flt=-r
+TARGET_CXXFLAGS+=	-Wl,-elf2flt=-r
 endif
 
 ifeq ($(ADK_TARGET_BINFMT_FLAT_SEP_DATA),y)

+ 1 - 1
target/config/Config.in.binfmt

@@ -16,7 +16,7 @@ config ADK_TARGET_BINFMT_FLAT
 	depends on ADK_TARGET_LIB_UCLIBC_NG
 	depends on !ADK_TARGET_WITH_MMU
 	depends on ADK_TARGET_ARCH_ARM || ADK_TARGET_ARCH_M68K || ADK_TARGET_ARCH_SH || ADK_TARGET_ARCH_XTENSA \
-		|| ADK_TARGET_ARCH_H8300 || ADK_TARGET_ARCH_LM32 || ADK_TARGET_ARCH_BFIN
+		|| ADK_TARGET_ARCH_H8300 || ADK_TARGET_ARCH_LM32 || ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_RISCV64
 
 config ADK_TARGET_BINFMT_FDPIC
 	bool "FDPIC"

+ 0 - 3
target/config/Config.in.cpu

@@ -1162,7 +1162,6 @@ config ADK_TARGET_CPU_RISCV64_RV64IMAC
 	bool "rv64imac"
 	select ADK_TARGET_SUPPORTS_THREADS
 	select ADK_TARGET_SUPPORTS_NPTL
-	select ADK_TARGET_WITH_MMU
 	select ADK_TARGET_ABI_LP64
 	depends on ADK_TARGET_ARCH_RISCV64
 
@@ -1170,7 +1169,6 @@ config ADK_TARGET_CPU_RISCV64_RV64IMAFC
 	bool "rv64imafc"
 	select ADK_TARGET_SUPPORTS_THREADS
 	select ADK_TARGET_SUPPORTS_NPTL
-	select ADK_TARGET_WITH_MMU
 	select ADK_TARGET_ABI_LP64F
 	depends on ADK_TARGET_ARCH_RISCV64
 
@@ -1178,7 +1176,6 @@ config ADK_TARGET_CPU_RISCV64_RV64IMADC
 	bool "rv64imadc"
 	select ADK_TARGET_SUPPORTS_THREADS
 	select ADK_TARGET_SUPPORTS_NPTL
-	select ADK_TARGET_WITH_MMU
 	select ADK_TARGET_ABI_LP64D
 	depends on ADK_TARGET_ARCH_RISCV64
 

+ 2 - 0
target/config/Config.in.rootfs

@@ -24,6 +24,8 @@ config ADK_TARGET_ROOTFS_INITRAMFSPIGGYBACK
 		ADK_TARGET_ARCH_MIPS || \
 		ADK_TARGET_ARCH_MIPS64 || \
 		ADK_TARGET_ARCH_PPC || \
+		ADK_TARGET_ARCH_RISCV32 || \
+		ADK_TARGET_ARCH_RISCV64 || \
 		ADK_TARGET_ARCH_SH || \
 		ADK_TARGET_ARCH_SPARC || \
 		ADK_TARGET_ARCH_X86 || \

+ 10 - 0
target/riscv64/Makefile

@@ -48,10 +48,17 @@ ifeq ($(ADK_TARGET_QEMU),y)
 	@echo 'qemu-system-riscv64 ${QEMU_ARGS} -kernel $(FW_DIR)/$(TARGET_KERNEL)'
 endif
 endif
+ifeq ($(ADK_TARGET_FS),nfsroot)
+targethelp:
+	@echo 'The kernel file is: $(FW_DIR)/${TARGET_KERNEL}'
+	@echo "The RootFS tarball is: $(FW_DIR)/$(ROOTFSUSERTARBALL)"
+endif
 
 kernel-strip:
+	@cp $(KERNEL) $(BUILD_DIR)/$(TARGET_KERNEL)
 
 kernel-install: kernel-strip
+	@cp $(BUILD_DIR)/$(TARGET_KERNEL) $(FW_DIR)/$(TARGET_KERNEL)
 
 # filesystem specific targets
 ifeq ($(ADK_TARGET_FS),archive)
@@ -66,3 +73,6 @@ endif
 ifeq ($(ADK_TARGET_FS),initramfspiggyback)
 imageinstall: createinitramfs targethelp
 endif
+ifeq ($(ADK_TARGET_FS),nfsroot)
+imageinstall: kernel-install $(FW_DIR)/$(ROOTFSUSERTARBALL) targethelp
+endif

+ 9 - 0
target/riscv64/kernel/sipeed-maix-bit

@@ -0,0 +1,9 @@
+CONFIG_RISCV=y
+CONFIG_SOC_CANAAN=y
+CONFIG_SOC_CANAAN_K210_DTB_BUILTIN=y
+CONFIG_SOC_CANAAN_K210_DTB_SOURCE="sipeed_maix_bit"
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_CMDLINE="earlycon console=ttySIF0"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y

+ 6 - 0
target/riscv64/systems/sipeed-maix-bit

@@ -0,0 +1,6 @@
+config ADK_TARGET_SYSTEM_SIPEED_MAIX_BIT
+	bool "Sipeed MAiX Bit"
+	select ADK_TARGET_CPU_RISCV64
+	select ADK_TARGET_KERNEL_IMAGE
+	help
+	  Sipeed MAiX Bit support.

+ 137 - 0
toolchain/elf2flt/patches/453398f917d167f8c308c8f997270c48ae8f8b12/0005-elf2flt-add-riscv-64-bits-support.patch

@@ -0,0 +1,137 @@
+From 1dea576eac4289602adc4a37f48c80330bf82e63 Mon Sep 17 00:00:00 2001
+From: Damien Le Moal <damien.lemoal@wdc.com>
+Date: Wed, 9 Sep 2020 17:31:33 +0900
+Subject: [PATCH] elf2flt: add riscv 64-bits support
+
+Add support for riscv 64bits ISA by defining the relocation types
+R_RISCV_32_PCREL, R_RISCV_ADD32, R_RISCV_SUB32, R_RISCV_32 and
+R_RISCV_64. riscv64 support also needs the __global_pointer$ symbol to
+be defined right after the relocation tables in the data section.
+Furthermore, the .got and .got.plt sections must be reversed. These 2
+requirements are handled with runtime modifications of the default
+linker script using the append_sed() function.
+(1) For the .got.plt and .got sections order swap, append_sed() is used
+to rename "(.got.plt)" to "(.got.tmp)" and to rename "(.got)" to
+"(.got.plt)". A last call finalize the name swap by replacing
+"(.got.tmp)" with "(.got)"
+(2) For the global pointer synbol, a definition line starting with
+"RISCV_GP" is added. The "RISCV_GP" string is removed if the target CPU
+type is riscv64. The definition line is dropped for other CPU types.
+
+With these changes, buildroot/busybox builds and run on NOMMU
+systems with kernel 5.13. Tested on Canaan Kendryte K210 boards.
+
+This patch is based on earlier work by Christoph Hellwig <hch@lst.de>.
+
+Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
+---
+ elf2flt.c     | 23 +++++++++++++++++++++++
+ elf2flt.ld.in |  9 +++++----
+ ld-elf2flt.c  | 16 ++++++++++++++++
+ 3 files changed, 44 insertions(+), 4 deletions(-)
+
+diff --git a/elf2flt.c b/elf2flt.c
+index f87f1fc..dbce467 100644
+--- a/elf2flt.c
++++ b/elf2flt.c
+@@ -80,6 +80,8 @@ const char *elf2flt_progname;
+ #include <elf/v850.h>
+ #elif defined(TARGET_xtensa)
+ #include <elf/xtensa.h>
++#elif defined(TARGET_riscv64)
++#include <elf/riscv.h>
+ #endif
+ 
+ #if defined(__MINGW32__)
+@@ -122,6 +124,8 @@ const char *elf2flt_progname;
+ #define ARCH	"nios2"
+ #elif defined(TARGET_xtensa)
+ #define ARCH	"xtensa"
++#elif defined(TARGET_riscv64)
++#define ARCH	"riscv64"
+ #else
+ #error "Don't know how to support your CPU architecture??"
+ #endif
+@@ -797,6 +801,16 @@ output_relocs (
+ 					goto good_32bit_resolved_reloc;
+ 				default:
+ 					goto bad_resolved_reloc;
++#elif defined(TARGET_riscv64)
++				case R_RISCV_32_PCREL:
++				case R_RISCV_ADD32:
++				case R_RISCV_SUB32:
++					continue;
++				case R_RISCV_32:
++				case R_RISCV_64:
++					goto good_32bit_resolved_reloc;
++				default:
++					goto bad_resolved_reloc;
+ #else
+ 				default:
+ 					/* The default is to assume that the
+@@ -1806,6 +1820,15 @@ int main(int argc, char *argv[])
+   if (!load_to_ram && !pfile)
+     load_to_ram = 1;
+ 
++#if defined(TARGET_riscv64)
++  /*
++   * riscv only supports loading text and data contiguously.
++   * So fail if load_to_ram is false.
++   */
++  if (!load_to_ram)
++    fatal("Loading to RAM ('-r' option) is required");
++#endif
++
+   fname = argv[argc-1];
+ 
+   if (pfile) {
+diff --git a/elf2flt.ld.in b/elf2flt.ld.in
+index ec1fe6f..c0c44b8 100644
+--- a/elf2flt.ld.in
++++ b/elf2flt.ld.in
+@@ -70,10 +70,11 @@ W_RODAT		*(.gnu.linkonce.r*)
+ 		. = ALIGN(0x20) ;
+ 		LONG(-1)
+ 		. = ALIGN(0x20) ;
+-R_RODAT		*(.rodata)
+-R_RODAT		*(.rodata1)
+-R_RODAT		*(.rodata.*)
+-R_RODAT		*(.gnu.linkonce.r*)
++RISCV_GP:	__global_pointer$ = . + 0x800 ;
++R_RODAT 	*(.rodata)
++R_RODAT 	*(.rodata1)
++R_RODAT 	*(.rodata.*)
++R_RODAT 	*(.gnu.linkonce.r*)
+ 		*(.data)
+ 		*(.data1)
+ 		*(.data.*)
+diff --git a/ld-elf2flt.c b/ld-elf2flt.c
+index e5de506..31b565f 100644
+--- a/ld-elf2flt.c
++++ b/ld-elf2flt.c
+@@ -324,6 +324,22 @@ static int do_final_link(void)
+ 		append_option(&other_options, concat(got_offset, "=", buf, NULL));
+ 	}
+ 
++	if (streq(TARGET_CPU, "riscv64")) {
++		/*
++		 * The .got section must come before the .got.plt section
++		 * (gcc/ld bug ?).
++		 */
++		append_sed(&sed, "(.got.plt)", "(.got.tmp)");
++		append_sed(&sed, "(.got.plt)", "(.got)");
++		append_sed(&sed, "(.got.tmp)", "(.got.plt)");
++
++		/* The global pointer symbol is defined after the GOT. */
++		append_sed(&sed, "^RISCV_GP:", "");
++	} else {
++		/* Get rid of the global pointer definition. */
++		append_sed(&sed, "^RISCV_GP:", NULL);
++	}
++
+ 	/* Locate the default linker script, if we don't have one provided. */
+ 	if (!linker_script)
+ 		linker_script = concat(ldscriptpath, "/elf2flt.ld", NULL);
+-- 
+2.31.1
+