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@@ -85,52 +85,52 @@ register unsigned int __r0 __asm__ ("r0");
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register unsigned int __r4 __asm__ ("r4") = n;
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register unsigned int __r5 __asm__ ("r5") = base;
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- __asm__ ("
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- mov #0, r0
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- div0u
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-
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- ! get one bit from the msb of the numerator into the T
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- ! bit and divide it by whats in %2. Put the answer bit
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- ! into the T bit so it can come out again at the bottom
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-
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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-
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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-
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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-
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4 ; div1 r5, r0
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- rotcl r4
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- mov r4, r0
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-"
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+ __asm__ ("" \
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+ "mov #0, r0\n\t" \
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+ "div0u\n\t" \
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+ "" \
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+ "! get one bit from the msb of the numerator into the T\n\t" \
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+ "! bit and divide it by whats in %2. Put the answer bit\n\t" \
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+ "! into the T bit so it can come out again at the bottom\n\t" \
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+ "" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4 ; div1 r5, r0\n\t" \
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+ "rotcl r4\n\t" \
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+ "mov r4, r0\n\t"
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+
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: "=r" (__r0)
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: "r" (__r4), "r" (__r5)
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: "r4", "cc");
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