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@@ -0,0 +1,464 @@
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+ /* This file is lisenced under LGPL.
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+ * Copyright (C) 2002-2003, George Thanos <george.thanos@gdt.gr>
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+ * Yannis Mitsos <yannis.mitsos@gdt.gr>
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+ */
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+#ifndef _BITS_UNISTD_H_
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+#define _BITS_UNISTD_H_
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+
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+#include <bits/proto.h>
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+#include <errno.h>
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+
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+#define __E1_COFF_GCC__
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+
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+/* The following macros have been provided by C.Baumhof
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+ * They can be inlined in contrast to the previous ones*/
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+#define _syscall0(type, name) \
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+type name(void) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2) \
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+ :"memory","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall1(type, name,atype, a) \
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+type name(atype a) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3) \
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+ :"memory","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall2(type, name,atype, a, btype, b) \
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+type name(atype a, btype b) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3), "l"(par4) \
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+ :"memory","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall3(type, name,atype, a, btype, b, ctype, c) \
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+type name(atype a, btype b, ctype c) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
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+ :"memory","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
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+type name(atype a, btype b, ctype c,dtype d) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
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+ :"memory","L10","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
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+type name(atype a, btype b, ctype c,dtype d, etype e) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ register int par7 __asm__("L9"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ par7 = (int)e; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
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+ :"memory","L9","L10","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+ return (type)(par1); \
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+}
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+
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+#define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
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+type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ register int par7 __asm__("L9"); \
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+ register int par8 __asm__("L8"); \
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+ int sys_retval; \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ par7 = (int)e; \
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+ par7 = (int)f; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
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+ :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall0(type, name) \
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+type name(...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2)\
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+ :"memory","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall1(type, name, atype, a) \
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+type name(atype a, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3)\
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+ :"memory","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall2(type, name,atype, a, btype, b) \
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+type name(atype a, btype b, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3), "l"(par4)\
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+ :"memory","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall3(type, name,atype, a, btype, b, ctype, c) \
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+type name(atype a, btype b, ctype c, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
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+ :"memory","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
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+type name(atype a, btype b, ctype c,dtype d, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
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+ :"memory","L10","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
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+type name(atype a, btype b, ctype c,dtype d, etype e, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ register int par7 __asm__("L9"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ par7 = (int)e; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
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+ :"memory","L9","L10","L11","L12","L13","L14","L15"); \
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+ \
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+ if( par1 < 0 ) { \
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+ __set_errno( -par1 ); \
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+ return -1; \
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+ } else \
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+ return (type)(par1); \
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+}
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+
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+#define __syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
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+type name(atype a, btype b, ctype c,dtype d, etype e, ftype f, ...) \
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+{ \
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+ register int par1 __asm__("L15"); \
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+ register int par2 __asm__("L14"); \
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+ register int par3 __asm__("L13"); \
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+ register int par4 __asm__("L12"); \
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+ register int par5 __asm__("L11"); \
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+ register int par6 __asm__("L10"); \
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+ register int par7 __asm__("L9"); \
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+ register int par8 __asm__("L8"); \
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+ par1 = -1; \
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+ par2 = __NR_##name; \
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+ par3 = (int)a; \
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+ par4 = (int)b; \
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+ par5 = (int)c; \
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+ par6 = (int)d; \
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+ par7 = (int)e; \
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+ par7 = (int)f; \
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+ __asm__ __volatile__( \
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+ "trap 47" \
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+ :"=l"(par1) \
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+ :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
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+ :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
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+ \
|
|
|
+ if( par1 < 0 ) { \
|
|
|
+ __set_errno( -par1 ); \
|
|
|
+ return -1; \
|
|
|
+ } else \
|
|
|
+ return (type)(par1); \
|
|
|
+}
|
|
|
+
|
|
|
+#include <sys/types.h>
|
|
|
+/* Taken from <bits/errno.h> */
|
|
|
+#ifndef _LIBC
|
|
|
+/* We don't support pthreads for the moment*/
|
|
|
+#define __set_errno(val) ((errno) = (val))
|
|
|
+#endif
|
|
|
+
|
|
|
+#if 0
|
|
|
+#define _syscall3(type, name,atype, a , btype, b, ctype, c) \
|
|
|
+type name(atype a, btype b, ctype c,) \
|
|
|
+{ \
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "movi L9, -1\n\t" \
|
|
|
+ "movi L8, %0\n\t" \
|
|
|
+ "ldw.d G3, L7, 0\n\t" \
|
|
|
+ "ldw.d G3, L6, 4\n\t" \
|
|
|
+ "ldw.d G3, L5, 8\n\t" \
|
|
|
+ :/* no output */ \
|
|
|
+ :"i"(__NR_##name) \
|
|
|
+ :"cc","memory","%L5","L6","L7","L8","L9");\
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "trap 47\n\t" \
|
|
|
+ "mov L2, L9\n\t"); \
|
|
|
+}
|
|
|
+
|
|
|
+#define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
|
|
|
+type name(atype a, btype b, ctype c,dtype d) \
|
|
|
+{ \
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "movi L11, -1\n\t" \
|
|
|
+ "movi L10, %0\n\t" \
|
|
|
+ "ldw.d G3, L9, 0\n\t" \
|
|
|
+ "ldw.d G3, L8, 4\n\t" \
|
|
|
+ "ldw.d G3, L7, 8\n\t" \
|
|
|
+ "ldw.d G3, L6, 12\n\t" \
|
|
|
+ :/* no output */ \
|
|
|
+ :"i"(__NR_##name) \
|
|
|
+ :"cc","memory","L6","L7","L8","L9","L10","L11");\
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "trap 47\n\t" \
|
|
|
+ "mov L2, L11\n\t"); \
|
|
|
+}
|
|
|
+
|
|
|
+#define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
|
|
|
+type name(atype a, btype b, ctype c,dtype d, etype e) \
|
|
|
+{ \
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "movi L13, -1\n\t" \
|
|
|
+ "movi L12, %0\n\t" \
|
|
|
+ "ldw.d G3, L11, 0\n\t" \
|
|
|
+ "ldw.d G3, L10, 4\n\t" \
|
|
|
+ "ldw.d G3, L9, 8\n\t" \
|
|
|
+ "ldw.d G3, L8, 12\n\t" \
|
|
|
+ "ldw.d G3, L7, 16\n\t" \
|
|
|
+ :/* no output */ \
|
|
|
+ :"i"(__NR_##name) \
|
|
|
+ :"cc","memory","L7","L8","L9","L10","L11","L12","L13");\
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "trap 47\n\t" \
|
|
|
+ "mov L2, L13\n\t"); \
|
|
|
+}
|
|
|
+
|
|
|
+#define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
|
|
|
+type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
|
|
|
+{ \
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "movi L15, -1\n\t" \
|
|
|
+ "movi L14, %0\n\t" \
|
|
|
+ "ldw.d G3, L13, 0\n\t" \
|
|
|
+ "ldw.d G3, L12, 4\n\t" \
|
|
|
+ "ldw.d G3, L11, 8\n\t" \
|
|
|
+ "ldw.d G3, L10, 12\n\t" \
|
|
|
+ "ldw.d G3, L9, 16\n\t" \
|
|
|
+ "ldw.d G3, L8, 20\n\t" \
|
|
|
+ :/* no output */ \
|
|
|
+ :"i"(__NR_##name) \
|
|
|
+ :"cc","memory","L8","L9","L10","L11","L12","L13","L14","L15");\
|
|
|
+ __asm__ __volatile__( \
|
|
|
+ "trap 47\n\t" \
|
|
|
+ "mov L2, L15\n\t"); \
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#endif /* !_HYPERSTONE_NOMMU_UNISTD_H_ */
|